JP2000058683A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: In a semiconductor device having a refractory metal silicide film as a gate material, a stopper film at the time of etching is formed in a SAS (Self-Align-Source) process without deteriorating the film quality of a gate oxide film. In addition to the above, abnormal oxidation of the refractory metal silicide film can be prevented. A polycrystalline silicon film and a tungsten silicide film are stacked in this order, and the gate has a polycide structure. A polycrystalline silicon film is formed in close contact with the tungsten silicide film. The polycrystalline silicon film 14 functions as a stopper film at the time of etching in the SAS process, and functions as a protective film for protecting the tungsten silicide film 12 at the time of ion implantation at a high dose. Further, since the polycrystalline silicon film 12 has a sufficient thickness, the tungsten silicide film 12 is prevented from being abnormally oxidized even in the oxidation step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a transistor structure of a semiconductor device, and more particularly to a semiconductor device using a refractory metal silicide film or a refractory metal film as a gate material and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, polycrystalline silicon (Poly S
i) A gate electrode having a polycide structure in which a high melting point metal silicide, for example, tungsten silicide (WSi ₂ ) is laminated in this order is being used. In the gate electrode having the polycide structure, in the oxidation step after the deposition of the tungsten silicide film, the phenomenon that the tungsten (W) in the tungsten silicide film is directly oxidized to form tungsten oxide (WOx) and cause abnormal volume expansion. Are known. This is because in the oxidation step,
This occurs when the oxidation rate is high or the oxidation amount is large, because the supply of silicon (Si) is insufficient. This phenomenon frequently occurs because as the miniaturization of the semiconductor device progresses, the width of the gate electrode becomes narrower, and the formed film becomes thinner, the supply amount of Si relatively decreases and the oxidation resistance margin decreases. Is to occur.

In order to avoid this problem, a method of depositing an oxide film on the tungsten silicide film and preventing supply of an oxidizing agent to the tungsten silicide film in a subsequent oxidation step has been adopted.

On the other hand, in recent years, especially in a stacked gate type nonvolatile memory, the gate electrode of a memory cell has a high aspect ratio, so that gate processing becomes difficult as miniaturization proceeds. In order to avoid this problem, a method of forming a mask material on the gate, processing at least the mask material with a resist, and processing the laminated gate with the mask material has been adopted. As described above, there is a method of forming an oxide film on a tungsten silicide film constituting a gate by combining the purpose of use as a mask material and the above-described purpose of oxidation resistance.

However, for example, when using a SAS (Self-Align-Source) process of forming a source diffusion layer by removing the source-side device isolation oxide film by self-alignment with the gate, an oxide film on the gate is used in this process. Is also etched, and the tungsten silicide film is exposed. In order to avoid this and stably process flash memory cells and the like, two layers of a silicon nitride film (SiN film) and a silicon oxide film are formed from below on the tungsten silicide film of the polycide gate electrode of the memory cell. Is formed. This method is described in Japanese Patent Application No. 8-347425.

FIGS. 48 and 49 show a cross-sectional structure in the channel length direction of the memory cell of this conventional example. FIG. 48 is a sectional view of a diffusion layer region, and FIG. 49 is a sectional view of an element isolation oxide film region.

As shown in FIG. 48, a tunnel oxide film 202, a floating gate 204, an Inter-Poly insulating film 206, a polycrystalline silicon film 208 forming a control gate, and a tungsten silicide film 210 are formed on a semiconductor substrate 200 in this order from the bottom. Is formed. In addition, tungsten silicide 210
On top, a silicon nitride film 21 as a mask material
2 and a silicon oxide film 214 are continuously formed. Then, using the silicon nitride film 212 as a stopper film, the element isolation oxide film (not shown) is etched and removed in a self-aligned manner to form the source diffusion layer 216 by the SAS process.

[0009] As shown in FIG. 49, a polycrystalline silicon film 208 and a tungsten silicide film 210 forming a control gate are formed on the element isolation oxide film 218 formed on the semiconductor substrate 200 on the element isolation oxide film region. Are formed, and a silicon nitride film 212 and a silicon oxide film 214 are sequentially formed. Then, by the SAS process, the element isolation oxide film 21 is self-aligned using the silicon nitride film 212 as a stopper film.
8 is removed by etching to form a source diffusion layer 216.

[0009]

However, in general, the silicon nitride film has a large film stress, and when deposited on the gate, the film quality of the gate oxide film may be deteriorated. Therefore, in the conventional semiconductor device, there is a possibility that the reliability of the element may be reduced due to the deterioration of the film quality of the gate oxide film.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in a semiconductor device having a polycrystalline silicon film, a refractory metal silicide film or a refractory metal film as a gate material, the quality of a gate oxide film is deteriorated. Without letting
Further, in the SAS (Self-Align-Source) process and the gate sidewall forming process, a stopper film is provided at the time of etching to facilitate the process, and also to prevent abnormal oxidation of the refractory metal silicide film or refractory metal film. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same.

[0011]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a two-layer gate structure having a refractory metal silicide film or a refractory metal film as a gate material. A first silicon film formed on the gate insulating film, a first insulating film formed on the first silicon film, and a second silicon film formed on the first insulating film. A high melting point metal silicide film or a high melting point metal film formed on the second silicon film; and a third silicon film formed on the high melting point metal silicide film or the high melting point metal film. And a film.

Further, the semiconductor device according to the present invention is a semiconductor device having a two-layer gate structure having a refractory metal silicide film or a refractory metal film as a gate material,
A first silicon film formed on the gate insulating film, a first insulating film formed on the first silicon film, and a second silicon film formed on the first insulating film A refractory metal silicide film or a refractory metal film formed on the second silicon film, and a third refractory metal silicide film or a refractory metal film formed on a film surface of the refractory metal film.
And a second insulating film formed on the third silicon film.

Further, according to a method of manufacturing a semiconductor device according to the present invention, there is provided a method of manufacturing a semiconductor device having a two-layer gate structure having a refractory metal silicide film or a refractory metal film as a gate material. Forming a first silicon film, forming a first insulating film on the first silicon film, forming a second silicon film on the first insulating film, Forming the high-melting-point metal silicide film or the high-melting-point metal film on the silicon film, and forming a third silicon film or the third silicon film on the film surface of the high-melting-point metal silicide film or the high-melting-point metal film Forming a laminated film of a first insulating film and a second insulating film, a first insulating film, a first insulating film, a high melting point metal silicide film or a high melting point film formed on the first insulating film. metal Forming a plurality of gates by patterning the third silicon film or a laminated film of the third silicon film and the second insulating film; and forming an element isolation insulator formed between the plurality of adjacent gates. A step of removing the film in a self-aligned manner using the gate as a mask; and a step of performing ion implantation to form a diffusion layer in the semiconductor substrate.

That is, in the semiconductor device and the method of manufacturing the same according to the present invention, in the semiconductor device having a refractory metal silicide film or a refractory metal film as a gate material and the method of manufacturing the same, the refractory metal silicide film or the refractory metal By forming a silicon film on the surface of the film, in the SAS (Self-Align-Source) process and the gate sidewall formation process, the silicon film functions as a stopper film at the time of etching to facilitate the process. . In addition, at the time of ion implantation at a high dose, the silicon film functions as a protective film to prevent the refractory metal silicide film or the refractory metal film from being damaged and abnormally oxidized. Further, since the silicon film having a sufficient thickness is formed on the refractory metal silicide film or the refractory metal film, the metal in the refractory metal silicide film or the refractory metal film is also used in the post-oxidation step. Oxidize to avoid volume expansion.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

[First Embodiment] First, the structure of a two-layer gate type nonvolatile memory according to a first embodiment of the present invention will be described.

FIGS. 1A and 1B are sectional views showing the structure of the nonvolatile memory according to the first embodiment. here,
FIG. 1A is a cross-sectional view of an element in a nonvolatile memory area.
(B) is a sectional view of the element in the peripheral circuit region.

In the non-volatile memory area, a gate insulating film 4 made of a silicon oxide film is formed on a semiconductor substrate 2 as shown in FIG. On the gate insulating film 4, a polycrystalline silicon film 6 forming a floating gate,
Inter-Poly insulating film (for example, ONO film) 8, polycrystalline silicon film 10 forming a control gate, and refractory metal silicide film such as tungsten silicide (WSix)
) The film 12 is formed sequentially from the bottom. Further, a polycrystalline silicon film 14 and a silicon oxide film 16 are sequentially formed on the tungsten silicide film 12 from below. The gate is configured as described above.

On the side surface from the polycrystalline silicon film 6 to the silicon oxide film 16, a sidewall 18 made of a silicon oxide film is formed. Source and drain diffusion layers 20 are formed in the semiconductor substrate 2 on both sides of such a gate. Further, a silicon oxide film 22 is formed on the semiconductor substrate 2 excluding the gate, and an interlayer insulating film 24 is formed so as to cover the entire surface of the semiconductor substrate 2.

Next, in the peripheral circuit region, as shown in FIG. 1B, a gate insulating film 26 made of a silicon oxide film is formed on the semiconductor substrate 2. On this gate insulating film 26, a polycrystalline silicon film 10 forming a gate and a refractory metal silicide film such as a tungsten silicide film 1 are formed.
2 are sequentially formed from the bottom. Further, the polycrystalline silicon film 1 is formed on the tungsten silicide film 12 from below.
4. A silicon oxide film 16 is sequentially formed.

On the side surface from the polycrystalline silicon film 10 to the silicon oxide film 16, a sidewall 18 made of a silicon oxide film is formed. In the semiconductor substrate 2 on both sides of the gate formed as described above,
The source and drain diffusion layers 20 are formed. further,
A silicon oxide film 22 is formed on the semiconductor substrate 2 excluding the gate, and an interlayer insulating film 24 is formed so as to cover the entire surface of the semiconductor substrate 2. The polycrystalline silicon film 1
4 may be another silicon film such as an amorphous silicon film.

Next, a method of manufacturing the nonvolatile memory according to the first embodiment will be described.

FIGS. 2 to 10 and FIG. 1 are cross-sectional views of respective manufacturing steps showing a method of manufacturing the nonvolatile memory according to the first embodiment. 2 (a) to 10 (a) and 1 (a) show elements in the nonvolatile memory area, and FIGS.
FIG. 1B and FIG. 1B show elements in the peripheral circuit area.

First, as shown in FIGS. 2A and 2B, an element isolation oxide film (not shown) is formed in a desired region on the semiconductor substrate 2 by a well-known technique, as shown in FIGS. ), A gate insulating film 4 made of a silicon oxide film is formed. Further, the gate insulating film 4
A polycrystalline silicon film 6 serving as a floating gate is formed thereon.
Is deposited. Subsequently, although not shown in the figure, the polycrystalline silicon film 6 is separated on the device isolation oxide film according to a normal method of manufacturing a two-layer gate nonvolatile memory,
An r-Poly insulating film (for example, ONO film) 8 is deposited on the entire surface.

Next, as shown in FIGS. 3A and 3B,
Only the non-volatile memory area is covered with the resist pattern 28 by photolithography, and the inter-Po
ly insulating film 8, polycrystalline silicon film 6, and gate insulating film 4
Are sequentially etched and removed. After stripping the resist pattern 28, as shown in FIG. 4B, the gate insulating film 2 for the transistor is formed in the peripheral circuit region by, for example, a thermal oxidation method.
6 is formed. At this time, the non-volatile memory area is
The poly insulating film 8 is exposed, and its surface is slightly oxidized.

Thereafter, in the nonvolatile memory area, FIG.
As shown in FIG. 1A, a polycrystalline silicon film 10 forming a control gate, a refractory metal silicide film such as a tungsten silicide film 12, and a polycrystalline silicon film 1 are formed.
4, and a silicon oxide film 30 are sequentially deposited from below. In the same process, in the peripheral circuit region, as shown in FIG. 4B, a polycrystalline silicon film 10 forming a gate electrode and a refractory metal silicide film such as a tungsten silicide film 12, a polycrystalline silicon film 14, And silicon oxide film 3
0 are sequentially deposited from the bottom.

The polycrystalline silicon film 14 has such a thickness that the polycrystalline silicon film 14 is not oxidized in the etching and oxidizing steps when forming the sidewalls 18 described later. For example, the polycrystalline silicon film 14 has a thickness of 50 nm to 300 n.
m (here, 50 nm). Further, the silicon oxide film 30 has a thickness that does not disappear during the processing of a gate described later. Here, for example, the silicon oxide film 30 is formed to a thickness of about 200 nm.

As is clear from FIGS. 4A and 4B, the gate electrode of the peripheral transistor in the peripheral circuit region is formed of the same film as the control gate electrode of the memory cell in the nonvolatile memory region. I have. That is, the gate electrode of the peripheral transistor is formed of a laminated film including the polycrystalline silicon film 10, the tungsten silicide film 12, and the polycrystalline silicon film 14.

Next, as shown in FIGS. 5A and 5B, a resist is applied to form a desired resist pattern 32 in both the nonvolatile memory area and the peripheral circuit area.
The silicon oxide film 30 and the polycrystalline silicon film 14 are etched. Thereafter, the resist pattern 32 is removed, and FIG.
As shown in (a) and (b), the tungsten silicide film 12 and the polycrystalline silicon film 10 are sequentially etched using the stacked film of the silicon oxide film 30 and the polycrystalline silicon film 14 as a mask.

Subsequently, as shown in FIGS. 7A and 7B, only the peripheral circuit area is covered with the resist pattern 34.
The non-volatile memory area is exposed, and the stacked film of the silicon oxide film 30 and the polycrystalline silicon film 14 is used as a mask.
The poly insulating film 8 and the polycrystalline silicon film 6 are sequentially etched to form a gate electrode.

As described above, according to the manufacturing method using the stacked film of the silicon oxide film 30 and the polycrystalline silicon film 14 as a mask, even if the miniaturization progresses and the space between the gates is narrowed, the gate of the stacked structure is used. When the electrode is etched to a layer that requires etching, the aspect ratio of the gate electrode portion is reduced because there is no resist. As a result, the etching gas reaches sufficiently, and the processing of the gate electrode becomes easy.

In the processing of the gate electrode having the laminated structure, for example, Cl ₂ + O ₂ gas and polycrystalline silicon films 10 and 6 are applied to the tungsten silicide film 12.
HBr gas, Inter-Poly insulating film (for example, ON
The O film 8 is processed using an etching gas such as CHF ₃ + CF ₄ + O ₂ gas.

In the processing of the gate electrode,
The silicon oxide film 30 serving as a mask material is also etched and thinned. For this reason, in the first embodiment, the thickness of the silicon oxide film 30 is set and formed so that the silicon oxide film 30 disappears and the underlying polycrystalline silicon film 14 is not exposed by processing the gate electrode. It is important to keep it.

As described above, the silicon oxide film 30 is provided to be used as a mask material at the time of gate processing, and is a material capable of securing a desired selection ratio at the time of etching for gate processing. is necessary. If the silicon oxide film 30 remains in the final step, the silicon oxide film 30 is required to be made of a material that does not adversely affect the reliability of the gate oxide film of the transistor, for example. As long as the material satisfies these conditions, the same effect can be obtained even if the material of the mask material during the gate processing is a film other than the silicon oxide film. The above description regarding the etching gas and the silicon oxide film 30 is the same in the following embodiments.

In the manufacturing method of the first embodiment described above, the laminated film of the silicon oxide film 30 and the polycrystalline silicon film 14 is patterned by the resist pattern 32, but only the silicon oxide film 30 is patterned by the resist pattern 32.
And the polycrystalline silicon film 14, the tungsten silicide film 12, the polycrystalline silicon film 10, the inter-poly insulating film 8, and the polycrystalline silicon film 6 are sequentially etched using the single-layer film of the silicon oxide film 30 as a mask material. Thus, a gate electrode may be formed.

FIG. 11 shows a cross section when the silicon oxide film 30 is patterned by the resist pattern 32 at this time. After the resist pattern 32 is stripped and the gate electrode is processed using the silicon oxide film 30 as a mask, the gate electrode has the same shape as the cross section shown in FIGS. 7A and 7B described above. Here, the method of processing the peripheral circuit region is the same as that of the above-described manufacturing method. After etching up to the polycrystalline silicon film 10, only the peripheral circuit region is covered with a resist. The gate electrode is formed by sequentially etching the inter-poly insulating film 8 and the polycrystalline silicon film 6 in the nonvolatile memory region with the layer film.

When processing the gate electrode, there are two methods, a method using a laminated film of the silicon oxide film 30 and the polycrystalline silicon film 14 as a mask material and a method using a single layer film of the silicon oxide film 30 as a mask material. Although there is no detailed description hereafter, the same applies to the following embodiments described later.

Further, in a second embodiment and later to be described later,
In the description of the method of manufacturing the two-layer gate nonvolatile memory cell, the gate of the transistor in the peripheral circuit region can be processed by the same manufacturing method as that described in the first embodiment. . That is, after depositing the polycrystalline silicon film 6 and the inter-poly insulating film 8 over the entire surface of the semiconductor substrate, the inter-poly insulating film 8 and the polycrystalline silicon film 6 are removed in the peripheral circuit region. When processing the respective gates of the peripheral circuit region and the peripheral circuit region, the processing can be performed simultaneously up to the middle, and the peripheral circuit region can be separately formed by coating the resist with the resist from the middle. Therefore, in the following embodiments, the transistor can be formed in the same manner as in the first embodiment, and the description of the method for manufacturing the transistor in the peripheral circuit region is omitted in both the description and the drawings.

Next, as shown in FIGS. 8A and 8B, for example, n- ions are implanted into the entire surface of the nMOS region on the semiconductor substrate 2 to form an LDD structure in both the nonvolatile memory region and the peripheral circuit region. After forming the diffusion layer 20, the semiconductor substrate 2
Silicon oxide film 18 for sidewall formation on the entire surface
Is deposited.

Further, as shown in FIGS. 9A and 9B, the entire surface of the silicon oxide film 18 is etched back by anisotropic etching to form sidewalls 18.
Immediately before the etching, a silicon oxide film 30 is present on the uppermost layer on the gate electrode. However, in order to perform a large amount of etching with a margin for forming the sidewall,
The silicon oxide film 30 is also etched away at the same time.

One purpose of the polycrystalline silicon film 14 under the silicon oxide film 30 is to serve as a stopper film at the time of etching for forming the sidewalls. The polycrystalline silicon film 14 is effective as a material for this purpose because it can ensure a sufficient etching selectivity with the silicon oxide film 18 as the sidewall material.

In the above description, a silicon oxide film is used as a sidewall material, but a silicon nitride film is generally used as another film. The polycrystalline silicon film can secure a sufficient etching selectivity with respect to the silicon nitride film under ordinary etching gas conditions, so that the same effect can be obtained.

Subsequently, for example, high-concentration n + ion implantation for forming source and drain diffusion layers is performed. In this structure, ion implantation is performed through the polycrystalline silicon film 14. If the high-concentration ion implantation is performed directly on the tungsten silicide film 12, which is a high-melting-point metal silicide film, the high-melting-point metal (here, tungsten) is abnormally oxidized by a slight oxidation process due to the damage. The problem that occurs. However, according to the above-described structure, this problem can be eliminated. This is because the tungsten silicide film 12 is covered with the polycrystalline silicon film 14, so that abnormal oxidation of the tungsten silicide film 12 due to ion implantation can be prevented.

Although not particularly shown in the figure, the ion implantation for forming the n− diffusion layer having the LDD structure and the high concentration n + diffusion layer is performed in the nonvolatile memory region and the peripheral circuit region. As described above, they can be formed simultaneously by injecting them into the entire surface of the nMOS region. Alternatively, different diffusion layers may be formed by performing separate ion implantation on each region, for example, by using a photoresist. This may be performed by a known method, and is not particularly limited in the present invention.

Thereafter, post oxidation is performed on both the nonvolatile memory area and the peripheral circuit area as shown in FIGS. 10 (a) and 10 (b). By the way, when the refractory metal silicide film is oxidized, if the oxidizing agent reaching the refractory metal silicide film surface exceeds the supply speed of silicon, the refractory metal is directly oxidized and causes abnormal volume expansion. The supply of silicon at this time is performed by movement from the tungsten silicide film 12 which is a refractory metal silicide film and movement from the lower polycrystalline silicon film 10. One of them is a silicon supply speed and an oxidation speed. The balance determines whether abnormal oxidation occurs. Abnormal oxidation also occurs when the absolute oxidation amount is large and exceeds the supplyable silicon amount.

In view of such a mechanism, according to the first embodiment, as shown in FIGS. 10A and 10B, one of the polycrystalline silicon films 14 on the tungsten silicide film 12 is formed. The part is oxidized and the silicon oxide film 16
Is formed, but by depositing a film thickness that cannot be completely oxidized, it is possible to prevent the tungsten silicide film 12 from being directly oxidized, and to greatly improve the oxidation amount margin of the process. it can.

Therefore, in the first embodiment,
Although the case where a tungsten silicide film is used as the refractory metal silicide film has been described, a similar effect can be obtained with a gate made of another refractory metal silicide film. Further, in the first embodiment,
As will be understood later, the tungsten silicide film 1
2 is not directly exposed to the oxidizing material and does not oxidize. Therefore, as a material to replace tungsten silicide,
In addition, the same effect can be obtained with a high melting point metal silicide film or a high melting point metal film.

Next, as shown in FIGS. 1A and 1B,
An interlayer insulating film 24 is deposited, a contact hole is opened, an electrode wiring forming step is performed, and a non-volatile memory is manufactured by attaching a passivation film in accordance with a normal semiconductor device manufacturing method.

As described above, according to the first embodiment, the refractory metal silicide film (here, tungsten silicide film) constituting the gate having the polycide structure is used.
By providing a laminated film of a polycrystalline silicon film and a silicon oxide film on the film surface of the above, it is possible to prevent the tungsten silicide film constituting the gate of the polycide structure from being abnormally oxidized during high-concentration ion implantation. Further, since a polycrystalline silicon film having a sufficient film thickness is formed on the tungsten silicide film, abnormal oxidation of the tungsten silicide film can be prevented even in the post-oxidation step.

Further, using a silicon oxide film as a mask material,
A gate electrode having a high aspect ratio can be easily processed, and the polycrystalline silicon film can have a function of a stopper film when a sidewall is formed thereafter.

When a silicon nitride film (SiN film) is used as the stopper film, there is a problem that the film quality of the gate oxide film is degraded due to film stress. However, as in this embodiment, a polycrystalline silicon film is used. The problem that the film quality of the gate oxide film is degraded due to the small film stress can be eliminated by using.

Although omitted in the above description of the manufacturing method, when an electrode wiring is connected to the gate, a contact hole must be formed on the polycrystalline silicon film 14 described in the first embodiment. become. Therefore, it is necessary that the polycrystalline silicon film 14 be doped with impurities in the final step and be a low resistance layer. The impurity concentration at this time may be 1 × 10 ¹⁹ cm ⁻³ or more. This is the same in the following embodiments.

In the first embodiment, the case where the uppermost silicon oxide film 30 on the gate electrode is simultaneously etched and removed by the etch back for forming the sidewalls has been described. However, the amount of over-etching is relatively small, and the silicon oxide film 30 may remain after the etch back. This case will be described below.

FIG. 12 is a cross-sectional view showing a case where the silicon oxide film 30 remains after the etch back at the time of forming the sidewall in the first embodiment.
FIG. FIG. 12 shows only the nonvolatile memory area.

As shown in FIG. 12, the polycrystalline silicon film 1
The silicon oxide film 30 whose thickness has been reduced by the etch-back remains on 4. Thereafter, when post-oxidation is performed, the oxidant reaches the interface of the polycrystalline silicon film 14 through the thin silicon oxide film 30, and the polycrystalline silicon film 1
4 is slightly oxidized, but also in this case, the polycrystalline silicon film 14 has a capability of preventing abnormal oxidation of the tungsten silicide film 12 as in the first embodiment.

FIG. 13 shows a cross section after the final step in this case, that is, a cross section corresponding to FIG. This FIG.
In the above, the silicon oxide film 30a is a film in which the silicon oxide film 30 contains an oxidative growth component by post-oxidation. Also in this case, the tungsten silicide film 12 is not directly exposed to the oxidizing agent and is not oxidized. Therefore, the same effect can be obtained by using another high melting point metal silicide film or a high melting point metal film as a material replacing the tungsten silicide film 12.

[Second Embodiment] Next, a method of manufacturing a nonvolatile memory according to a second embodiment of the present invention will be described.

In the first embodiment, the side wall is formed after the gate processing, and the post-oxidation is performed thereafter. In the second embodiment, the post-oxidation is performed before the formation of the side wall. .

The steps up to the gate processing are the same as those in the first embodiment, and are shown in FIGS. 2 (a) and 2 (b) to 7 (a).
The process is as shown in FIG. As mentioned above,
The method of manufacturing the elements in the peripheral circuit region is the same as in the first embodiment, and a description thereof will be omitted.

First, as shown in FIGS. 2A and 2B, an element isolation oxide film (not shown) is formed in a desired region on the semiconductor substrate 2 by a well-known method in both the nonvolatile memory region and the peripheral circuit region. Is formed, a gate insulating film 4 made of a silicon oxide film is formed. Further, a polycrystalline silicon film 6 serving as a floating gate is deposited on the gate insulating film 4.

Subsequently, although not shown in the figure, after the polycrystalline silicon film 6 is separated on the element isolation oxide film according to a normal method of manufacturing a two-layer gate type nonvolatile memory, the
An r-Poly insulating film (for example, ONO film) 8 is deposited on the entire surface.

Next, as shown in FIGS. 3A and 3B,
Only the non-volatile memory area is covered with the resist pattern 28 by photolithography, and the inter-Po
ly insulating film 8, polycrystalline silicon film 6, and gate insulating film 4
Are sequentially etched and removed. After stripping the resist pattern 28, as shown in FIG. 4B, the gate insulating film 2 for the transistor is formed in the peripheral circuit region by, for example, a thermal oxidation method.
6 is formed. At this time, the non-volatile memory area is
The poly insulating film 8 is exposed, and its surface is slightly oxidized.

Thereafter, in the nonvolatile memory area, FIG.
As shown in FIG. 1A, a polycrystalline silicon film 10 forming a control gate, a refractory metal silicide film such as a tungsten silicide film 12, and a polycrystalline silicon film 1 are formed.
4, and a silicon oxide film 30 are sequentially deposited from below. In the same process, in the peripheral circuit region, as shown in FIG. 4B, a polycrystalline silicon film 10 forming a gate electrode and a refractory metal silicide film such as a tungsten silicide film 12, a polycrystalline silicon film 14, And silicon oxide film 3
0 are sequentially deposited from the bottom.

The polycrystalline silicon film 14 has such a thickness that the polycrystalline silicon film 14 is not oxidized in the etching and oxidizing steps at the time of forming sidewalls 18 described later. For example, the polycrystalline silicon film 14 has a thickness of 50 nm to 300 n.
m (here, 50 nm). Further, the silicon oxide film 30 has a thickness that does not disappear during the processing of a gate described later. Here, for example, the silicon oxide film 30 is formed to a thickness of about 200 nm.

As is clear from FIGS. 4A and 4B, the gate electrode of the peripheral transistor in the peripheral circuit region is formed of the same film as the control gate electrode of the memory cell in the nonvolatile memory region. I have. That is, the gate electrode of the peripheral transistor is formed of a laminated film including the polycrystalline silicon film 10, the tungsten silicide film 12, and the polycrystalline silicon film 14.

Next, a resist is applied, and a desired resist pattern 32 is formed in both the nonvolatile memory area and the peripheral circuit area as shown in FIGS. 5A and 5B.
The silicon oxide film 30 and the polycrystalline silicon film 14 are etched. Thereafter, the resist pattern 32 is removed, and FIG.
As shown in (a) and (b), the tungsten silicide film 12 and the polycrystalline silicon film 10 are sequentially etched using the stacked film of the silicon oxide film 30 and the polycrystalline silicon film 14 as a mask.

Subsequently, as shown in FIGS. 7A and 7B, only the peripheral circuit area is covered with the resist pattern 34.
The non-volatile memory area is exposed, and the stacked film of the silicon oxide film 30 and the polycrystalline silicon film 14 is used as a mask.
The poly insulating film 8 and the polycrystalline silicon film 6 are sequentially etched to form a gate electrode. The steps up to the step of processing the gate as described above are the same as in the first embodiment, and have a shape as shown in FIG.

Next, after removing the resist pattern 34, post oxidation is performed as shown in FIG. At this time, if the oxidation amount due to the post-oxidation is relatively large, the oxidizing material may penetrate through the silicon oxide film 30 and oxidize a part of the polycrystalline silicon film 14. Since the polycrystalline silicon film 14 and the silicon oxide film 30 are deposited, the tungsten silicide film 12 is not oxidized except on its side.

FIG. 14 is a sectional view showing the structure of the nonvolatile memory area after the post-oxidation. As shown in FIG. 14, the side surface of the gate electrode is oxidized and a silicon oxide film 36 is formed.
Is formed. In this case, the tungsten silicide film 1
2 is oxidized. For example, in a device of a generation in which the thickness of the tungsten silicide film 12 is about 100 nm, the amount of post-oxidation is generally at most 10 nm on the wafer.
It is about 20 nm. In the case of such an oxidized amount, the tungsten silicide film 1 is formed as in the second embodiment.
A polycrystalline silicon film 1 serving as a silicon supply source above and below 2
If the structure is formed such that the tungsten silicide film 12 is exposed to the oxidizing atmosphere, only a small area of the side surface of the gate is required. it can.

Next, for example, n-ion implantation is performed on the entire surface to form a diffusion layer 20 having an LDD structure as shown in FIG. 15, and then a silicon oxide film 18 for forming a sidewall is deposited. Further, as shown in FIG. 16, the entire surface of the silicon oxide film 18 is etched back by anisotropic etching to form sidewalls 18. Also in the second embodiment, similar to the first embodiment,
The polycrystalline silicon film 14 plays a role as a stopper film at the time of etching for forming the sidewall.

Subsequently, for example, high-concentration n + ion implantation for forming source and drain diffusion layers is performed. On the tungsten silicide film 12, as shown in FIG.
Since the tungsten silicide film 12 is covered with the polycrystalline silicon film 14, abnormal oxidation of the tungsten silicide film 12 due to ion implantation can be prevented.

Thereafter, as shown in FIG. 17, an interlayer insulating film 24 is deposited, a contact hole is opened, an electrode wiring forming step is performed, and a passivation film is formed according to a normal method of manufacturing a nonvolatile semiconductor memory. The manufacture of the nonvolatile memory is the same as that of the first embodiment.

As described above, according to the second embodiment, a refractory metal silicide film (here, a tungsten silicide film) constituting a gate having a polycide structure is used.
By providing a laminated film of a polycrystalline silicon film and a silicon oxide film on the film surface of the above, it is possible to prevent the tungsten silicide film constituting the gate of the polycide structure from being abnormally oxidized during high-concentration ion implantation. Further, since a polycrystalline silicon film having a sufficient film thickness is formed on the tungsten silicide film, abnormal oxidation of the tungsten silicide film can be prevented even in the post-oxidation step.

Further, using a silicon oxide film as a mask material,
A gate electrode having a high aspect ratio can be easily processed, and the polycrystalline silicon film can have a function of a stopper film when a sidewall is formed thereafter.

When a silicon nitride film is used as the stopper film, there is a problem that the film quality of the gate oxide film is degraded due to film stress. However, if a polycrystalline silicon film is used as in this embodiment, the film becomes thin. The problem that the film quality of the gate oxide film is deteriorated due to small stress can be eliminated.

In the first embodiment, post-oxidation is performed after forming a sidewall after gate processing.
In the second embodiment, after gate processing, post oxidation is performed, and then sidewalls are formed. In any of the embodiments, the effect of preventing abnormal oxidation of the tungsten silicide film by forming the polycrystalline silicon film 14 on the tungsten silicide film 12 constituting the gate having the polycide structure is the same.

[Third Embodiment] Next, a method for manufacturing a nonvolatile memory according to a third embodiment of the present invention will be described. In the second embodiment, the side wall is formed after the post-oxidation is performed after the gate processing. In the third embodiment, after the gate processing step, the post-oxidation step, and the side wall forming step, Further, a manufacturing method in the order of steps for performing post-oxidation will be described. Also in this case, the steps from the gate processing to the post-oxidation to form the sidewalls are the same as those in the second embodiment, and the following steps are performed.

The steps up to the gate processing are the same as those in the first embodiment, and are shown in FIGS. 2 (a) and 2 (b) to 7 (a).
The process is as shown in FIG. As mentioned above,
The method of manufacturing the elements in the peripheral circuit region is the same as in the first embodiment, and a description thereof will be omitted.

First, as shown in FIGS. 2A and 2B, an element isolation oxide film (not shown) is formed in a desired region on the semiconductor substrate 2 by a well-known method in both the nonvolatile memory region and the peripheral circuit region. Is formed, a gate insulating film 4 made of a silicon oxide film is formed. Further, a polycrystalline silicon film 6 serving as a floating gate is deposited on the gate insulating film 4. Subsequently, although not shown in the figure, the polycrystalline silicon film 6 is separated on the element isolation oxide film according to a normal method of manufacturing a two-layer gate nonvolatile memory,
A ter-Poly insulating film (for example, ONO film) 8 is deposited on the entire surface.

Next, as shown in FIGS. 3A and 3B,
Only the non-volatile memory area is covered with the resist pattern 28 by photolithography, and the inter-Po
ly insulating film 8, polycrystalline silicon film 6, and gate insulating film 4
Are sequentially etched and removed. After stripping the resist pattern 28, as shown in FIG. 4B, the gate insulating film 2 for the transistor is formed in the peripheral circuit region by, for example, a thermal oxidation method.
6 is formed. At this time, the non-volatile memory area is
The poly insulating film 8 is exposed, and its surface is slightly oxidized.

Thereafter, in the non-volatile memory area, FIG.
As shown in FIG. 1A, a polycrystalline silicon film 10 forming a control gate, a refractory metal silicide film such as a tungsten silicide film 12, and a polycrystalline silicon film 1 are formed.
4, and a silicon oxide film 30 are sequentially deposited from below. In the same process, in the peripheral circuit region, as shown in FIG. 4B, a polycrystalline silicon film 10 forming a gate electrode and a refractory metal silicide film such as a tungsten silicide film 12, a polycrystalline silicon film 14, And silicon oxide film 3
0 are sequentially deposited from the bottom.

The polycrystalline silicon film 14 has such a thickness that the polycrystalline silicon film 14 is not oxidized in the etching and oxidizing steps at the time of forming the sidewalls 18 described later. For example, the polycrystalline silicon film 14 has a thickness of 50 nm to 300 n.
m (here, 50 nm). Further, the silicon oxide film 30 has a thickness that does not disappear during the processing of a gate described later. Here, for example, the silicon oxide film 30 is formed to a thickness of about 200 nm.

As is clear from FIGS. 4A and 4B, the gate electrode of the peripheral transistor in the peripheral circuit region is formed of the same film as the control gate electrode of the memory cell in the nonvolatile memory region. I have. That is, the gate electrode of the peripheral transistor is formed of a laminated film including the polycrystalline silicon film 10, the tungsten silicide film 12, and the polycrystalline silicon film 14.

Next, a resist is applied, and a desired resist pattern 32 is formed on both the nonvolatile memory area and the peripheral circuit area as shown in FIGS. 5A and 5B.
The silicon oxide film 30 and the polycrystalline silicon film 14 are etched. Thereafter, the resist pattern 32 is removed, and FIG.
As shown in (a) and (b), the tungsten silicide film 12 and the polycrystalline silicon film 10 are sequentially etched using the stacked film of the silicon oxide film 30 and the polycrystalline silicon film 14 as a mask.

Subsequently, as shown in FIGS. 7A and 7B, only the peripheral circuit area is covered with the resist pattern 34.
The non-volatile memory area is exposed, and the stacked film of the silicon oxide film 30 and the polycrystalline silicon film 14 is used as a mask.
The poly insulating film 8 and the polycrystalline silicon film 6 are sequentially etched to form a gate electrode. The steps up to the step of processing the gate as described above are the same as in the first embodiment, and have a shape as shown in FIG.

Next, until the side wall is formed by performing post-oxidation, it is the same as the second embodiment.
The process is as shown in FIGS.

First, after the resist pattern 34 is peeled off, post oxidation is performed as shown in FIG. At this time, if the oxidation amount due to the post-oxidation is relatively large, the oxidizing material may penetrate through the silicon oxide film 30 and oxidize a part of the polycrystalline silicon film 14. Since the polycrystalline silicon film 14 and the silicon oxide film 28 are deposited, the tungsten silicide film 12 is not oxidized except on its side.

FIG. 14 is a sectional view showing the structure of the nonvolatile memory area after the post-oxidation. As shown in FIG. 14, the side surface of the gate electrode is oxidized and a silicon oxide film 36 is formed.
Is formed. In this case, the tungsten silicide film 1
2 is oxidized. For example, in a device of a generation in which the thickness of the tungsten silicide film 12 is about 100 nm, the amount of post-oxidation is generally at most 10 nm on the wafer.
It is about 20 nm. In the case of such an oxidized amount, the tungsten silicide film 1 is formed as in the second embodiment.
A polycrystalline silicon film 1 serving as a silicon supply source above and below 2
If the structure is formed such that the tungsten silicide film 12 is exposed to the oxidizing atmosphere, only a small area of the side surface of the gate is required. it can.

Next, for example, n-ions are implanted on the entire surface to form a diffusion layer 20 having an LDD structure as shown in FIG. 15, and then a silicon oxide film 18 for forming a sidewall is deposited. Further, as shown in FIG. 16, the entire surface of the silicon oxide film 18 is etched back by anisotropic etching to form sidewalls 18. Also in the third embodiment, similar to the first embodiment,
The polycrystalline silicon film 14 plays a role as a stopper film at the time of etching for forming the sidewall.

Subsequently, for example, high-concentration n + ion implantation for forming source and drain diffusion layers is performed. On the tungsten silicide film 12, as shown in FIG.
Since the tungsten silicide film 12 is covered with the polycrystalline silicon film 14, abnormal oxidation of the tungsten silicide film 12 due to ion implantation can be prevented.

Next, post oxidation is performed on the semiconductor substrate shown in FIG. By this post-oxidation, as shown in FIG. 18, a part of polycrystalline silicon film 14 is oxidized to form oxide film 16. The silicon oxide film 22 is a silicon oxide film similarly formed on the surface of the semiconductor substrate 2 by post-oxidation. Also in this case, the polycrystalline silicon film 14 has a capability of preventing abnormal oxidation of the tungsten silicide film 12 as in the above-described embodiment. FIG. 18 is a cross-sectional view after the final step in this case, that is, a cross-sectional view corresponding to FIG.

Also in this case, the tungsten silicide film 12 is not directly exposed to the oxidizing agent and is not oxidized. Therefore, as a material replacing the tungsten silicide film 12, other refractory metal silicide films,
The same effect can be obtained even with a high melting point metal film.

Thereafter, as shown in FIG. 18, an interlayer insulating film 24 is deposited, a contact hole is opened, an electrode wiring forming step is performed, and a passivation film is deposited according to a normal method of manufacturing a nonvolatile semiconductor memory. The method of manufacturing the nonvolatile memory by the same method as in the first and second embodiments is described.

As described above, according to the third embodiment, a refractory metal silicide film (here, a tungsten silicide film) constituting a gate having a polycide structure.
By providing a laminated film of a polycrystalline silicon film and a silicon oxide film on the film surface of the above, it is possible to prevent the tungsten silicide film constituting the gate of the polycide structure from being abnormally oxidized during high-concentration ion implantation. Further, since a polycrystalline silicon film having a sufficient film thickness is formed on the tungsten silicide film, abnormal oxidation of the tungsten silicide film can be prevented even in the post-oxidation step.

Further, using a silicon oxide film as a mask material,
A gate electrode having a high aspect ratio can be easily processed, and the polycrystalline silicon film can have a function of a stopper film when a sidewall is formed thereafter.

In the case where a silicon nitride film is used as the stopper film, there is a problem that the film quality of the gate oxide film is deteriorated due to film stress. However, if a polycrystalline silicon film is used as in this embodiment, The problem that the film quality of the gate oxide film is degraded due to small film stress can be eliminated.

In any of the first, second and third embodiments, the polycrystalline silicon film 14 is formed on the tungsten silicide film 12 constituting the gate of the polycide structure, so that the tungsten silicide film 12 The effect of preventing abnormal oxidation is the same. Note that the same effects as those of the embodiments can be obtained even if a post-oxidation step is further added or the order becomes complicated.

[Fourth Embodiment] Next, a method for manufacturing a nonvolatile memory according to a fourth embodiment of the present invention will be described.

FIGS. 2 to 6 and FIGS. 19 to 28 are cross-sectional views of respective manufacturing steps showing a method of manufacturing the nonvolatile memory according to the fourth embodiment.

After an element isolation oxide film (not shown) is formed on semiconductor substrate 2 in accordance with a normal semiconductor device manufacturing method, gate insulating film 4 made of a silicon oxide film is formed. Further, on the gate insulating film 4, a polycrystalline silicon film 6 serving as a floating gate, an inter-poly insulating film (for example, an ONO film) 8, a polycrystalline silicon film 10 serving as a control gate, and a refractory metal silicide film, for example, Tungsten silicide film 12, polycrystalline silicon film 1
4, and a silicon oxide film 30 are sequentially deposited from below. After that, the gate made of these laminated films is processed. The manufacturing method up to this point is the same as in the first to third embodiments, and FIG. 19 shows a cross section of the nonvolatile memory area after the end of the manufacturing steps up to this point.

Subsequently, in order to form a source diffusion layer, FIG.
As shown in FIG. 0, a part of the strip-shaped element isolation oxide film 38 is removed. FIG. 20 is a view corresponding to the plan view of the semiconductor device shown in FIG. 19, and shows a step immediately after a resist pattern 40 is newly applied after gate processing. The region of the silicon oxide film 30 shown in FIG. 20 shows a gate pattern formed of the laminated film after the gate processing.

The resist pattern 40 is a pattern used in a SAS (Self-Align-Source) process for forming a source diffusion layer, and is formed by a photolithography method using the resist pattern 40 as a mask as shown in FIG. Then, a region to be a source diffusion layer between adjacent gates is exposed. FIG. 21 is a cross-sectional view taken along the line X1-X1 'in FIG. 20, and is the same cross-section as FIG.

In this manner, the element isolation oxide film 38 is etched in a self-aligned manner by covering the region serving as the drain with the resist pattern 40 and using the gate of the laminated film having the silicon oxide film 30 as the uppermost layer as a mask. Subsequently, as shown in FIGS. 22 and 23, after part of the element isolation oxide film 38 is removed by etching, the source and drain diffusion layers 20 are formed. In particular, FIG. 23 is a view showing a portion where a source diffusion layer is formed in a subsequent step after a part of an element isolation oxide film is removed by etching in a SAS step, and FIGS. X1-X1 ',
It is sectional drawing when cut | disconnected by X2-X2 '.

In this SAS step, FIGS.
As shown in (1), in any region, of the silicon oxide film 30 which is a mask material at the time of gate processing, regions not covered with the resist pattern 40 are simultaneously etched and removed. At this time, the polycrystalline silicon film 14 under the silicon oxide film 30 is processed by using an etching gas set under a condition that gives a normal high selectivity to silicon.
As a stopper film at the time of etching, the gate insulating film 4
Then, the element isolation oxide film 38 is etched into a desired shape.

Thereafter, high-concentration ion implantation with a dose of about 1.0 × 10 ¹⁵ cm ⁻² or more is performed to form source and drain diffusion layers. Also in this embodiment, since this ion implantation is performed through the polycrystalline silicon film 14, abnormal oxidation of the tungsten silicide film constituting the gate having the polycide structure can be prevented.

Subsequently, a silicon oxide film for forming a sidewall is deposited on the entire surface, and as shown in FIG. 24, the silicon oxide film is etched back by anisotropic etching. As a result, sidewalls 18 are formed on the side surfaces of the gate. Immediately before the anisotropic etching, the silicon oxide film 30 or the polycrystalline silicon film 14 exists in the uppermost layer of the gate.
Functions as a stopper film during etching. In addition,
FIG. 24 shows the same cross section as FIG.

At this time, the silicon oxide film 30 is also removed by etching at the same time.
Since a sufficient etching selectivity can be secured with respect to the silicon oxide film as the material of the side wall 18, it is effective as a material for this purpose.

In the above description, a silicon oxide film is used as a sidewall material, but a silicon nitride film is generally used as another film. Even in this case, since the polycrystalline silicon film can secure a sufficient processing selectivity with respect to the silicon nitride film under ordinary etching gas conditions, the same effect can be expected.

Further, in the above description, the high-concentration ion implantation for forming the source and drain diffusion layers is performed immediately after the SAS processing step. However, there is no problem if the high-concentration ion implantation is performed after the formation of the sidewall. Alternatively, the source and the drain may be separately ion-implanted. Again,
Since the ion implantation is performed through the polycrystalline silicon film 14, abnormal oxidation of the tungsten silicide film constituting the gate having the polycide structure can be prevented.

Thereafter, post oxidation is performed on the semiconductor substrate shown in FIG. By this post-oxidation, as shown in FIG. 25, a part of polycrystalline silicon film 14 is oxidized to form silicon oxide film 16. The silicon oxide film 22 is a silicon oxide film similarly formed on the surface of the semiconductor substrate 2 by post-oxidation. However, by depositing such a thickness that the entire polycrystalline silicon film 14 is not oxidized, the tungsten silicide film 12 which is a high-melting metal silicide film under the polycrystalline silicon film 14 is directly oxidized. Therefore, the oxidation margin of the process can be greatly improved.

Thereafter, as shown in FIG. 26, after depositing an interlayer insulating film 24, a contact hole is opened in accordance with a normal semiconductor device manufacturing method, and an electrode wiring forming step is performed.
A non-volatile memory is manufactured by depositing a passivation film.

As described above, according to the fourth embodiment, the refractory metal silicide film (here, tungsten silicide film) constituting the gate having the polycide structure is used.
By providing a laminated film of a polycrystalline silicon film and a silicon oxide film on the film surface of the above, a tungsten silicide film constituting a gate of a polycide structure can be formed at the time of high-concentration ion implantation for forming a source diffusion layer after SAS processing. Abnormal oxidation can be prevented. Further, since a polycrystalline silicon film having a sufficient film thickness is formed on the tungsten silicide film, abnormal oxidation of the tungsten silicide film can be prevented even in the post-oxidation step.

Further, using a silicon oxide film as a mask material,
A gate electrode having a high aspect ratio can be easily processed, and the polycrystalline silicon film can have a function of a stopper film when a sidewall is formed thereafter.

When a silicon nitride film is used as the stopper film, there is a problem that the film quality of the gate oxide film is degraded due to film stress. However, when a polycrystalline silicon film is used as in this embodiment, the film becomes thin. The problem that the film quality of the gate oxide film is deteriorated due to small stress can be eliminated.

According to the fourth embodiment, the structure is such that a polycrystalline silicon film is formed on a tungsten silicide film which is a high melting point metal silicide film.
Since the tungsten silicide film is not directly oxidized, the oxidation margin of the process can be greatly improved.

Further, the polycrystalline silicon film on the tungsten silicide film, which is a refractory metal silicide film,
It has a function as a stopper film at the time of etching in the SAS step, a stopper film at the time of etching in the sidewall formation step, and an abnormal oxidation prevention film in the post-oxidation step. Therefore, it is important that the film has a thickness enough to remain as a residual film in anticipation of a decrease in the film thickness in each step.

As described above, the polycrystalline silicon film formed on the refractory metal silicide film does not cause deterioration of the gate oxide film as in the case of the silicon nitride film (SiN film). At the same time as being used as a stopper film at the time of etching, it functions as a damage protection film (prevention of abnormal oxidation) at the time of subsequent ion implantation for forming a diffusion layer. Further, it also has a function of a stopper film at the time of etching in a subsequent sidewall formation step, and has an effect of improving a post-oxidation margin by covering the surface of the refractory metal silicide film.

In the fourth embodiment, the case where the silicon oxide film 30 at the uppermost layer of the gate is simultaneously etched and removed in the etch back for forming the sidewalls has been described. However, the over-etching amount may be relatively small, and the silicon oxide film 30 may remain after the etch back. FIG. 24 in this case
27 is shown in FIG.

Thereafter, post oxidation is performed. In this case as well, the polycrystalline silicon film 14 has the ability to prevent abnormal oxidation in the same manner as in the first to third embodiments. FIG. 28 shows a cross section after the final step in this case, that is, a cross section corresponding to FIG. In FIG. 28, the silicon oxide film 30a is a film in which the silicon oxide film 30 contains an oxidized and multiplied portion by post-oxidation. The silicon oxide film 22 is a silicon oxide film similarly formed on the surface of the semiconductor substrate 2 by post-oxidation.

Note that, in the fourth embodiment as well,
The tungsten silicide film, which is a refractory metal silicide film, is not directly exposed to the oxidizing material and is not oxidized. Therefore, the same effect can be obtained by using a high melting point metal film other than the high melting point metal silicide film.

[Fifth Embodiment] Next, a method for manufacturing a nonvolatile memory according to a fifth embodiment of the present invention will be described. In the fourth embodiment, the sidewall is formed after the SAS step, and post-oxidation is performed thereafter. In the fifth embodiment, the post-oxidation is performed after the SAS step, and the sidewall is formed thereafter. A manufacturing method in the order of steps will be described.

FIGS. 2 to 6, FIGS. 19 to 21, and FIGS. 29 to 34 are cross-sectional views of respective manufacturing steps showing a method of manufacturing the nonvolatile memory according to the fifth embodiment.

The steps up to the gate processing are the same as those in the first embodiment, and are steps as shown in FIGS. 2 to 6 and FIG. As described above, since the method of manufacturing the element in the peripheral circuit region is the same as in the first embodiment,
Description is omitted.

First, after a device isolation oxide film (not shown) is formed in a desired region on the semiconductor substrate 2 by a known method, a gate insulating film 4 made of a silicon oxide film is formed. Further, a polycrystalline silicon film 6 serving as a floating gate is deposited on the gate insulating film 4. continue,
Although not shown in the figure, after the polycrystalline silicon film 6 is separated on the element isolation oxide film according to the usual method of manufacturing a two-layer gate type nonvolatile memory, an Inter-Poly insulating film (for example, ON
O film) 8, a polycrystalline silicon film 10 forming a control gate, and a refractory metal silicide film such as a tungsten silicide film 12, a polycrystalline silicon film 14, and a silicon oxide film 30 are sequentially deposited from below. The polycrystalline silicon film 14 has such a thickness that the polycrystalline silicon film 14 is not oxidized in the etching and oxidizing steps in the later-described SAS step and sidewall formation. Also, the silicon oxide film 30
Has a film thickness that does not disappear during gate processing described later.

Next, after applying a resist to form a desired resist pattern, the silicon oxide film 30 and the polycrystalline silicon film 14 are etched. Thereafter, the resist pattern is removed, and the tungsten silicide film 12, the polycrystalline silicon film 10, the Inter-Poly insulating film 8, and the polycrystalline silicon film 6 are sequentially formed using the laminated film of the silicon oxide film 30 and the polycrystalline silicon film 14 as a mask. Etching is performed to form a gate electrode. Then, S is formed for forming a source diffusion layer.
An AS process is performed to etch the element isolation region.
Subsequently, the process is the same as that of the fourth embodiment up to the point where high-concentration ion implantation for forming a diffusion layer is performed. FIG. 29 shows a cross section of the semiconductor device after the steps up to here.

Next, post oxidation is performed on the semiconductor device shown in FIG. As a result of this post-oxidation, as shown in FIG. 30, a part of the polycrystalline silicon film 14 including the silicon oxide film 30 covering a part of the polycrystalline silicon 14 is oxidized. A silicon oxide film 22 is formed. At this time, since the polycrystalline silicon film 14 is formed on the tungsten silicide film 12, the upper surface of the tungsten silicide film 12 can be prevented from being oxidized.

In this case, the tungsten silicide film 12
Is oxidized, for example, in a device of the generation in which the thickness of the tungsten silicide film 12 is about 100 nm, the post-oxidation amount is generally at most 10 nm on the wafer.
About 20 nm. In the case of such an oxidation amount, as in the fifth embodiment, the structure may be such that the polycrystalline silicon films 14 and 10 serving as a silicon supply source are formed above and below the tungsten silicide film 12. Since the tungsten silicide film 12 is exposed to the oxidizing atmosphere only in a small area on the side surface of the gate, abnormal oxidation of the tungsten silicide film 12 can be prevented.

Next, for example, a silicon oxide film for forming a sidewall is deposited on the entire surface, and as shown in FIG. 31, the silicon oxide film is etched back by anisotropic etching to form a sidewall 18. I do. Also in the fifth embodiment, similarly to the fourth embodiment, the polycrystalline silicon film 14 functions as a stopper film at the time of etching for forming a sidewall. At this time, a part of the silicon oxide film 22 remains unless the etching amount is sufficiently large.

Thereafter, as shown in FIG. 32, after depositing an interlayer insulating film 24, a contact hole is opened in accordance with a normal semiconductor device manufacturing method, and an electrode wiring forming step is performed.
A non-volatile memory is manufactured by depositing a passivation film. This is the same as in the above embodiment.

As described above, according to the fifth embodiment, a refractory metal silicide film (here, a tungsten silicide film) constituting a gate having a polycide structure.
By providing a laminated film of a polycrystalline silicon film and a silicon oxide film on the film surface of the above, a tungsten silicide film constituting a gate of a polycide structure can be formed at the time of high-concentration ion implantation for forming a source diffusion layer after SAS processing. Abnormal oxidation can be prevented. Further, since a polycrystalline silicon film having a sufficient film thickness is formed on the tungsten silicide film, abnormal oxidation of the tungsten silicide film can be prevented even in the post-oxidation step.

Further, using a silicon oxide film as a mask material,
A gate electrode having a high aspect ratio can be easily processed, and the polycrystalline silicon film has a function of a stopper film at the time of etching in a SAS process and a function of a stopper film at the time of etching in a subsequent sidewall formation process. Can be provided.

In the case where a silicon nitride film is used as the stopper film, there is a problem that the film quality of the gate oxide film is deteriorated by film stress. However, when a polycrystalline silicon film is used as in this embodiment, the film becomes thin. The problem that the film quality of the gate oxide film is deteriorated due to small stress can be eliminated.

According to the fifth embodiment, the structure is such that the polycrystalline silicon film is formed on the tungsten silicide film, which is a high melting point metal silicide film.
Since the tungsten silicide film is not directly oxidized, the oxidation margin of the process can be greatly improved.

As described above, in the fifth embodiment, similarly to the fourth embodiment, the polycrystalline silicon film formed immediately above the polycide gate is a silicon hydride film (SiN The film is used as a stopper film at the time of etching at the time of the SAS process without causing the deterioration of the gate oxide film as in the case of the film of FIG. Functions as antioxidant).

In the above description, the case where the silicon oxide film 22 remains when the side wall is formed has been described. However, the silicon oxide film 22 may be entirely removed by increasing the amount of etching excessively. FIG. 33 shows a cross section corresponding to FIG. 31 in this case. FIG. 32
34 is shown in FIG. Also in this case, the etching in the sidewall formation step can be stopped at the polycrystalline silicon film 14.

[Sixth Embodiment] Next, a method of manufacturing a nonvolatile memory according to a sixth embodiment of the present invention will be described. In the above-described fourth embodiment, post-oxidation is performed after forming the sidewalls after the SAS processing. On the other hand, in the fifth embodiment, the sidewall is formed after the post-oxidation after the SAS processing, but in any of the embodiments, the sidewall is formed on the tungsten silicide film 12 forming the gate of the polycide structure. The effect of preventing abnormal oxidation of tungsten silicide film 12 by forming crystalline silicon film 14 is the same.

In the sixth embodiment, a description will be given of a manufacturing process in the order of performing a post-oxidation process, a sidewall forming process, and a post-oxidation process after the SAS processing. Also in this case, the steps from the SAS processing to the post-oxidation to form the sidewalls are the same as in the fifth embodiment, and are as shown in FIG. FIG. 35 shows a cross section when post oxidation is performed in addition to this. As a result of this post-oxidation, as shown in FIG. 35, a silicon oxide film 22a is formed on the polycrystalline silicon film 14 in which the silicon oxide film 22 contains an oxidized growth component.

As described above, according to the sixth embodiment, a refractory metal silicide film (here, a tungsten silicide film) constituting a gate having a polycide structure.
By providing a laminated film of a polycrystalline silicon film and a silicon oxide film on the film surface of the above, a tungsten silicide film constituting a gate of a polycide structure can be formed at the time of high-concentration ion implantation for forming a source diffusion layer after SAS processing. Abnormal oxidation can be prevented. Further, since a polycrystalline silicon film having a sufficient film thickness is formed on the tungsten silicide film, abnormal oxidation of the tungsten silicide film can be prevented even in the post-oxidation step.

Further, using a silicon oxide film as a mask material,
A gate electrode having a high aspect ratio can be easily processed, and the polycrystalline silicon film has a function of a stopper film at the time of etching in a SAS process and a function of a stopper film at the time of etching in a subsequent sidewall formation process. Can be provided.

In the case where a silicon nitride film is used as the stopper film, there is a problem that the film quality of the gate oxide film is deteriorated due to film stress. However, if a polycrystalline silicon film is used as in this embodiment, the film becomes thin. The problem that the film quality of the gate oxide film is deteriorated due to small stress can be eliminated.

According to the sixth embodiment, the structure is such that the polycrystalline silicon film is formed on the tungsten silicide film which is a high melting point metal silicide film.
Since the tungsten silicide film is not directly oxidized, the oxidation margin of the process can be greatly improved.

As described above, in the sixth embodiment, similarly to the fourth and fifth embodiments, the polycrystalline silicon film formed on the upper surface of the gate having the polycide structure is made of silicon nitride. It is used as an etching stopper film at the time of a SAS process without causing deterioration of a gate oxide film like a ride film (SiN film).
Subsequently, it functions as a damage protection film (abnormal oxidation prevention) at the time of ion implantation for forming a diffusion layer. Furthermore, the same effects as those of the fourth to sixth embodiments can be obtained even when the position of the post-oxidation step is changed or added.

[Seventh Embodiment] Next, a description will be given of a two-layer gate nonvolatile memory which is a semiconductor device according to a seventh embodiment of the present invention.

FIGS. 36 to 40 are cross-sectional views of respective manufacturing steps showing a method of manufacturing a semiconductor device according to the seventh embodiment.
First, the structure of the semiconductor device according to the seventh embodiment will be described with reference to FIG.

As shown in FIG. 40, a gate insulating film 84 made of a silicon oxide film is formed on a semiconductor substrate 82. On the gate insulating film 84, a polycrystalline silicon film 86 serving as a floating gate, an Inter-Poly insulating film (for example, ONO film) 88, a polycrystalline silicon film 90 serving as a control gate, and a refractory metal silicide film such as tungsten A silicide (WSi) film 92 is sequentially formed from below. Further, the tungsten silicide film 9
A polycrystalline silicon film 94 and a silicon oxide film 96 are sequentially formed on the upper part 2 from below. The gate is configured as described above.

On the side surface from the polycrystalline silicon film 86 to the silicon oxide film 96, a side wall 98 made of a silicon oxide film is formed. Source and drain diffusion layers 100 are formed in the semiconductor substrate 82 on both sides of such a gate. Further, a silicon oxide film 102 is formed on the semiconductor substrate 82 excluding the gate,
An interlayer insulating film 104 is formed so as to cover the entire surface of the semiconductor substrate 82. Note that the polycrystalline silicon film 94 is
Another silicon film such as an amorphous silicon film may be used.

Next, a method of manufacturing the semiconductor device according to the seventh embodiment will be described.

First, as shown in FIG.
After a device isolation oxide film (not shown) is formed in a desired region on the substrate 2 by a known method, a gate insulating film 84 made of a silicon oxide film is formed. On this gate insulating film 84, a polysilicon film 86 serving as a floating gate is formed.
Is deposited.

Although not shown in the figure, after the polycrystalline silicon film 86 is separated on the element isolation oxide film according to the usual method for manufacturing a two-layer gate type nonvolatile memory, an Inter-Poly insulating film (for example, ONO Film) 88, a polycrystalline silicon film 90 serving as a control gate, a refractory metal silicide film, for example, a tungsten silicide film 92, and a polycrystalline silicon film 94 are sequentially deposited from below. The polycrystalline silicon film 94 has such a thickness that the polycrystalline silicon film 94 is not lost in the etching in the formation of the sidewalls described later and the oxidation in the oxidation step. For example, the polycrystalline silicon film 94
Is formed to a thickness of about 50 nm to 300 nm (here, 50 nm).

Subsequently, as shown in FIG. 37, after a resist is applied to form a desired resist pattern 106,
Polycrystalline silicon film 94, tungsten silicide film 9
2. The polycrystalline silicon film 90, the inter-poly insulating film 88, and the polycrystalline silicon film 86 are sequentially etched to form a gate electrode.

Next, for example, n- ions are implanted into the entire surface of the semiconductor substrate to form a diffusion layer 100 having an LDD structure, and then a silicon oxide film for forming a sidewall is deposited on the entire surface. Then, as shown in FIG. 38, the entire surface of the silicon oxide film is etched back by anisotropic etching to form side walls 98. Here, since the polycrystalline silicon film 94 can secure a sufficient etching selectivity with the silicon oxide film 98 as the sidewall material, it functions as a stopper film at the time of etching.

In the above description, the silicon oxide film 98 is used as a sidewall material, but a silicon nitride film is generally used as another film. A polycrystalline silicon film can ensure a sufficient processing selectivity with respect to a silicon nitride film under ordinary etching gas conditions, and therefore, the same effect can be expected.

Next, for example, high-concentration n + ions are implanted for forming source and drain diffusion layers. In such a structure, ion implantation is performed through the polycrystalline silicon film 94. Therefore, it is possible to eliminate the problem that the high-melting point metal (here, tungsten) in the tungsten silicide film 92 is abnormally oxidized.

Thereafter, post oxidation is performed on the semiconductor substrate shown in FIG. By this post-oxidation, as shown in FIG. 39, a part of the polycrystalline silicon film 94 is oxidized,
A silicon oxide film 96 is formed. Also, the silicon oxide film 102 is similarly formed on the semiconductor substrate 82 by post oxidation.
2 shows a silicon oxide film formed on a surface. here,
By depositing the thickness of the polycrystalline silicon film 94 to such an extent that it cannot be completely oxidized, it is possible to prevent the tungsten silicide film 92 from being directly oxidized, and to greatly improve the oxidation margin of the process. Can be.

Thereafter, as shown in FIG.
After depositing 04, a contact hole is opened and an electrode wiring forming step is performed in accordance with a normal semiconductor device manufacturing method.
A non-volatile memory is manufactured by depositing a passivation film.

As described above, according to the seventh embodiment, a refractory metal silicide film (here, a tungsten silicide film) constituting a gate having a polycide structure.
By providing a polycrystalline silicon film on the surface of the film, it is possible to prevent the tungsten silicide film constituting the gate having the polycide structure from being abnormally oxidized during high-concentration ion implantation. Furthermore, on the tungsten silicide film,
Because a polycrystalline silicon film of sufficient thickness is formed,
Also in the post-oxidation step, abnormal oxidation of the tungsten silicide film can be prevented.

In addition, the polycrystalline silicon film can have a function of a stopper film at the time of etching in the side wall forming step. When a silicon nitride film is used as the stopper film, there is a problem that the film quality of the gate oxide film is deteriorated by film stress. However, when a polycrystalline silicon film is used as in this embodiment, the film stress is small. Therefore, the problem that the film quality of the gate oxide film is deteriorated can be eliminated.

According to the seventh embodiment, the structure is such that a polycrystalline silicon film is formed on a tungsten silicide film which is a high melting point metal silicide film.
Since the tungsten silicide film is not directly oxidized, the oxidation margin of the process can be greatly improved.

Note that in the seventh embodiment,
The tungsten silicide film is not directly exposed to the oxidizing material and is not oxidized. Therefore, the same effect can be obtained even if the material is a high melting point metal film other than the high melting point metal silicide film. [Eighth Embodiment] Next, an eighth embodiment according to the present invention will be described. A method for manufacturing a two-layer gate nonvolatile memory, which is a semiconductor device according to an embodiment, will be described.

FIGS. 41 to 47 are cross-sectional views of respective manufacturing steps showing a method of manufacturing the semiconductor device according to the eighth embodiment.

First, an element isolation oxide film (not shown) is formed in a desired region on the semiconductor substrate 112 by a known method, and then a gate insulating film 114 made of a silicon oxide film is formed. On this gate insulating film 114, a polysilicon film 116 serving as a floating gate is deposited.

Although not shown in the figure, after the polycrystalline silicon film 116 is separated on the element isolation oxide film according to the usual method for manufacturing a two-layer gate type nonvolatile memory, an Inter-Poly insulating film (for example, an ONO film) is formed. 118) A polycrystalline silicon film 120 serving as a control gate, a refractory metal silicide film, for example, a tungsten silicide film 122, and a polycrystalline silicon film 124 are sequentially deposited from below. The polycrystalline silicon film 124 has such a thickness that the polycrystalline silicon film 124 is not lost in etching in forming sidewalls and oxidation in an oxidation step, which will be described later. For example, the polycrystalline silicon film 124 has a thickness of 50 nm to 300 nm (here, 50 nm).
m).

Subsequently, after applying a resist to form a desired resist pattern, the polycrystalline silicon film 124, the tungsten silicide film 122, and the polycrystalline silicon film 12 are formed.
0, Inter-Poly insulating film 118, and polycrystalline silicon film 1
16 are sequentially etched to form a gate electrode. Up to this point, the operation is the same as in the eighth embodiment, and FIG.
The shape is as shown in FIG.

Next, in order to form a source diffusion layer, SAS
The element isolation oxide film is partially etched by the process.
The resist pattern 126 at this time is the same as that of the fourth embodiment shown in FIG. 21 as shown in FIG. 42, and FIG. 43 shows a cross-sectional shape immediately after the etching. In this SAS step, the gate insulating film 114 and the element isolation oxide are formed by using the polycrystalline silicon film 124 as a stopper film at the time of etching by processing using an etching gas set to a condition that gives a normal high selectivity to silicon. The film is etched into the desired shape. Due to this etching, a slight step is formed in the polycrystalline silicon film 124.

In the case where a silicon hydride film (SiN film) is used as the stopper film, there is a problem that the film quality is deteriorated in the gate oxide film due to the film stress. As described above, when the polycrystalline silicon film 124 is used, since the film stress is small, the problem of deterioration of the film quality of the gate oxide film can be eliminated.

Next, after the resist pattern 126 is peeled off, as shown in FIG.
Although high-concentration n + ions are implanted to form 28, ion implantation is performed through the polycrystalline silicon film 124 in such a structure. Therefore, it is possible to eliminate the problem that the high melting point metal (here, tungsten) in the tungsten silicide film is abnormally oxidized.

Further, as shown in FIG. 44, a silicon oxide film 1 for forming a sidewall is formed on the entire surface of the semiconductor substrate.
Deposit 30. Thereafter, as shown in FIG. 45, using the polycrystalline silicon film 124 as a stopper film at the time of etching, the silicon oxide film 130 is entirely etched back by anisotropic etching to form a sidewall 130. At this time, since the polycrystalline silicon film 124 can secure a sufficient etching selectivity with the silicon oxide film 130 as the sidewall material, it is effective as a material for this purpose.

In the above description, a silicon oxide film is used as a sidewall material, but a silicon nitride film is generally used as another film. A polycrystalline silicon film can ensure a sufficient processing selectivity with respect to a silicon nitride film under ordinary etching gas conditions, and therefore, the same effect can be expected.

In the above description, the high-concentration ion implantation for forming the source and drain diffusion layers is performed immediately after the SAS processing step. However, there is no problem if the ion implantation is performed after the sidewall is formed. Alternatively, the drains may be separately ion-implanted. Also in this case, since the ion implantation is performed through the polycrystalline silicon film 124, the problem that the high melting point metal (here, tungsten) in the tungsten silicide film is abnormally oxidized can be eliminated.

Thereafter, post oxidation is performed on the semiconductor substrate shown in FIG. According to the eighth embodiment, as shown in FIG. 46, a part of polycrystalline silicon film 124 is oxidized to form silicon oxide film 132. The silicon oxide film 134 is a silicon oxide film similarly formed on the surface of the semiconductor substrate 112 by post-oxidation.
Here, by depositing the film thickness of the polycrystalline silicon film 124 to such an extent that the entire film cannot be oxidized, the tungsten silicide film 122 is prevented from being directly oxidized, and the oxidization margin of the process is greatly reduced. Can be improved.

Thereafter, as shown in FIG. 47, an interlayer insulating film 136 is deposited, a contact hole is opened according to a normal semiconductor device manufacturing method, and an electrode wiring forming step is performed.
A non-volatile memory is manufactured by depositing a passivation film.

As described above, according to the eighth embodiment, a refractory metal silicide film (here, a tungsten silicide film) constituting a gate having a polycide structure.
By providing a polycrystalline silicon film on the surface of the film, it is possible to prevent the tungsten silicide film constituting the gate having the polycide structure from being abnormally oxidized during high-concentration ion implantation. Furthermore, on the tungsten silicide film,
Because a polycrystalline silicon film of sufficient thickness is formed,
Also in the post-oxidation step, abnormal oxidation of the tungsten silicide film can be prevented.

Further, the polycrystalline silicon film can have a function of a stopper film at the time of etching in the SAS processing step and a function of a stopper film at the time of etching in the side wall forming step. When a silicon nitride film is used as the stopper film, there is a problem that the film quality of the gate oxide film is deteriorated by film stress. However, when a polycrystalline silicon film is used as in this embodiment, the film stress is reduced. The problem that the film quality of the gate oxide film is deteriorated due to the small size can be eliminated.

According to the eighth embodiment, the structure is such that the polycrystalline silicon film is formed on the tungsten silicide film which is a high melting point metal silicide film.
Since the tungsten silicide film is not directly oxidized, the oxidation margin of the process can be greatly improved.

Note that also in the eighth embodiment,
The tungsten silicide film is not directly exposed to the oxidizing material and is not oxidized. Therefore, a similar effect can be obtained even if the material is a high melting point metal film other than the high melting point metal silicide film. That is, according to the embodiment of the present invention, the high melting point metal silicide film or the high melting point By forming a silicon film on the metal, it can function as a stopper film at the time of etching back in the sidewall formation step, and by not exposing the high melting point metal silicide film or the high melting point metal at the time of high concentration ion implantation. In addition, abnormal oxidation of the high melting point metal can be prevented. Further, the amount of oxidation in the oxidation step can be greatly increased.

Further, also in the SAS step of etching the oxide film in a self-aligned manner using the gate as a mask, the refractory metal silicide film or the silicon film on the refractory metal film can function as a stopper film. As described above, by using polycrystalline silicon as a material, the semiconductor device and the semiconductor device described above can be manufactured without deteriorating the film quality of the gate oxide film when using a silicon nitride film or the like and without increasing the number of manufacturing steps. It is possible to achieve the required purpose in the manufacturing method.

[0177]

As described above, according to the present invention, in a semiconductor device having a polycrystalline silicon film, a high melting point metal silicide film or a high melting point metal film as a gate material,
Without deteriorating the film quality of the gate oxide film, the SAS (Self
-Align-Source) process and a gate side wall forming process have a stopper film at the time of etching to facilitate the process and prevent abnormal oxidation of the refractory metal silicide film or refractory metal film. It is possible to provide an apparatus and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a cross-sectional view of each manufacturing step showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 12 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 13 is a cross-sectional view of each manufacturing step showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 14 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 17 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 18 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 19 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fourth embodiment of the present invention.

FIG. 20 is a plan view of each manufacturing step showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 21 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 22 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fourth embodiment of the present invention.

FIG. 23 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fourth embodiment of the present invention.

FIG. 24 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fourth embodiment of the present invention.

FIG. 25 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fourth embodiment of the present invention.

FIG. 26 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 27 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fourth embodiment of the present invention.

FIG. 28 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fourth embodiment of the present invention.

FIG. 29 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fifth embodiment of the present invention.

FIG. 30 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.

FIG. 31 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fifth embodiment of the present invention.

FIG. 32 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fifth embodiment of the present invention.

FIG. 33 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fifth embodiment of the present invention.

FIG. 34 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the fifth embodiment of the present invention.

FIG. 35 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention.

FIG. 36 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the seventh embodiment of the present invention.

FIG. 37 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device of the seventh embodiment of the present invention.

FIG. 38 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the seventh embodiment of the present invention.

FIG. 39 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the seventh embodiment of the present invention.

FIG. 40 is a sectional view showing a structure of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 41 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the eighth embodiment of the present invention.

FIG. 42 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the eighth embodiment of the present invention.

FIG. 43 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the eighth embodiment of the present invention.

FIG. 44 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the eighth embodiment of the present invention.

FIG. 45 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the eighth embodiment of the present invention.

FIG. 46 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device of the eighth embodiment of the present invention.

FIG. 47 is a cross-sectional view of each manufacturing step showing the method for manufacturing the semiconductor device of the eighth embodiment of the present invention.

FIG. 48 is a cross-sectional view showing a structure of a conventional semiconductor device.

FIG. 49 is a cross-sectional view showing a structure of a conventional semiconductor device.

[Explanation of symbols]

 2 semiconductor substrate 4 gate insulating film 6 polycrystalline silicon 8 Inter-Poly insulating film (ONO film) 10 polycrystalline silicon film 12 tungsten silicide (WSi) film 14 polycrystalline silicon film 16 silicon oxide film Reference Signs List 18 sidewall 20 diffusion layer 22, 22a silicon oxide film 24 interlayer insulating film 26 gate insulating film 28 resist pattern 30, 30a silicon oxide film 32 resist pattern 34 resist pattern 36 silicon oxide film 38 ... Element isolation oxide film 40 ... Resist pattern 82 ... Semiconductor substrate 84 ... Gate insulating film 86 ... Polycrystalline silicon film 88 ... Inter-Poly insulating film (ONO film) 90 ... Polycrystalline silicon film 92 ... Tungsten silicide (WSi) film 94 ... polycrystalline silicon film 96 ... silicon oxide film 98 ... sidewall 100 ... Diffusion layer 102 ... Silicon oxide film 104 ... Interlayer insulating film 106 ... Resist pattern 112 ... Semiconductor substrate 114 ... Gate insulating film 116 ... Polycrystalline silicon film 118 ... Inter-Poly insulating film (ONO film) 120 ... Polycrystalline silicon film 122 ... Tungsten silicide film 124 ... Polycrystalline silicon film 126 ... Resist pattern 128 ... Diffusion layer 130 ... Sidewall (silicon oxide film) 132 ... Silicon oxide film 134 ... Silicon oxide film 136 ... Interlayer insulating film

Claims (10)

[Claims] 1. A semiconductor device having a two-layer gate structure having a refractory metal silicide film or a refractory metal film as a gate material, wherein: a first silicon film formed on a gate insulating film; A first insulating film formed on the film; a second silicon film formed on the first insulating film; and the high melting point metal silicide film or the high melting point metal formed on the second silicon film. A semiconductor device comprising: a melting point metal film; and a third silicon film formed on a film surface of the high melting point metal silicide film or the high melting point metal film. 2. A semiconductor device having a two-layer gate structure having a refractory metal silicide film or a refractory metal film as a gate material, wherein: a first silicon film formed on a gate insulating film; A first insulating film formed on the film; a second silicon film formed on the first insulating film; and the high melting point metal silicide film or the high melting point metal formed on the second silicon film. A third melting point metal film, a third silicon film formed on a film surface of the high melting point metal silicide film or the high melting point metal film, and a second insulating film formed on the third silicon film. A semiconductor device, comprising: 3. A method according to claim 1, wherein sidewalls are formed on side surfaces of the first, second, and third silicon films, the first insulating film, and the refractory metal silicide film or the refractory metal film. The semiconductor device according to claim 1, wherein: 4. A gate including the third silicon film is regularly arranged, and a part of an isolation oxide film between adjacent gates is removed in a self-aligned manner using the third silicon film as a mask. 4. The semiconductor device according to claim 1, wherein the semiconductor device has a structured structure. 5. The semiconductor device according to claim 1, wherein said third silicon film is a polycrystalline silicon film. 6. The polycrystalline silicon film has an impurity concentration of:
^{6. The structure according} to claim 5, wherein the size is 1 × 10 ¹⁹ cm ⁻³ or more.
3. The semiconductor device according to claim 1. 7. A method of manufacturing a semiconductor device having a two-layer gate structure having a refractory metal silicide film or a refractory metal film as a gate material, comprising: forming a first silicon film on a semiconductor substrate; Forming a first insulating film on the first silicon film; forming a second silicon film on the first insulating film; and forming the refractory metal silicide film on the second silicon film. Alternatively, a step of forming a high melting point metal film, and forming a third silicon film or a laminated film of the third silicon film and a second insulating film on the film surface of the high melting point metal silicide film or the high melting point metal film The first and second silicon films formed on the first insulating film, the first insulating film, a refractory metal silicide film or a refractory metal film, and the third silicon film or Third Patterning a stacked film of the silicon film and the second insulating film to form a plurality of gates; and forming an element isolation insulating film formed between a plurality of adjacent gates in a self-aligned manner using the gate as a mask. A method for manufacturing a semiconductor device, comprising: a step of removing; and a step of forming a diffusion layer in the semiconductor substrate by performing ion implantation. 8. The method further comprises: depositing a sidewall material on the entire surface of the semiconductor substrate on which the gate is formed; and etching the sidewall material to form a sidewall on a side surface of the gate. The method of manufacturing a semiconductor device according to claim 7, wherein: 9. The method according to claim 7, wherein after the step of forming the gate, thermal oxidation is performed on the semiconductor substrate. 10. The method according to claim 10, wherein the third silicon film is formed on the refractory metal silicide film or the refractory metal film on a surface thereof.
The method for manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is formed to have a thickness of from about 300 nm to about 300 nm.