JP2000058447A - Charged particle beam exposure apparatus and semiconductor device manufacturing method - Google Patents

Abstract

[PROBLEMS] To provide a charged particle beam exposure apparatus capable of minimizing thermal deformation of a reticle mark or a mark portion on a reticle stage and forming a pattern with higher accuracy. SOLUTION: This charged particle beam exposure apparatus irradiates a reticle 1 on which a pattern is formed with a charged beam, and transfers the pattern by passing the reticle to form an image of the patterned charged beam on a sensitive substrate. It is. Reticle 1
The hoods 7 and 6 for shielding the mark member 5 on the reticle stage 3 and the area around the mark of the reticle are provided closer to the charged particle beam source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an exposure apparatus which uses a charged particle beam such as an electron beam or an ion beam as an exposure energy source for transfer exposure of a semiconductor device pattern. In particular, the present invention relates to a charged particle beam exposure apparatus improved so that thermal deformation of a reticle or a mark member of a reticle stage is prevented as much as possible and more precise pattern formation can be performed. Further, the present invention relates to a method for manufacturing a highly accurate semiconductor device using such a charged particle beam exposure apparatus. The reticle referred to in this specification is
Patterns, including variable-shape aperture plates, character projection type reticles, and reticle patterns that divide the reticle pattern corresponding to the exposure chip pattern into small areas, hold them on the reticle, and connect and transfer the small areas. It means a general transfer mask.

[0002]

2. Description of the Related Art The prior art will be described by taking transfer exposure using an electron beam as an example. The drawback of electron beam exposure is high accuracy but low throughput, and various techniques have been developed to overcome the drawback. At present, a figure portion batch exposure method called cell projection, character projection or block exposure has been put to practical use. In the figure part batch exposure method,
Repeatable small circuit pattern (10 μm on wafer
Using a reticle on which a plurality of types of similar small patterns are formed, transfer exposure is repeatedly performed using one small pattern as one unit. However, even in this method, the variable shaping method is used for pattern portions having no repeatability.

On the other hand, as an electron beam transfer exposure system aiming at a much higher throughput than the graphic partial batch exposure system, a reticle having a circuit pattern of an entire semiconductor die is prepared, and an electron beam is applied to the area of the reticle. An electron beam reduction transfer device that irradiates and reduces and transfers an image of a pattern in an irradiation range by a projection lens has been proposed.
In this type of apparatus, when the entire area of the reticle is irradiated with an electron beam and a pattern is to be transferred at once,
The pattern cannot be transferred accurately. Also, it is difficult to manufacture a reticle serving as an original. Therefore, a system which has been studied vigorously recently does not expose one die (chips on a wafer) or a plurality of dies at once, but has a large optical field as an optical system, but the pattern is divided into small regions. And performing transfer exposure (hereinafter, referred to as a division transfer system). At this time, for each of the small areas, exposure is performed while correcting aberrations such as the focal point of the image of the small area formed on the surface to be exposed and the field distortion. This makes it possible to perform exposure with high resolution and accuracy over an optically wide area as compared with batch transfer of the entire die.

[0004]

In an exposure apparatus using a charged particle beam of this type, a reticle or a reticle stage is used for the purpose of calibration of an optical system of the apparatus, alignment with a wafer to be transferred, and the like. The mark pattern image provided above is projected onto a mark pattern provided on a wafer or a wafer stage, and the mark and its periphery are scanned to perform "mark detection" for obtaining the relative positions of the marks. In the above-described apparatus such as the split transfer system aiming at high resolution, the acceleration voltage is large, and therefore, the amount of reflected electrons emitted from the target surface is small. Therefore, in order to perform mark detection with high accuracy, it is necessary to slow down the scanning time or increase the number of scans. For this reason, the beam irradiation amount to the mark pattern area provided on the reticle or the reticle stage increases, the temperature of the mark pattern area member increases, and the thermal pattern deteriorates the position accuracy of the mark pattern.

[0005] A decrease in the positional accuracy of the mark pattern directly leads to a decrease in the alignment accuracy and, consequently, a decrease in the overlay accuracy. Further, a decrease in the calibration accuracy of the optical system leads to a decrease in the joining accuracy of the transfer patterns and the like, and increases defects such as short-circuiting, disconnection of the device pattern, and uneven resistance value.

SUMMARY OF THE INVENTION The present invention has been made in view of such problems, and a charged particle beam exposure capable of minimizing thermal deformation of a reticle or a mark member of a reticle stage and performing more accurate pattern formation. It is intended to provide a device. Still another object of the present invention is to provide a method for manufacturing a highly accurate semiconductor device using such a charged particle beam exposure apparatus.

[0007]

In order to solve the above problems, a charged particle beam exposure apparatus of the present invention illuminates a reticle on which a pattern is formed with a charged beam, and passes a patterned charged beam through the reticle. What is claimed is: 1. A charged particle beam exposure apparatus that forms an image on a sensitive substrate to transfer a pattern, wherein a charged particle beam source side of a reticle is shielded from irradiating a beam to a peripheral region of a mark provided on a reticle or a reticle stage. A hood is provided.

In an exposure method having a relatively wide transfer range such as a division transfer method, the size of an illumination beam on a reticle surface is considerably large (for example, 100 to 1,000 μm square). On the other hand, the size of the mark pattern is often several μm to 100 μm. Therefore, when irradiating a mark with a beam at the time of calibration or alignment, an unnecessarily wide beam is applied to the reticle or the mark member on the reticle stage. Unnecessarily wide illumination beam
As described above, the problem of thermal deformation of the reticle and the mark member on the reticle stage occurs. On the other hand, the size of the illumination beam can be reduced by the variable shaping method only when the mark is detected, but the irradiation optical system becomes complicated, which is not preferable. Therefore, a hood for blocking the beam irradiation to the peripheral region of the mark as described above is installed on the charged particle beam source side (upstream side) of the mark, and the beam irradiated on the reticle or the mark itself is minimized, so that the reticle Thermal deformation of the mark member on the reticle stage is minimized.

A semiconductor device manufacturing method according to the present invention is characterized in that exposure in a lithography step is performed using the above charged particle beam exposure apparatus.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the entire electron beam exposure apparatus according to one embodiment of the present invention will be described with reference to FIG.

The electron beam exposure apparatus shown in FIG. 5 has an electron gun 101 shown at the top of the figure. The electron gun 101 emits an electron beam downward. Below the electron gun 101, two stages of condenser lenses 103 and 105 are provided.
3 and 105, the crossover is imaged on the blanking aperture 107.

Below the condenser lens 105, a rectangular opening 106 is provided. The rectangular opening 106 allows only the electron beam illumination light for an area corresponding to one exposure unit small area to pass. Specifically, the opening 106 forms the illumination light into, for example, a square having a dimension slightly over 1 mm square in reticle size conversion. The image of the aperture 106 is
To form an image on the reticle 110.

Below the opening 106, the above-mentioned blanking opening 107 is provided at a position where a crossover is formed. A deflector 108 is disposed below the deflector 108. The deflector sequentially scans the illumination light mainly in the X direction in FIG. 5 to illuminate a small area in the optical field including deflection on the reticle. Below the deflector 108, a condenser lens 109 is arranged. Condenser lens 109
Converts the electron beam into a parallel beam, impinges it on the reticle 110, and forms an image of the aperture 106 on the reticle 110.

The reticle 110 is shown in FIG.
Although only a small area is shown, it actually extends in a direction perpendicular to the optical axis (XY direction) and has many small areas.
When illuminating and exposing each small area in the field of view of the optical system, the electron beam is deflected by the deflector 108 as described above. The reticle 110 is placed on a reticle stage 111 that can move in the X and Y directions. The wafer 114, which is a material to be exposed, is also placed on a wafer stage 115 that can move in the X and Y directions. By scanning these reticle stage 111 and wafer stage 115 in directions opposite to each other in the Y direction (lenses 112 and 113
In the case of a lens), each small area in the die pattern is continuously exposed. In addition, both stages 111 and 115 have
An accurate position measurement system using a laser interferometer is provided, and each small area is accurately joined on the wafer 114 by separate alignment means and adjustment of each deflector.

A projection lens 11 is provided below the reticle 110.
2 and 113 (objective lens) and a deflector 131 are provided. Then, one small region of the reticle 110 is irradiated with an electron beam, and the electron beam patterned by the reticle 110 is reduced and deflected by the projection lenses 112 and 113 to form an image at a predetermined position on the wafer 114. . An appropriate resist is applied on the wafer 114, and the resist is given a dose of an electron beam, so that a reduced pattern of a reticle image is transferred onto the wafer 114. The wafer 114 is mounted on the wafer stage 115 movable in the direction perpendicular to the optical axis as described above. Reference numeral 133 above the wafer 114 is a backscattered electron detector used for mark detection.

Next, the configuration around the reticle stage, which is a feature of the present invention, will be described. FIG. 1 is a sectional view showing details around a reticle stage of an electron beam exposure apparatus according to one embodiment of the present invention. In the figure, a reticle 1 is mounted on a reticle stage 3. At the left end of the reticle stage 3, a mark member 5 is arranged. The mark member 5 is made of a plate made of Si or the like having a thickness of about 1 μm to 800 μm, for example, like the reticle 1.
One or more marks (fiducial marks) as shown in FIG. A charged particle beam (beam axis 8) is applied to this mark, and a beam almost passing through the mark is projected onto a wafer or a wafer stage.

A hood 7 which is a feature of the present invention is provided on the mark member 5. Food 7 is Ta or Mo
And a plate having a thickness of about 0.1 to 1 mm. In this example, the hood 7 rises on the reticle stage 3 at the portion of the leg 7 b, from which the hood plate 7 c extends in a cantilever shape so as to cover the mark member 5. The gap between the mark member 5 and the hood 7 is about 0.1 to several mm. The legs 7b can be provided on both sides of the hood plate 7c or other portions. Note that reference numeral 9 shown outside the hood 7b
Is a laser mirror (a mirror used in a laser interference type length measuring device).

A hole 7a is formed in the center of the hood plate 7c. The hole 7a is opened above the mark portion of the mark member 5 with a size slightly larger than the mark. The accuracy of the edge of the hole 7a may be coarser than the edge of the pattern on the mask. The details of the hole 7a will be described later with reference to FIG. Similarly, on reticle 1,
A hood 6 is provided. The hood 6 has a reference numeral 6a at a position corresponding to the alignment mark of the reticle 1.
The hole shown by is indicated.

FIG. 2 is a plan view for explaining the relationship between the mark and the illumination beam. FIG. 2A shows a collective transfer area 11 of a pattern on a reticle and a beam 13 illuminating the area. The batch transfer area 11 is an area including a pattern transferred from the reticle to the wafer at a certain moment of transfer exposure. In the case of the division transfer method, the size of this area is a square or a rectangle of 100 to 1000 μm square on the reticle, and the reduction rate (for example, 1
/ 4), which is 25 to 250 μm square. In the current figure part batch transfer method such as cell projection,
The size of the batch transfer area 11 is 100 to 250 on the reticle.
μm square, reduction rate on wafer (eg 1/25)
It is reduced to about 5 μm square.

The illumination beam 13 is slightly larger than the collective transfer area 11, for example, the collective transfer area 11 is 1000 μm.
In the case of a corner, the illumination beam 13 is 1100 μm square.

Next, the details of the mark will be described. FIG. 2B shows a relatively large pattern for alignment or carburetion of the main field of view of the optical system. The mark pattern 23 has a width of, for example, 1.6 μm on the reticle surface.
, And a line and space pattern having an interval of 3.2 μm and a length of 50 μm. The mark pattern 23 is illuminated with a charged particle beam, the beam that has passed through the pattern is projected onto a wafer (or a wafer stage), and scanning is performed to detect the overlap with the mark on the wafer using an electron beam detector or the like. . Based on the detection signal, alignment (alignment) with a pattern already formed on the wafer is performed, and the magnification, rotation, distortion, and projection position of the projection optical system are calibrated (carbureted).

FIG. 2C shows a small pattern for strain carburetion in the batch transfer small area. The mark pattern 33 includes a plurality of lines 35 having a width of 1 μm and a length of 10 μm, as shown in an enlarged manner in FIG.
The space between them is 2 μm wide.

Both the mark pattern shown in FIG. 2B and the mark pattern shown in FIG. 2C are considerably smaller than the illumination beam 13, and most of the illumination beam is useless.
When the entire useless illumination beam is irradiated on the mark member 5 (or the reticle 1), local heat distortion occurs in the mark portion due to the irradiation heat, or the mark member or the reticle is thermally deformed. The shape and position of the mark will change. Then, the accuracy of alignment and carburetion is reduced, and the transfer accuracy is also reduced.

Therefore, the hoods 7 and 6 which are the features of the present invention are described.
(FIG. 1) is provided. FIG. 3 is a plan view showing a detailed example of the mark hood of the charged particle beam exposure apparatus according to one embodiment of the present invention. FIG. 3A shows the plan shape of the hood 7 or 6. The outer shape of the hood 7 or 6 is 1100
It is larger than the illumination beam 13 of μm square. A hole 7a or 6a of 55 μm square is opened at the center of the hood 7 or 6. Below the hole 7a or 6a, there is a mark pattern 23 which is present in a region of approximately 50 μm square. In this state, the illumination beam 13 hits the mark 23, so that only the beam that is truly necessary to illuminate the mark 23 hits the mark member 5, and does not give useless heat to the mark member 5.

FIG. 3B is a plan view showing a modification of the hood. This example is an effective hood when the space between the lines 23 'of the mark pattern is relatively large. In this example, the hole 7a 'of the hood 7' is divided into slits and opened. For example, mark line 2
3 'width 5μm, length 50μm, slit 7
a ′ has a width of 5.5 μm, a length of 51 μm, and a line 23 ′.
Is slightly larger than the dimensions. If you do this,
By reducing the number of illumination beams hitting the mark member, thermal deformation can be further suppressed.

FIG. 4 is a side sectional view showing a main part of a charged particle beam exposure apparatus according to another embodiment of the present invention. In this example, the hood 51 with a hole is placed at a position away from the mark member 57. That is, the pattern hood 51 is arranged on the beam upstream side of the mark member 57 via the lens 53. The beam 55 that has passed through the opening 51 a on the hood 51 is projected and formed on the mark pattern 57 a on the mark member 57 by the action of the lens 53.
Also in this case, an illumination beam can be selectively applied to the mark pattern on the mark member (or reticle) to avoid thermal deformation of the mark member due to unnecessary beam irradiation.

Next, an example of a mode of use of the exposure apparatus of the present invention will be described. FIG. 6 is a flowchart showing an example of the semiconductor device manufacturing method of the present invention. The manufacturing process of this example includes the following main processes. Wafer manufacturing process for manufacturing a wafer (or wafer preparing process for preparing a wafer) Mask manufacturing process for manufacturing a mask to be used for exposure (or mask preparing process for preparing a mask) Wafer processing process for performing necessary processing on a wafer Wafer Chip assembling step of cutting out the chips formed on the chip one by one to make it operable Chip inspecting step of inspecting the resulting chips Each of the steps further includes several sub-steps.

Of these main steps, the main step that has a decisive effect on the performance of the semiconductor device is the wafer processing step. In this step, designed circuit patterns are sequentially stacked on a wafer, and a number of chips that operate as memories and MPUs are formed. This wafer processing step includes the following steps. A thin film forming step (using CVD, sputtering, etc.) for forming a dielectric thin film serving as an insulating layer, a wiring portion, or a metal thin film forming an electrode portion (using CVD or sputtering, etc.) A lithography process of forming a resist pattern using a mask (reticle) in order to selectively process etc. An etching process of processing a thin film layer or a substrate according to a resist pattern (for example, using a dry etching technique) An ion / impurity implantation diffusion process Resist stripping step Inspection step for inspecting the processed wafer Further, the wafer processing step is repeated by a necessary number of layers to manufacture a semiconductor device that operates as designed.

FIG. 7 is a flowchart showing a lithography step which is the core of the wafer processing step shown in FIG. This lithography step includes the following steps. A resist coating step of coating a resist on a wafer on which a circuit pattern has been formed in the preceding step An exposing step of exposing the resist A developing step of developing the exposed resist to obtain a resist pattern Stabilizing the developed resist pattern Annealing Step for Using the exposure apparatus of the present invention in the above-mentioned exposure step, the accuracy of pattern formation in the lithography step is greatly improved.
In particular, the process related to realizing the required minimum line width and the overlay accuracy corresponding thereto is a lithography process, in particular, an exposure process including alignment control, and it has been difficult until now by applying the present invention. Semiconductor devices can be manufactured.

[0030]

As is apparent from the above description, according to the present invention, since a shielding member is provided above a reticle mark or a mark member on a reticle stage, a useless illumination beam to a mark pattern portion is provided. Can be reduced as much as possible, so that the thermal expansion of the mark portion can be reduced, and the mark detection accuracy is improved. Further, a method for manufacturing a semiconductor device with high accuracy using such a charged particle beam exposure apparatus can be provided.

[Brief description of the drawings]

FIG. 1 is a partially sectional side view showing details around a reticle stage of a charged particle beam exposure apparatus according to one embodiment of the present invention.

FIG. 2 is a plan view for explaining a relationship between a mark and an illumination beam.

FIG. 3 is a plan view showing a detailed example of a mark hood of the charged particle beam exposure apparatus according to one embodiment of the present invention.

FIG. 4 is a side sectional view showing a main part of a charged particle beam exposure apparatus according to another embodiment of the present invention.

FIG. 5 is a diagram showing an image forming relationship in the entire optical system of the electron beam exposure apparatus according to one embodiment of the present invention.

FIG. 6 is a flowchart illustrating an example of a semiconductor device manufacturing method according to the present invention.

FIG. 7 is a flowchart showing a lithography step which is the core of the wafer processing step of FIG. 6;

[Explanation of symbols]

Reference Signs List 1 reticle 3 reticle stage 5 mark member 6 hood 6a hole 7 hood 7a hole 7b leg 7c hood plate 8 beam axis 9 laser mirror 11 batch transfer area 13 illumination beam area 21, 31 batch transfer area 23, 33 mark pattern 51 hood with hole 51a aperture 53 lens 55 charged particle beam 57 mark part 57a mark pattern

Claims (2)

[Claims] 1. A charged particle beam exposure apparatus for irradiating a reticle on which a pattern is formed with a charged beam, transferring the pattern by passing the reticle and forming an image of the patterned charged beam on a sensitive substrate; A charged particle beam exposure apparatus characterized in that a hood is provided closer to a charged particle beam source side than a reticle to block beam irradiation to an area around a mark provided on a reticle or a reticle stage. 2. A method for manufacturing a semiconductor device, comprising performing exposure in a lithography step using the charged particle beam exposure apparatus according to claim 1.