JP2000049575A - Interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interface circuit by which proper comparative levels are obtained in respective places and prescribed internal data is obtained when a master and a slave are mounted on a circuit board. SOLUTION: The interface circuit is constituted so that a clock wiring 101 for transmitting a clock signal from the master 10 to the slave 20 and a data wiring 102 for transmitting a data signal have mutually the same material, cross sectional shape and length, the slave is provided with an average circuit 21 for generating an average voltage value from an internal clock and, in the slave, a clock signal input buffer 22A for outputting the internal clock 23 and a data signal input buffer 22 for outputting internal data 24 have the same characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit, and more particularly, to a clock signal averaging circuit, which generates an average voltage value of a clock signal, and compares the average voltage value with a comparison level of an interface of a device. Hereinafter, V
ref).

[0002]

2. Description of the Related Art An interface circuit as shown in FIG. 8 is disclosed in Japanese Patent Application Laid-Open No. Hei 7-221612 in order to compensate for the deterioration of the duty ratio of an interface signal accompanying the increase in the speed of an interface.

In FIG. 8, a clock signal generated by a clock generator 11 provided in a transmission unit (master) 10 is output from a clock signal output buffer 12A and input to an averaging circuit 61 to generate an average voltage value. The average voltage value is received by the receiving unit (slave) by the Vref wiring 121.
The data signal is sent as Vref to the data signal input buffer 62.

On the other hand, a plurality of data signals are transmitted from a plurality of data signal output buffers 12 of a transmission unit 10 to data lines 11.
2 and is sent to the data signal input buffer 62 of the receiving unit 60, and is compared with the above-mentioned Vref to output the internal data 64, respectively.

[0005] When this prior art is constructed on a circuit board, it is as shown in FIG.

In FIG. 9, a circuit board (board) 110
Above, the transmitting unit 10 in FIG. 8 is a master chip (a master that is a semiconductor chip, and hereinafter simply referred to as a master,
The averaging circuit 6 shown in FIG.
1 is fixedly mounted as a chip 61, and the receiving unit 60 in FIG.
Are fixedly mounted as first to third slave chips (slaves that are semiconductor chips, hereinafter simply referred to as slaves) 70, 80, and 90, respectively.

A clock signal (external clock signal) output from the clock signal output buffer 12A of the master 10
Is input to an averaging circuit 61 by a wiring formed on a circuit board to generate an average voltage value, and the average voltage value is sent to a Vref wiring 121 extending in the X direction.

On the other hand, a plurality of data wirings 112 extend from the master 10 in the X direction to the respective terminating circuits 115, and the data signals from the plurality of data signal output buffers 12 each have a characteristic impedance of 50Ω.
12 is sent.

The slaves 70, 80, and 90 are arranged in the X direction between the master 10 and the terminating circuit 115. The slaves 70, 80, and 90 are connected to the Vref wiring 121 and the data wiring 112 at respective locations to receive Vref and data signals, and The comparison is made by the signal input buffer 62, and the respective slaves output the respective internal data 64. Further, the structure as shown in FIG.
m, and the dimension in the Y direction is about 2 cm.

[0010]

The data signal is a combination of the H level and the L level, like the clock signal, and the transmitted data signal is the comparison level Vre.
The data is compared by the data signal input buffer using f as a threshold value to output the internal data. However, the waveform of the data signal is gradually reduced during transmission.

Therefore, the dullness of the waveform of the data signal that arrives at each location is different, and the appropriate level of Vr at each location is met.
ef is required.

However, in the above-mentioned prior art, an averaging circuit is provided between the master and the slave, and Vref, which has become a DC potential, is transmitted through the Vref wiring before the averaging circuit. This is different from the rounding, and it is impossible to obtain predetermined internal data.

That is, since the master and the slave themselves are semiconductor ICs and each wiring is about 1 mm in size at most, there is no influence from the routing of the Vref line when considering only the inside of the slave.

However, when a master and a slave are mounted on a circuit board as shown in FIG.
At a distance of 0 cm or more, one of them propagates the DC potential Vref, and the other propagates a continuous pulse signal data signal, so that an appropriate Vref level cannot be obtained at each location. Cannot be obtained.

It is therefore an object of the present invention to provide an interface circuit capable of obtaining an appropriate Vref level at each location and obtaining predetermined internal data when a master and a slave are mounted on a circuit board. .

[0016]

The present invention is characterized in that a master provided on a circuit board for outputting a clock signal and a data signal; a slave provided on the circuit board at a distance from the master; Provided on a circuit board,
A clock wiring for transmitting the clock signal from the master to the slave; and a data wiring provided on the circuit board and transmitting the data signal from the master to the slave. A clock signal input buffer for inputting a clock signal from the internal clock and outputting an internal clock, a data signal input buffer for inputting a data signal from the master and outputting internal data, and an average for generating an average voltage value from the internal clock And a means for supplying the average voltage value from the averaging circuit as Vref to the clock signal input buffer and the data signal input buffer, respectively, and the clock wiring between the master and the slave, The data wirings are made of the same material, the same cross-sectional shape, and the same length It has, and the clock signal input buffer and the data signal input buffer is in the interface circuit has the same characteristics of each other.

Here, the clock wiring and the data wiring are formed from the master to the respective termination circuits, and a plurality of the slaves can be provided therebetween while being connected thereto.

The clock wiring and the data wiring may be provided linearly in one direction from the master to the slave. Alternatively, the clock wiring and the data wiring may have the same bent shape and may be provided from the master to the slave. Alternatively, when one of the clock wiring and the data wiring has a detour shape that bypasses a wiring obstacle, the other wiring having no wiring obstacle may have the same detour shape. it can.

Further, the clock signal input buffer and the data signal input buffer may have the same circuit configuration by including a differential amplifier having the same characteristics and a buffer having the same characteristics. In this case, the differential amplifier in the clock signal input buffer and the data signal input buffer includes a resistor having the same characteristics, a field-effect transistor (hereinafter referred to as FET) having the same characteristics, and a constant current source circuit having the same characteristics. And have the same circuit configuration,
The buffers in the clock signal input buffer and the data signal input buffer have the same characteristics as each other.
It is preferable that T has the same circuit configuration.

According to the present invention, a clock signal having a continuous pulse waveform and a data signal having a continuous pulse waveform are routed in the same manner on a circuit board.
The dull state of both signals at each location is the same, so that Vref obtained from the clock signal at each location is at an appropriate level at that location, thereby enabling predetermined internal data to be obtained at each location.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a first embodiment of the interface circuit of the present invention. A master 10 and a slave 20 are fixedly mounted on a circuit board 100. On the semiconductor chip of the master 10, a clock generator 11, a clock signal output buffer 12A, and a plurality of data signal output buffers 12 are formed. Slave 2
0, the clock signal input buffer 22
A, averaging circuit 21, plural data signal input buffers 2
2 is formed, and the clock signal input buffer 22A
And the data signal input buffer 22 have the same characteristics.

A clock wiring 10 extending linearly in the X direction is provided on a circuit board between the master 10 and the slave 20.
1 and the data wiring 102 are formed, but the master 1
The clock wiring and the data wiring between 0 and the slave 20 have the same material, the same cross-sectional shape, and the same length.

The clock signal generated by the clock generator 11 provided in the master 10 is output from the clock signal output buffer 12A, and propagates from the clock signal output buffer 12A as an external clock to the clock signal input buffer 22A of the slave 20. It is input and compared with Vref to output an internal clock. This Vref is an average voltage value of the internal clock obtained by the averaging circuit 21, and is a comparison level in each buffer.

On the other hand, a data signal is output from each of the plurality of data signal output buffers 12 provided in the master 10 and propagates through the data line 102 to be input to the data signal input buffer 22 of the slave 20 where the Vr
ef and outputs the respective internal data 24.

Clock wiring 10 between master and slave
1 and the data wiring 102 have the same configuration, so that the dull state of the clock signal and the data signal reaching the slave 20 is the same, and the buffers 22A and 22 have the same characteristics.

Therefore, the data signal from the master 10 can be used in the slave 20 to obtain predetermined internal data at an appropriate Vref level.

That is, since the clock wiring and the data wiring on the circuit board have a length of a unit of cm, it is necessary that the clock wiring and the data wiring have the same structure so that both signals have the same rounded state.

On the other hand, the routing of Vref in the slave and the difference between the clock wiring and the data wiring in the slave and the master are negligible because the slave and the master are about 1 mm at most in the semiconductor IC. I can do it.

FIG. 2A shows an external clock reaching the slave 20, FIG. 2B shows an internal clock 23, FIG. 2C shows a data signal reaching the slave 20, and FIG. D) shows the internal data 24.

Since the waveform of the external clock arriving at the slave 20 and the data signal arriving at the slave 20 are in the same rounded state, the Vr generated from this clock is used.
Predetermined internal data 24 is obtained by ef.

FIG. 3 is a circuit diagram showing a clock signal input buffer and an averaging circuit according to the first embodiment.

In FIG. 3A, a clock signal input buffer 22A enclosed by a dotted line is composed of two differential amplifiers 51 and 51 and two buffers 52 and 52 connected in series. And the other buffer 52 is provided to equalize the load of the output of the differential amplifier. The averaging circuit 21 is coupled to the clock signal input buffer 22A.

FIG. 3B shows a clock signal input buffer 2.
FIG. 2 is a circuit diagram showing a 2A differential amplifier 51. A series connection of the resistor R ₁ and the N-channel insulated gate FET ₁ , and the resistors R ₂ and N
And a series body and the constant current source circuit P ₁ of channel insulated gate FET _2.

FIG. 3C shows a clock signal input buffer 2.
FIG. 3 is a circuit diagram showing a buffer 52 of 2A. It comprises a CMOS comprising a P-channel insulated gate FET ₃ and an N-channel insulated gate FET ₄ and a CMOS comprising a P-channel insulated gate FET ₅ and an N-channel insulated gate FET ₆ .

FIG. 4D is a circuit diagram showing the averaging circuit 21. The CMOS comprising the P-channel insulated gate FET ₇ and the N-channel insulated gate FET _{8 is connected} to the constant current source circuits P ₂ and P ₂ having the same current value. ₃ is connected between Vcc on the high power supply side and ground on the low power supply side via
C connected between the output terminal of the power supply and the ground on the low power supply side
Are connected.

FIG. 4 is a circuit diagram showing a data signal input buffer according to the first embodiment.

In FIG. 4A, a data signal input buffer 22 surrounded by a dotted line is composed of two differential amplifiers 51 and 51 and two buffers 52 and 52 connected in series. And the other buffer 52 is provided to equalize the load of the output of the differential amplifier.

FIG. 4B shows the data signal input buffer 22.
3 is a circuit diagram showing a differential amplifier 51 of FIG. A series body of a resistor R ₁ and an N-channel insulated gate FET _1, a series body of a resistor R ₂ and an N-channel insulated gate FET ₂ , and a constant current source circuit P ₁
It is composed of

FIG. 4C shows the data signal input buffer 22.
3 is a circuit diagram showing a buffer 52 of FIG. It comprises a CMOS comprising a P-channel insulated gate FET ₃ and an N-channel insulated gate FET ₄ and a CMOS comprising a P-channel insulated gate FET ₅ and an N-channel insulated gate FET ₆ .

That is, the clock signal input buffer 22A shown in FIG. 3 and the data signal input buffer 22 shown in FIG.
Means that the circuits have the same characteristics due to the circuit having the same configuration using elements having the same characteristics.

FIG. 5 is a plan view showing a second embodiment of the interface circuit of the present invention. In FIG. 5, the same or similar portions as those in FIG.

Clock wiring 101 and data wiring 102
Are formed on the circuit board 101 so as to extend linearly in the X direction from the master chip 10 to the respective termination circuits 105. Both wirings 101 and 102 are wirings having a characteristic impedance of 50Ω provided on a FR4 board material in which a dielectric layer having a predetermined thickness is formed on a ground plate.
They have the same material and the same cross-sectional shape.

First, second, and third slaves 30, 40, and 50 having the same configuration as the slave 20 of FIG. 1 are connected to these wirings and arranged in the X direction. That is, the clock wiring 101 and the data wiring 102 extend under the slaves via the insulating layer. And the master 20, the slaves 30, 40, 5
0, the layout dimensions including the termination circuit 105 are, for example, X
The dimension in the direction is about 15 cm, and the dimension in the Y direction is 2c.
m and the master 20 and each slave 3
Between 0, 40, and 50, the lengths of the clock wiring 101 and the data wiring 102 have the same dimensions.

A portion A of an external clock signal propagating through the clock wiring 101 and a data signal propagating through the data wiring,
The waveforms at the points B and C are shown in FIGS.
(B) and FIG. 6 (C) respectively.

The waveform has a fast rising and slow falling dull state, and the dull state becomes larger with propagation. However, the external clock signal and the data signal are in the same dull state at each location.

Therefore, in the first slave 30 shown in FIG. 6B, a suitable Vref1 is generated and predetermined internal data is output to the first slave 30.
In the third slave 50 shown in FIG.
ref3 is generated and predetermined internal data is output to the third slave 50.

FIG. 7 is a plan view showing a third embodiment of the interface circuit according to the present invention. Note that, in FIG. 7, the same or similar portions as those in FIGS. 1 and 5 are denoted by the same reference numerals, and duplicate description will be omitted.

In FIG. 7, the clock wiring 101 and the plurality of data wirings 102 between the master 10 and the first slave 30 have the same length in the same bent shape according to having the X-direction component and the Y-direction component. It is becoming.

The clock wiring 101 between the second slave 40 and the third slave 50 has a wiring obstruction 104 having the same layer pattern, so that the clock wiring 101 has a detour shape that bypasses it. On the other hand, a plurality of data wires 102
However, in order to make the length the same as that of the clock wiring, a similar detour shape is formed in each of the plurality of data wirings 102.

[0051]

As described above, according to the present invention, a clock signal having a continuous pulse waveform and a data signal having a continuous pulse waveform are routed on the circuit board in the same manner, so that both signals at each location are provided. Therefore, Vref obtained from the clock signal at each location is at an appropriate level at that location, and thereby predetermined internal data can be obtained at each location.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a diagram showing waveforms according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a clock signal input buffer and an averaging circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a data signal input buffer according to the first embodiment of the present invention.

FIG. 5 is a plan view showing a second embodiment of the present invention.

FIG. 6 is a diagram showing waveforms according to the second embodiment of the present invention.

FIG. 7 is a plan view showing a third embodiment of the present invention.

FIG. 8 is a plan view showing a conventional technique.

FIG. 9 is a plan view showing a case where the conventional technique of FIG. 8 is arranged on a circuit board. It is a figure showing a waveform in an embodiment.

[Explanation of symbols]

 Reference Signs List 10 master 11 clock generator 12 data signal output buffer 12A clock signal output buffer 20 slave 21 averaging circuit 22 data signal input buffer 22A clock signal input buffer 23 internal clock 24 internal data 30 first slave 40 second slave 50 first 3 slave 51 differential amplifier 52 buffer 60 slave 61 averaging circuit 62 data signal input buffer 64 internal data 70 first slave 80 second slave 90 third slave 100 circuit board 101 clock wiring on circuit board 102 circuit Data wiring on board 104 Wiring obstacle 105 Termination circuit 110 Circuit board 111 Clock wiring 112 Data wiring 115 Termination circuit 121 Vref wiring

Claims (7)

[Claims] A master chip provided on a circuit board for outputting a clock signal and a data signal; a slave chip provided on the circuit board apart from the master chip; and a slave chip provided on the circuit board; A clock wiring for transmitting the clock signal from the master chip to the slave chip, and a data wiring provided on the circuit board and transmitting the data signal from the master chip to the slave chip; A clock signal input buffer for receiving a clock signal from the master and outputting an internal clock, a data signal input buffer for receiving a data signal from the master and outputting internal data, and an average voltage from the internal clock. An averaging circuit for generating a value, and the averaging circuit from the averaging circuit. Means for supplying a value as a comparison level to the clock signal input buffer and the data signal input buffer, respectively, wherein the clock wiring and the data wiring between the master chip and the slave chip have the same material and the same cross section. An interface circuit having the same shape and the same length, wherein the clock signal input buffer and the data signal input buffer have the same characteristics as each other. 2. The method according to claim 1, wherein the clock wiring and the data wiring are formed from the master chip to the respective termination circuits, and a plurality of the slave chips are provided therebetween while being connected thereto. The interface circuit according to claim 1, wherein 3. The clock wiring and the data wiring are provided linearly in one direction from the master chip to the slave chip.
Interface circuit as described. 4. The interface circuit according to claim 1, wherein the clock wiring and the data wiring have a similar bent shape and are provided from the master chip to the slave chip. 5. When one of the clock wiring and the data wiring has a detour shape bypassing a wiring obstacle, the other wiring having no wiring obstacle also has the same detour shape. The interface circuit according to claim 1, wherein 6. The circuit according to claim 1, wherein the clock signal input buffer and the data signal input buffer have the same circuit configuration including a differential amplifier having the same characteristics and a buffer having the same characteristics. Interface circuit. 7. The same circuit configuration in which the differential amplifiers in the clock signal input buffer and the data signal input buffer include a resistor having the same characteristics, a field effect transistor having the same characteristics, and a constant current source circuit having the same characteristics. 7. The interface circuit according to claim 6, wherein said buffer in said clock signal input buffer and said buffer in said data signal input buffer have field effect transistors having the same characteristics and have the same circuit configuration. .