JP2000049343A - Semiconductor device - Google Patents

Abstract

(57) Abstract: A fixed potential insulating electrode 6 comprising an insulating film 5 formed in a U-shaped groove and a MOS type electrode 4 surrounded by the insulating film 5, wherein the MOS type electrode is fixed to a source potential. In a semiconductor device having a gate region 8 which is not in contact with the source region 3, the reverse bias withstand voltage between the gate and the source is improved. In the semiconductor device having the fixed potential insulating electrode, the drain region is provided at an end of a first groove having the fixed potential insulating electrode in a state where the drain region and the source region are cut off. In order to alleviate the concentration of the electric field from the main surface, there is a second groove facing the main surface, in contact with the gate region 8 and not in contact with the first groove and the source region 3. Is a semiconductor device having a first floating electrode 16 composed of a second MOS type electrode 14 insulated from a drain region 2 and a gate region 8 by a second insulating film 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar type vertical power device.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 6-252408 filed by the present applicant is cited as a background art of the present invention. 8 and 9 are structural views of the semiconductor device cited from the above publication. It should be noted that the numbers and the names of parts in the drawings are appropriately changed and described for explanation. FIG. 8 is a perspective view illustrating the basic structure, and FIG. 9 is a sectional view of the same side as FIG. FIG. 9 shows two units of the basic structure shown in FIG.

In the figure, reference numeral 51 denotes an n ⁺ type substrate region,
52 is an n-type drain region, 53 is an n ⁺ -type source region, 54 is a MOS electrode, and 55 is an insulating film. MOS
The mold electrode 54 is made of high concentration p ⁺ -type polysilicon. 6
Reference numeral 1 denotes a drain electrode, which is in ohmic contact with the substrate region 51. A source electrode 63 is in ohmic contact with the source region 53 and the MOS electrode 54. That is, the MOS type electrode 54 is fixed at the source potential. Therefore, the MOS type electrode 54 and the insulating film 55
Are collectively referred to as “fixed potential insulating electrode” 56. The cross-sectional structure of the fixed potential insulating electrode has a side wall formed in a substantially vertical groove, for example, like a letter "U". Further, the drain region 52 sandwiched between the fixed potential insulating electrodes 56 is called a channel region 57.

Further, the source region 5 is in contact with the insulating film 55.
A p-type gate region 58 is present at a position distant from 3. In FIG. 9, reference numeral 68 denotes an electrode in ohmic contact with the gate region 58, which is called a "gate electrode". Note that 60
Is an interlayer insulating film. The “dashed line” in the drawing indicates the presence of the fixed potential insulating electrode 56 in the depth direction of the paper as can be seen from the relationship with FIG.

In this device, for example, the source electrode 63 is grounded (to 0 V), and the drain electrode 61 is used by applying an appropriate positive potential via a load. When the gate electrode 68 is grounded or a negative potential is applied, a depletion layer associated with the built-in potential of the MOS type electrode 54 is formed around the fixed potential insulating electrode 56 and the channel region 57
In this case, a sufficient potential barrier for conduction electrons is formed by the depletion region, so that the element is cut off. When a positive potential is applied to the gate electrode 68, the potential of the p-type gate region 58 rises, holes flow into the interface of the insulating film 55, and an inversion layer is formed. Since the inversion layer shields the electric lines of force from the MOS-type electrode 54 and p ⁺ -type to the channel region 57, the depletion region open channel is reduced or disappears, becomes conductive. Further, when the potential applied to the gate electrode 68 is increased, the gate region 58
And a pn junction formed by the surrounding n-type region is in a forward bias state, and holes are directly injected into the drain region 52 and the channel region 57. Since these n-type regions are formed with a low impurity concentration in order to maintain the breakdown voltage or the blocking property of the channel, the conductivity is improved when a large amount of holes are injected, and the electrons emitted from the source region 53 It moves to the substrate region 51 with high conductivity. That is, the n-type region is in a high-level injection state, and the drain current flows with a low resistance.

[0006]

In order to switch the above-mentioned element from the conductive state to the cut-off state, the potential of the gate electrode 68 is changed from a positive potential to a negative (or ground) potential. The magnitude of the negative potential applied to the gate electrode 68 is determined by the gate potential at which avalanche breakdown occurs between the gate and the source when the source electrode 63 is grounded and a negative potential is applied to the gate electrode 68 (hereinafter referred to as “gate potential”). / Reverse bias withstand voltage between sources). Therefore, the reverse bias withstand voltage between gate and source should be as large as possible. In this conventional structure, when a reverse bias is applied between the gate electrode 68 and the source electrode 63, the fixed potential insulating electrode 56 fixed to the source electrode 63
Are in contact with the gate region 58, so that the fixed potential insulating electrode 56 is in contact with the gate region 58.
When the electric field in the vicinity of the insulating film 55 reaches a critical electric field even if the magnitude of the reverse bias voltage is small, avalanche breakdown occurs there. That is, in this conventional structure, there is a limit in improving the "gate / source reverse bias breakdown voltage".

The present invention focuses on the above problems,
It is an object of the present invention to provide a semiconductor device having a high “gate / source reverse bias withstand voltage”.

[0008]

Means for Solving the Problems In order to achieve the above-mentioned object, the present invention has a configuration as described in the claims. That is, according to the first aspect of the present invention, the same conductivity type (here, n type) is in contact with one main surface of one conductivity type (for example, n type) semiconductor substrate which is a drain region.
And a first groove arranged in contact with the main surface and sandwiching the source region. Generally, two grooves are required to sandwich the source region, but they may be sandwiched by a single U-shaped groove.

A fixed potential insulating electrode insulated from the drain region by a first insulating film and kept at the same potential as the source region is provided inside the first groove. The electrode is made of a conductive material (for example, p-type polysilicon) having a work function that forms a depletion region in the drain region adjacent via the first insulating film. And a channel region that is part of the drain region that is in contact with the source region and that is sandwiched between the fixed potential insulating electrodes. Furthermore, the semiconductor device has a gate region of the opposite conductivity type (for example, p-type) facing the main surface and not in contact with the source region. Further, in a state where the drain region and the source region are cut off, in order to reduce the concentration of an electric field from the drain region at the end of the first groove, the drain region faces the main surface and contacts the gate region. A second groove that does not contact the first groove and the source region, and is insulated from the drain region and the gate region by a second insulating film inside the second groove. It has a configuration having a first floating electrode. In addition, the above-described configuration is, for example, shown in FIGS.
Corresponding to

The operation of such a configuration will be described. When a voltage near the voltage at which avalanche breakdown occurs is applied between the gate region and the source region in a reverse bias state, the potential of the first floating electrode becomes (1) the potential of the first floating electrode and the gate. And (2) the capacitance between the first floating electrode and the fixed potential insulating electrode and (3) the capacitance between the first floating electrode and the drain region. (4) the potential of the second insulating film interface in contact with the drain region, (5) the potential of the source region, and (6) the potential of the gate region. Naturally determined from the relationship,
The first floating electrode has a potential between the potential of the gate region and the potential of the source region. Then, a portion where the lines of electric force are dense between the gate region and the source region includes: (a) the second insulating film of the first floating electrode in contact with the gate region;
A second insulating film facing the first floating electrode and the fixed potential insulating electrode, (c) a first insulating film, and (d)
The drain region sandwiched therebetween. That is, since there are a plurality of portions where the lines of electric force are dense between the gate region and the source region, the breakdown voltage between the gate region and the source region is improved. Further, at the time of turn-off, a strong inversion layer is formed at the interface between the first floating electrode and the second insulating film, and the mobility of minority carriers is improved, so that the switching speed is improved.

Further, in the invention according to claim 2,
In the configuration of claim 1, in the cutoff state, facing the main surface, to reduce the concentration of the electric field from the drain region at the end of the first groove and the end of the second groove, A third groove not in contact with the first groove and the second groove and the source region and the gate region, and a third insulating film inside the third groove; And a second floating electrode insulated from the second floating electrode. This configuration corresponds to, for example, FIG. 5 described later.

The operation of such a configuration will be described. When a voltage near the voltage at which avalanche breakdown occurs is applied in a reverse bias state between the gate region and the source region, the potential of the first floating electrode and the potential of the second floating electrode are
(7) the capacitance between the first floating electrode and the gate region and (8) the capacitance between the first floating electrode and the second floating electrode and (9) the capacitance between the first floating electrode and the second floating electrode. (10) the capacitance between the two floating electrodes and the fixed potential insulating electrode and (10) the capacitance between the first floating electrode and the interface of the second insulating film in contact with the drain region and ( 11) a capacitance relationship between the second floating electrode and the third insulating film interface in contact with the drain region;
(12) the potential of the interface of the second insulating film in contact with the drain region and (13) the potential of the interface of the third insulating film in contact with the drain region, and (14) the potential of the source region and (15) In this configuration, the potential of the first floating electrode becomes a potential between the potential of the gate region and the potential of the second floating electrode, and the potential of the second floating electrode becomes the potential of the second floating electrode. The potential of the floating electrode is a potential between the potential of the first floating electrode and the potential of the source region. Then, between the source region and the gate region, a portion where lines of electric force are dense is (e) the second insulating film of the first floating electrode in contact with the gate region, and (f) the second insulating film. One floating electrode, a second insulating film facing the fixed potential insulating electrode, (g) a first insulating film, and (h) the drain region sandwiched therebetween.
(I) a third insulating film facing the second floating electrode and the first floating electrode, (j) a second insulating film, and (k) the drain region sandwiched therebetween.
(L) a second insulating film in which the second floating electrode and the fixed potential insulating electrode face each other, (m) a first insulating film, and (n) the drain region interposed therebetween, and the lines of electric force are dense. , The breakdown voltage between the gate region and the source region is further improved.

Further, in the invention according to claim 3,
In the configuration of claim 2, the floating electrode is connected to the gate region. This configuration corresponds to, for example, FIG. 6 described later.

The operation of the above configuration will be described. The potential of the first floating electrode is the same as the potential of the gate region, and the shape of the first floating electrode and the second floating electrode facing each other, and the second floating electrode and the fixed potential insulation Since the shapes of the electrodes facing each other are equal, the capacitance between the first floating electrode and the second floating electrode and the static capacitance between the second floating electrode and the fixed potential insulating electrode are different. Electric capacity is equal. That is,
The distribution of lines of electric force in the region where the second floating electrode and the first floating electrode face each other is equal to the distribution of lines of electric force in the region where the first floating electrode and the fixed potential insulating electrode face each other. , Withstand voltage is improved.

Further, in the invention according to claim 4,
In the configuration of claims 1 to 4, adjacent grooves among the first groove, the second groove, and the third groove are not in the same straight line, that is, are in the vicinity. The ends of the two grooves are not facing each other,
It is configured to be disposed so as to face the drain region. This configuration corresponds to, for example, FIG. 7 described later.

The operation of such a configuration will be described. In this structure, the facing area of the two electrodes in the vicinity of the fixed potential insulating electrode, the first floating electrode, and the second floating electrode increases, so that the capacitance between the electrodes increases, The potential of one floating electrode is not affected by the drain potential and becomes more stable.

[0017]

According to the structure of the first aspect, the "gate / source reverse bias withstand voltage" is improved. Further, the turn-off speed is improved. In the configuration of claim 2, the "gate / source reverse bias withstand voltage" is further improved as compared with claim 1. In the configuration of claim 3, the "gate / source reverse bias withstand voltage" is further improved as compared with claim 2. In the configuration of the fourth aspect, the potentials of the first floating electrode and the second floating electrode are less likely to be affected by the potential of the drain region, and the reliability is improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS.
FIG. 1 is a diagram showing a first embodiment of the present invention. This corresponds to claim 1. 1 is a perspective view illustrating the basic structure of the element, FIG. 2 is a cross-sectional view showing the same portion as the front surface of FIG. 1, FIG. 3 is a surface view showing the same portion as the front surface of FIG. 1, and FIG. It is the same sectional view as. FIG. 2 is a cross-sectional view taken along the line AA in the front view of FIG. 3 and perpendicular to the paper surface, and FIG. 4 is a cross-sectional view taken along the line BB. 3 and 4 both show two units of the basic structure shown in FIG. FIGS. 1 and 3 show a state where the metal film (the source electrode 13 and the gate electrode 18) and the surface protection film (the interlayer insulating film 60), which are the electrodes on the surface, are removed for explanation. In this embodiment, the semiconductor will be described as silicon.

First, the element structure will be described. First, in FIGS. 1 to 4, reference numeral 1 denotes an n ⁺ -type substrate region, 2 denotes an n ⁻ -type drain region, 3 denotes an n ⁺ -type source region, and 4 denotes a first M region.
The OS type electrode 5 is a first insulating film. The first MOS type electrode 4 is made of high-concentration p ⁺ type polysilicon. Reference numeral 11 denotes a drain electrode, which is in ohmic contact with the substrate region 1. Reference numeral 13 denotes a source electrode, which is in ohmic contact with the source region 3 and the first MOS type electrode 4. That is, the first MOS type electrode 4 is fixed at the source potential. Therefore, the first MOS type electrode 4 and the first insulating film 5 are collectively referred to as a “fixed potential insulating electrode” 6. As shown in FIG. 2, the cross-sectional structure of the fixed potential insulating electrode 6 is such that the side wall is formed in a substantially vertical groove, for example, like a letter "U". Although the source region 3 is drawn in contact with the first insulating film 5 in the drawing, the source region 3 may not be in contact if the source region 3 is arranged so as to be sandwiched between the fixed potential insulating electrodes 6. . Further, in FIG. 2, the drain region 2 sandwiched between the fixed potential insulating electrodes 6 is called a channel region 7. The configuration up to here is the same as that of the above-described conventional example.

Further, in the present invention, as shown in FIGS. 1 and 4, a p-type gate region 8 exists at a position away from the source region 3. In FIG. 4, reference numeral 18 denotes an electrode which makes ohmic contact with the gate region 8 and is called a “gate electrode”. Then, as shown in FIGS. 1 and 3, the source region 3 and the fixed potential insulating electrode 6 are in contact with the gate region 8.
And a first floating electrode 16 formed by a second MOS type electrode 14 not in contact with the second MOS type electrode 14 and a second insulating film 15 for insulating it from the drain region 2. This first floating electrode 16 is
0 also insulates the surface.

The cross-sectional structure of the first floating electrode 16 is, like the fixed potential insulating electrode 6, formed in a substantially vertical groove like a "U". The second MOS type electrode 14 may be made of the same conductive material as the first MOS type electrode 4, that is, for example, high-concentration p ⁺ type polysilicon. Further, the second insulating film 15 may be the same as the first insulating film 5. Also, the “dashed line” in FIG. 4 indicates the existence of the fixed potential insulating electrode 6 and the first floating electrode 16 in the depth direction of the paper as can be seen from the relationship with FIG. 1 and 4, the ends of the fixed potential insulating electrode 6 and the first floating electrode 16 are drawn at right angles, but the shape of the end may be polygonal or curved. .

The potential of the first floating electrode 16 is determined by the potential distribution around the first floating electrode 16 and the magnitude of the capacitance with the surroundings. That is, for example, the potential of the interface of the second insulating film 15 in contact with the gate region 8 is V1, the potential of the fixed potential insulating electrode 6 is V2, and the second insulating film in contact with the drain region 2 and facing the drain electrode 11. The potential at the interface of the film 15 is V3, the capacitance between the first floating electrode 16 and the interface of the second insulating film 15 in contact with the gate region 8 is C1, the first floating electrode 16 and the fixed potential insulating electrode 6 Let C2 be the capacitance between the first floating electrode 16 and the interface of the second insulating film 15 in contact with the drain region 2, which is affected by the drain electric field. The potential V of the floating electrode 16 is a potential that satisfies the relational expression of C1 × (V−V1) + C2 × (V−V2) + C3 × (V−V3) = 0 (Equation 1).

Next, the operation will be described. In this element, for example, the source electrode 13 is grounded (0 V) and the drain electrode 1
1 is used by applying an appropriate positive potential via a load. First, when a negative potential is applied to the gate electrode 18, the element is in a cutoff state. In the following, referring to FIG. 2, a depletion layer is formed around the fixed potential insulating electrode 6 due to the built-in potential of the first MOS type electrode 4. If the distance between the potential insulating electrodes 6 (hereinafter referred to as “channel thickness H”) is sufficiently small, a sufficient potential barrier for conduction electrons is formed in the channel region 7 by the depletion region. For example, if the thickness of the first insulating film 5 is 10
0 nm or less, the impurity concentration of the channel region 7 is 1 × 10 ¹⁴
cm ~ ³ or less, by setting the "Channel Thickness H" to 2μm or less, the conduction electrons of the source region 3 is formed a sufficient potential barrier to be moved through the channel region 7 to the drain region 2 side Can be. The distance from the source region 3 to the bottom of the fixed potential insulating electrode 6 (hereinafter, referred to as “channel length L”) so that the potential barrier does not decrease due to the influence of the electric field from the drain region 2. ) Is 2-3 of the channel thickness H.
It is set to more than twice.

In this embodiment, the gate electrode 18
In order to improve the voltage at which avalanche breakdown occurs between the gate and the source when a reverse bias is applied between the gate electrode and the source electrode 13 (this is referred to as “gate / source reverse bias breakdown voltage”) as compared with the conventional structure. Under the condition that a voltage close to the “gate / source reverse bias withstand voltage” is applied between the gate electrode 18 and the source electrode 13, at least the first floating electrode 16 Is set to be a potential between the gate potential and the source potential. That is, under the condition that the source electrode 13 is grounded, the drain electric field affects the second floating electrode 16 in contact with the first floating electrode 16 and the drain region 2 so that the potential of the first floating electrode 16 does not become a positive potential. The capacitance C3 between the interface and the interface of the insulating film 15 is set.

By the way, in this embodiment, the drain region 2 is made to have a high resistance, and in a cut-off state, a potential distribution is generated in a depletion layer extending to the drain region 2. The potential V3 at the interface between the second insulating film 15 and the interface 11 is smaller than the potential applied to the drain electrode 11. For example, assuming that the second insulating film 15 is formed of an oxide film, the dielectric constant is ε _OX , the electric field spreading over the second insulating film 15 is E _OX , and the electric field of the drain region 2 at the interface of the first floating electrode 16 is Assuming that the dielectric constant is ε _SI and the electric field that spreads to the drain region 2 at the interface of the first floating electrode 16 is E _SI , the following equation (2) is established from the electric flux continuity equation.

Ε _OX × E _OX = ε _SI × E _SI (Equation 2) For example, if the impurity concentration of the drain region 2 is 1 × 10 ¹⁴ cm ³
The gate region 8 and the source region 3 are grounded, a predetermined voltage is applied to the drain electrode 11, and the drain region 2
When the avalanche breakdown occurs at the junction surface between the gate electrode 8 and the gate region 8, the electric field strength at the portion where the avalanche breakdown occurs is approximately 2.4 × 10 ⁵ V / cm. At this time, for example, if the depth of the first floating electrode 16 is equal to the depth at which the avalanche breakdown occurs, the electric field that spreads to the drain region 2 at the interface of the first floating electrode 16 in the above (Equation 2) E _SI is about avalanche electric field 2.
Since it is equal to 4 × 10 ⁵ V / cm, the electric field E _OX spreading to the second insulating film 15 is approximately 7.4 × 10 ⁵ V / cm.
cm. Further, the thickness of the second insulating film 15 is, for example, 1000 ° and the second MOS type electrode 14
Is 0 V, the potential of the drain region 2 at the interface of the first floating electrode 16 is at most about 7.4 V.

From this, for example, the potential V1 at the interface of the second insulating film 15 in contact with the gate region 8 is about -5 V, the potential V2 of the grounded fixed potential insulating electrode 6 is about 0 V, Assuming that the potential V3 at the interface of the second insulating film 15 facing the drain electrode 11 is about 8 V, from the above equation (1), (C1 + C2 + C3) * V = 8 * C3-5 * C1. That is, when the potential V1 at the interface of the second insulating film 15 in contact with the gate region 8 is set to about −5 V,
If the capacitance C1 is at least 1.6 times the capacitance C3, the potential of the first floating electrode 16 becomes a negative potential and becomes a potential between the gate potential and the source potential. That is, under the condition that the fixed potential insulating electrode 6 is grounded, it is only necessary to design such that C1 and C3 satisfy C1> (C3 × V3) / V1.

By optimally designing the structure of the first floating electrode 16, it is easy to change the ratio of the capacitance to each region. For example, if the thickness of the second insulating film 15 of the first floating electrode 16 is uniform on the side wall and the bottom surface, the first floating electrode 16 and the interface of the second insulating film 15 in contact with the gate region 8 may be formed. The ratio of the capacitance C1 between the first floating electrode 16 affected by the drain electric field and the capacitance C3 between the interface of the second insulating film 15 in contact with the drain region 2 is: The ratio of the area of the bottom surface of the first floating electrode 16 in contact with the drain region 2 to the size of the surface area of the first floating electrode 16 in contact with the gate region 8 is substantially equal. As described above, under the condition that the reverse bias voltage is applied between the gate and the source, under the condition that the potential of the first floating electrode 16 is a potential between the gate potential and the source potential, the gate region 8 and the source region 3 Are the lines of electric force caused by the potential difference between the gate region 8 and the first floating electrode 16, and the fixed potential insulating electrode 6 connected to the first floating electrode 16 and the source region.
And electric lines of force caused by the potential difference of In the former, the lines of electric force of the second insulating film 15 where the gate region 8 and the first floating electrode 16 are in contact with each other become dense. For the latter, the first floating electrode 16
Of the second insulating film 15, the first insulating film 5, and the drain lines 2 sandwiched between the two insulating films in the region where the fixed potential insulating electrode 6 faces. As described above, in this embodiment, even when a reverse bias is applied between the gate and the source, there are a plurality of portions where the lines of electric force are dense without being concentrated on a part. In other words, a reverse bias voltage can be applied between the gate and the source until any part of the region where the electric flux lines become dense reaches the critical electric field.
An element having a high "gate / source reverse bias withstand voltage" can be obtained.

Next, in a conductive state, when a positive potential of +0.5 V, for example, is applied as the potential of the gate electrode 18, that is, the potential of the p-type gate region 8, holes are conversely formed in the p-type gate region 8. Flows into the interface of the first insulating film 5 to form an inversion layer, and shields the lines of electric force from the first MOS type electrode 4 forming the potential barrier to the channel region 7. Lowers the potential barrier to conduction electrons. At this time, since the first floating electrode 16 is always at a positive potential, the potential barrier at the interface of the second insulating film 15 has disappeared, and there is no difference from the operation in the conventional structure. That is, the drain region 2 and the source region 3 are brought into conduction. When the potential of the gate electrode 18 is further increased, the pn junction formed by the p-type gate region 8 and the surrounding n-type region is forward-biased, and holes are directly injected into the drain region 2 and the channel region 7. As a result, the conductivity of these n-type regions, which have been made low in impurity concentration and high in resistance in order to maintain the withstand voltage of the device, is increased, and current flows with low resistance.

Next, turn-off will be described. When a negative potential is applied to the gate electrode 18 in order to turn off the element in the conductive state, excess holes in the drain region 2 and the channel region 7 start flowing into the p-type gate region 8. Eventually, the excess holes in the channel region 7 disappear, and the potential barrier for electrons is restored. At this time, similarly to the cutoff state, the first floating electrode 1
The potential V of 6 becomes a negative potential. That is, since a strong inversion layer is formed at the interface between the first floating electrode 16 and the second insulating film 15 and the mobility of minority carriers is improved, the switching speed is improved.

(Second Embodiment) FIG. 5 is a diagram showing a second embodiment. This is a surface view of the element corresponding to FIG. 3, and the same numbers in the figure indicate the same elements.
As shown in FIG. 5, a second floating electrode 26 is provided between the fixed potential insulating electrode 6 and the first floating electrode 16.
Exists. The second floating electrode 26 is composed of a third MOS type electrode 24 and a third insulating film 25 and has basically the same structure as the fixed potential insulating electrode 6 and the first floating electrode 16. However, FIG. 5 illustrates a case where the surface shape is T-shaped.

When the source electrode 13 is grounded and a negative potential is applied to the gate electrode 18 so that the gate region 8 and the source region 3 are in a reverse bias state, the potential of the first floating electrode 16 and the second Of the floating electrode 26 of the second insulating film 1 in contact with the gate region 8
5, the potential of the fixed potential insulating electrode 6, the potential of the interface of the second insulating film 15 in contact with the drain region 2, the potential of the interface of the third insulating film 25 in contact with the drain region 2, A capacitance between one floating electrode 16 and the gate region 8, a capacitance between the first floating electrode 16 and the second floating electrode 26, and a fixed potential insulation from the second floating electrode 26. The capacitance between the electrode 6, the capacitance of the second insulating film 15 that is in contact with the drain region 2 and faces the drain electrode 11, and the third insulation that faces the drain electrode 11. The potential is naturally determined from the relationship with the capacitance of the film 25. Then, the respective potentials of the first floating electrode and the second floating electrode are expressed as: source potential <potential of the second floating electrode 26 <potential of the first floating electrode 16 <
At least the capacitance between the first floating electrode 16 and the gate region 8 is in contact with the drain region 2 and the capacitance of the second insulating film 15 facing the drain electrode 11 so as to satisfy the relationship of the gate potential. Greater than the capacity, and
The capacitance between the second floating electrode 26 and the first floating electrode 16 is larger than the capacitance of the third insulating film 25 facing the drain electrode 11.

As a result, the portion where the lines of electric force between the gate region 8 and the source region 3 become denser is the portion of the second insulating film 1 of the first floating electrode 16 which is in contact with the gate region 8.
5, the third insulating film 25 facing the second floating electrode 26 and the first floating electrode 16, the second insulating film 15, the drain region 2 interposed therebetween, and the first floating electrode 16 The potential insulating electrode 6 becomes the second insulating film 15 and the first insulating film 5 facing each other, and the drain region 2 sandwiched therebetween. That is, the number of places where the lines of electric force are denser between the gate region 8 and the source region 3 is further increased as compared with the first embodiment, so that the “gate / source reverse bias breakdown voltage” is further improved.

In FIG. 5, the shape of the second floating electrode 26 is T-shaped, but by doing so, the capacitance between the first floating electrode and the second floating electrode is reduced. Has the effect of increasing

Next, FIG. 6 is a diagram showing a third embodiment. This is a surface view of the device corresponding to FIG. 5,
The same numbers in the drawings indicate the same elements. In FIG. 6, the first floating electrode 16 is a gate electrode 18
(Not shown in FIG. 6, but present above the gate region 8), and the potential of the first floating electrode 16 becomes the same potential as the gate potential.

With this structure, as in the second embodiment, the source electrode 13 is grounded so that the gate region 8 and the source region 3 are in a reverse bias state, and the gate electrode 18 has a negative potential. Is applied, the portion where the line of electric force between the gate and the source becomes dense is the third insulating film 25 and the second insulating film 15 where the second floating electrode 26 and the first floating electrode 16 face each other. The drain region 2 sandwiched between the first floating electrode 16 and the fixed potential insulating electrode 6 faces the second insulating film 15 and the first insulating film 5 and the drain region 2 sandwiched therebetween. At this time,
When the shape of the region where the second floating electrode 26 and the first floating electrode 16 face and the shape of the region where the first floating electrode 16 and the fixed potential insulating electrode 6 face are the same, the respective capacitances are equal. That is, the electric field distribution in the region where the second floating electrode 26 and the first floating electrode 16 face each other is almost equal to the electric field distribution in the region where the first floating electrode 16 and the fixed potential insulating electrode 6 face each other. / Reverse bias breakdown voltage between sources ”is further improved.

Next, FIG. 7 is a diagram showing a fourth embodiment. This is a front view of the element corresponding to FIG. 6, and the same reference numerals in the drawing indicate the same elements. In the fourth embodiment, the first floating electrode 16 is not arranged on the same straight line as the fixed potential insulating electrode 6 with respect to the first embodiment, and faces the channel region 7. Structure.

With this structure, the facing area between the first floating electrode 16 and the fixed potential insulating electrode 6 can be increased up to √2 times at the maximum. 6 can be increased up to √2 times at the maximum. This makes the potential of the first floating electrode more stable without being affected by the drain potential.

[Brief description of the drawings]

FIG. 1 is a perspective view of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a surface structure according to the first embodiment of the present invention.

FIG. 4 is a sectional view of the first embodiment of the present invention viewed from another angle.

FIG. 5 is a front view of the second embodiment of the present invention.

FIG. 6 is a front view of a third embodiment of the present invention.

FIG. 7 is a front view of a fourth embodiment of the present invention.

FIG. 8 is a perspective view of a conventional example of the present invention.

FIG. 9 is a sectional view of a conventional example of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 substrate region 2 drain region 3 source region 4 first M
OS type electrode 5 ... first insulating film 6 ... fixed potential insulating electrode 7 ... channel region 8 ... gate region 10 ... interlayer insulating film 11 ... drain electrode 13 ... source electrode 14 ... second MOS type electrode 15 ... second Insulating film 16 First floating electrode 18 Gate electrode 24 Third MOS electrode 25 Third insulating film 26 Second floating electrode 51 n ⁺ type substrate region 52 n type drain region 53 ... n ⁺ type source region 54 ... MOS
Type electrode 55 ... Insulating film 56 ... Fixed potential insulating electrode 57 ... Channel region 58 ... P-type gate region 60 ... Interlayer insulating film 61 ... Drain electrode 63 ... Source electrode 68 ... Gate electrode H ... Channel thickness L ... Channel length

Claims (4)

[Claims] A first conductive type source region which is in contact with one main surface of a semiconductor substrate of one conductivity type which is a drain region, and which is arranged so as to be in contact with said main surface and sandwich said source region. A fixed potential insulating electrode which is insulated from the drain region by a first insulating film and is kept at the same potential as the source region inside the first groove; The potential insulating electrode is made of a conductive material having a work function such that a depletion region is formed in the drain region adjacent via the first insulating film, and is a part of the drain region in contact with the source region. Having a channel region sandwiched by the fixed potential insulating electrodes, having a gate region of opposite conductivity type facing the main surface and not in contact with the source region, further comprising the drain region and the source region Is blocked In this state, the first groove and the source region face the main surface and contact the gate region so as to reduce the concentration of the electric field from the drain region at the end of the first groove. A second floating groove that is not in contact with the first groove and a first floating electrode insulated from the drain region and the gate region by a second insulating film inside the second groove. Semiconductor device. 2. In the cut-off state, the first groove and the second groove face the main surface so as to reduce the concentration of an electric field from the drain region at the end of the second groove and the end of the second groove. A third groove that does not contact the first groove and the second groove, the source region, and the gate region, and is insulated from the drain region by a third insulating film inside the third groove; Having a second floating electrode,
The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 2, wherein said first floating electrode is connected to said gate region. 4. The semiconductor device according to claim 1, wherein adjacent grooves among said first groove, said second groove and said third groove are arranged so as not to be on the same straight line. The semiconductor device according to claim 1.