JP2000047995A - Parallel processing method and apparatus, and visual inspection apparatus using the same - Google Patents

Abstract

(57) [Problem] To efficiently distribute data to each processor and maintain a high operation rate of the processor. SOLUTION: Input data D is divided into partial data A at a data input unit 1 and transferred to a PE (processor element) 6 via a bus 2. Each PE6, for example PE6b
Receives the data input permission signal C transmitted from the transmission unit 9 of the PE 6a having a higher priority, and when the data input permission signal C indicates the permission of data capture, the partial data from the data bus 2 A is fetched from the input I / F 11 and is processed by the processor 7 using the memory 8. The processed partial data A is transferred from the output I / F 12 to the data output unit 5 via the bus 3. PE6b
Is a data input enable signal C indicating its own state such as a data input wait state, a data fetch state, and a data processing state.
Is transmitted from the transmission unit 9 to the PEs 6c of lower priority.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing device capable of performing data processing in parallel and a visual inspection device using the same, and more particularly, to a plurality of signal processing processors (hereinafter, processors). By realizing high-speed data processing by allocating data processing to each and performing data processing in parallel, high-speed data such as image data and capturing a large amount of detected data, at the same time, The present invention relates to a parallel processing method and apparatus suitable for the case where it is necessary to process the data, and a visual inspection apparatus using the same.

[0002]

2. Description of the Related Art Conventionally, as a parallel processing apparatus for performing parallel processing of data using a plurality of processors, information such as the operating state of each processor is concentrated in order to improve the operation rate of such processors and thereby enhance the operation performance. For example, Japanese Patent Laid-Open Publication No. 3-177951 has proposed a parallel processing apparatus having a management unit for managing and determining which processor should process data to be processed next based on the information. . Information such as the operating status of each processor
For example, information that indicates whether the processor is processing, waiting for processing data, or outputting a calculation result, and how long the data processing currently being performed will end. And information predicted at that time.

FIG. 11 is a block diagram showing such a conventional parallel processing apparatus, in which 100 is a data input unit, 101 is an input bus, 102 is an output bus, 103 is a data output unit,
104 is a processor, 105 is a memory, 106 is a status register, and 107 is a management unit.

In FIG. 1, a data input unit 100 is for inputting data from the outside, and the input data is transferred to a processor 104 via an input bus 101. The processor 104 processes this data using the memory 105. The data processing result in each processor 104 is transferred via the output bus 102 and stored in the data output unit 103. The processor 104 processes the received data, and the memory stores data necessary for the processing performed by the processor 104.

The status register 106 stores information for each processor 104.
And is connected to each processor 104. The management unit 107 determines which processor 104 should process the next input data by referring to the contents of the status register 909, and notifies each processor 104 of the result.

In such a configuration, the processor 104 fetches data from the input bus 101 and performs processing only when instructed by the management unit 107 to fetch and process the next data to be transferred. Is completed, the operation result is transferred to the data output unit 103 via the output bus, and thereafter, the status register 10
6 is notified that the transfer of the operation result has been completed and that the next data can be fetched.

On the other hand, the management unit 107
6 is constantly monitored, and when it finds a processor 104 that is ready to take in the next data, it informs the processor 104 that the next data should be taken in and processed.

As described above, by managing the state of each processor 104 by the management unit 107, priority is given to the processor 104 which has completed the processing earlier because the processing time is shorter than the processing time of the other processors 104. Can be given the following data,
04 can be reduced, and the operating rate of the processor of the entire parallel processing apparatus can be improved.

[0009]

However, in the above-mentioned prior art, a large amount of data input at high speed, for example,
There is a problem when processing a large amount of data detected by an image detector such as a video camera or an image sensor in real time.

That is, in such a case, the processing target is image data that is input at a fixed time interval based on a synchronization signal given to an image detector such as a video camera or an image sensor. It is necessary to perform processing without fail and to finish the process up to output of the calculation result within a predetermined time. In the prior art shown in FIG. 11, each processor 104 needs to notify its own status to the status register 106. In order to prevent a situation in which a plurality of processors 104 access the status register 106 at the same time, Arbitrates between the processors 104,
Exclusive control must be performed so that only one processor 104 can access the status register 106. However, the time required for this arbitration depends on the processor 104.
Is a wasteful time for the processor 104, which causes a decrease in the operation rate of the processor 104.

In the management unit 107, the status register 1
06, it is necessary to determine the processor 104 to which the data to be processed next is to be allocated. However, as the number of processors increases, the time required for this determination increases. Processor 10
4 and the parallel processing is carried out, the decision of the processor 104 to take in the data before the next data is transferred cannot be made in time, and data may be missed.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem, to surely process high-speed and large-volume input data such as image data without dropping it, and to improve the operating rate of each processor mounted. Another object of the present invention is to provide a parallel processing method and apparatus having high processing efficiency and a visual inspection apparatus using the same.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method of acquiring data into another processor element for each processor element including a processor for processing data and a circuit for controlling the processor. And a second data input permission signal indicating whether or not to permit taking in of data from another processor element. By adding a receiving unit and connecting the transmitting unit and the receiving unit between the processor elements, a plurality of processor elements are connected in an array,
In addition, all the processor elements are connected to the input bus, and the data input unit transfers the input data to the input bus and, at the same time, transmits the data transfer information defining the data unit to be captured by each processor element to each processor. Each processor element determines whether or not to input data based on the second data input permission reception signal received by itself, this data transfer information and its own state at that time. The first data input permission transmission signal is transferred to another processor element based on the determination result.

This enables each processor element to autonomously input data depending on the state of itself and other processor elements, and manages the operation state of all processor elements. The operation rate of each processor element can be improved without the need for a unit and without causing a dead time such as arbitration between the processor elements.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an overall configuration of an embodiment of a parallel processing method and apparatus according to the present invention, wherein 1 is a data input unit, 2 is an input bus, 3 is an output bus,
4 is a control bus, 5 is a data output unit, 6a, 6b and 6c are processor elements (hereinafter referred to as PEs), 7 is a processor (P), 8 is a local memory (M), and 9 is a data input permission transmission unit (T ), 10 is a data input permission receiving section (R), 11 is an input I / F section, and 12 is an output I / F section.

In FIG. 1, data D input from the outside to a data input unit 1 is transmitted to a plurality of PEs through an input bus 2.
6 (here, three PEs 6a, 6b, 6
Although c is shown, it is not limited to this number. If the PE is not specified, it is referred to as “PE6”.) The processing result of each PE 6 is transferred via the output bus 3 and stored in the data output unit 5.

The PE 6 forms one processing unit including a processor 7, a local memory 8 used by the processor 7 for data processing, and other control circuits.
Here, the local memory 8 is a memory used when the processor 7 performs data processing, and stores data necessary for processing as well as processing programs. The data input permission transmitting section 9 has a function of transmitting information indicating whether or not another PE 6 can take in the input data. The data input permission receiving section 10 allows the own PE 6 to take in the data. It has a function of receiving information indicating whether or not it can be performed from another PE. The input I / F unit 11 performs control for data input, and the output I / F unit 12 controls output of a calculation result.

The data D input from the outside is divided into a plurality of partial data A in the data input section 1 and transmitted to the input bus 2. Then, the data input unit 1 transmits the partial data A and simultaneously transmits the partial data A.
Is transmitted on the input bus 2 during the transmission of
Is transferred to the control bus 4
To each PE 6 via the.

The data input permission receiving section 10 of each PE 6 is connected to the data input permission transmitting section 9 of another PE 6 and receives the data input permission signal C from the data input permission transmitting section 9. That is, the PE 6a receives the data input permission signal C from the data input permission transmission unit 9 of the PE 6 in the preceding stage, not shown, and the PE 6b receives the data input permission signal C from the data input permission transmission unit 9 of the PE 6a. The PE 6c receives the data input permission signal C from the data input permission transmission unit 9 of the PE 6b.

When each of the PEs 6 determines from the data transfer information B and the information content of the data input permission signal C received by the data input permission receiving section 10 and the operation state at that time that the data should be fetched, the input bus 2 to obtain partial data A. Further, the data input permission transmitting section 9 transmits a data input permission signal C to another PE 6 according to the state of the PE 6 at this time.

Therefore, for example, the PE 6b is permitted to fetch data based on the information content of the data input permission signal C from the PE 6a received by the data input permission receiving unit 10 and its own state at this time. When the effective period during which the partial data A is transferred on the input bus 2 is reached due to B, the PE 6b takes in the partial data A whose transfer is started on the input bus 2. When the PE 6b fetches the partial data A, the processor 7 performs predetermined arithmetic processing on the partial data B according to a program stored in the local memory 8 in advance, and outputs the processing result via the output bus 3. The data is transferred to the data output unit 5. This is the other P
The same applies to E6.

The processing performed in each PE 6 can be all the same, or different processing can be given. In each PE 6, data input, data processing, and transfer of the processing result are performed each time data is taken.

FIG. 2 is a diagram showing a specific example of data D input to the data input unit 1. Here, the data D is detected by an image detection device (hereinafter, referred to as a sensor) such as a video camera or an image sensor. Image data is taken as an example.

In FIG. 1, input image data D is image data detected by a sensor, and x,
This is two-dimensional data having a size in the y direction. The input image data D is divided into a plurality of partial image data A in the data input unit 1, and each of the partial image data A is
6 is the processing target. The sizes of the partial image data A may all be the same or may be different. Also,
In FIG. 2, the x-direction size of the partial image data A and the x-direction size of the sensor are the same. However, the present invention is not limited thereto.
Any size can be adopted as long as the size does not exceed the direction size. Further, at the boundary of the partial image data A, the images can be overlapped as necessary.

FIG. 3 is a block diagram showing a specific example of the data input unit 1 in FIG. 1, wherein 1a is a memory, 1b is a switch, 1c is a division information storage unit, 1d is a division control unit, 1e
Is a transfer buffer.

In FIG. 1, image data D from a sensor (not shown), a synchronizing signal SYC synchronized with the image data D, and a data input unit 1 are input. This data input unit 1 is a memory 1
a, switch 1b, division information storage section 1c, division control section 1
d and a transfer buffer 1e. Information necessary for dividing the image data D, such as a predetermined size of the partial image data A, is stored in the division information storage unit 1c. The division control unit 1d stores the synchronization signal SYC and the division information storage unit 1c. A control signal for creating predetermined partial image data B and data transfer information B are generated using the information contents of the above.

Here, the synchronization signal SYC corresponds to the image data D
And a signal indicating a break of one line of an image.

The input image data D is supplied directly to the terminal a of the switch 1b, and after being delayed by a predetermined time in the memory 1a, supplied to the terminal b of the switch 1b.
The switch 1b is normally closed on the terminal a side under the control of the division control unit 1d, and supplies the input image data D supplied to the terminal a side to the transfer buffer 1e. In the transfer buffer 1e, the data of the input image data D is sequentially accumulated, and when all the data constituting one partial image data A are accumulated, the division control unit 1d detects this and stores the data in the transfer buffer 1e. Control this transfer buffer 1
The data stored in e is transferred to the input bus 2 (FIG. 1) as one partial image data A. The division control unit 1d compares the count value of the synchronization signal SYC by the built-in counter or the like with the information stored in the division information storage unit 1c, so that all data constituting one partial image data A is transferred to the transfer buffer. 1e can be determined.

FIG. 4 is a diagram showing the timing relationship between the input image data D, the partial image data A, and the data transfer information B. As shown in FIG.
This is generated intermittently for each partial image data. After one partial image data A has been transferred from the transfer buffer 1e, the next input image data D is generated and sent to the data input unit 1. Sent.

Further, as described above, the division control unit 1d
During the period when the partial image data A is transferred from the transfer buffer 1e to the input bus 2, the data transfer information B is output (the "H" (high level) period of the data transfer information B in FIG. 4) and the control bus 4 (FIG. Transfer to 1).

The memory 1a is used to hold the overlapping portion when it is necessary to make the partial image data overlap each other. Now, in FIG. 2, when an overlapping portion is provided between the partial images A ₁ and A ₂ , the input image data D for the partial image data A ₁ is transferred to the transfer buffer via the switch 1 b which is closed to the terminal a. 1
e, the input image data D is stored in the memory 1a.
Is also supplied. All data of the partial image data A ₁ is stored in the transfer buffer 1e, it is initiated input bus 2 partial image data A ₁ to transfer therefrom, the memory 1a, the required data in the partial image data A ₁ Is held. Then, although the input image data D for the next partial image data A ₂ is initiated input, it switches the switch 1b is on the terminal b at the timing prior to this,
Necessary data is read from the memory 1a, and the switch 1
b, the data is transferred to the transfer buffer 1e. Switch 1b is switched to the terminal a side together with the read completion of the necessary data, the switch 1 from the start of the partial image data A ₂
b, the data is transferred to the transfer buffer 1e. In this way, it is intended to contain the same contents of data between the start portion partial image data A ₁ end portion and the next partial image data A _2, these partial image data A _1, A ₂ overlaps a portion Will have.

Further, if the memory 1a has a large capacity, it is possible to include a plurality of image data having a long time interval in the detection timing in the same partial image data.

FIG. 5 is a block diagram showing a specific example of the PE 6 shown in FIG.
Is a switch circuit, and 15 is a status register. The parts corresponding to those in FIG.

In FIG. 3, the data fetch unit 13, the switch circuit 14, and the status register 15 correspond to the input I / F in FIG.
11 and the other portions correspond to the respective portions in FIG. Here, the data input permission signal received by the data input permission receiving unit 10 from another PE is C1 and the data input permission signal transmitted from the data input permission transmitting unit to the other PE is C2.

The data fetch control unit 13 includes the data transfer information B from the control bus 4 (FIG. 1) and the data input permission receiving unit 1.
In response to the data input permission signal C1 received at 0 and the output information of the status register 15, the control of the capture of the partial image data A from the input bus 2 (FIG. 1) is controlled. The switch circuit 14 is connected between the input bus 2 and the local memory 8, and is controlled on and off by the data acquisition control unit 13. The status register 15 is a PE
6 is stored. Here, the operation state of the PE is roughly classified into “(1) data input wait state”.
And "(2) data processing state". The “data processing state” includes the output processing state of the calculation result.

Here, when the level of the data input permission signal C1 notified from another PE (not shown) is "H", the PE shown in the figure receiving the data input permission signal C1 (hereinafter referred to as another PE). 6 indicates that the capture of the partial image data A is permitted. When the level is “L” (low level), the capture of the partial image data A is permitted. Shall be shown.

In the own PE 6, the data acquisition control unit 1
3 is only when the own PE 6 determines from the received data input permission signal C1, the data transfer information B and the information content of the status register 15 that the partial image data A should be fetched,
A control operation for capturing the partial image data A is performed.

More specifically, the data input permission signal C1 from another PE indicates "H" to indicate that the data fetch is permitted, and the information of the status register 15 indicates that the state of the own PE 6 is "(1)". When it is recognized as “data input waiting state” and the data transfer information B changes from “L” to “H”, the data capture control unit 13 turns on the switch circuit 14. Thereby, under the control of the processor 7,
The partial image data A is written from the input bus 2 to the local memory 8 via the switch circuit 14. Then, the data for one partial image data is stored in the local memory 8, and when the data transfer information B changes from "H" to "L", the data capture control unit 13 turns off the switch circuit 14 to capture the data. And after that, the processor 7
Fetches the partial image data A from the local memory 8 and starts its arithmetic processing. Then, when this arithmetic processing is completed, the processing result is transferred to the output bus 3 (FIG. 1) via the output I / F 12.

The data acquisition control section 13 controls the data input permission transmission section 9 to transmit a data input permission signal C2 corresponding to the information content of the status register 15 to another PE (not shown). Here, (1) when the own PE 6 is in the data input waiting state and the data fetch state, the data input permission signal C2 is set to "L", and the other PEs are informed that the data fetch is not permitted. (2) The data input permission signal C2 is set to "H" when the own PE 6 completes the data fetch. Further, in cases other than the above (1) and (2), the data input permission transmitting section 9 transmits the data input permission signal C1 from another PE received by the data input permission receiving section 10 as it is as a data input permission signal C2. I do.

FIG. 6 is a timing chart showing the above operation of the own PE 6 shown in FIG.

In the figure, at time T1, the own PE 6
Is not in the data input waiting state, and the data input permission signal C1 received by the data input permission receiving unit 10 is "L". It not, is not to capture partial image data a ₁ that is transferred to input bus 2 during a period of time T1 to T2. The partial image data A ₁ is taken up by another PE.

Thereafter, at time T6 until time T2, the data processing is completed and a data input wait state is established (at this time, the data input permission signal C2 transmitted from the data input permission transmission section 9 becomes "L"). , The capture of the partial image data A _{1 by} the other PEs is also completed, and the data input permission signal C 1
Becomes “H”, but since the data transfer information B is “L”, the own PE 6 does not enter the data capturing state. However, at this time, the own PE 6 is in a data input waiting state,
Since the data input enable signal C1 is received is "H", at time T3 the next partial image data A ₂ is transferred via the input bus 2, the same time, the data transfer information B becomes "H", self PE6 captures the partial image data a _2. Then, at time T4, the partial image data A ₂
When the uptake is complete, the self PE6 is starts the processing of the partial image data A _2, the data input enable signal C2 is sent to "H", the prohibit incorporation of the self PE6 of the next partial image data A ₃ At the same time, it is possible to take in other PEs.

As described above, by using the data input permission signal C1 given from another PE, the state of the own PE 6, and the data transfer information B, the control of the data acquisition is performed, and the data acquisition to the other PEs is performed. , Each PE autonomously performs data input and processing.

Next, as shown in FIG. 1, the data input permission signal C transmitted by each PE 6 is transmitted to the data input permission receiving section 10 of another PE 6 to form a one-dimensional array. The operation in the case where the PEs 6 are connected in sequence will be described.

In FIG. 1, the other PE 6 that provides the data input permission signal C to the own PE 6 is referred to as an upstream PE 6, and the other PE 6 to which the own PE 6 provides the input permission signal is referred to as a downstream PE 6. . For example, in the configuration shown in FIG. 1, the PE 6a is connected to the upstream P
E, and PE6c is a downstream PE.

In the most upstream PE 6, the data input permission signal C received by the data input permission receiving section 10 is always “H”, and the P 6 in the data input waiting state.
When a plurality of E6s exist simultaneously, the upstream PE6
Should always take priority over the downstream PE6. In other words, each PE 6 is in a state where the own PE 6 can input data, and the PEs on the upstream side thereof
If No. 6 does not take in data, it becomes possible to take in data.

FIG. 7 is a timing chart showing, as an example, the data fetching and processing order in the three PEs 6a, 6b, 6c connected in a one-dimensional array in the order shown in FIG.

As is clear from FIG. 1, the PE 6a is the most upstream PE and has the highest priority, and the PE 6c is the most downstream PE and has the lowest priority. PE6b
Has an intermediate dominance.

Therefore, in FIG.
6c is in all data input standby state, when the partial image data A ₁ has been transferred to input bus 2, the partial image data A ₁ is received by the highest priority PE6a, arithmetic processing is performed. During data processing in this PE6a, the next partial image data A ₂ is transferred, PE6b in the data input wait state in this case, among 6c, priority higher PE6b this partial image data A ₂ is fetched and arithmetic processing is performed. And these P
E6a, during data processing in 6b, furthermore, when the next partial image data A ₃ coming transferred, remaining PE6c performs arithmetic processing captures the partial image data A _3. In this way, each of the PEs 6a to 6c is arranged in descending order of priority.
Fetches the partial image data A and performs arithmetic processing.

[0050] Then, the calculation processing and output of the processing result of the data is completed PE6b and PE6b is made to the data input wait state, the next partial image data A ₄ in this state is transferred, the data input P in waiting state
Since E is only PE6b, the partial image data A ₄ is taken in this PE6b, it is processing. next,
When the data processing and the output of the processing result are completed in the PEs 6a and 6c, they enter a data input waiting state.
Further the next partial image data A ₅ in such a state comes transferred, PE6a the higher priority captures the partial image data A _5, arithmetic processing.

When the data processed by each PE 6 is image data, even if the processing program of each PE 6 is the same and the size of the partial image data A processed by each PE 6 is the same, Depending on the information content of the data A, the processing time in each PE 6 may be different. Therefore, as shown in FIG. 7, by taking the partial image data A to be processed next preferentially in the PE 6 that has completed the processing, the operation rate of the PE 6 can be effectively increased.

In this case, since each PE 6 outputs the calculation result in the order in which the data processing has been completed,
The partial image data transferred to the data output unit 5 is not always in the transfer order of the partial image data from the data input unit 1 or the data input order of the input image data D. Therefore, when transferring the data of the operation result to the data output unit 5, each PE 6 transfers the data of the operation result in the post-processing such as the data indicating the PE 6 that has processed the data of the operation result or the data input order. Information necessary for rearranging in order is added to the data of the operation result and transferred to the data output unit 5.

In the above-described embodiment, when viewed from the overall apparatus, a PE which is in a data input waiting state is provided without a management unit which collectively manages the operation states of all the PEs as in the related art. On the other hand, data to be processed next can be efficiently distributed, and the processing efficiency of the processor can be increased.

FIG. 8 is a block diagram showing an embodiment of a semiconductor wafer appearance inspection apparatus using a parallel processing apparatus according to the present invention, wherein 16 is a stage, 17 is a semiconductor wafer, 18
Denotes a lens, 19 denotes a linear sensor, and 20 denotes a parallel processing device according to the present invention.

In this embodiment, the appearance of a semiconductor wafer is inspected. In FIG. 8, a semiconductor wafer 17 to be inspected is mounted on a stage 16. The stage 16 can be driven in the x and y directions.
The processed part of the semiconductor wafer 17 is imaged on the linear sensor 19 via the lens 18, and an image of this part is output from the linear sensor 19 as image data D and transferred to, for example, the parallel processing device 20 shown in FIG. Is done. As described above, the parallel processing device 20 has a plurality of PEs 6 so that effective parallel processing of the image data D can be performed.

In general, in the appearance inspection of a semiconductor wafer, the amount of image data D detected by the linear sensor 20 is enormous, and the detection speed of the sensor is also improved. Requires high computing performance. In addition, since the image obtained by detecting the appearance of the semiconductor wafer 17 has a difference in image contrast depending on the detection site, the calculation time required for processing is compared for a plurality of images having different detection sites. However, even if the data size is the same, the processing time may be different. Thus, even when there is a difference in the processing time between the mounted PEs, the PEs can be efficiently processed.
The appearance inspection apparatus is required to exhibit high performance by using the PE, but by using the parallel processing apparatus according to the present invention, the PE can be operated efficiently and the necessary minimum PE can be used.
, A low-cost inspection apparatus with high processing performance can be realized.

The data input unit 1 shown in FIG.
Determines the size of the partial image data A based on the information stored in the division information storage unit 1c. For example, in a semiconductor wafer appearance inspection apparatus as shown in FIG. In some cases, it is necessary to vary the size of the partial image data according to the geometrical characteristics such as the size and shape of the wafer and the pattern of the surface, or the contents of the processing. In such a case, it takes time and effort for the operator to change the information content of the divided information storage unit 1c in FIG.

FIG. 9 is a block diagram showing another embodiment of the data input unit 1 in FIG. 1 in which such a problem has been solved. In FIG. 9, 1f denotes a data division determining unit, and parts corresponding to those in FIG. And duplicate explanations are omitted.

In the figure, a data division determining unit 1f for determining the size of partial image data is provided, and geometrical characteristics such as the size and shape of a semiconductor wafer to be inspected and the pattern of the surface, or processing. When information E indicating inspection conditions such as contents is input, the data division determining unit 1f automatically determines the division information of the input image data D that determines the size of the partial image data conforming to the inspection conditions. The divided information thus stored is stored in the divided information storage unit 1c.

Therefore, in the data input section 1, the division control section 1d operates as described above based on the division information newly stored in the division information storage section 1c, and the division control section 1d has a size suitable for the inspection object at this time. Since the divided image data A is obtained, the operation rate of the PE can be improved.

Although the inspection object is a semiconductor wafer here, the invention is not particularly limited to this, and other inspection objects such as a printed wiring board can obtain the same effects as described above.

The parallel processing device shown in FIG.
Although each of the six is separate, as shown in FIG. 10, a plurality of PEs 6 to be mounted, the input bus 2, the output bus 3, and the like may be formed as an integrated circuit 21. By thus forming an integrated circuit, the operation of each of the PEs 6 can be speeded up, and the speed of communication of the data input permission signal C between the PEs 6 can be increased, so that the speed of data processing can be further increased.

In FIG. 10, the input bus 2, the PE 6, and the output bus 3 are integrated in one integrated circuit 21,
In addition, the data input unit 1 and the data output unit 5 can be integrated on the same integrated circuit. As described above, by using an integrated circuit in which a plurality of PEs are integrated, the entire parallel processing apparatus can be compactly realized even for an application requiring a large amount of calculation and requiring many PEs.

[0064]

As described above, according to the present invention,
It is possible to provide a parallel processing device capable of effectively utilizing a plurality of processors and capable of processing a large amount of data at high speed and having an excellent price / performance ratio, and a visual inspection device using the same.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a parallel processing method and apparatus according to the present invention.

FIG. 2 is a diagram showing input data and partial data in the embodiment shown in FIG.

FIG. 3 is a block diagram showing a specific example of a data input unit in FIG.

FIG. 4 is a timing chart showing partial data and data transfer information generated by a data input unit shown in FIG. 3;

FIG. 5 is a block diagram showing a specific example of a processor element in FIG. 1;

FIG. 6 is a timing chart showing an operation of the processor element shown in FIG.

FIG. 7 is a timing chart showing the operation of the embodiment shown in FIG. 1;

FIG. 8 is a block diagram showing an embodiment of a semiconductor wafer appearance inspection apparatus using the parallel processing method and apparatus according to the present invention.

FIG. 9 is a block diagram showing another specific example of the data input unit in FIG. 1;

FIG. 10 is a diagram showing the embodiment shown in FIG. 1 as an integrated circuit;

FIG. 11 is a block diagram illustrating an example of a conventional parallel processing device.

[Explanation of symbols]

 Reference Signs List 1 data input unit 1a memory 1b switch circuit 1c division information storage unit 1d division control unit 1e transfer buffer 1f data division determination unit 2 input bus 3 output bus 4 control bus 5 data output unit 6a, 6b, 6c processor element (PE) 7 Processor 8 Local memory 9 Data input permission transmission section 10 Data input permission reception section 11 Input I / F 12 Output I / F section 13 Data capture control section 14 Switch circuit 15 State register 16 Stage 17 Semiconductor wafer 18 Lens 19 Linear sensor 20 Parallel Processing unit 21 Integrated circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Kawaguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in Hitachi, Ltd. Production Engineering Research Laboratories F-term (reference) 5B045 AA01 BB12 EE12 GG02

Claims (15)

[Claims] 1. A parallel processing method in which a plurality of processor elements are used to assign input data to respective processor elements for processing, wherein a priority is assigned to each of the processor elements, and the processor elements each include: A parallel processing method wherein the input data is permitted to be fetched and processed according to its own state and the state of a processor element having a higher priority than itself. 2. A parallel processing method in which a plurality of processor elements are used to allocate input data to respective processor elements for processing, wherein a priority is assigned to each of the processor elements, and a processor having a higher priority is assigned. The information indicating its own state is transmitted in order from the element toward the processor element with the lower priority, and the processor element receiving the information from the processor element with the higher priority is in a data input waiting state, When the information indicates that the processor element having the higher priority is not in the data input waiting state or the data fetch state, the input data is fetched and processed. Parallel processing method. 3. The processor element according to claim 1, wherein the input data is divided into partial data having a size required for one processing of the processor element, and the processor element permitted to take in the data is the partial data. A parallel processing method characterized by detecting a transfer period of the data and starting to fetch the partial data. 4. The parallel processing method according to claim 3, wherein the size of the partial data can be set arbitrarily. 5. The processor element according to claim 3, wherein data transfer information indicating a transfer period of the partial data is transferred together with the partial data, and the processor element permitted to take in the data transfers the data transfer information from the data transfer information. A parallel processing method comprising detecting a transfer period of partial data. 6. The parallel processing method according to claim 1, wherein the input data is image data detected by an image detection device. 7. A parallel processing device wherein data transferred from a data input unit via a data bus is allocated to a plurality of processor elements connected to the data bus and processed, wherein each of the processor elements comprises: A first receiving unit that receives a data input permission signal transmitted from another processor element; a transmitting unit that transmits a data input permission signal indicating its own state to another processor element; A second receiving unit that receives data transfer information indicating a transfer period of the data, a state of the other processor element indicated by the data input permission signal received by the first receiving unit, and the second reception Based on the data transfer information received by the unit and its own status, the data transfer and data transfer via the data bus is allowed to be fetched and processed. And a determining whether or not measures are, the based on the judgment result judging unit captures the data transferred via the data bus, a parallel processing apparatus characterized by processing. 8. A parallel processing apparatus wherein data transferred from a data input unit via a data bus is assigned to a plurality of processor elements connected to the data bus and processed, wherein each of the processor elements has a priority. A first receiving unit that receives a data input permission signal indicating that the processor element has not taken in the data transmitted from the processor element having a higher priority; A transmission unit for transmitting a data input permission signal indicating its own state to the processor element having a lower priority, and a second reception for receiving data transfer information indicating a transfer period of the data transmitted from the data input unit Unit, a state storage unit for storing its own state, and the data input permission signal received by the first receiving unit Indicates that the data is not ready to be fetched, and when it is in a data input wait state, it is determined that the data fetch and processing are permitted, and the data is fetched based on the data transfer information. And a means for parallel processing. 9. The parallel processing device according to claim 7, wherein the plurality of processor elements are integrated in a single integrated circuit. 10. The processor element according to claim 7, 8 or 9, wherein each of the processor elements has its first receiving unit provided to the transmitting unit of another processor element having a priority higher by one than its own. The parallel processing device, wherein the transmission unit is connected to the first reception unit of the other processor element having a priority lower than that of the transmission unit by one. 11. The data input unit according to claim 7, wherein the data input unit divides the input data into partial data having a size necessary for one processing of the processor element. A parallel processing device for outputting the data transfer information indicating a data transfer period together with the output to the data bus. 12. The parallel processing device according to claim 11, wherein the size of the partial data can be set arbitrarily. 13. The input data according to claim 7, wherein the input data is image data detected by an image detection device, and the data transfer information is based on a synchronization signal synchronized with the input data. A parallel processing device characterized by being generated. 14. A parallel processing device according to claim 7, wherein said detecting means detects an appearance of the inspection object, and data obtained by said detecting means is supplied as said input data. An appearance inspection apparatus for inspecting the appearance of the inspection object, such as the shape, size, and surface pattern. 15. The parallel processing device according to claim 12, comprising: a detection unit for detecting an appearance of the inspection object; and the parallel processing device according to claim 12, wherein data obtained by the detection unit is supplied as the input data. In the data input unit, the partial data is input to the processor element by the processor element 1 based on geometrical information such as the shape, size, and surface pattern of the inspection object, and inspection conditions according to the content of processing. An appearance inspection apparatus, comprising: a data size determination unit that automatically determines a size used in each process.