JP2000043320A - Image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize displacement of pictures as for as possible in the case when a plurality of image data-processing units are used to form image on a plurality of lines simultaneously. SOLUTION: An image forming device is equipped with a clock generating unit 7a, generating a plurality of clock signals having the same frequency and a different phase with respect to a reference clock signal, a clock selecting unit 8 selecting a clock signal whose level rises up soonest after the falling of level of a video signal out of the clock signals, a delay difference operating unit 9 operating a delay difference between respective selected clock signals, and a control unit 12 controlling so that a pulse width modulating circuit 10 processes an image data signal based on a reference clock signal and, at the same time, another pulse width modulating circuit 11 processes another image data signal based on a clock signal which is delayed by that delay difference with respect to the reference clock signal. Accordingly, excellent images can be obtained even in the case when the images are formed simultaneously on a plurality of lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more particularly, to an image forming apparatus having a plurality of image data processing units for processing an image data signal based on a clock signal.

[0002]

2. Description of the Related Art In order to express a multi-valued image, it is necessary to change the light emission time of a video signal (laser light emission signal from an image) according to the image. For this reason, a pulse width modulation circuit excellent in multi-tone expression is often used as an image data processing unit for processing a video signal by processing an image data signal based on a clock signal. Here, pulse width modulation (PW
M) is a method of modulating the width of a carrier pulse in accordance with the amplitude of an input signal, and a circuit using this method includes, for example, a PWM-IC capable of expressing 256 gradations. . Conventionally, since image formation is performed line by line, only one pulse width modulation circuit is used. However, with the recent increase in copy speed, it has become necessary to form images on two lines at the same time. In response to such a request, light beams for writing are respectively obtained from the two semiconductor lasers, the scanning positions of the light beams on the surface to be scanned are shifted by a predetermined pitch in the sub-scanning direction, and the two lines are simultaneously scanned. A main scanning recording method was developed. In this case, in order to represent a multi-valued image, two pulse width modulation circuits are used.
Must be used.

[0003]

The pulse width modulation circuit constituting the image data processing section has a wide processing delay time on the data sheet. Even if data is input in synchronization with the rising edge of the clock signal, for example, 12-28n at 25 ° C
s varies. Therefore, when one of the two pulse width modulation circuits has a processing delay time of 12 ns and the other has a processing delay time of 28 ns, even if data is input in synchronization with the rising edge of the same clock signal, 16 ns A processing delay time difference will occur. In this case, 37
Since two lines are simultaneously formed at the control speed of ns, even if the same image is output on the odd lines and the even lines, the images are shifted from each other by about half a pixel in the main scanning direction. The present invention improves an image forming apparatus in order to solve the problems in the conventional technology,
Provided is an image forming apparatus capable of minimizing an image shift in the main scanning direction caused by a processing delay time difference between image data processing units when a plurality of lines are simultaneously formed by using a plurality of image data processing units. It is intended to do so.

[0004]

According to the present invention, there is provided an image forming apparatus comprising a plurality of image data processing units for processing an image data signal based on a clock signal. A clock generation unit for generating a plurality of clock signals having the same period and different phases; and among the plurality of generated clock signals, the level is the earliest after the level of the image data signal passed through the image data processing unit changes. A clock selector for selecting a changing clock signal; a delay difference calculator for calculating a delay difference between clock signals respectively selected for a plurality of image data signals by the clock selector; , An image data processing unit processes an image data signal based on the reference clock signal, and An image data processing unit, comprising: a control unit that controls processing of another image data signal based on a clock signal delayed by the delay difference with respect to the reference clock signal. It is configured as a forming device.

In such a configuration, a plurality of clock signals having the same cycle and different phases with respect to the reference clock signal are generated, and among the plurality of generated clock signals, the image data signal passed through the image data processing unit is generated. A clock signal whose level changes earliest after the level of the image data has changed is selected, a delay difference between the selected clock signals is calculated for a plurality of image data signals, and a certain image data of the plurality of data processing units is calculated. At the same time that the processing section processes a certain image data signal based on the reference clock signal, the other image data processing section processes another image data based on the clock signal delayed by the delay difference with respect to the reference clock signal. Control is performed so that signal processing is performed. As a result, the phase of the clock signal input to the image data processing unit having the longer processing delay time is advanced from the phase of the clock signal of the image data processing unit having the smaller processing delay time. Due to the characteristics of the data processing unit, the difference in the processing delay time, which cannot be avoided, is almost compensated for after processing each image data signal. Therefore, using multiple image data processing units,
Even when a plurality of lines are formed simultaneously, it is possible to minimize the image shift in the main scanning direction caused by the processing delay time difference of the image data processing unit. As a result, a good image with little distortion can be obtained.

[0006]

Embodiments of the present invention will be described below with reference to the accompanying drawings to provide an understanding of the present invention.
It should be noted that the following embodiments are examples embodying the present invention, and do not limit the technical scope of the present invention. FIG. 1 is a block diagram showing an example of a system configuration of a copying machine according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing an optical system of the copying machine, FIG. 3 is a chart showing clock selection timing, 4 is a flowchart showing an example of a correction control operation of the copying machine according to the embodiment of the present invention, FIG. 5 is a chart showing a clock selection timing in the first correction control operation, and FIG. 6 is a second correction control. FIG. 10 is a chart showing clock selection timing in operation.

The optical system of the copying machine (a type of image forming apparatus) according to the present embodiment is, for example, an LSU as shown in FIG.
(Laser Scanner Unit) 15, a light beam 2 emitted from a light source unit 1 including two semiconductor lasers is deflected by a rotating polygon mirror 3,
The photosensitive drum 4 is scanned via the fθ lens 3a, the condenser lens 3b, and the like. A detection sensor 5 is provided at an end of the photosensitive drum 4, and the detection sensor 5 detects the light beam 2 every time the light beam 2 scans the photosensitive drum 4 once, and detects the image data. Signal D1,
D2 is output to the device 6. The device 6 is, for example, an ASIC (Apulication Specific Integ
As shown in FIG. 1, a plurality of clock signals CLK1, CLK2, C2 having the same cycle but different phases with respect to the reference clock signal CLK0.
LK3,..., And a plurality of clock signals CLK1, CLK2, C
LK3, a clock selecting unit 8 for selecting a clock signal whose level changes fastest after the level of a certain reference signal (A signal) changes, and a clock selecting unit 8
, A delay difference calculation unit 9 for calculating a delay difference between clock signals selected for each of the plurality of video signals D1 ′ and D2 ′, which is an A signal, and a pulse width modulation circuit (equivalent to a certain image data processing unit) outside the device. ) 10 processes an image data signal D1 based on the reference clock signal CLK0, and at the same time, a pulse width modulation circuit (corresponding to another image data processing unit) 11 outside the device 11 The control unit 12 includes a control unit 12 that controls to process another image data signal D2 based on the clock signal SCLK delayed by the delay difference.

The clock generator 7a uses a plurality of delay elements to generate clock signals CLK of various phases from the reference clock signal CLK0 generated by the crystal oscillator 7.
1, CLK2, CLK3,...
The structure of the clock selection unit 8 is described in Japanese Patent Laid-Open No. 7-25022.
An edge detection circuit similar to the one described in the bulletin No. 5 capable of detecting the rising or falling edge of the clock signal is provided, so that, for example, as shown in FIG. CLK2, C
The clock signal CLK2 that rises first after the fall of the A signal is selected from LK3,. However, the edge detection circuit may be one that selects the clock signal that falls the earliest after the fall of the A signal, one that selects the fastest fall after the rise of the A signal, or one that selects the rising clock signal. Can respond to any of these. As shown in FIG. 1, when two lines of image data signals D1 and D2 are input, the device 6 receives the reference clock signal CLK0 generated by the crystal oscillator 7 and the clock signals CLK1 and CLK1 selected by the clock selection unit 8. CLK2, CL
The flip-flops 13 and 14 output the image data signals D1 and D2 at the timing of SCLK which is one of K3,.
Are latched, and the pulse width modulation circuits 10 and 1 outside the device are latched.
1 is output. The image data signals D1 and D2 are processed by the pulse width modulation circuits 10 and 11, respectively, to become video signals D1 'and D2' and LS
U15 and the video signals D1 ', D1'
2 'is also sent back to the device 6 as an A signal.

This copying machine operates as follows. (Before the copy operation) When correcting the processing delay difference between the two pulse width modulation circuits 10 and 11, first, as shown in FIGS. 1 and 4, the copy start switch "ON" is checked (step S1). Next, the line processing delay of the image data signal D1 is measured. Here, the line processing clock of the image data signal D1 is set to the reference clock signal CLK0 (step S2), and the start of the line processing delay measurement of the image data signal D1 is set (step S3). At this time, the level of the image data signal D1 changes from “H” to “L”.
Is input to the device 6. The image data signal D1 is latched by the flip-flop 13 at the timing of the reference clock signal CLK0. As a result, the image data signal D1 is processed by the pulse width modulation circuit 10 in synchronization with the reference clock signal CLK0, and the video signal D1 'delayed with respect to the reference clock signal CLK0.
Is output as Therefore, the level of the video signal D1 'also changes from "H" to "L". This video signal D
When 1 'is input to the clock selection unit 8 of the device 6 as an A signal, the clock selection unit 8 selects the clock signal that rises first after the fall of the video signal D1' by its edge detection circuit. At this time, the clock signal CLK having a different phase with respect to the reference clock signal CLK0.
.., CLK2, CLK3,..., 1st, 2nd, 3rd,
The numbers are assigned as numbers. The line processing delay measurement status of the image data signal D1 is read (step S4). At this time, by reading the internal register of the device 6, it can be determined whether the measurement is being performed or the measurement is completed. The number of the clock signal selected by the clock selection unit 8 is read (step S
5). At this time, the number of the selected clock signal can be known by reading the internal register of the device 6, and the number is read. The clock signal selected here is assumed to be CLK2, for example, as shown in FIG.

Next, the line processing delay of the image data signal D2 is measured. Here, the line processing clock of the image data D2 is set to the reference clock signal CLK0 (step S6), and the start of the line processing delay measurement of the image data signal D2 is set (step S7). At this time, data whose level changes from "H" to "L" is input to the device 6 as the image data signal D2. The image data signal D2 is latched by the flip-flop 14 at the timing of the reference clock signal CLK0. As a result, the image data signal D2 is processed by the pulse width modulation circuit 11 in synchronization with the reference clock signal CLK0,
It is output as a video signal D2 'delayed from LK0. Therefore, the level of the video signal D2 'is also "H".
From “L” to “L”. When this video signal D2 'is input as an A signal to the clock selection unit 8 of the device 6, the clock selection unit 8 selects the clock signal which rises first after the fall of the video signal D2' by the edge detection circuit. At this time, the clock signals CLK1, CLK2 and CLK2 having different phases with respect to the reference clock signal CLK0.
CLK3,... Respectively.
Numbers are assigned in the order of small phase difference of 0, 1, 2, 3,.... The line processing delay measurement status of the image data signal D2 is read (step S8). At this time, by reading the internal register of the device 6, it can be determined whether the measurement is being performed or the measurement is completed. The number of the clock signal selected by the clock selector 8 is read (step S9). At this time,
The number of the selected clock signal can be known by reading the internal register of the device 6, and
Read that number. The clock signal selected here is assumed to be CLK5, for example, as shown in FIG.

Then, a correction setting is made. Here, the delay difference calculation unit 9 calculates the delay difference between the line processing of the image data signal D1 and the line processing of the image data signal D1 (step S10). Here, _{assuming that} the delay time difference between two clock signals CLK _{n + 1} and CLK _n adjacent to each other is the same, the time when the image data signal D1 is output as the video signal D1 ′ and the time when the image data signal D2 is the difference between the time to be outputted as a video signal D2 'is three times the delay time difference between the clock signal _{CLK n + 1, CLK n (} CLK5
ＣＬＫCLK2). Actually, in this delay difference calculation, a clock number difference is calculated. The line processing clock of the image data signal D1 is changed to the reference clock signal CL.
It is set to K0 (step S11). Image data signal D
The second line processing clock is set to a clock signal having the number of the clock number difference obtained by the delay difference calculation (step S12). That is, when the image data D1 is processed by the reference clock signal CLK0, when the image data signal D2 is processed by the clock signal CLK3, the delay time difference between the pulse width modulation circuits 10 and 11 can be almost compensated. After the above operation is completed, a copy operation is started (step S13). Note that this series of correction control is considered to have little change in the ambient temperature during the normal copy operation, so it is sufficient to perform the correction control every time before the copy operation. (During copy operation) During the copy operation, the image data signals D1 and D2 are
14 is latched at the corrected clock timing. And pulse width modulation circuits 10 and 11
Are processed into video signals D1 'and D2'. These video signals D1 'and D2' are sent to the LSU 15, and a copy operation is performed. As described above, according to the present embodiment, the phase of the clock signal input to the image data processing unit having the longer processing delay time is made smaller than the phase of the clock signal of the image data processing unit having the smaller processing delay time. By proceeding, the difference in the processing delay time, which cannot be avoided due to the characteristics of the individual pulse width modulation circuits constituting each image data processing unit, is almost compensated for after processing each image data signal. Therefore, even when a plurality of lines are simultaneously formed by using a plurality of pulse width modulation circuits, it is possible to minimize the image shift in the main scanning direction caused by the processing delay time difference between the pulse width modulation circuits. it can. As a result, a good image with little distortion can be obtained. In the above embodiment, two pulse width modulation circuits are provided in order to form an image simultaneously on two lines. However, more pulse width modulation circuits are provided to process more lines simultaneously. By performing
The copy speed can be further increased. Further, as long as it has such a function, it goes without saying that a processing circuit other than the pulse width modulation circuit may be used as the image data processing section. Furthermore, in the above embodiment, a copying machine has been described as an example of an image forming apparatus. However, the present invention is not limited to this, and can be applied to any other image forming apparatuses such as a printer and a facsimile.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the above embodiment, before the copy operation, the delay difference calculating section 9 controls the video signal D by the clock selecting section 8.
Although the time difference between the clock signals selected for 1 ′ and D2 ′ is calculated, this calculation may be performed during the copy operation. In that case, after the delay difference calculation section 9 performs the above calculation during the copy operation, the control section 12 processes the image data signal D1 based on the reference clock signal CLK0 by the pulse width modulation circuit 10 and outputs the video signal D1.
At the same time, the image data signal D2 is generated by the pulse width modulation circuit 11 based on the clock signal SCKL delayed by the delay difference with respect to the reference clock signal CLK0.
Is processed so as to be converted into a video signal D2 '. However, since the time required for the calculation is short, it is considered that there is no particular problem.

[0013]

As described above, according to the present invention,
By setting the phase of the clock signal input to the image data processing unit having the longer processing delay time ahead of the phase of the clock signal of the image data processing unit having the smaller processing delay time, Due to the characteristics described above, the difference in the processing delay time, which cannot be avoided, is almost compensated for after processing each image data signal. Therefore, even when a plurality of image data processing units are used to form an image on a plurality of lines at the same time, it is possible to minimize the image shift in the main scanning direction caused by the processing delay time difference between the image data processing units. As a result, a good image with little distortion can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a system configuration of a copying machine according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing an optical system of the copying machine.

FIG. 3 is a chart showing clock selection timing.

FIG. 4 is a flowchart showing an example of a correction control operation of the copying machine according to the embodiment of the present invention.

FIG. 5 is a chart showing clock selection timing in a first correction control operation.

FIG. 6 is a chart showing clock selection timings in a second correction control operation.

[Explanation of symbols]

Reference Signs List 6 device 7 crystal oscillator 7a clock generation unit 8 clock selection unit 9 delay difference calculation unit 10 pulse width modulation circuit (corresponding to a certain image data processing unit) 11 pulse width modulation circuit (other image data processing) 12 control units 13, 14 flip-flops 15 LSU CLK0 reference clock signal SCLK clock signal D1 (corresponding to a certain image data signal) D2 (corresponding to another image data signal) D1 '... (Equivalent to video signal, A signal) D2 '... (equivalent to video signal, A signal)

Claims (4)

[Claims] 1. An image forming apparatus comprising a plurality of image data processing units for processing image data signals based on a clock signal, wherein a clock generation unit for generating a plurality of clock signals having the same cycle and a different phase from a reference clock signal. A clock selecting unit that selects a clock signal of which the level changes fastest after the level of the image data signal passed through the image data processing unit changes, among the plurality of generated clock signals; A delay difference calculating section for calculating a delay difference between clock signals respectively selected for the plurality of image data signals by the section; and an image data processing section among the plurality of data processing sections, based on the reference clock signal. At the same time as processing a certain image data signal, another image data processing unit An image forming apparatus comprising: a control unit that controls processing of another image data signal based on a clock signal delayed by the delay difference. 2. The image processing apparatus according to claim 1, wherein the delay difference calculating unit performs an image forming process.
A delay difference between clock signals selected for each of the plurality of image data signals by the clock selection unit is calculated, and the control unit is controlled by an image data processing unit among the plurality of data processing units during image forming processing. At the same time that an image data signal is processed based on the reference clock signal, another image data signal is processed by another image data processing unit based on a clock signal delayed by the delay difference with respect to the reference clock signal. The image forming apparatus according to claim 1, wherein the control is performed so as to be performed. 3. The clock selecting unit selects a clock signal whose level rises or falls first after the level of the image data signal falls or rises among the plurality of generated clock signals. The image forming apparatus according to claim 1. 4. The image forming apparatus according to claim 1, wherein said image data processing section comprises a pulse width modulation circuit.