JP2000041022A - Synchronizing capture circuit and communication terminal equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten time required for synchronizing capture through code generators are required as many as correlaters to result in the magnification of the circuit scale, on the other hands. SOLUTION: While specifying the phase of a spreading code with which the output of high correlation with a received signal appears, the synchronizing capture circuit for synchronizing the received signal and spreading code is provided with following means, namely, a spreading code generator 2 for generating one spreading code based on a reference phase and plural correlaters 4-0 to 4-(k-1) for successively and serially transferring the spreading code generated by the spreading code generator, generating a spreading code delaying a phase just for the number of steps from first one, and calculating the output of correlation between the spreading code and received signals parallelly inputted to all the steps for each step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code division multiple access (CDMA) as a communication system.
ccess) system can be applied to a communication system (such as a digital cellular system) employing the system.

[0002]

2. Description of the Related Art In a receiver of a mobile communication system adopting a CDMA system, a function of establishing code synchronization called synchronization acquisition is essential. Here, synchronization acquisition refers to specifying the phase of the spread code in the received signal by using the same spread code used by the transmitter for spreading.

In the synchronous acquisition, generally, a correlation operation using various phases is performed on a channel or symbol on which data modulation is not performed, and the phase of a spread code is specified from the correlation power. Therefore, an enormous amount of time is required for synchronization acquisition.

For example, if the resolution is 1 / N, the spreading code length to be processed is L, and the correlation length is M,
As shown in FIG. 2, the time required for synchronous acquisition is L × M ×
It is given by N [chip]. When the resolution is 1 (that is, N = 1), the time required for synchronization acquisition is L × M
[Chip].

[0005]

On the other hand, on the other hand, due to fluctuations in the propagation environment and requests from users, it is desired to reduce the time required for synchronization acquisition.

One of the methods for shortening the synchronization acquisition time is to use a plurality of correlators. However, this method requires the number of code generators corresponding to the number of correlators, and the circuit scale is multiplied by the number of correlators, resulting in an increase in size.

The present invention has been made in consideration of the above problems, and has as its object to propose a synchronization acquisition circuit having a small circuit size and a short synchronization acquisition time. It is another object of the present invention to propose a communication terminal device in which the package is small and the time required for line switching is short by using such a synchronization acquisition circuit.

[0008]

SUMMARY OF THE INVENTION Therefore, in a synchronization acquisition circuit according to the present invention, which specifies a phase of a spread code in which a high correlation output appears between the received signal and the code, and realizes code synchronization between the received signal and the spread code. , (1) a spreading code generator that generates one spreading code based on the reference phase, and (2) a spreading code generated by the spreading code generator are sequentially transferred in series, and the phase is shifted by the number of stages from the first stage. A plurality of correlators for generating a delayed spread code and calculating a correlation output between the spread code and a received signal input in parallel to all stages for each stage are provided.

Further, the synchronization acquisition circuit is provided in a communication terminal device.

As described above, in the synchronization acquisition circuit of the present invention, each of the plurality of correlators is provided with a function of sequentially delaying the spreading code and providing it to the subsequent stage, so that the correlation output with the received signal can be calculated in parallel. Thus, a plurality of spread codes having different phases can be generated.

Therefore, the time required for synchronization acquisition can be reduced by parallel processing using spread codes of a plurality of phases, while a spread code of a plurality of phases required at that time can be generated by a single spread code generator. In addition, the size of the device can be reduced as compared with the conventional device.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a basic block configuration of a synchronization acquisition circuit proposed in this specification. FIG.
Here, a synchronization acquisition circuit capable of acquiring synchronization with 1 / N chip accuracy will be described.

The synchronization acquisition circuit includes one clock generator 1
, One code generator 2, one correlator control unit 3,
It is composed of K correlators 4-0 to 4- (K-1) (hereinafter, referred to as correlators 0 to K-1) and a synchronous phase identification circuit (not shown).

First, the functional configuration of each unit will be described.

The clock generator 1 receives a chip clock and an N × chip clock having a frequency multiplied by N, and delays the phase of each clock by 1 / N of the chip time T (ie, T / N). N clocks Clk0
To ClkN-1. The clock generator 1 outputs each of the clocks Clk0 to ClkN-1 to the corresponding correlators 0 to K-1.

The code generator 2 is a circuit for generating one spreading code (Code0) in accordance with the processing timing of the correlator 0. As described above, the point that only one code generator 2 is provided is a feature of the synchronization acquisition circuit.

The correlator control unit 3 sets the phase of each signal to 1 / N of the chip time T (ie, T / N) according to the correlation length M.
K start / end signals (Start / En
d). Note that the correlator control unit 3
Each of the correlation start / end signals (Start / End) is output to the corresponding correlators 0 to K-1.

Each of the correlators 0 to K-1 is arranged in parallel with the received signal (Signal), and correlates the received signal with the code at a timing synchronized with the clock timing given from the clock generator 1. This is a circuit that outputs a result.

Each of the correlators 0 to K-1 is arranged in series with a spreading code (Code), and sequentially outputs a spreading code (Code) given from the code generator 2 or the preceding stage. The delay is delayed by 1 / N of the chip time T (that is, T / N) and given to the correlator at the subsequent stage.

Next, the synchronization acquisition operation by the synchronization acquisition circuit having the above configuration will be described with reference to FIG.

In FIG. 4, when N = 4 and K = 4, that is, each of the four correlators 0 to 3 has a phase difference of 1/4 of the chip time T. A case where different types of clocks are provided will be described.

In FIG. 4, it is assumed that a received signal (Signal) which has been subjected to multiple sampling in advance (here, sampled at a clock speed four times the chip clock) is supplied to a corresponding correlator. This is to improve the accuracy of acquisition by the synchronization acquisition circuit.

In the synchronization acquisition circuit, first, the correlator 0 operates first. Correlator 0 outputs a correlation start / end signal (Start / End signal).
The correlation value R0 (0) between the received signal (Signal) and the spreading code with zero phase difference (Code0) is calculated according to the rising timing of the clock Clk0 input after the signal End0 falls to the “L” level.

At the same time, the correlator 0 delays the spread code (Code0) input from the code generator 2 by 1/4 chip time to generate a spread code (Code1). Output.

After 1/4 chip time from the start of the operation of the correlator 0, the correlator 1 starts the operation, and the received signal (Signal) and 1
A correlation value R1 (0) with the spread code (Code1) after a チ ッ プ chip time delay is calculated. The correlator 1 also has
The spread code (Code2) obtained by delaying the spread code (Code1) input from the correlator 0 by 1/4 chip time is output to the correlator 3 at the next stage.

Thereafter, each time the 1/4 chip time elapses, the correlator 2 and the correlator 3 start operating in order, and the correlation value R2 (0) between each spread code (Code3, Code4) and the received signal,
R3 (0) is calculated. And the correlator 3 which is the last stage
When 1/4 chip time has passed since
Again, the first stage correlator 0 calculates the next correlation value, and the same operation is repeated thereafter.

Thus, in the synchronization acquisition circuit according to the present embodiment, four correlation values are calculated within one chip time. FIG. 5 shows this in a diagram. In addition,
FIG. 5 shows a general case. Therefore, if K and N in the drawing are each 4, the operation timing of this embodiment is obtained.

At this time, the synchronization acquisition time by the synchronization acquisition circuit is given by (4 × M + 3) × L / 4. The general formula for calculating the synchronization acquisition time is (N × M + K−
1) × L / K Incidentally, the resolution is set to 1 (that is, N
= 1), the time required for synchronization acquisition is (M + K
-1) × L / K [chip].

After that, a synchronization phase specifying circuit (not shown) specifies the phase at which the maximum value is obtained, and sets the phase as a phase for generating a spread code that is code-synchronized with the received signal.

As described above, if the synchronization acquisition circuit having the configuration according to the present embodiment is mounted on a communication terminal device, the code generator can be replaced by one.
The time required for the synchronization acquisition can be remarkably reduced as compared with the conventional device using only one device.

Further, even if compared with a conventional device that uses a plurality of correlators to reduce the time required for synchronization acquisition, it is not necessary to prepare code generators for the number of correlators as in the conventional device.
The circuit scale can be significantly reduced.

By mounting the synchronization acquisition circuit having such a configuration, it is possible to reduce the size of the package of the communication terminal device on which the circuit is mounted and to shorten the line switching time.

Further, since this synchronization acquisition circuit has a function of separating multipaths in addition to establishing code synchronization, it is possible to separate multipaths with an accuracy of 1 / N of one chip time.

In the above-described embodiment, the correlator controller 3 shifts K by 1 / N chip time.
The case where the correlation start / end signals (Start / End) are generated and supplied to the corresponding correlators 0 to K-1 has been described. The same correlation start / end signal (Start / End0) may be provided.

However, in this case, it is necessary to wait until the output after the initial reset of the code generator 2 is input to all the correlators 0 to K-1, but the time required for synchronization acquisition is reduced. It is the same as the case of the form.

Further, in the above-described embodiment, the case where a multiply-sampled signal is used as a received signal to be input to the correlator has been described. However, a correlation value can be calculated for a non-multisampled signal.

In the above embodiment, the CDM
The description has been given on the premise of the receiver of the mobile communication system adopting the A system. However, the present invention can be applied to a communication system of a system that spreads and modulates communication data and transmits the data, and is also applicable to communication between fixed stations.

[0038]

As described above, in the synchronization acquisition circuit according to the present invention, the spread code generator for generating one spread code based on the reference phase and the spread code generated by the spread code generator are sequentially transmitted. A plurality of correlations are serially transferred to generate a spread code whose phase is delayed by the number of stages from the first stage, and calculate a correlation output between the spread code and a received signal input in parallel to all stages for each stage. A plurality of spreading codes having different phases can be generated in parallel with the calculation of the correlation output with the received signal, so that the time required for synchronization acquisition can be reduced and the size of the apparatus can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a synchronization acquisition circuit according to an embodiment.

FIG. 2 is a diagram showing a synchronization acquisition time of a conventional device.

FIG. 3 is a diagram illustrating a phase relationship between clocks generated by a clock generator.

FIG. 4 is a diagram showing operation timing in each correlator.

FIG. 5 is a diagram illustrating a synchronization acquisition time of the synchronization acquisition circuit according to the embodiment.

[Explanation of symbols]

1 clock generator, 2 code generator, 3 correlator controller, 4-0 to 4- (K-1) correlator, Code spreading code, Start /
End: Correlation start / end signal.

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Claims (2)

[Claims] 1. A synchronization acquisition circuit for specifying a phase of a spread code in which a high correlation output appears between a received signal and realizing code synchronization between the received signal and the spread code. A spreading code generator that generates the spreading code of the above, a spreading code generated by the spreading code generator is sequentially serially transferred, and a spreading code whose phase is delayed by the number of stages from the first stage is generated. A synchronization acquisition circuit, comprising: a plurality of correlators for calculating a correlation output with a reception signal input in parallel to all stages for each stage. 2. A synchronization acquisition circuit according to claim 1, further comprising:
A communication terminal device for establishing a call using the phase information.