JP2000040968A - Encoding method and encoding device, decoding method and decoding device, and providing medium - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the size of an encoder and operate it at high speed. In an encoding method for encoding m-bit data into an n-bit code, the n-bit code is a code generated in accordance with a finite state transition diagram representing a restriction on ADS and RDS that a code sequence receives. The two states included in the set of states starting from the n-bit code in the finite state transition diagram exist at positions symmetric with respect to the center point of the finite state transition diagram, or Either at a position symmetrical with respect to the ADS axis passing through the point or at a position symmetrical with respect to the RDS axis passing through the center point of the finite state transition diagram. The data is encoded into an n-bit codeword starting from a predetermined state included in a set of states starting from the code, and n starting from another state included in the set of states starting from the code.
The bit codeword is obtained by further transforming the encoded codeword.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding method and an encoding device, a decoding method and a decoding device, and a providing medium, and more particularly to, for example, converting video data, audio data, and other digital data into magnetic data. Discs, magnetic tapes, optical discs, magneto-optical discs, recorded on recording media such as phase change discs, and suitable encoding method and encoding apparatus used when reproducing the same, decoding method and decoding apparatus, In addition, it relates to a providing medium.

[0002]

2. Description of the Related Art When digitally recording and reproducing video data and audio data on a disk such as a magnetic disk, an optical disk, and a magneto-optical disk or a magnetic tape, the data can be recorded with as high density as possible and with high reliability. It is desired. To achieve this, PRML (Partial Response signaling with Maxim) combining the partial response method and maximum likelihood decoding (maximum likelihood detection)
um Likelihood detection) is known to be suitable. According to PRML, recording with higher density and higher reliability is possible. In recording digital data, a partial response (1, 1) or a partial response (1, 0, -1) is generally used. As a method of maximum likelihood decoding, Viterbi decoding (Viterbi detection) is usually used. .

[0003] Furthermore, by combining the partial response method and the coding technique, a squared free euclidean distance d ² _free
There is known a technology for improving the SNR (Signal to Noise Ratio) on the output of the partial response channel to enable high-density and high-reliability recording, which is based on TCPR (Trellis Coded Partial Response). Codes created by this technique are called trellis codes.

Here, the free-square Euclidean distance d ²
_{A free} is a trellis diagram (hereinafter, a detection trellis (Detec) representing an output sequence of a partial response channel.
tor Trellis). Viterbi detection is performed based on this detection trellis), and is the minimum Euclidean distance between two different paths starting from a common state and ending at a common state. Note that the start and end states need not be the same.

For example, a partial response (1, 0,
-1) (hereinafter abbreviated as PR4), if d ² _free of the conventional bit-by-bit detection method is set to 1, by performing Viterbi detection, d ² _{free is set} to 2
(PR4ML). Here, PR4ML is
This is a method combining PR4 and maximum likelihood decoding (Viterbi detection). This d ² _free means that the larger the value is, the more the SNR can be improved, and the higher the density and the more reliable the recording becomes. Furthermore, for PR4, for example, a practical trellis code for setting d ² _free to 4 is also known (TCPR4). Here, TCPR4 is a scheme in which a trellis code is combined with PR4.

[0006] By the way, the power density of the code (power densit)
A theory is known that d ² _free can be increased by matching the null point of (y) with the null point of the transfer function of the transmission path, and a trellis created based on this theory is known. The code is called an MSN (Matched Spectral Null) code.

[0007] For example, in the PR4, its transfer function is DC component and recording rate (1 / T _C, T _C is 1 sign bit duration (bit period)) 1/2 of the frequency components (so-called Nyquist frequency) It is null. Accordingly, by making one or both of the DC component of the code power density and the Nyquist frequency null, d ² _free can be increased.

For example, in a partial response (1, 1) (hereinafter abbreviated as PR1), its transfer function is null in a Nyquist frequency component.
Therefore, by making the Nyquist frequency component of the code power density null, d ² _free can be increased.

Here, the sign bit "1" or "0"
Are assigned symbols "+1" or "-1", respectively, and the sum of symbols from the start point (start point) of the code sequence or from infinity past to the present time, that is, RDS (Running Digital Sum) is This is an index for evaluating the DC component described above, and indicates that if the RDS falls within a certain range, the DC component of the code power density becomes null.

As in the case of the RDS, the symbol “+1” or “−1” assigned to the code bit has 1
The sum of symbols from the start point or infinity past to the present time multiplied by “−1” every bit, that is, ADS (Alternating Digital Sum) is an index for evaluating the Nyquist frequency component described above. This indicates that if the ADS falls within a certain range, the Nyquist frequency component of the power density of the code becomes null.

When the transfer function has a DC component like PR1, it is generally required that the DC component of the code power density be null. That is, for example,
In the magnetic recording / reproducing having a differential characteristic in the reproducing system,
In order to prevent an error due to fluctuation of a reference level from occurring when a code is detected from a reproduced signal by Viterbi detection, for example, in recording / reproducing of an optical disk or a magneto-optical disk, in a servo control of a disk device, In order to prevent fluctuations from occurring in various error signals such as a tracking error signal, it is required that a code that is a recording signal does not include a DC component.

For this reason, for example, in an 8/10 conversion code (Rate 8/10 Code) adopted in a digital audio tape recorder (DAT), the amplitude value of RDS (the maximum value of RDS−
Control is performed so that the DSV (Digital Sum Variation), which is the minimum value of the RDS, is finite so that the power density of the code does not have a DC component and the DSV is reduced as much as possible. Here, the lower the DSV, the more the low frequency component of the code power density is suppressed. The code subjected to the DSV control is called a DC free code.

[0013] EFM (Eight-to-Fourteen Modulation), which is used in compact disk (CD) players, is not completely DC-free. However, in order to suppress the low-frequency component of its power density, DSV is not used. Control is performed to make the size as small as possible.

Further, when the PRML method is applied, the length of the path memory at the time of Viterbi detection becomes a problem. The path memory is a storage device that stores a temporary determination value for detection until the Viterbi detection result is determined, and requires a length (storage capacity) proportional to a time interval until the detection result (decoding result) is determined. Becomes

The time interval until the Viterbi detection result is determined, that is, the length of the path memory, is usually a quasi-catastrophic sequence (Q
uasi-Catastrophic sequences) (hereafter referred to as QC sequence), and a minimum distance error event (minim
It is controlled by configuring the code to minimize the maximum length of um-distance error events).

Here, the minimum distance error event generally indicates an error event resulting from a sequence forming d ² _free on the detection trellis. A QC sequence is two or more different paths that are infinite (existing) without their squared Euclidean distance being accumulated on the trellis diagram. For example, code sequence 101010
…, On the trellis diagram, the state transitions are 111…, 333
If the paths…, 555… continue indefinitely, these three paths are called a QC sequence. In the QC sequence, since the distance between each of these paths is zero and is not accumulated forever, it cannot be determined which of these sequences is correct, that is, the path cannot be determined,
Therefore, when a QC sequence occurs, the result of Viterbi detection cannot be determined.

When a device for performing Viterbi detection is actually realized, it is impossible to have an infinite path memory.
In addition, it is necessary to have a path memory as short as possible in terms of cost, size of occupied space (apparatus scale), power consumption, and the like. Therefore, the following measures are taken to eliminate the QC sequence.

That is, for example, when the 8/10 code is applied to PR1, NRZI (Non Return to Zero Invert) is applied.
ed) QC sequences can be eliminated by limiting the number of consecutive ones in the previous data sequence.

On the other hand, the so-called T
_min (minimum continuation length of the same symbol) and T _max (maximum continuation length of the same symbol) are also important as indexes for evaluating the performance of the code. For example, it is desirable that T _max be as small as possible.

That is, for example, in magnetic recording and reproduction,
If _Tmax is large, the erasing rate at the time of overwriting may become a problem. In addition, when azimuth recording is performed, crosstalk from an adjacent track increases, and the quality of reproduced data deteriorates. Further, with respect to a PLL (Phase Locked Loop), if _Tmax is large, information for synchronization is reduced, which causes a malfunction.

By the way, in combination with the above PR4, one of the MSN codes for setting d ² _free to 4 is an 8/10 rate MSN code (Partitioned-MSN code) by a method called “partitioning”. ) Is L.
Fredrickson, R. Karabed, J. Rae, P. Siegel, H. Thapar and
R. Wood, “Improved Trellis-Coding for Partial-Respo
nse Channels ”, IEEE Transaction on Magnetics, Vol.3
1, No. 2, March 1995, pp. 1141-1148. This code is the same 8/10 rate MSN code that has been reported so far, for example, USP 5,095,484 and H. Thapar, J. Rac, C.
Shung, R. Karabed and P. Siegel, “On the performance o
fa Rate 8/10 Matched Spectral NullCode for Class-
4 Partial Response ”, IEEE Transaction on Magnetic
s, Vol. 28, No. 5, September 1992, pp. 2883-2888, the length of the path memory can be reduced.

[0022]

By the way, when PR1 and PR4 are compared, PR1 is more suitable for high linear density because the transfer function of the high frequency band is suppressed and the high frequency noise is less emphasized. ing. This is because H. Ino and Y. Shinpuku, “8/1
0PR1ML for High Density and High Rate Tape Strage
Systems ”, IEEE Transaction on Magnetics, Vol. 31, No.
6, November 1995, pp. 3036-3038 and H. Ino, S. Higashino, a
nd Y. Shinpuku, “Performance of Trellis-Coded Class
-1 Partial Response ”, IEEE Transaction on Magnetic
s, Vol. 33, No. 5, September 1997, pp. 2752-2754, and the like.

By the way, the applicant of the present application has proposed a trellis code having a conversion efficiency (coding rate) of 4/5, which is intended to be applied to PR1, and further to a partial response whose transfer function has a null point at the Nyquist frequency. 16/20 MSN
The code has been proposed earlier (Japanese Patent Application No. 9-64231).
The power density of this code is null at the Nyquist frequency, and also null at direct current (DC).
When applying this code to PR1 (TCPR1), when the 2 d ² _free when not performed coding, it is possible to make the d ² _free to 4. The maximum length of the minimum distance error event is 5 code lengths (1 code length is 20 bits), and the maximum continuous length of the same symbol is 10.

In this case, since the maximum length of the minimum distance error event is 5 code lengths, the length of the required path memory is also about 5 code lengths. It is desired to further reduce the length of the memory.

On the other hand, the interleaved code of the Partitioned-MSN code intended to be applied to PR4 described above can be applied to PR1 as well as PR4. This is because the power density of the interleaved code is null not only at DC but also at its Nyquist frequency.
This is because it also works for PR1. Since the DC component of the power density is null, it is a DC free code, and since the Nyquist frequency component is null, d ² _free can be set to 4 even for TCPR1. Also, in TCPR1,
If this Partitioned-MSN code is applied, GTD (General
sized Truncation Depth) is 40 bits,
This is considerably smaller than the 5 code length (100 bits) in the 6/20 MSN code.

Here, GTD is a pair of paths existing on the detection trellis and starting from any common state.
The squared Euclidean distance is the free squared Euclidean distance d ²
_It is the maximum length before reaching _free (for example, 4 in the case of the above-mentioned Partitioned-MSN code). However, it is assumed that at least one of a pair of paths starting from a common state is a code sequence. This GTD is used when the detection trellis is time-varying, and is an index indicating the required length of the path memory, as well as the maximum length of the minimum distance error event.

However, in the case of TCPR1 based on the Partitioned-MSN code, upon detection, the same method as that of TCPR4, that is, L. Fredrickson, R. Karabed, J. Rae, P. Si
egel, H. Thapar and R. Wood, “Improved Trellis-Coding
for Partial-Response Channels ”, IEEE Transaction
on Magnetics, Vol. 31, No. 2, March 1995, pp. 1141-1148, the TCPR1 detection trellis contains extra state transitions that do not correspond to code sequences. As a result, there is a problem that a part of the sequence becomes a QC sequence.

Therefore, the applicant of the present application has filed Japanese Patent Application No. 8-329.
No. 376 and the aforementioned H. Ino, S. Higashino, and Y. Shinpuku,
“Performance of Trellis-Coded Class-1 Partial Res
ponse ”, IEEE Transaction on Magnetics, Vol.33, No.5,
In September 1997, pp. 2752-2754, when a Partitioned-MSN code is applied to a partial response whose transfer function has a null point at the Nyquist frequency, a method is first proposed to make the QC sequence invalid from the detection trellis. are doing. The maximum consecutive length of the same symbol of the Partitioned-MSN code taken here is 10.

However, the above-described method requires an additional process to remove the QC sequence from the detection trellis, which has a problem that the speed of the Viterbi detector is hindered. Further, it is desirable that the maximum continuous length of the same symbol of the Partitioned-MSN code be smaller.

FIG. 12 shows a configuration example of a conventional encoder. First, a 16-bit data word is encoded by the encoding circuit 1.
01 is input. The encoding circuit 101 associates a 16-bit data word with a 20-bit code word, and converts an input data word into a code word. Register 1
02 stores the state of the end point in the state transition diagram for codeword generation. The output of the register 102 is fed back to the encoding circuit 101, and the encoding circuit 101
A codeword is generated based on the state of the end point in the dataword and the previous codeword. The 20-bit code word and the state of the end point of the code word are supplied to the parallel / serial converter 103, and the parallel / serial converter 103 converts the supplied data into serial data and outputs it.

FIG. 13 shows a configuration example of a conventional decoder. When a 20-bit code word is input, the decoding circuit 111 converts the code word into a 16-bit data word and outputs it.

However, in the encoder of FIG. 12, if the state of the end point in the previous codeword is not determined,
Since the current codeword cannot be generated, there is a problem that the speed of the encoder cannot be increased.

The present invention has been made in view of such a situation, and speeds up an encoder that generates an MSN code whose transmission polynomial can be applied to a partial response having a null point at the Nyquist frequency. Is what you can do.

The maximum continuous length of the same symbol is small.
An MSN code can be provided.

[0035]

According to a first aspect of the present invention, there is provided an encoding method for encoding m-bit data into an n-bit code, wherein the n-bit code is an ADS received by the code sequence. The codes generated according to the finite state transition diagram expressing the restriction of the RDS, and the two states included in the set of states starting from the n-bit code in the finite state transition diagram are located at the center point of the finite state transition diagram. ADS that exists at a position symmetrical with respect to or passes through the center point of the finite state transition diagram
Either at a position symmetrical with respect to the axis or at a position symmetrical with respect to the RDS axis passing through the center point of the finite state transition diagram. An n-bit codeword that is encoded into an n-bit codeword starting from a predetermined state included in a set of states to be a starting point, and that starts from another state included in the set of states starting from a code is , Obtained by further transforming the encoded codeword.

According to a twelfth aspect of the present invention, in the encoding device for encoding m-bit data into an n-bit code, a set of states in which a code starts from an input m-bit data word is provided. Encoding means for converting into an n-bit codeword starting from one of the predetermined states included therein;
A codeword checking means for checking the state and type of the end point of the codeword based on the codeword supplied from the coding means; and a code output from the codeword conversion means for outputting the state of the end point supplied from the codeword checking means. End point state conversion means for converting the state to the end point state of the word, and storage means for storing the end point state output by the end point state conversion means for one codeword, and outputting the start point state of the code word output next time by the code word conversion means. Based on the state of the starting point of the code word supplied from the storage means and the type of the code word supplied from the code word checking means, An n-bit code word starting from one determined state is defined as n starting from another state included in the set of states starting from the code.
Codeword conversion means for converting the codeword into a codeword of bits.

According to a seventeenth aspect of the present invention, in the decoding method for decoding an n-bit code into m-bit data, the n-bit code is an ADS received by a code sequence.
And the codes generated according to the finite state transition diagram expressing the restriction of the RDS. The two states included in the set of states starting from the n-bit code in the finite state transition diagram are the center points of the finite state transition diagram. Exists symmetrically with respect to
Either at a position symmetric with respect to the ADS axis passing through the center point of the finite state transition diagram, or at a position symmetrical with respect to the RDS axis passing through the center point of the finite state transition diagram And an n-bit codeword starting from one of the states included in the set of states starting from the code is defined as one predetermined state included in the set of states starting from the code as a starting point. The m-bit data word is converted to another n-bit code word, and the m-bit data word is obtained by decoding the converted code word.

A decoding device for decoding an n-bit code into m-bit data according to a thirty-second aspect of the present invention, wherein the input n-bit code word is used as a starting point to check a state and a type. Checking means, and an n-bit code starting from one of the states included in the set of states starting from the input code, based on the state and type of the starting point of the codeword supplied from the codeword checking means Codeword conversion means for converting a word into another n-bit codeword starting from one predetermined state included in a set of states starting from a code, and a code converted by the codeword conversion means Decoding means for decoding the word into an m-bit data word.

A providing medium according to a thirty-third aspect is a providing medium in which an n-bit code obtained by encoding m-bit data is recorded, wherein the n-bit code is:
A code generated according to a finite state transition diagram showing the restrictions on ADS and RDS that a code sequence receives, and two states included in a set of states starting from an n-bit code in the finite state transition diagram are finite states RDS that exists at a position symmetrical with respect to the center point of the transition diagram, at a position symmetrical with respect to the ADS axis passing through the center point of the finite state transition diagram, or that passes through the center point of the finite state transition diagram It is characterized in that it exists either at a position symmetrical with respect to the axis.

[0040]

FIG. 1 is a block diagram showing a configuration of an embodiment of a recording / reproducing apparatus to which the present invention is applied.

For example, as shown in FIG. 2, the encoder 1 converts a 16-bit data word into a 20-bit code word, and converts the code word output from the encoding circuit 21 into another code word. A code word conversion circuit 22 for converting words into words, a parallel / serial (P / S) converter 23 for converting parallel data output from the code word conversion circuit 22 into serial data,
From the codeword output by the encoding circuit 21, the state of the end point
(end-state) A code word check circuit 24 for checking the type and a state where the code word output from the coding circuit 21 is an end point is converted into a state where the code word output from the code word conversion circuit 22 is an end point. An end-point state conversion circuit 25 that stores the end-point state output by the end-point state conversion circuit 25 for one codeword, and a register 26 that outputs a state in which the codeword output next by the codeword conversion circuit 22 is the start point. Is done.

The encoder 1 includes, for example, video data as an information sequence (binary data) to be recorded on a medium 3 such as an optical disk, a magneto-optical disk, a magnetic disk, a magnetic tape, and a phase change disk; Audio data and other data are input in units of 16 bits, and the encoder 1 converts (encodes) the 16-bit data word into a code word having a code length of 20 bits. The data is output to a recording amplifier (REC.Amp) 2. The recording amplifier 2 amplifies the code sequence as serial data from the encoder 1 and records it on the medium 3.

The reproduction amplifier (PB.Amp) 4 amplifies the reproduction signal from the medium 3 and supplies it to the equalizer amplifier (EQ.Amp) 5. The equalizer amplifier 5 equalizes the waveform of the reproduction signal from the reproduction amplifier 4,
The data is supplied to the PLL circuit 9. The sampler 6 samples the reproduced signal from the equalizer amplifier 5 according to the clock from the PLL circuit 9.
The sample value obtained as a result is transmitted to the Viterbi detector 7 for TCPR.
And output it to the PRML Viterbi detector 10. The TCPR Viterbi detector 7 detects a code sequence from the sample values supplied from the sampler 6 (Viterbi decoding), and supplies the detection result (Viterbi decoding result) to the decoder 8. I have.

The decoder 8 is, for example, as shown in FIG.
A code word check circuit 31 for checking a state where an input code word is a starting point and a type of the code word, and a code word conversion for converting an input code word into another code word based on an output of the code word check circuit 31 The circuit 32 includes a decoding circuit 33 that decodes the converted code word, and decodes a 20-bit code word into an original 16-bit data word.

The PLL circuit 9 generates a clock based on the reproduced signal from the equalizer amplifier 5, and outputs the clock to the sampler 6, TC
The Viterbi detector 7 for PR, the decoder 8, the Viterbi detector 10 for PRML, and the SYNC detector 11 are output to the sampler 6, the Viterbi detector 7 for TCPR, the decoder 8, PRML Viterbi detector 10 and SYNC detector 11
Operate according to the clock from the PLL circuit 9.

The PRML Viterbi detector 10 detects a code sequence from the sample values supplied from the sampler 6 (Viterbi decoding), and supplies the detection result (Viterbi decoding result) to the SYNC detector 11. Has been made.

The SYNC detector 11 is a PRML Viterbi detector 1
The SYNC pattern (symbol synchronization pattern) is detected from the code sequence supplied from 0, and the detection result is supplied to the Viterbi detector 7 for TCPR and the decoder 8.

Next, the operation will be described.

The 16-bit data word input to the encoder 1 is converted into a 20-bit code word in accordance with a predetermined association between the data word and the code word. Here,
The values of ADS and RDS that this codeword can take must satisfy the following seven constraints.

Restriction 1 on Codeword "The maximum amplitude (maximum change width) of the ADS of the code sequence (a series of codewords) is 10, and the maximum amplitude (maximum change width) of the RDS is 1
Must be 0 ".

The above constraint 1 on the code word makes the maximum amplitude of ADS and RDS of the code sequence finite. Therefore, if a code is designed based on this constraint, the power density of the code becomes Nyquist frequency and DC ( Null at DC). That is, for a partial response whose transfer function has a null point at the Nyquist frequency or direct current (DC),
MSN code can be designed.

For example, a code based on a constraint 1 for a code word is converted to a code whose transfer function has a null point at the Nyquist frequency.
When applied to PR1, if d ² _free when encoding is not performed is 2, d ² _free can be set to 4. This code is DC-free, its DSV is 10 or less, and the maximum continuous length of the same symbol is 10 or less.

FIG. 4 is a finite state transition diagram (FSTD) showing the constraints of ADS and RDS that the code sequence must satisfy.
(Finite-State Transition Diagram)). A codeword to be encoded by the encoder 1 is selected from a path (a series of state transitions) consisting of 20 state transitions based on the FSTD.

Next, in order to specifically select a 20-bit code word, necessary restrictions are further added to the state of FIG. First, a state where the code word is a start point (start states) is selected. In FIG. 4, there are many possible ways to select a state in which the code word is the start point. In this case, the start point is selected according to the following three start point selection constraints A to C.

Constraint A for starting point selection "If the number of elements included in the set of states selected as the starting point is plural, the two states included in the set are (1) the center point of the FSTD (in FIG. 4, ADS axis located at a position symmetrical with respect to the state (5, 5) or passing through the center point of the FSTD (RDS = 5 in FIG. 4)
Which is located symmetrically with respect to the RDS axis passing through the center point of the FSTD (in FIG. 4, the axis where ADS = 5). Or (2) exists at a position symmetrical with respect to the center point of the FSTD, at a position symmetrical with respect to an axis where ADS = RDS, or orthogonal to an axis where ADS = RDS Must be satisfied whether it exists at a position that is symmetrical with respect to the axis to be set. " Here, the state is represented by (ADS, RDS).

Constraint B for starting point selection "A set of states selected as starting points is such that all elements can be the end points of the codeword for each of the elements included in the set. Must be set ".

Constraint C for starting point selection C The number of different paths from each element included in the set of states selected as the starting point to all elements included in the set is determined by the number of required codewords. If the set of states selected as the starting point includes elements with different ADS values, the number of paths after the above partitioning is required Must satisfy the number of codewords. "

The constraint A for starting point selection is intended to facilitate exchange between codes having different states as starting points. It is easy to generate a code word starting from the remaining state as a starting point from a code word starting from any one state of the starting point constraint A (details will be described later). Further, the number of states at the start point according to the restriction A of the start point selection is four at the maximum.

In this embodiment, the maximum amplitudes of ADS and RDS are both 10. In FIG. 4, the center point of the FSTD is the state (5, 5). In general, if the maximum amplitudes of both ADS and RDS are even, FSTD showing the limits of ADS and RDS
Has a symmetrical structure with respect to its center point. But AD
If one or both of the maximum amplitudes of S and RDS are odd, the symmetry is broken (in this case, there is no central state of the FSTD). This is easily confirmed by drawing the FSTD. The exchange between codes starting from different states is actually performed using the symmetry of FSTD,
If the symmetrical structure is broken, conversion between codes is wasted, so that the maximum amplitudes of ADS and RDS are both even numbers.

The reason why the constraint A for starting point selection is provided is to facilitate exchange between codes having different states as starting points. This has the following two advantages. First, the circuit scale of the encoder 1 and the decoder 8 can be reduced. The reason is that the encoder 1 needs to have a correspondence table for converting a data word into a code word only for a code starting from one state, and the decoder uses a code word as a data word. This is because it is only necessary to have a correspondence table for converting to a code starting from one state. For example, in a conventional encoder, a correspondence table of codes starting from all elements included in a set of states selected as starting points must be stored, but in FIG. Of the states included in the set of states selected as starting points, only a conversion table of codes starting from a certain state is stored, and codes starting from the remaining states are generated by the code word conversion circuit 22. Is done. The newly added code word conversion circuit 22, code word inspection circuit 24, and end point state conversion circuit 25 perform very simple processing, and their circuit scale is small.

Another advantage is that the operation speed of the encoder 1 can be improved. Generally, the portion of a device that forms a loop determines the operating speed of the device. And the more complicated the process in the loop, the more
The operating speed of the device is reduced. In FIG. 2, there is a loop from the output of the register 26 to the input of the register 26 via the end point state conversion circuit 25. In this loop, since the processing of the end point state conversion circuit 25 is simple, the The device 1 can be operated at a higher speed.

The constraint B for starting point selection will be described. FIG.
Are classified into the following four sets (S _{0 to} S ₃ ).

S ₀ = ｛(1,1), (1,5), (1,
9), (3,3), (3,7), (5,1), (5,
5), (5, 9), (7, 3), (7, 7), (9,
1), (9, 5), (9, 9)}

S ₁ = ｛(0,4), (0,8), (2,
2), (2,6), (2,10), (4,0), (4,
4), (4,8), (6,2), (6,6), (6,1)
0), (8, 0), (8, 4), (8, 8), (10,
2), (10, 6)｝

S ₂ = ｛(1,3), (1,7), (3,
1), (3,5), (3,9), (5,3), (5,
7), (7,1), (7,5), (7,9), (9,
3), (9, 7)｝

S ₃ = ｛(0,2), (0,6), (2,
0), (2,4), (2,8), (4,2), (4,
6), (4,10), (6,0), (6,4), (6,
8), (8, 2), (8, 6), (8, 10), (1
(0,0), (10,4), (10,8)}

There is no common element among the above four sets. Here, for example, consider a state transition when a starting point to any condition included in the set S _0. In this case, in one of the states at time 1 included in the set S _1, in one of the states at time 2 included in the set S _2, at time 3 in one of the states included in the set S ₃ The state transits and returns to one of the states included in the set S ₀ again at time 4. Thereafter, the state transition of S ₀ → S ₁ → S ₂ → S ₃ → S ₀ is repeated. Here, time 0 represents the time at which the code word takes the starting point. The time at which the 20-bit code word ends is 20
And the time 20 of the current codeword coincides with the time 0 at which the next codeword starts.

As described above, the FS expressing the restriction of ADS and RDS
In the TD, states can be classified into four sets that do not have a common element, and these four sets transit in a four-time cycle.
In the present embodiment, the code length of the code is 20 bits (4
For example, if a state included in the set S ₀ is selected as a start point, the state of the end point is set again to the set S ₀
Will be included.

Next, a case is considered where both the state included in the set S ₀ and the state included in the set S ₁ are selected as starting points. Assuming that a state included in the set S ₀ as a coding initial value is a start point, an end point of the first codeword is a state included in the set S ₀ . Since the start of the next code word must be this state, after all, as the start point and the end point of the code word, will not be used only states included in the set S _0. This is meaningless selected state included in the set S ₁ as the start and end points. Furthermore, assuming that the start point of the states included in the set S ₁ as the initial value for encoding, meaningless selected state included in the set S _0. Therefore, the condition to start, of the set S ₀ to S _3, it must be selected either from a single set.

The constraint C for starting point selection will be described. This restriction is natural. This is because, if the number of passes is not enough, there is no code word corresponding to some data words, and as a result, encoding cannot be performed. In this embodiment, state 1 as a starting point
On the other hand, the number of required different paths to all the states to be terminated is 2 ¹⁶ . Basically, the closer the starting point state is to the center point of the FSTD, the greater the number of paths from that point to all the end point states. Also, the number of paths depends on the number of selected end states, and the greater the number of end states, the greater the number.

Next, among the constraints A to C for selecting the starting point, selection examples 1 to 6 satisfying the constraints A and B will be described.
It is confirmed whether or not this satisfies the constraint C.

The first selection example is a case where the state (5, 5) is selected as a starting point. The states (5, 5) are shown in FIG.
This is the center point of the FSTD, and if one state is selected as the starting point, the most codewords can be taken. However, when examining the number of codewords that can be taken from the state (5, 5), there are only 55404 codewords, which does not satisfy the constraint C.

In the selection example 2, the state (5, 3) and the state (5, 3)
7) is selected as the starting point. State (5, 3)
Is the starting point, and the number of codewords having the state (5, 3) or the state (5, 7) as the end point is 83025.
7) as a starting point, state (5, 3) or state (5, 7)
The number of code words ending with is also 83025. Therefore, states (5, 3) and (5, 7) may be used as codeword starting points. Also, states (5, 1) and (5, 3) similar to states (5, 3) and (5, 7)
9) is a direction away from the center point of the FSTD, so that the number of candidate codewords is reduced. The number of codewords actually checked is 27783, which does not satisfy the constraint C.

In the selection example 3, the state (3, 5) and the state (7,
This is the case where 5) is selected as the starting point. Condition (3,5)
Is the starting point, and the number of codewords having the state (3, 5) or the state (7, 5) as the end point is 57375, which does not satisfy the constraint C.

In the selection example 4, the state (4, 4) and the state (6,
6) is selected as the starting point. Condition (4,4)
Is the starting point, and the number of codewords having the state (4, 4) or the state (6, 6) as the end point is 57834, which does not satisfy the constraint C.

When the two states are selected as the starting point and the ending point, it is obvious that the constraint C is not satisfied, except for the above-described selection examples 2 to 4, which are farther from the center point of the FSTD.

In the selection example 5, the state (3, 3) and the state (3, 3)
7), state (7, 3) and state (7, 7) are selected as starting points. Starting from state (3,3) or state (7,7), state (3,3), state (3,3)
7), the number of codewords ending at any one of the states (7, 3) and (7, 7) is 88992,
The constraint C is satisfied. Starting from state (3,7) or state (7,3), state (3,3), state (3,3)
7), the number of codewords ending at any of the states (7, 3) and (7, 7) is 82944,
The constraint C is satisfied.

In the selection example 6, the state (3, 5), the state (5,
3), the state (5, 7) and the state (7, 5) are selected as the starting points. Starting from state (5, 3) or state (5, 7), state (3, 5), state (5, 5)
The number of codewords ending at any one of 3), state (5, 7) and state (7, 5) is 111051, which satisfies constraint C. On the other hand, the state (3, 5) or the state (7, 5) is a starting point, and any one of the state (3, 5), the state (5, 3), the state (5, 7), and the state (7, 5) is used. The number of codewords ending with is 50814, which does not satisfy the constraint C.

When the four states are selected as the starting point and the ending point, the number of codewords is reduced because they are farther from the center point of the FSTD except for the above selection examples 5 and 6. When actually inspected, the constraint C is not satisfied except for the selection example 5.

In addition to the above selection examples 1 to 6, it is conceivable that three states are set as the starting points. However, these are not described here because no advantage is found.

Therefore, the selection examples 2 and 5 satisfy the constraints A to C of the start point selection. Selection example 2
Is an example in which the most codewords can be selected among the selection methods that do not require partitioning, and selection example 5 is an example in which the most codewords can be selected among the entire selection methods.
In the present embodiment, selection example 5 in which the number of codewords is the largest is used as a method of selecting a starting point.

That is, in the constraint 2 on the code word “FSTD, the state at time 0 and time 20 is the state (3,
3), state (3, 7), state (7, 3) and state (7, 7) ".

By the way, in the present embodiment, QC
Partitioning is used as a rule to prevent sequences. The restriction required for the code power density to be null at the Nyquist frequency is for ADS, and Viterbi detection is also performed using ADS information. Therefore, partitioning is also performed on ADS.

According to the partitioning, the state (3,
Among the codes starting from four states of 3), state (3, 7), state (7, 3) and state (7, 7), ADS is 3
The code word whose starting point is the state of AD
A code word whose SDS does not become 3 or less and the ADS is 7 as a starting point does not have an ADS of 7 or more at any one same time.

Generally, when the time subject to the above restriction is set to a later time, the number of code words can be increased. However, when the time is delayed, the number of different paths from the starting point to the time increases. Therefore, in the present embodiment, J.
W. Rae, GS Christinansen, P. Siegel, R. Karabed, H. Thapa
r, and S.Shih, “Design and Performance of a VLSI120
Mb / s Trellis-Coded Partial Response Channel ”, IEEE
Transactions on Magnetics, Vol. 31, No. 2, March 1995,
Assuming that a part of the method proposed in pp.1208-1214 is applied to the Viterbi detector, the time to be restricted is set to 7.

That is, the constraint 3 on the codeword "(1) A path started from a state where ADS is 3 at time 0 passes through a state where ADS is 0 and ADS is 2 at time 7 (2) A path started from the state where the ADS is 7 at time 0 must not pass through the state where the ADS is 8 and the state where the ADS is 10 at time 7 ".

In this embodiment, when the state (3, 3) or the state (7, 7) is the starting point, the number of codewords is eight.
The number of codewords when 8992, the state (3, 7) or the state (7, 3) is the starting point is 82944. The number of codewords required in the present invention is 65536, and in any case, a considerable number of codewords are left.

Therefore, the maximum continuous length of the same symbol of the code is made smaller than 10. In the FSTD of FIG. 4, the same bit continues for the longest time because the RDS increases by one and the minimum R
When transitioning from DS (minimum value of RDS) to maximum RDS (maximum value of RDS), RDS decreases by 1 and the maximum RDS changes to the minimum RDS
This is the case when the transition is made. Therefore, the same bit is continuous for the longest case.

In order to set the maximum continuous length of the same symbol of the code to 9, in the FSTD of FIG. 4, the state where the RDS is 10 is reached after 10 state transitions from the state where the RDS is 0. In addition, it is only necessary to prohibit from starting from the state where the RDS is 10 and to reach the state where the RDS is 0 in ten state transitions. It is impossible to set the maximum continuous length of the same symbol of the code to 8 because the number of candidate codewords is insufficient.

Restriction 4 on Codeword “(1) RD at time 0
The path starting from the state where S is 3 does not pass through the state where RDS is 0 at time 3;
Does not pass through the state where the DS is 10; (c) does not transition from the state where the RDS is 0 at time 5 to the state where the RDS is 10 at time 15 by increasing the RDS by 1;
(D) RDS at time 7 changes from 0 to 1
In this case, the condition that the RDS at time 17 does not transit to the state of 10 must be satisfied. (2)
At time 0, the path starting from the state where the RDS is 7 is
(A) Do not pass the state where the RDS is 10 at time 3,
(B) do not pass the state where RDS is 0 at time 7;
(C) From the state where the RDS is 10 at time 5, the RDS decreases by 1 and does not transition to the state where the RDS is 0 at time 15. (D) From the state where the RDS is 10 at time 7, the RDS Decreases by 1 and the RDS at time 17
Must not satisfy the following four conditions. Is set.

The 20-bit code word output from the encoding circuit 21 is supplied to a code word check circuit 24, where the type and end point of the code word are checked. The type and end point can be known from the process of sequentially calculating the ADS and RDS values from the bit on the starting point side of the code word, using the ADS and RDS values at the start point of the supplied code word as initial values, and the results. it can. ADS and R
The method of calculating DS is clear from the above definition.

Assuming that the RDS at the start point of the codeword to be encoded by the codeword circuit 21 is 3, in the process of sequentially calculating the value of the RDS, it is determined whether the RDS is greater than 6 by checking whether the RDS is greater than 6. Determine the word type. In the present embodiment, RDS is 6
The case where it does not become larger is referred to as “type 0”, and the case where the RDS becomes larger than 6 is referred to as “type 1”. By the way, since the initial value of the RDS is 3, if the RDS is larger than 6, the RDS must be set at any time after time 4 (including time 4).
Becomes 7. In addition, the time at which the RDS may be 7 is only an even time according to the definition of the RDS. From this, the type of the code word is determined based on whether or not the value of the RDS becomes 7 at an even-numbered time after the time 4.

As described above, when the RDS that is the start point of the codeword to be encoded by the codeword circuit 21 is 3,
The type of the code word is determined based on whether or not the RDS is 7, but the RD in the state where the code word is encoded by the code word circuit 21 is the starting point.
If S is 7, the codeword type is determined based on whether RDS is 3. Details will be described later. Obviously, the result of determining ADS and RDS up to the last bit of the codeword indicates the state of the end point of the codeword.

FIG. 5 shows an example of a specific circuit configuration of the codeword check circuit 24 when the start point of the codeword to be encoded by the codeword circuit 21 is the state (3, 3).

First, the RDS 3-bit UP / DOWN counter 44 and the ADS 3-bit UP / DOWN counter 50 are initialized and set to 1 at the boundaries between codewords. Further, the output of the comparator 45 is reset. Thereafter, the input 20-bit code word is converted to a parallel / serial converter 41.
, The data is divided into two bits from the starting point side, and are sequentially transmitted. The transmitted 2-bit data is supplied to the EXNOR 42 and the AND 43, respectively, and operated. EXNOR42
Is the ENABLE of the RDS 3-bit UP / DOWN counter 44
Is supplied to the terminal, and the output of AND43 is 3-bit UP / D for RDS
It is supplied to the UP / DOWN terminal of the OWN counter 44. 3 for RDS
The bit UP / DOWN counter 44 sequentially calculates RDS.

In the 2-bit data sent from the parallel / serial converter 41, the bit on the time side later than the start point is inverted by the inverter 47, and the EXNOR 48
And AND 49, respectively, and are operated. EXNOR
The output of 48 is the EN of the 3-bit UP / DOWN counter 50 for ADS.
Supplied to the ABLE terminal, the output of AND49 is 3 bits for ADS
It is supplied to the UP / DOWN terminal of the UP / DOWN counter 50. ADS
The 3-bit UP / DOWN counter 50 sequentially calculates ADS.

ADS and R obtained by calculating to the end of the code word
The value of DS takes the second bit from the LSB, and is stored in the end point register 51 at the boundary between codewords. RDS
The output of the 3-bit UP / DOWN counter 44 for
, And are sequentially compared with 3 until the end of the codeword. If there is a match even once, the output of the comparator 1 is set to 1 and stored in the type register 46 at the boundary between codewords. The output of the type register 46 and the output of the end point register 51 are output from the code word check circuit 24 as the code word type and end point.

When the ADS at the start of the codeword to be encoded by the codeword circuit 21 is 7, the ADS 3-bit UP / DOWN is used.
The initial value of the counter 50 is set to 3. Further, when the RDS at the start point of the codeword to be encoded by the codeword circuit 21 is 7, the initial value of the RDS 3-bit UP / DOWN counter 44 is set to 3, and the comparator 45 compares it with 1. .

FIG. 5 shows a configuration in which the values of ADS and RDS are successively calculated for two bits together. this is,
This is because it is most efficient for ADS and RDS to operate on two bits collectively due to the nature of the definition. In the case of sequentially calculating one bit at a time, the operation of setting the values of ADS and RDS to “+1” or “−1” is repeated 20 times.
On the other hand, when two bits are sequentially calculated, "+
The operation of “2”, “−2”, or nothing is repeated ten times. Here, "+2"
And "-2" may be replaced with "+1" and "-1". The operation of "+1" and "-1" can be realized by the UP / DOWN counter.
The UP / DOWN counter must be capable of counting from 0 to 10 (a 4-bit counter). Meanwhile, 2
In the case of sequentially calculating the bits collectively, a device capable of counting from 0 to 4 (a 3-bit counter) may be used. That is, the configuration in which two bits are operated collectively requires half the number of operations as compared with the configuration in which one bit is operated, and the UP / D
The bit width of the OWN counter can be reduced by one bit.

By the way, it is also possible to check the type and end point of the code word in advance and store it in the encoding circuit 21 together with the code word. In this case, the code word inspection circuit 24
Although unnecessary, the circuit scale of the encoding circuit 21 increases.

The state where the code word output from the code word check circuit 24 is the end point is supplied to the end point state conversion circuit 25. The end point state conversion circuit 25 converts the supplied end point state into the code word conversion circuit 22 stored in the register 26.
The codeword output this time from the codeword conversion circuit 22 is determined to be the end point based on the state in which the codeword output this time from this time is the start point (the state in which the codeword previously output from the codeword conversion circuit 22 is the end point). Calculate the state to perform. The state of the end point output from the end point state conversion circuit 25 is stored in the register 26, and is set to a state in which the next codeword output from the codeword conversion circuit 22 is the start point.

The state where the code word output this time from the code word conversion circuit 22 is the starting point is different from the state where the code word output this time from the encoding circuit 21 is the starting point, in a position symmetric with respect to a point or an axis. In some cases, the state in which the codeword currently output from the codeword conversion circuit 22 is the end point is different from the state in which the codeword currently output from the encoding circuit 21 is the end point in a position symmetric with respect to a point or an axis. is there. Therefore, the encoding circuit 21
The state where the code word output from is the end point is converted to a state at a position symmetrical with respect to a point or an axis. That is, a state where the code word output from the code word conversion circuit 22 is the starting point (output of the code word check circuit 24), and a state where the code word output from the encoding circuit 21 is the starting point (output of the register 26). Are different, the element in the state of the end point output from the encoding circuit 21 corresponding to the different element (ADS or RDS) has a different value (3 becomes 7 and 7 becomes 3). Is converted to

In the present embodiment, there are only 3 or 7 ADSs and RDSs at the start and end points. This means that both the ADS and RDS at the start and end points can be represented by one bit.

Therefore, the state in which the code word output from the encoding circuit 21 is the starting point is (0, 0), and the state in which the other starting point and the ending point are the ADS and RDS values is ADS and RDS starting from the output codeword
Is represented by 0 when the values are the same, and by 1 when the values are different. For example, when the start point of the codeword to be encoded by the encoding circuit 21 is the state (3, 3), the state (3, 3) is the state (0, 0), and the state (3, 7) is the state (0). , 1)
The state (7, 3) is expressed as a state (1, 0), and the state (7, 7) is expressed as a state (1, 1).

In other words, in the end point state conversion circuit 25, the output of the register 26 (the code word conversion circuit 22
In the case where each bit in the state where the code word output from is the starting point is 1 and the bit is 1, the corresponding code word check circuit 2
4 output bits may be inverted. This is nothing but adding mod2 for each bit.
That is, as shown in FIG. 6, the conversion of the end point state can be performed using the mod2 adders (EXOR) 61 and 62.

Next, the code word conversion circuit 22 will be described. Codeword output from coding circuit 21, type of codeword output from codeword checking circuit 24, and register 2
6 is the starting point, the code word conversion circuit 2
2 is supplied. The codeword conversion circuit 22 converts, for example, a codeword whose starting point is in the state (0, 0) into a codeword whose starting point is the state indicated by the register 26, based on the type of the codeword.

The state where the code word output from the code word conversion circuit 22 is the starting point is located symmetrically with respect to the point or axis with respect to the state where the code word output from the coding circuit 21 is the starting point. In this case, the code word output from the encoding circuit 21 is converted into a code word that transitions from a start point to an end point, a target point or an axis and a state at a target position. However, in the structure of FIG. 4, if the ADS axis or the RDS axis passing through the center point of the FSTD is considered sequentially from the start point for the state transition after the conversion, it is possible to transition to the state at the axisymmetric position at even-numbered times. At an odd-numbered time, the state cannot be shifted to an axially symmetric position. Therefore, in the present invention, ADS passing through the center point of FSTD
In the case of conversion on the axis or the RDS axis, the codeword output from the encoding circuit 21 transitions from a start point to an end point, a state at a position symmetrical to the target axis at even-numbered times, and a transition to an even-numbered time at odd-numbered times. It is assumed that a state that is uniquely determined from a state to be changed is converted into a code word that changes. This allows for conversion between codewords whose starting point state is symmetric with respect to the point or axis. Also, the code word conversion circuit 2
The data word assigned to the code word before conversion (the code word output from the encoding circuit 21) is directly assigned to the code word converted in step 2.

However, in consideration of decoding, some of the codewords should not be applied with the above conversion rule.

Restriction on Code Word Assignment "(1) Code words having different starting states must be assigned to the same data word. (2) Code words having an all-bit inversion relationship are the same. Must be assigned to the data word. "

The constraint (1) on code word allocation will be described. If the code word c ₁₁ included in the code C ₁ starting from a certain state and the code word c ₂₁ included in the code C ₂ starting from another state are the same code word, the code word c ₁₁ is converted to data D
Data word d ₁ contained, assigning a codeword c ₂₁ to another data word d ₂ included in the data D, it is impossible to know the starting point of the code word at the time of decoding. Therefore, when the code word c ₁₁ or the code word c ₂₁ is obtained, it cannot be determined which of the data words d ₁ and d ₂ should be decoded.

In the present embodiment, the code word check circuit 31 checks the starting point of the code word at the time of decoding. However, the code word check circuit 31 identifies the state of the start point in the same code word by the ADS. This is impossible because the transitions of RDS and RDS are exactly the same. This means that if the same codeword exists in a code starting from a point or axis symmetric state and these are assigned to different data words, which data word should be decoded? It means that you cannot judge.

For example, consider two code words C ₁₁ and C ₁₂ included in a code C ₁ starting from a certain state and being symmetric with respect to the starting point or an axis passing therethrough. Here, C ₁₁ and C ₁₂ are different data words d ₁ and d ₂ , respectively.
Suppose you were assigned to These C ₁₁ and C ₁₂ are
If converted to code words C ₂₁ and C ₂₂ that are symmetric about the center point of the FSTD or an axis parallel to the axis passing through it, then C ₂₁ and C ₂₂ are data words d ₁ and d ₂ , respectively.
Will be assigned to

The code words C ₁₁ and C ₁₂ are symmetric with respect to a point or an axis, and the code words C ₁₂ and C ₂₂ are also symmetric with respect to a point or an axis. Doing symmetric conversion twice to point symmetry conversion or the same axis, since it is clear to return to the original code word, C ₁₁ and C ₂₂ will be the same code word. Accordingly, C ₁₁ and C ₂₂ are to be assigned to the same data word, when thus performs conversion based on the code word conversion rule will be assigned to another data word d ₁ and d _2.

In the present embodiment, the same code word exists in the codes starting from a state symmetric with respect to the ADS axis passing through the center point of the FSTD in FIG. These must be assigned to the same data word. However, if the aforementioned codeword conversion rules are applied to all codewords, they will be assigned to different data words.
Further, among the codes starting from the center point of the FSTD itself and the state symmetrical to the RDS axis passing through the center point of the FSTD, the same code word does not exist due to the restriction 3 on the code word.

Next, the constraint (2) on code word allocation will be described. Assume that code words C ₁₁ and C ₃₁ are in an all-bit inversion relationship, and that C ₁₁ is assigned to data word d ₁ and C ₃₁ is assigned to data word d ₂ . Here, C ₁₁ and C ₃₁ is because it is another code word, if the polarity of the recording and reproduction in the original all the recording and reproducing apparatus has been properly managed, can be decoded without problems. However, if the polarity upon reproducing the polarity of the recording had been reversed, for example, when receiving the C ₁₁ at the time of decoding, the data word d ₁ without resulting in erroneously decoded data word d _2.

It is complicated to manage all the polarities of the individual recording / reproducing devices, and depending on the detection method, it is not possible to identify the polarity because the magnetization reversal is detected instead of the magnetization direction. , Are generally assigned to the same data word.

Consider two code words C ₁₁ and C ₁₂ included in a code C ₁ starting from a certain state and being symmetric with respect to an axis passing through the starting point. Here, the C ₁₁ and C ₁₂ are, were respectively assigned to different data words d ₁ and d _2. The C ₁₁ and C _12, when the converted code word C ₃₁ and C ₃₂ is symmetrical with respect to an axis orthogonal to the aforementioned axis passing through the center point of FSTD, C ₃₁ and C ₃₂ are respectively data Word d
It will be assigned to ₁ and d _2.

Incidentally, the code words C ₁₁ and C ₁₂ are symmetric with respect to the axis, and the code words C ₁₂ and C ₃₂ are symmetric with respect to the axis orthogonal thereto. It is clear that performing a conversion once for each orthogonal axis results in a code word with all bits inverted, so that C ₁₁ and C ₃₂ are code words with all bits inverted. Accordingly, C ₁₁ and C ₃₂ is to be allocated to the same data word, when the conversion based on the code word conversion rule will be assigned to another data word d ₁ and d _2.

In the present embodiment, the code words in an all-bit inversion relationship are defined between the codes starting from a state symmetric with respect to the center point of the FSTD and the RDS axis passing through the center point of the FSTD. It exists between codes starting from a symmetric state. These must be assigned to the same data word. The conversion for the center point of the FSTD is all-bit inversion according to the codeword conversion rule, and there is no problem because the codewords having the all-bit inversion relation are assigned to the same data word. However, the conversion for the RDS axis passing through the center point of the FSTD may be assigned to a different data word if the code word conversion rule is applied to all code words. Also, the code itself starting from each state, and FSTD
There is no codeword in an all-bit inversion relationship between codewords starting from a symmetric state with respect to the ADS axis passing through the center point due to the restriction 3 on the codeword.

In order to satisfy the above-mentioned restriction (1) on code word allocation, the following two cases are considered. (A) whether code words C ₁₁ and C ₁₂ are assigned to the same data word d ₁ ,
Or of C ₁₁ and C _12, it does not use either as a code word. (B) If C ₁₂ with respect to C ₁₁ are present, C ₁₁
Not to perform code word conversion of C _12.

In the case of (a), the codeword conversion rule can be applied as it is, but in the case of (b), the codeword conversion rule needs to be partially corrected. When comparing (a) and (b),
(B) requires less codewords to be wasted.

In order to satisfy the above-mentioned restriction (2) on code word allocation, the following two cases can be considered. (A) whether code words C ₁₁ and C ₁₂ are assigned to the same data word d ₁ ,
Or of C ₁₁ and C _12, it does not use either as a code word. (B) If C ₁₂ with respect to C ₁₁ are present, C ₁₁
A code word conversion of C ₁₂ is the all-bit inversion.

In the case of (a), the code word conversion rule can be applied as it is, but in the case of (b), the code word conversion rule needs to be partially corrected.

Therefore, the code word conversion rules are modified as follows. (1) If a code word has a code word that is symmetric with respect to its starting point or an axis passing through the code word, the code word is positioned with respect to the center point of the FSTD or an axis parallel to the aforementioned axis passing through it. Do not convert. In this case, the codeword conversion circuit 22 outputs the input codeword as it is.
(2) If a code word has a code word that is symmetric with respect to an axis passing through the start point, the code word is shifted with respect to an axis passing through the center point of the FSTD and orthogonal to the above-described axis. When conversion is performed, all bits are inverted.

In the present embodiment, as described above, the same code word exists in codes starting from a state symmetric with respect to the ADS axis passing through the center point of FSTD, and the center point of FSTD is Among the codes starting from a state symmetric with respect to the passing RDS axis, there is a code word having an all-bit inversion relation.
Therefore, the correction items (1) and (2) of the codeword conversion rule
Is the ADS axis passing through the center point of the FSTD.

A case where an axially symmetric code word exists in a code word is a case where an axially symmetric state exists for all the even-time states from the start point to the end point of the code word. In the present embodiment, the AD passing through a certain code word through its starting point
The case where a target codeword exists on an axis parallel to the S-axis means that a codeword whose RDS is 3 as a starting point has
When the DS is 6 or less, the codeword starting from the state where the RDS is 7 is a case where the RDS is 4 or more.

This is the type of the code word described above. If the RDS starting from the codeword encoded by the encoding circuit 21 is 3, if the RDS of the codeword is 6 or less, the type is 0;
If it is 7 or more, the type is 1. If the RDS starting from the codeword encoded by the encoding circuit 21 is 7, the type is 0 if the RDS of the codeword is 4 or more, and the type is 1 if the RDS of the codeword is 3 or less.

FIG. 7 shows an example of the circuit configuration of the code word conversion circuit 22. The codeword conversion performed by the codeword converter 72 by modifying the codeword conversion rules and the codeword conversion rules will be described with reference to FIG. Start point state (0,0)
, No codeword conversion is performed. Therefore, the codeword input to the codeword conversion circuit 22 is output as it is.

In the case of the starting point state (0, 1), when the type of the code word is 0, the code word is not converted in accordance with the correction item (1) of the code word conversion rule. When the type of the code word is 1, the code word is divided into 10 pieces in units of 2 bits according to the code word conversion rule, and 00 is 11 for each.
Is converted to 00.

In the state of the starting point (1, 0), when the type of the code word is 0, all bits of the code word are inverted according to the correction item (2) of the code word conversion rule. When the type of the code word is 1, the code word is divided into 10 pieces in 2-bit units according to the code word conversion rule, and 01 is 10 for each.
Is converted to 01.

In the case of the starting point state (1, 1), all bits of the code word are inverted according to the code word conversion rule.

By the way, when the code word is converted according to FIG. 9, even if the code starting from the fixed state output from the encoding circuit 21 complies with the constraints 3 and 4 for the code word, the code Some codewords starting from a state different from that output from the word conversion circuit 22 may break the restrictions 3 and 4 on the codeword.

When considering only the transition of ADS, the constraint 3 on the code word has a structure symmetrical with respect to the axis in the time direction passing through the center in the ADS direction.
Has a structure that is symmetric with respect to the time axis passing through the center in the RDS direction when considering only the RDS transition. Therefore, if the codeword conversion rule allows a completely axially symmetric conversion, even if the codeword conversion is performed according to the codeword conversion rule, the constraints 3 and 4 cannot be broken. However, due to the structure shown in FIG. 4 (that is, due to the nature of ADS and RDS), a completely axisymmetric conversion is not possible, so that the conversion based on the codeword conversion rule may break the constraint. Also, it is clear that the modification of the codeword conversion rule is not an axially symmetric conversion, and the conversion based on the modification of the codeword conversion rule may break the constraint.

Therefore, when the path from the start point to the end point on the FSTD is converted according to the code word conversion rule and the path of the converted word breaks the given constraint, the corresponding path before conversion is prohibited. .

In the present embodiment, the encoding circuit 21
The following constraints 5 to 7 are set in order to select a codeword stored in. As a result, even if conversion between codewords having a starting point symmetric with respect to the axis is performed, the above-described constraint violation is eliminated.

Constraint 5 on Code Words "(1) If the starting point of a code to be encoded by the encoding circuit 21 is the state (3, 3), of the paths started from this state at time 0,
A path whose ADS at time 6 is 3 and whose ADS at time 7 is 4 and whose ADS at time 8 is 3 must not have an RDS of 7 at any time. (2) When the starting point of the code to be encoded by the encoding circuit 21 is the state (3, 7), among the paths started from this state at the time 0, the ADS at the time 6 is 3
A path whose ADS at time 7 is 4 and whose ADS at time 8 is 3 must not have an RDS of 3 at any time.
(3) When the starting point of the code to be encoded by the encoding circuit 21 is the state (7, 3), among the paths started from this state at the time 0, the ADS at the time 6 is 7 and the ADS at the time 7 is ADS
The path whose ADS is 6 at time 8 and the ADS is 7 at time 8 must not have RDS 7 at any time. (4) When the starting point of the code to be encoded by the encoding circuit 21 is the state (7, 7), of the paths started from this state at time 0,
A path whose ADS at time 6 is 7 and whose ADS at time 7 is 6 and whose ADS at time 8 is 7 must not have an RDS of 3 at any time. Is set.

Restriction 6 on Codeword “(1) If the RDS at the start point of the code to be encoded by the encoding circuit 21 is 3,
Of the paths started from this state at time 0, time 3
A path with an RDS of 6 must have an RDS of 7 at any time. (2) If the RDS at the starting point of the code to be encoded by the encoding circuit 21 is 7, the RDS at time 3 of the path started from this state at time 0 is 4
Must have an RDS of 3 at any time. Is set.

Restriction on Codeword 7 "(1) If the RDS at the start point of the code to be encoded by the encoding circuit 21 is 3,
The path started from this state at time 0 is (a) the RDS at time 2 is 1 and the RDS at time 3 is 2 and the RD at time 4 is
S is 1 and RDS does not become 7 or more at any time (b) RDS at time 4 is 1 and RDS at time 5 is 2 and RDS at time 6 is 1 and RDS at time 14 is 9 and Time 15
RDS at time 8 and RDS at time 16 do not become 9 (c)
RDS at time 6 is 1 and RDS at time 7 is 2 and RDS at time 8 is 1 and RDS at time 16 is 9 and RD at time 17
S is 8 and RDS at time 18 does not become 9 (d) Time 6
RDS at time 9 and RDS at time 7 is 8 and RDS at time 8
Must be satisfied that does not become 9. (2) If the RDS at the start of the code to be encoded by the encoding circuit 21 is 7, the path started from this state at time 0 is
(A) RDS at time 2 is 9 and RDS at time 3 is 8 and RDS at time 4 is 9 and RDS does not become 3 or less at any time (b) RDS at time 4 is 9 and time RDS at 5 is 8
RDS at time 6 is 9; RDS at time 14 is 1; RDS at time 15 is 2; and RDS at time 16 is not 1. (c) RDS at time 6 is 9 and RDS at time 7 Is 8 and the RDS at time 8 is 9 and the RDS at time 16 is 1 and time 17
RDS at time 2 and RDS at time 18 do not become 1 (d)
The RDS at time 6 is 1 and the RDS at time 7 is 2 and the RDS at time 8 does not become 1. Is set.

The constraint 5 on the code word is set so as not to break the constraint 3 on the code word when the code word is converted in accordance with the code word conversion rule. The constraint 6 on the codeword is set so as not to break the constraint 4 on the codeword when the codeword is converted in accordance with the modification of the codeword conversion rule. The constraint 7 on the code word is set so as not to break the constraint 4 on the code word when the code word is converted according to the code word conversion rule.

There are 70773 code words at each start point that satisfy the above restrictions 1 to 7 on code words, and 65536 code words are selected from these. In this way, the 16-bit data word encoded by the selected encoding circuit 21 is assigned to the 20-bit code word in a one-to-one relationship.

FIGS. 10 and 11 show a part of the correspondence between data words and code words when the starting point to be encoded by the encoding circuit 21 is in the state (3, 3). 1 in the left column
A 6-bit data word is shown in hexadecimal, and a 20-bit code word is shown in the right column in binary.

The 20-bit code word output from the code word conversion circuit 22 is converted into a parallel / serial (P / S) converter 23.
Supplied to In the P / S converter 23, the 20-bit codeword as parallel data from the codeword conversion circuit 22 is converted into serial data and output.

The 20-bit code word string as serial data is recorded on the medium 3 via the recording amplifier 2.

When the medium 3 is reproduced, a reproduction signal obtained by the reproduction is amplified by a reproduction amplifier 4, then equalized by an equalizer amplifier 5, and sampled by a sampler 6.
Is supplied to the PLL circuit 9.

The PLL circuit 9 generates a clock from the input reproduced signal, and outputs the generated clock to the sampler 6, TC
It is supplied to a PR Viterbi detector 7, a decoder 8, a PRML Viterbi detector 10, and a SYNC detector 11.

In the sampler 6, the ternary reproduced signal to which disturbance from the equalizer amplifier 5 has been added is sampled in synchronization with the clock supplied from the PLL circuit 9. Then, the sample value obtained as a result is the Viterbi detector 7 for TCPR and
The data is supplied to the PRML Viterbi detector 10, whereby the original binary code is detected.

The codeword string detected by the PRML Viterbi detector 10 is supplied to a SYNC detector 11 where a SYNC pattern is detected. Then, a synchronization signal for the code word obtained as a result is supplied to the Viterbi detector 7 for TCPR, and the synchronization is achieved.

Since the Viterbi detector 7 for TCPR has a time-varying structure (the structure changes with time) corresponding to the restrictions 2 and 3 on the codeword, the boundary of the 20-bit codeword cannot be known. And detection cannot be started. for that reason,
Before starting the Viterbi detection of TCPR, it is necessary to detect a bit string by the PRML Viterbi detector 10 and to detect a code boundary by the SYNC detector 11 from the bit string. still,
Since the PRML Viterbi detector 10 has a time-invariant structure,
No synchronization signal is required for the codeword.

The 20-bit code word detected by the Viterbi detector 7 for TCPR is supplied to a decoder 8 and decoded into an original 16-bit data word.

The starting points of the codeword input to the decoder 8 are state (3, 3), state (3, 7), state (7,
3) There is a possibility in all of the states (7, 7). However, in the present embodiment, the starting point of the codeword to be decoded by the decoding circuit 33 is any one state. Therefore,
In order for the decoding circuit 33 to decode correctly, the codeword input to the decoder 8 must be converted into a codeword that can be decoded by the decoding circuit 33 in advance. To do so, the starting point and type of the input codeword must be known.

The codeword input to the decoder 8 is input to a codeword check circuit 31 which is a circuit for checking the starting point and type of the code. In the codeword check circuit 31, the input is performed on the assumption that any one of the states (3, 3), (3, 7), (7, 3), and (7, 7) is the starting point. The transitions of ADS and RDS of the codeword obtained are examined.

The ADS at the start of a codeword can be known from whether or not the examined transition of the ADS satisfies the constraint 3 on the codeword. If constraint 3 for the codeword is satisfied, the ADS at the starting point assumed in advance is correct, and
If not, the assumed starting ADS was wrong.

The RDS at the start of the codeword can be known from whether or not the transition of the examined RDS satisfies the constraint 1 for the codeword. There is a common codeword between codes starting from different RDS states. Therefore, when the transition of the RDS satisfies the constraint 1, the starting RDS cannot be specified for these common codewords. But,
By modifying the codeword conversion rules, the same codeword with a different starting RDS is assigned to the same data word, so the starting RD
Even if S is wrong, the decryption result is the same, and eventually R
It is not necessary to specify DS. For codewords that are not common, if the RDS transition satisfies constraint 1,
The RDS of the starting point assumed in advance is correct, and if the constraint 1 is not satisfied, the RDS of the assumed starting point is wrong.

The type of the code word is determined based on the definition of the type described above based on whether or not there is a symmetric code word with respect to the axis in the ADS direction passing through the state assumed as the starting point. can do. In the present embodiment, when a symmetric codeword exists, the type of the codeword is set to 0, and when no symmetric codeword exists, the type of the codeword is set to 1.

The following processing is performed in the code word inspection circuit 31. Assuming that the starting ADS is 3, A at time 7
The DS is checked. If the DS is larger than 3, the ADS at the start of the input codeword is 3, and if the DS is smaller than 3, the ADS at the start of the codeword is 7.

Assuming that the ADS at the start point is 7, the ADS at time 7 is examined. If the ADS is smaller than 7, the ADS at the start point of the input codeword is 7; It is assumed that the ADS at the start point of is 3.

Assuming that the starting RDS is 3, the RDS
And if this does not become −1 at any time, it is assumed that the RDS at the starting point of the input codeword is 3,
Otherwise, assume that the RDS at the start of the input codeword is 7.

Assuming that the starting RDS is 3, the RDS
Is examined, and if this does not become -1 or 7 at any time, it is assumed that the codeword type is 0, and otherwise, it is 1.

Assuming that the starting RDS is 7, the RDS
, And when this does not become 11 at any time, it is assumed that the RDS at the starting point of the input codeword is 7,
Otherwise, assume that the RDS at the start of the input codeword is 3.

Assuming that the starting RDS is 7, the RDS
Is examined, and if this does not become 3 or 11 at any time, it is assumed that the codeword type is 0, and otherwise, it is 1.

FIG. 8 shows an example of the configuration of the code word check circuit 31 when the start point of the code word encoded by the encoding circuit 21 is in the state (3, 3).

First, the RDS 3-bit UP / DOWN counter 84 and the ADS 3-bit UP / DOWN counter 90 are initialized and set to 1 at the boundaries between codewords. Further, the outputs of the comparator 85 and the comparator 91 are reset. Thereafter, the input 20-bit codeword is divided by the parallel / serial converter 81 into two bits each from the starting point side, and is sequentially sent out. The transmitted 2-bit data is supplied to the EXNOR 82 and the AND 83, respectively, and operated. The output of the EXNOR 82 is supplied to the ENABLE terminal of the RDS 3-bit UP / DOWN counter 84, and the output of the AND 83 is supplied to the UP / DOWN terminal of the RDS 3-bit UP / DOWN counter 84. The RDS 3-bit UP / DOWN counter 84
Operate RDS sequentially.

In the 2-bit data transmitted from the parallel / serial converter 81, the bit on the time side later than the start point is inverted by the inverter 87, and the EXNOR 88
And AND 89, respectively, and are operated. EXNOR
The output of 88 is the EN of the 3-bit UP / DOWN counter 90 for ADS.
Supplied to the ABLE terminal, the output of AND89 is 3 bits for ADS
It is supplied to the UP / DOWN terminal of the UP / DOWN counter 90. ADS
The 3-bit UP / DOWN counter 90 sequentially calculates ADS.

The output of the RDS 3-bit UP / DOWN counter 84 is supplied to a comparator 85, and is sequentially compared with 3 and 7 until the end of the code word. If any one of them matches, one of the outputs of the comparator 85 is set to 1, and
The data is stored in the type register 86 at the boundary between codewords. Also, in the comparison with 7, if the values match even once, the comparator 8
The remainder of the output of 5 is set to 1 and stored on the LSB side of the starting point register 92 at a break between codes.

On the other hand, ADS 3-bit UP / DOWN counter 90
Is supplied to the comparator 91. From the counter value obtained by calculating up to the sixth bit of the code word and the seventh bit of the code word, the counter value is 1 and the inversion of the seventh bit is 0,
Counter value is 0, counter value is 7, counter value is 6
Is checked. If any one of them is true, the output of the comparator 91 is set to 1 and stored on the MSB side of the starting point register 92 at the boundary between codewords.
The output of the type register 86 and the output of the start point register 92 are used as the code word type and the start point as the code word check circuit 3.
1 is output.

The start point and type of the code word output from the code word check circuit 31 are supplied to the code word conversion circuit 32. The codeword conversion circuit 32 receives the 20-bit codeword as it is. Then, the codeword conversion circuit 32 converts the input codeword into a codeword to be decoded by the decoding circuit 33 based on the starting point and the type of the code. The conversion method is the same as in FIG. That is, the code word conversion circuit 32
Is the same as the code word conversion circuit 22.

The code word converted by the code word conversion circuit 32 is decoded by the decoding circuit 33 into the original 16-bit data word associated with the coding circuit 21.

It should be noted that various modifications and application examples can be considered without departing from the gist of the present invention. Therefore, the gist of the present invention is not limited to the present embodiment.

In this specification, provided media for providing a user with a computer program for executing the above processing include information recording media such as a magnetic disk and a CD-ROM, as well as networks such as the Internet and digital satellites. Transmission media is also included.

[0170]

As described above, according to the encoding method according to the first aspect and the encoding apparatus according to the sixteenth aspect, the encoding from the data word starts from one predetermined state. , And a code word starting from another state can be obtained by further conversion. Therefore, it is possible to reduce the size of the encoder and operate it at high speed.

According to the decoding method of the seventeenth aspect and the decoding apparatus of the thirty-second aspect, the input codeword is converted into a codeword starting from one predetermined state, and the Words are obtained by decoding codewords. Therefore, the size of the decoder can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a recording and reproducing apparatus to which an encoding method and a decoding method of the present invention are applied.

FIG. 2 is a block diagram illustrating a configuration example of an encoder 1 in FIG.

FIG. 3 is a block diagram showing a configuration example of a decoder 8 of FIG.

FIG. 4 is a finite state transition diagram.

FIG. 5 is a block diagram illustrating a configuration example of a codeword check circuit 24 in FIG. 2;

FIG. 6 is a circuit diagram illustrating a configuration example of an end point state conversion circuit 25 of FIG. 2;

FIG. 7 is a block diagram illustrating a configuration example of a codeword conversion circuit 22 of FIG. 2;

FIG. 8 is a block diagram illustrating a configuration example of a codeword check circuit 31 in FIG. 3;

FIG. 9 is a codeword conversion table performed by the codeword conversion circuit 22;

FIG. 10 shows the correspondence between data words and code words when the starting point to be encoded by the encoding circuit 21 is in state (3, 3).

FIG. 11 shows a continuation of FIG. 10;

FIG. 12 is a diagram illustrating a conventional encoder.

FIG. 13 is a diagram showing a conventional decoder.

[Explanation of symbols]

1 encoder, 2 recording amplifier, 3 media,
4 reproduction amplifier, 5 equalizer amplifier, 6 sampler, 7 Viterbi detector for TCPR, 8 decoder, 9
PLL circuit, 10 Viterbi detector for PRML, 11 SYN
C detector, 22, 101 Coding circuit, 22, 32
Codeword conversion circuit, 23, 41, 71, 81, 103
PS converter, 24, 31 code word check circuit, 25 end point state conversion circuit, 26, 102 register, 33,
111 Decoding circuit, 44, 84 RDS 3-bit UP /
DOWN counter, 45, 85, 91 comparator, 46,
86 type register, 50/90 ADS 3-bit UP /
DOWN counter, 51 end point register, 72 code word converter, 73 SP converter, 92 start point register

Claims (33)

[Claims] 1. An encoding method for encoding m-bit data into an n-bit code, wherein the n-bit code includes ADS and R received by a code sequence.
DS is a code generated according to a finite state transition diagram representing the restriction of DS, two states included in the set of states starting from the n-bit code in the finite state transition diagram, the two states of the finite state transition diagram An RDS axis that exists at a position symmetrical with respect to the center point, or a position that is symmetrical with respect to the ADS axis passing through the center point of the finite state transition diagram, or that passes through the center point of the finite state transition diagram The m-bit data is an n-bit code word starting from a predetermined state included in a set of states starting from the code. An n-bit codeword that is encoded and has another state as a starting point included in the set of states starting from the code is obtained by further transforming the encoded codeword. An encoding method characterized by the following. 2. When a maximum value or a minimum value of the ADS is a maximum ADS or a minimum ADS, respectively, a maximum ADS and a minimum ADS are set.
When the difference between the maximum RDS and the minimum RDS is the maximum RDS or the minimum RDS, respectively, the difference between the maximum RDS and the minimum RDS is 2
The encoding method according to claim 1, wherein the encoding method is a multiple of the following. 3. The state in which the n is a multiple of 4 and the state on the finite state transition diagram is represented by (ADS, RDS), where (minimum ADS + maximum A
When (DS) / 2 is the center ADS and (minimum RDS + maximum RDS) / 2 is the center RDS, the states starting from the code are state (center ADS-2, center RDS-2) and state (center ADS). −
2, center RDS + 2), state (center ADS + 2, center RDS−
3. The encoding method according to claim 2, wherein there are four states: 2) and state (center ADS + 2, center RDS + 2). 4. The encoding method according to claim 3, wherein said m is 16 and said n is 20. 5. The encoding method according to claim 4, wherein a difference between the maximum ADS and the minimum ADS is 10, and a difference between the maximum RDS and the minimum RDS is 10. 6. A path departing from a state where the ADS is the center ADS-2 at time 0, when the time at which the codeword takes the starting point is set to 0, a state where the ADS is less than the center ADS-2 at the time 7 6. The encoding method according to claim 5, wherein a path that does not reach the state where the ADS is at the center ADS + 2 at time 0 does not reach the state where the ADS is at or above the center ADS + 2 at time 7. 7. On the finite state transition diagram, starting from a state in which the RDS is a minimum RDS, a maximum RDS is obtained in ten state transitions.
Is prohibited, and the RD
6. The encoding method according to claim 5, wherein starting from a state in which S is the maximum RDS and arriving at a state with the minimum RDS in ten state transitions is prohibited. 8. A conversion between codewords starting from a state symmetrical with respect to a center point of the finite state transition diagram includes: a state in which a codeword before conversion takes a start point to an end point; Each state that the converted codeword takes from the start point to the end point is set to a position symmetrical with respect to the center point, that is, inverting all bits of the codeword. The encoding method according to claim 7, wherein 9. Passing through a center point of the finite state transition diagram
The conversion between codewords starting from a state symmetrically positioned with respect to the ADS axis is as follows: each state in which a codeword before conversion takes an even number of times from a start point to an end point; and a codeword after conversion. Each state taken at even time from the start point to the end point passes through the center point
The positions that are symmetrical with respect to the ADS axis are such that each state that the converted codeword takes at an odd time is uniquely determined from the state that the converted codeword takes at an even time. That is, the code word is divided in 2-bit units from the bit on the starting point side, and 00 is 11 for each of them.
The encoding method according to claim 7, wherein 01 is 01, 10 is 10, and 11 is 00. 10. A conversion between codewords whose starting point is a state symmetrical with respect to an RDS axis passing through a center point of the finite state transition diagram is performed when the codeword before conversion is a starting point to an ending point. Each state taken at even time and each state taken at the even time from the starting point to the ending point of the converted codeword is a symmetrical position with respect to the RDS axis passing through the center point, and the converted codeword is Are taken at odd-numbered times so that the converted codeword is uniquely determined from the state taken at even-numbered times, that is, the codeword is 2 bits from the bit on the starting point side.
Separated in bit units, 00 is 00 for each
The encoding method according to claim 7, wherein 01 is 10, 10 is 01, and 11 is 11. 11. When the state in which a predetermined code word takes at each time from a start point to an end point has a state symmetric with respect to a state in which the predetermined code word is a start point, the predetermined code word 9. The encoding method according to claim 8, wherein the conversion for the center point is not performed. 12. The method according to claim 1, wherein all states of the predetermined code word at even-numbered times from the start point to the end point include a state symmetric with respect to an ADS axis passing through a state where the predetermined code word is a start point. The encoding method according to claim 9, wherein the conversion is not performed on an ADS axis passing through the center point for the word. 13. A method according to claim 1, wherein all states of the predetermined code word at even-numbered times from the start point to the end point have a state symmetric with respect to an RDS axis passing through a state where the predetermined code word is a start point. The encoding method according to claim 10, wherein the conversion is not performed on the RDS axis passing through the center point for the word. 14. The method according to claim 1, wherein all states of the predetermined code word at even-numbered times from the start point to the end point include a state symmetric with respect to an RDS axis passing through a state where the predetermined code word is a start point. The encoding method according to claim 9, wherein for a word, the transformation on the ADS axis passing through the center point is all-bit inversion. 15. The method according to claim 1, wherein all states of the predetermined code word at even-numbered times from the start point to the end point include a state symmetric with respect to an ADS axis passing through a state where the predetermined code word is a start point. 11. The encoding method according to claim 10, wherein for a word, the transformation on the RDS axis passing through the center point is all-bit inversion. 16. An encoding apparatus for encoding m-bit data into an n-bit code, comprising: a predetermined one of a set of states in which an input m-bit data word starts from the code; An encoding unit that converts the state into an n-bit codeword starting from a state; a codeword inspection unit that checks a state and a type of an end point of the codeword based on the codeword supplied from the encoding unit; End point state conversion means for converting the state of the end point supplied from the word inspection means to the state of the end point of the code word output by the code word conversion means; and storing the end point state output by the end point state conversion means for one code word. A storage unit that outputs a state of a start point of a code word output next time by the code word conversion unit; a state of a start point of a code word supplied from the storage unit; and a type of a code word supplied from the code word inspection unit. Based on And an n-bit code word starting from one predetermined state included in a set of states starting from the code supplied from the encoding means, as a set of states starting from the code. An encoding device comprising: a codeword conversion unit configured to convert into an n-bit codeword starting from another included state. 17. A decoding method for decoding an n-bit code into m-bit data, wherein the n-bit code includes ADS and R received by a code sequence.
DS is a code generated according to a finite state transition diagram representing the restriction of DS, two states included in the set of states starting from the n-bit code in the finite state transition diagram, the two states of the finite state transition diagram An RDS axis that exists at a position symmetrical with respect to the center point, or a position that is symmetrical with respect to the ADS axis passing through the center point of the finite state transition diagram, or that passes through the center point of the finite state transition diagram Is an n-bit codeword starting from one of the states included in the set of states starting from the code, the code being a starting point. To another n-bit codeword starting from one predetermined state included in the set of states to be obtained, and the m-bit data word is obtained by decoding the converted codeword. Decoding characterized by the fact that Method. 18. When the maximum value or the minimum value of the ADS is the maximum ADS or the minimum ADS, respectively, the difference between the maximum ADS and the minimum ADS is a multiple of 2, and the maximum value or the minimum value of the RDS Is the maximum RDS or the minimum RDS, respectively, the difference between the maximum RDS and the minimum RDS is 2
18. The decoding method according to claim 17, wherein the decoding method is a multiple of. 19. The above n is a multiple of 4, the state on the finite state transition diagram is represented by (ADS, RDS), (minimum ADS + maximum ADS) / 2 is defined as the center ADS, and (minimum RDS + maximum RDS) / 2
Is the center RDS, the state where the code is the starting point is
State (center ADS-2, center RDS-2), state (center ADS-
2, center RDS + 2), state (center ADS + 2, center RDS−
19. The decoding method according to claim 18, wherein there are four states: 2) and state (central ADS + 2, central RDS + 2). 20. The decoding method according to claim 19, wherein said m is 16 and said n is 20. 21. The decoding method according to claim 20, wherein a difference between the maximum ADS and the minimum ADS is 10, and a difference between the maximum RDS and the minimum RDS is 10. 22. Assuming that the time at which the code word takes a starting point is 0, a path that departs from a state where ADS is the center ADS-2 at time 0 is a state where the ADS is equal to or less than the center ADS-2 at time 7 22. The decoding method according to claim 21, wherein a path that has not reached the ADS and has departed from the state where the ADS is the center ADS + 2 at time 0 does not reach the state where the ADS is not less than the center ADS + 2 at the time 7. 23. On the finite state transition diagram, starting from the state in which the RDS is the minimum RDS, the maximum RDS is obtained in ten state transitions.
DS is prohibited from reaching the state,
22. The decoding method according to claim 21, wherein a state in which the RDS has a maximum RDS and reaches a minimum RDS in 10 state transitions is prohibited. 24. Conversion between codewords starting from a state symmetrical with respect to a center point of the finite state transition diagram is as follows:
Each state that the codeword before conversion takes from the start point to the end point;
Each state that the converted codeword takes from the start point to the end point is
24. The decoding method according to claim 23, wherein the position is symmetric with respect to the center point, that is, all bits of the codeword are inverted. 25. Conversion between codewords starting from a state at a position symmetrical with respect to an ADS axis passing through the center point of the finite state transition diagram is performed by converting a codeword before conversion from a start point to an end point. Each state taken at an even time and each state taken at the even time from the start point to the end point of the converted codeword becomes a symmetrical position with respect to the ADS axis passing through the center point, and the converted codeword Are taken at odd-numbered times so that the converted codeword is uniquely determined from the state taken at even-numbered times, that is, the codeword is 2 bits from the bit on the starting point side.
Separated in bit units, 00 is 11 for each
24. The decoding method according to claim 23, wherein 01 is 01, 10 is 10, and 11 is 00. 26. Conversion between codewords whose starting point is a state at a position symmetrical with respect to an RDS axis passing through the center point of the finite state transition diagram is performed when the codeword before conversion is a starting point to an ending point. Each state taken at even time and each state taken at the even time from the starting point to the ending point of the converted codeword is a symmetrical position with respect to the RDS axis passing through the center point, and the converted codeword is Are taken at odd-numbered times so that the converted codeword is uniquely determined from the state taken at even-numbered times, that is, the codeword is 2 bits from the bit on the starting point side.
Separated in bit units, 00 is 00 for each
24. The decoding method according to claim 23, wherein 01 is 10, 10 is 01, and 11 is 11. 27. In a case where a state symmetric with respect to a state where the predetermined code word is a start point exists in all states where a predetermined code word takes at respective times from a start point to an end point, 25. The decoding method according to claim 24, wherein the conversion for the center point is not performed. 28. The method according to claim 28, wherein all states at which the predetermined code word takes an even number of times from the starting point to the ending point include a state symmetrical with respect to an ADS axis passing through the state starting from the predetermined code word. 26. The decoding method according to claim 25, wherein the word is not transformed with respect to an ADS axis passing through the center point. 29. The method according to claim 29, wherein all states in which the predetermined code word takes an even number of times from the start point to the end point have a state symmetric with respect to an RDS axis passing through a state in which the predetermined code word is a start point. 27. The decoding method according to claim 26, wherein the word is not transformed with respect to the RDS axis passing through the center point. 30. The method according to claim 30, wherein all states of the predetermined code word at even-numbered times from the start point to the end point include a state symmetric with respect to an RDS axis passing through a state where the predetermined code word is a start point. 26. The decoding method according to claim 25, wherein for a word, the transformation on the ADS axis passing through the center point is all-bit inversion. 31. The method according to claim 32, wherein all states of the predetermined codeword at even-numbered times from the start point to the end point include a state symmetric with respect to an ADS axis passing through a state where the predetermined codeword is a start point. 27. The decoding method according to claim 26, wherein for a word, the transformation on the RDS axis passing through the center point is all-bit inversion. 32. A decoding apparatus for decoding an n-bit code into m-bit data, comprising: a codeword checker for checking a state and a type starting from an input n-bit codeword; Based on the state and type of the starting point of the code word supplied from the above, the n-bit code word starting from one of the states included in the set of states starting from the input code is referred to as the starting point. Codeword conversion means for converting the codeword converted by the codeword conversion means into another n-bit codeword starting from one predetermined state included in the set of states Decoding means for decoding into data words. 33. A providing medium in which an n-bit code obtained by encoding m-bit data is recorded, wherein the n-bit code is ADS and R received by a code sequence.
DS is a code generated according to a finite state transition diagram representing the restriction of DS, two states included in the set of states starting from the n-bit code in the finite state transition diagram, the two states of the finite state transition diagram An RDS axis that exists at a position symmetrical with respect to the center point, or a position that is symmetrical with respect to the ADS axis passing through the center point of the finite state transition diagram, or that passes through the center point of the finite state transition diagram Providing medium provided at a position symmetrical with respect to the medium.