JP2000040703A - Transistor electrode structure - Google Patents

Abstract

(57) Abstract: The present invention relates to a bipolar transistor, and proposes a specific structure in which the shapes of a base electrode and an emitter electrode are optimized. The base electrode includes a first layer base electrode provided in a base region, a base via metal layer provided on an interlayer insulating film formed of a silicon nitride film, and a base via metal layer. A planar second-layer base electrode 10 on the interlayer insulating film is electrically integrated;
Similarly, the emitter electrode includes a first-layer emitter electrode 6 provided in the emitter region 3, an emitter via metal layer 9 provided on an interlayer insulating film 7 made of a silicon nitride film, and Planar second on membrane
The structure is such that the layer emitter electrode 11 is electrically integrated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor electrode structure. Above all, one of the transistors that realizes a reduction in saturation voltage by increasing the perimeter of the emitter is one in which a plurality of island-shaped base regions are arranged in the emitter region up to the main surface of the semiconductor substrate. A transistor having a structure, or in other structures,
A transistor having a structure composed of emitters of "E type", "king shape" and "comb shape", wherein an electrode structure for extracting each base region and emitter region has a two-layer structure and a bonding pad is a flat plate. The present invention relates to an electrode structure of a transistor configured in a shape.

[0002]

2. Description of the Related Art In a conventional bipolar transistor, various improvements have been made to reduce the saturation voltage and improve the breakdown voltage. It is summarized in the improvement of the shape of the emitter region in the base region and the structure for taking out the base electrode and the emitter electrode. FIG. 4 and FIG. 5 show a transistor having a base region divided into islands in the conventional structure, and FIG. 6 shows a transistor having an "E-type" or "king-shaped" or "comb-shaped" emitter region. I do.

FIGS. 4A and 4B are a plan view (A) and a cross-sectional view AA '(B) illustrating a conventional bipolar transistor having a base region divided into islands.
It is. FIG. 4 is a diagram in which after a base region and an emitter region are provided, a base layer and an emitter electrode of the first layer are arranged by piercing an oxide film covering the substrate surface. A transistor is constituted by providing a base region 2 and an emitter region 3 provided on a semiconductor substrate 1 serving as a collector. At this time, the base region 2 divided into islands is obtained by performing selective diffusion using a checkerboard pattern when forming the emitter region 3. As is clear from the figure, an island-shaped base region does not indicate that islands are separated independently from each other, but only looks as if they are separated when viewed from the surface of the emitter. There is a structure in which the base region is divided into an island shape in a checkered pattern and appears on the surface of the semiconductor substrate as described above in order to increase the peripheral length of the emitter. In FIG. 4A, the base region 2 divided into island shapes is shown.
Indicates that they are arranged in four columns and five rows on the surface of the semiconductor substrate. A transistor formed of the base region divided into islands and the emitter region 3 around the base region is hereinafter referred to as a “cell”. A first layer base electrode 4 and a first layer emitter electrode 5 are provided by making a hole in the oxide film 6 covering the surfaces of the base region 2 and the emitter region 3 to make electrical connection from each region.

In FIG. 4A, the base region 2 divided into an island shape located at the leftmost and uppermost position is defined as the origin, and the base region of three cells from one column and three rows to one column and five rows is defined. Reference numeral 2 denotes a first-layer base electrode 4 which is connected in advance to mount a second-layer emitter electrode to be formed later. Also, 3 rows and 4
A portion corresponding to the first to second rows of the emitter region 5 divided by the base region divided into islands with columns, and a first layer emitter to be provided in the emitter region 5 outside (right side) of four columns Electrodes are omitted. This is omitted in order to mount a second layer base electrode to be formed later.

FIG. 5 is a plan view of a conventional bipolar transistor having a base region divided into islands as shown in FIG. 4 and showing plan views (A) and (B) for explaining the arrangement of the upper electrodes in FIG. It is sectional drawing B of -B '. As shown in the figure, an interlayer insulating film 7, a first layer emitter electrode 5, a through hole for obtaining electrical connection with the first layer base electrode 4, an emitter via metal layer 8, a base via metal layer 9, and an interlayer insulating film 7 A second-layer base electrode 10 and a second-layer emitter electrode 11 are provided thereon to form a base electrode 12 and an emitter electrode 13.
Is configured.

FIG. 6 is a plan view for explaining a comb-shaped transistor. Base region 2 and emitter region 3 provided on a semiconductor substrate to increase the peripheral length of the emitter.
Is provided, and the emitter region 3 is formed in an “E type”, a “king shape”, a “comb shape”, or the like. A base electrode 4 and an emitter electrode 5 that are electrically connected to each other are provided. In this case, since an external terminal cannot be connected only on the base region 2 and the emitter region 3, a bonding pad is generally provided beyond the junction. In this case, since the bonding pads are provided outside the base region 2 and the emitter region 3, the semiconductor substrate must be qualitatively enlarged by that amount. However, since no interlayer insulating film is used, the number of steps is small. He had gained some support.

In the prior art, as described with reference to FIGS. 4 and 5, an appropriate separation distance (M-M distance) is always provided between the base electrode and the emitter electrode which are branched into a plurality. It is necessary to place them, and it is necessary to provide an overlapping distance (overlap distance) between the base electrode and the emitter electrode with respect to the nitride film. Usually, the overlapping distance is longer than that provided in the first layer base emitter electrode. The reason for this is that at least the nitride film formed thick by CVD has more severe irregularities than the oxide film formed by heat treatment.

In the example shown in FIG. 5, the size of the base region divided into islands is 40 μm on one side and the distance between the electrodes is 10 μm, and the base regions divided into islands are 4 columns and 5 rows as described above. , There is a possibility that it can be reduced by up to 80 μm in the row direction. Since the same applies to the vertical direction, there is a possibility that the size can be reduced by 100 μm at maximum for five rows. This indicates that the base area divided into islands can be further increased by two columns and two rows as a maximum value, or the same can be achieved with a chip size smaller by that amount.

Furthermore, the base electrode and the emitter electrode are arranged not only at the separation distance but also at an overlap distance (overlap) with respect to the interlayer insulating film. If the necessary overlapping distance is, for example, 10 μm, under the above conditions, the horizontal direction may be further reduced by 80 μm and the vertical direction may be further reduced by 100 μm. When this is combined, a shrinkage of 160 μm in the horizontal direction and 200 μm in the vertical direction, which is 40% or more, can be obtained.

With respect to the above-mentioned separation distance and superposition distance, if a paradoxical description method is adopted, in the case of the illustrated transistor, the pattern rule is loosened by the extent that the transistor can be shrunk, and the relationship between the chip size and the yield is further reduced. The yields determined by these are getting worse.

[0011]

The present invention relates to a bipolar transistor, and more particularly to a transistor having a base region divided into islands, and an emitter arranged in an "E" type, "king" shape, or "comb shape". In a transistor having a region or base region structure, it is possible to reduce the chip size by optimizing the shape of the base electrode and the emitter electrode described in the previous section, or to reduce the chip size. The present invention proposes a specific structure for improving performance by incorporating many cells without changing the chip size. In addition, a bonding pad portion for performing external connection by applying two-layer wiring is arranged on the chip, and the thickness of the interlayer insulating film in the pad portion is configured to be thicker than other electrode portions. The structure can be embodied.

[0012]

According to the present invention, there is provided a bipolar transistor comprising an emitter region, a base region divided into islands in the emitter region, and a collector region. A first layer base electrode electrically connected to the divided base region and a through hole corresponding to the first layer base electrode via an interlayer insulating film, and a base via metal electrically connected to the through hole A base electrode composed of a layer and a plate-shaped second layer base electrode provided on the interlayer insulating film, and a first layer emitter electrode provided electrically connected to the emitter region and the interlayer insulating film. Composed of through holes corresponding to the first layer emitter electrode, an emitter via metal layer electrically connecting them, and a plate-shaped second layer emitter electrode provided on the interlayer insulating film. An electrode structure of the transistors and having an emitter electrode.

That is, the present invention provides a transistor chip having an island-shaped base region, or an “E-type” transistor chip.
An interlayer insulating film for two-layer wiring is provided on a transistor chip having an emitter region in the shape of a “king” or “comb”, and a first-layer base electrode and a first-layer emitter electrode are provided below the interlayer insulating film. It is characterized in that a second-layer base electrode and a second-layer emitter electrode provided for a bonding pad portion are provided in a plate shape on the interlayer insulating film.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. In each of the figures, (A) is a plan view, and (B) is a cross-sectional view at a position designated in the plan view of (A), each showing a transistor having a base region divided into an island shape. 1 is a diagram in which a base region and an emitter region are formed, FIG. 2 is a diagram in which a first-layer base electrode and a first-layer emitter electrode are formed, and FIG. 3 is a diagram connecting the interlayer insulating film and the first layer from FIG. FIG. 3 is a diagram illustrating a via metal layer, a final emitter electrode, and a base electrode.

The structure of an embodiment of the present invention will be described below in detail by showing its manufacturing sequence. As shown in FIG. 1, a base region 2 and an emitter region 3 are provided using a semiconductor substrate 1 as a collector region, and an oxide film 4 is provided by oxidizing the surface of the semiconductor substrate. Here, a transistor having a base region divided into islands, which is one feature of the present invention, will be described.

Increasing the peripheral length of the emitter in a transistor is necessary for reducing the saturation voltage of the transistor and improving the current capacity. Therefore, in the case of the transistor having the base region 2 divided in an island shape, when the emitter region 3 is provided, the base region 2
It is natural that the base region 2 divided into islands of 4 columns and 5 rows is masked in a checkered pattern so as to be exposed on the semiconductor substrate 1 as shown in FIG. Spread. Rather than simply forming the emitter region 3 in a rectangular shape, if it is arranged as shown in FIG. Therefore, how to reduce the area per one surface of the base region 2 divided into islands and how to increase the area is the point that determines the peripheral length of the emitter.

Next, as shown in FIG. 2, a first-layer base electrode 5 and a first-layer emitter electrode 6 are formed in the oxide film 4 to make electrical connection from the emitter region 3 and the base region 2 by drilling. I do. As will be described later, the first-layer base electrode 5 has an emitter electrode provided in a flat plate shape.
3 cells from row to 5th row, 3 cells per row, total 1
Two are provided integrally in each row. The first-layer emitter electrode 6 is arranged in the whole area surrounding the periphery of the base area divided into islands so as to reduce the contact resistance as little as possible. The first-layer emitter electrode is omitted only in the portion formed by connecting the cells in the third and fifth columns.

In the present invention, as a next step, an interlayer insulating film 7 of a silicon nitride film is first provided on the first layer base electrode 5 and the first layer emitter electrode 6 as shown in FIG. The interlayer insulating film 7 is laminated in a thickness of 3.2 μm, and a through hole is provided at a necessary position. In addition, since the interlayer insulating film 7 is attached as thick as 3.2 μm, it can be provided in two layers.
If an interlayer insulating film composed of two layers is used, a through-hole having a gentle taper can be easily obtained if the through-hole is divided into two parts and the hole is first made small and then large. Therefore, when the base via metal layer 8 and the emitter via metal layer 9 are obtained by filling the through holes later, this is an effective process for solving the step coverage problem. At this time, the interlayer insulating film 7 is formed into a thick portion and a thin portion. That is, the portion where the gold ball is actually connected later is 3.2 μm, and the portion where the through hole is provided is 2 μm.

In practice, it is formed simultaneously with the via metal layer. However, the planar second layer emitter electrode 11 connected to the respective via metal layers 8 and 9 and the planar second layer emitter electrode 11 are similarly formed.
A layer base electrode 10 is generated. As a result, the base electrode comprises a first layer base electrode 5, a base via metal layer 8 provided on an interlayer insulating film 7 made of a silicon nitride film deposited thereon, and a planar electrode on the interlayer insulating film. Second
Similarly, the emitter electrode is provided on the first-layer emitter electrode 6 and on the interlayer insulating film 7 made of a silicon nitride film deposited thereon. Emitter via metal layer 9 and a planar second-layer emitter electrode 1 on the interlayer insulating film.
1 is electrically integrated.

One of the features of the present invention is that the second-layer base electrode 10 and the second-layer emitter electrode 11 are flat and not branched in a comb shape. By arranging them in a plate shape, there is no necessity to provide an indispensable separation distance and an overlapping distance between the emitter electrode and the base electrode shown in FIG. That is, since the second-layer emitter electrode and the second-layer base electrode are not arranged in a comb shape but are flat and have a simple boundary, the distance between them so that they are not in electrical contact with each other is one distance. Even if it is straight or bent, it means that there is no problem if only one is provided, and if the value of the separation distance is properly designed, the purpose is achieved. or,
If the superposition distance is provided only on one side of the outermost end, this also achieves the purpose.

In another embodiment of the present invention, the present invention can be applied not only to a transistor having a base region divided into islands but also to a comb-shaped transistor as shown in FIG. is there. A first-layer emitter electrode and a first-layer base transistor are provided in an emitter region formed in an “E” type or a “king” type;
An interlayer insulating film, a through hole, a base via metal layer electrically connecting the respective electrodes, an emitter via metal layer, and a plate-shaped second layer base electrode and a second layer emitter electrode provided in an interlayer insulating film shape; Is an electrode structure including a base electrode and an emitter electrode. However, it should be noted that the first layer emitter electrode and the first layer base electrode can be arranged without departing from the emitter region and the base region, respectively. Needless to say, this is made possible by adopting a two-layer wiring structure. When the shrinkage progresses and the chip size becomes too small and the demand from bonding is larger than the area of the base region, it naturally expands beyond this and is not an essential requirement, but a necessary one. It is intended to provide a structure in which each electrode can be arranged at times by shrinking.

[0022]

According to the prior art, referring to FIG. 5, as long as the second-layer base electrode and the second-layer emitter electrode are arranged in a comb on the interlayer insulating film, they are electrically separated. It was shown that it was necessary to take a separation distance in order to do so. It was also shown that a superposition distance was necessary to enhance the reliability of the transistor. In addition, in this example, it was shown that there is a possibility of shrinking a maximum of 160 μm in the row direction and a maximum of 200 μm in the column direction. In one embodiment of the present invention, the second-layer base electrode and the second-layer emitter electrode are integrally formed in a plate shape. Therefore, in this example, the separation distance and the superposition distance close to the maximum value are omitted, that is, the shrinkage is reduced. Was completed. This is because, as shown in FIG. 3, since they are not arranged in a comb shape, only one spacing is required in the present invention.

In the electrode structure of the transistor according to the present invention, since a part of the area of the second layer base electrode and the second layer emitter electrode is used as the bonding pad, it basically corresponds to the selected part of the bonding pad. Since it is provided by a two-stage division method that can increase the thickness of only the portion to be formed, it is possible to limit the stress from the minimum necessary nitride film. Disconnection or the like is likely to occur due to the influence on the electrodes due to the pressure during bonding, but this can be prevented because the portion used as the pad is thickened.

Further, since the transistor according to the present invention is a two-layer wiring and has a second-layer base electrode and a second-layer emitter electrode at the top, it is naturally used as a wire bonding pad. Or L which is directly connected to the lead by the lead frame and sealed
It is most suitable for application of an OC (Lead On Chip) structure.

[Brief description of the drawings]

FIG. 1 is a plan view (A) and a cross-sectional view (B) for describing the present invention.

FIG. 2 is a plan view (A) and a cross-sectional view (B) for describing the present invention.

FIG. 3 is a plan view (A) and a cross-sectional view (B) for describing the present invention.

4A and 4B are a plan view and a cross-sectional view illustrating a structure of a conventional transistor.

5A and 5B are a plan view and a cross-sectional view illustrating a structure of a conventional transistor.

FIG. 6 is a plan view illustrating a structure of a conventional transistor.

Claims (5)

[Claims] 1. A first layer base electrode electrically connected to a base region, a through hole corresponding to the first layer base electrode via an interlayer insulating film, and a base via electrically connected to the through holes. A base electrode composed of a metal layer and a plate-shaped second layer base electrode provided on the interlayer insulating film, a first layer emitter electrode electrically connected to the emitter region and an interlayer insulating film are provided. Through-holes corresponding to the first-layer emitter electrode via an emitter via metal layer electrically connecting them and an emitter electrode composed of a plate-shaped second-layer emitter electrode provided on the interlayer insulating film. An electrode structure of a transistor, comprising: 2. The transistor electrode structure according to claim 1, wherein the base region is divided into islands in the emitter region and is disposed so as to reach the surface of the semiconductor substrate. 3. An "E" type, a "king" type,
2. The transistor electrode structure according to claim 1, comprising emitter regions arranged in a "comb shape". 4. An overlapping portion on a first layer base electrode and a second layer emitter electrode disposed via an interlayer insulating film has a first layer base electrode connected in advance. The electrode structure of the transistor according to claim 1. 5. An electrode structure for a transistor according to claim 1, wherein said second base electrode and said second emitter electrode disposed on said interlayer insulating film have a substantially rectangular plate shape on said base region. .