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ITTO920463A1 - Metodo di rilevamento di connesioni erronee in schede elettroniche - Google Patents

Metodo di rilevamento di connesioni erronee in schede elettroniche

Info

Publication number
ITTO920463A1
ITTO920463A1 IT000463A ITTO920463A ITTO920463A1 IT TO920463 A1 ITTO920463 A1 IT TO920463A1 IT 000463 A IT000463 A IT 000463A IT TO920463 A ITTO920463 A IT TO920463A IT TO920463 A1 ITTO920463 A1 IT TO920463A1
Authority
IT
Italy
Prior art keywords
errone
connections
detection
electronic boards
boards
Prior art date
Application number
IT000463A
Other languages
English (en)
Inventor
Luciano Bonaria
Original Assignee
Spea Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spea Srl filed Critical Spea Srl
Priority to ITTO920463A priority Critical patent/IT1259395B/it
Publication of ITTO920463A0 publication Critical patent/ITTO920463A0/it
Priority to EP93108451A priority patent/EP0571963B1/en
Priority to DE69320535T priority patent/DE69320535T2/de
Publication of ITTO920463A1 publication Critical patent/ITTO920463A1/it
Application granted granted Critical
Publication of IT1259395B publication Critical patent/IT1259395B/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
    • G01R31/2808—Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/70—Testing of connections between components and printed circuit boards

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
ITTO920463A 1992-05-29 1992-05-29 Metodo di rilevamento di connesioni erronee in schede elettroniche IT1259395B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
ITTO920463A IT1259395B (it) 1992-05-29 1992-05-29 Metodo di rilevamento di connesioni erronee in schede elettroniche
EP93108451A EP0571963B1 (en) 1992-05-29 1993-05-25 Method of connection testing electronic boards
DE69320535T DE69320535T2 (de) 1992-05-29 1993-05-25 Verfahren zum Prüfen der Verbindungen elektronischer Karten

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITTO920463A IT1259395B (it) 1992-05-29 1992-05-29 Metodo di rilevamento di connesioni erronee in schede elettroniche

Publications (3)

Publication Number Publication Date
ITTO920463A0 ITTO920463A0 (it) 1992-05-29
ITTO920463A1 true ITTO920463A1 (it) 1993-11-29
IT1259395B IT1259395B (it) 1996-03-13

Family

ID=11410503

Family Applications (1)

Application Number Title Priority Date Filing Date
ITTO920463A IT1259395B (it) 1992-05-29 1992-05-29 Metodo di rilevamento di connesioni erronee in schede elettroniche

Country Status (3)

Country Link
EP (1) EP0571963B1 (it)
DE (1) DE69320535T2 (it)
IT (1) IT1259395B (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5513188A (en) * 1991-09-10 1996-04-30 Hewlett-Packard Company Enhanced interconnect testing through utilization of board topology data
US5521513A (en) * 1994-10-25 1996-05-28 Teradyne Inc Manufacturing defect analyzer
JP3459765B2 (ja) 1997-07-16 2003-10-27 シャープ株式会社 実装検査システム
GB2394780B (en) 2002-10-29 2006-06-14 Ifr Ltd A method of and apparatus for testing for integrated circuit contact defects

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0306656A1 (de) * 1987-08-20 1989-03-15 Siemens Aktiengesellschaft Einrichtung zur Prüfung von IC-Bausteinen
US5101152A (en) * 1990-01-31 1992-03-31 Hewlett-Packard Company Integrated circuit transfer test device system utilizing lateral transistors
DE4110551C1 (it) * 1991-03-30 1992-07-23 Ita Ingenieurbuero Fuer Testaufgaben Gmbh, 2000 Hamburg, De

Also Published As

Publication number Publication date
DE69320535T2 (de) 1999-04-22
ITTO920463A0 (it) 1992-05-29
EP0571963B1 (en) 1998-08-26
DE69320535D1 (de) 1998-10-01
IT1259395B (it) 1996-03-13
EP0571963A2 (en) 1993-12-01
EP0571963A3 (it) 1994-04-13

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970529