[go: up one dir, main page]

IT7925589A0 - Fabbricazione di circuiti integrati utilizzando configurazioni spesse di alta risoluzione. - Google Patents

Fabbricazione di circuiti integrati utilizzando configurazioni spesse di alta risoluzione.

Info

Publication number
IT7925589A0
IT7925589A0 IT7925589A IT2558979A IT7925589A0 IT 7925589 A0 IT7925589 A0 IT 7925589A0 IT 7925589 A IT7925589 A IT 7925589A IT 2558979 A IT2558979 A IT 2558979A IT 7925589 A0 IT7925589 A0 IT 7925589A0
Authority
IT
Italy
Prior art keywords
fabrication
integrated circuits
high resolution
thick high
resolution setup
Prior art date
Application number
IT7925589A
Other languages
English (en)
Other versions
IT1122539B (it
Inventor
Fraser David Bruce
Maydan Dan
Moran Joseph Michael
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of IT7925589A0 publication Critical patent/IT7925589A0/it
Application granted granted Critical
Publication of IT1122539B publication Critical patent/IT1122539B/it

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094—Multilayer resist systems, e.g. planarising layers
    • H10P76/4088—
    • H10P14/69433—
    • H10P76/2041—
    • H10P76/2045—
    • H10P76/2047—
    • H10P14/6336—
    • H10P14/68—
    • H10P14/683—
    • H10P14/69215—

Landscapes

  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
IT25589/79A 1978-09-11 1979-09-10 Fabbricazione di circuiti integrati utilizzando configurazioni spesse di alta risoluzione IT1122539B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/941,369 US4244799A (en) 1978-09-11 1978-09-11 Fabrication of integrated circuits utilizing thick high-resolution patterns

Publications (2)

Publication Number Publication Date
IT7925589A0 true IT7925589A0 (it) 1979-09-10
IT1122539B IT1122539B (it) 1986-04-23

Family

ID=25476352

Family Applications (1)

Application Number Title Priority Date Filing Date
IT25589/79A IT1122539B (it) 1978-09-11 1979-09-10 Fabbricazione di circuiti integrati utilizzando configurazioni spesse di alta risoluzione

Country Status (13)

Country Link
US (1) US4244799A (it)
JP (1) JPS55500646A (it)
BE (1) BE878667A (it)
CA (1) CA1123118A (it)
DE (1) DE2953117A1 (it)
ES (1) ES483987A1 (it)
FR (1) FR2435819A1 (it)
GB (1) GB2043345B (it)
IE (1) IE48479B1 (it)
IT (1) IT1122539B (it)
NL (1) NL7920069A (it)
SE (1) SE434896B (it)
WO (1) WO1980000639A1 (it)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2945854A1 (de) * 1979-11-13 1981-05-21 Deutsche Itt Industries Gmbh, 7800 Freiburg Ionenimplantationsverfahren
DE3027941A1 (de) * 1980-07-23 1982-02-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von reliefstrukturen aus doppellackschichten fuer integrierte halbleiterschaltungen, wobei zur strukturierung hochenergetische strahlung verwendet wird
US4323638A (en) * 1980-08-18 1982-04-06 Bell Telephone Laboratories, Incorporated Reducing charging effects in charged-particle-beam lithography
US4333793A (en) * 1980-10-20 1982-06-08 Bell Telephone Laboratories, Incorporated High-selectivity plasma-assisted etching of resist-masked layer
DE3173581D1 (en) * 1980-10-28 1986-03-06 Toshiba Kk Masking process for semiconductor devices using a polymer film
US4362597A (en) * 1981-01-19 1982-12-07 Bell Telephone Laboratories, Incorporated Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices
US4343677A (en) * 1981-03-23 1982-08-10 Bell Telephone Laboratories, Incorporated Method for patterning films using reactive ion etching thereof
US4377437A (en) * 1981-05-22 1983-03-22 Bell Telephone Laboratories, Incorporated Device lithography by selective ion implantation
US4407933A (en) * 1981-06-11 1983-10-04 Bell Telephone Laboratories, Incorporated Alignment marks for electron beam lithography
JPS58110038A (ja) * 1981-12-23 1983-06-30 Nec Corp パタ−ン形成方法
DE3275447D1 (en) * 1982-07-03 1987-03-19 Ibm Deutschland Process for the formation of grooves having essentially vertical lateral silicium walls by reactive ion etching
US4496419A (en) * 1983-02-28 1985-01-29 Cornell Research Foundation, Inc. Fine line patterning method for submicron devices
US4451349A (en) * 1983-04-20 1984-05-29 International Business Machines Corporation Electrode treatment for plasma patterning of polymers
US4510173A (en) * 1983-04-25 1985-04-09 Kabushiki Kaisha Toshiba Method for forming flattened film
US4572765A (en) * 1983-05-02 1986-02-25 Fairchild Camera & Instrument Corporation Method of fabricating integrated circuit structures using replica patterning
US4482424A (en) * 1983-05-06 1984-11-13 At&T Bell Laboratories Method for monitoring etching of resists by monitoring the flouresence of the unetched material
EP0139549B1 (fr) * 1983-08-12 1988-12-28 Commissariat A L'energie Atomique Procédé de positionnement d'une ligne d'interconnexion sur un trou de contact électrique d'un circuit intégré
US5215867A (en) * 1983-09-16 1993-06-01 At&T Bell Laboratories Method with gas functionalized plasma developed layer
US4534826A (en) * 1983-12-29 1985-08-13 Ibm Corporation Trench etch process for dielectric isolation
JPS60214532A (ja) * 1984-04-11 1985-10-26 Nippon Telegr & Teleph Corp <Ntt> パタ−ン形成方法
US4523372A (en) * 1984-05-07 1985-06-18 Motorola, Inc. Process for fabricating semiconductor device
US4532005A (en) * 1984-05-21 1985-07-30 At&T Bell Laboratories Device lithography using multi-level resist systems
US4557797A (en) * 1984-06-01 1985-12-10 Texas Instruments Incorporated Resist process using anti-reflective coating
JPS60262150A (ja) * 1984-06-11 1985-12-25 Nippon Telegr & Teleph Corp <Ntt> 三層レジスト用中間層材料及びそれを用いた三層レジストパタン形成方法
US4683024A (en) * 1985-02-04 1987-07-28 American Telephone And Telegraph Company, At&T Bell Laboratories Device fabrication method using spin-on glass resins
US4693780A (en) * 1985-02-22 1987-09-15 Siemens Aktiengesellschaft Electrical isolation and leveling of patterned surfaces
US4609614A (en) * 1985-06-24 1986-09-02 Rca Corporation Process of using absorptive layer in optical lithography with overlying photoresist layer to form relief pattern on substrate
KR880701400A (ko) * 1986-03-24 1988-07-26 엘리 와이스 집적 회로 장치의 제조방법
DE3788981T2 (de) * 1986-06-26 1994-05-19 American Telephone & Telegraph Verfahren zur Herstellung von integrierten Schaltungen unter Verwendung einer mehrschichtigen Photolackstruktur.
US4892635A (en) * 1986-06-26 1990-01-09 American Telephone And Telegraph Company At&T Bell Laboratories Pattern transfer process utilizing multilevel resist structure for fabricating integrated-circuit devices
EP0313683A1 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element
GB8729652D0 (en) * 1987-12-19 1988-02-03 Plessey Co Plc Semi-conductive devices fabricated on soi wafers
DE3879186D1 (de) * 1988-04-19 1993-04-15 Ibm Verfahren zur herstellung von integrierten halbleiterstrukturen welche feldeffekttransistoren mit kanallaengen im submikrometerbereich enthalten.
EP0363547B1 (en) * 1988-09-12 1993-12-29 International Business Machines Corporation Method for etching mirror facets of III-V semiconductor structures
JPH088243B2 (ja) * 1989-12-13 1996-01-29 三菱電機株式会社 表面クリーニング装置及びその方法
US5126231A (en) * 1990-02-26 1992-06-30 Applied Materials, Inc. Process for multi-layer photoresist etching with minimal feature undercut and unchanging photoresist load during etch
JP3041972B2 (ja) * 1991-01-10 2000-05-15 富士通株式会社 半導体装置の製造方法
US5323047A (en) * 1992-01-31 1994-06-21 Sgs-Thomson Microelectronics, Inc. Structure formed by a method of patterning a submicron semiconductor layer
US5264076A (en) * 1992-12-17 1993-11-23 At&T Bell Laboratories Integrated circuit process using a "hard mask"
US5326727A (en) * 1992-12-30 1994-07-05 At&T Bell Laboratories Method for integrated circuit fabrication including linewidth control during etching
US5950106A (en) * 1996-05-14 1999-09-07 Advanced Micro Devices, Inc. Method of patterning a metal substrate using spin-on glass as a hard mask
US5874010A (en) * 1996-07-17 1999-02-23 Headway Technologies, Inc. Pole trimming technique for high data rate thin film heads
EP0895278A3 (de) * 1997-08-01 2000-08-23 Siemens Aktiengesellschaft Strukturierungsverfahren
US6087270A (en) * 1998-06-18 2000-07-11 Micron Technology, Inc. Method of patterning substrates
US6136511A (en) * 1999-01-20 2000-10-24 Micron Technology, Inc. Method of patterning substrates using multilayer resist processing
DE60037395T2 (de) * 1999-03-09 2008-11-27 Tokyo Electron Ltd. Herstellung eines halbleiter-bauelementes
US6605412B2 (en) 2000-02-18 2003-08-12 Murata Manufacturing Co., Ltd. Resist pattern and method for forming wiring pattern
US6872506B2 (en) * 2002-06-25 2005-03-29 Brewer Science Inc. Wet-developable anti-reflective compositions
US6740469B2 (en) 2002-06-25 2004-05-25 Brewer Science Inc. Developer-soluble metal alkoxide coatings for microelectronic applications
US7507783B2 (en) * 2003-02-24 2009-03-24 Brewer Science Inc. Thermally curable middle layer comprising polyhedral oligomeric silsesouioxanes for 193-nm trilayer resist process
JP5368674B2 (ja) * 2003-10-15 2013-12-18 ブルーワー サイエンス アイ エヌ シー． 現像液に可溶な材料および現像液に可溶な材料をビアファーストデュアルダマシン適用において用いる方法
US7320170B2 (en) * 2004-04-20 2008-01-22 Headway Technologies, Inc. Xenon ion beam to improve track width definition
US20050255410A1 (en) 2004-04-29 2005-11-17 Guerrero Douglas J Anti-reflective coatings using vinyl ether crosslinkers
US20070207406A1 (en) * 2004-04-29 2007-09-06 Guerrero Douglas J Anti-reflective coatings using vinyl ether crosslinkers
US7914974B2 (en) 2006-08-18 2011-03-29 Brewer Science Inc. Anti-reflective imaging layer for multiple patterning process
US20090008430A1 (en) * 2007-07-06 2009-01-08 Lucent Technologies Inc. Solder-bonding process
JP5357186B2 (ja) 2008-01-29 2013-12-04 ブルーワー サイエンス アイ エヌ シー． 多重暗視野露光によるハードマスクのパターン形成のためのオントラックプロセス
US9640396B2 (en) 2009-01-07 2017-05-02 Brewer Science Inc. Spin-on spacer materials for double- and triple-patterning lithography
CN103034047B (zh) * 2011-09-29 2014-10-29 上海微电子装备有限公司 一种提高分辨率的光刻工艺

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1230421A (it) * 1967-09-15 1971-05-05
US3867216A (en) * 1972-05-12 1975-02-18 Adir Jacob Process and material for manufacturing semiconductor devices
US3873361A (en) * 1973-11-29 1975-03-25 Ibm Method of depositing thin film utilizing a lift-off mask
DE2547792C3 (de) * 1974-10-25 1978-08-31 Hitachi, Ltd., Tokio Verfahren zur Herstellung eines Halbleiterbauelementes
US3962004A (en) * 1974-11-29 1976-06-08 Rca Corporation Pattern definition in an organic layer
US4024041A (en) * 1974-12-18 1977-05-17 Hitachi, Ltd. Method of forming deposition films for use in multi-layer metallization
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
US4004044A (en) * 1975-05-09 1977-01-18 International Business Machines Corporation Method for forming patterned films utilizing a transparent lift-off mask
JPS609342B2 (ja) * 1975-05-28 1985-03-09 株式会社日立製作所 パタ−ンの作製法
JPS5269270A (en) * 1975-12-05 1977-06-08 Matsushita Electronics Corp Coating method of photoresist
DE2629996A1 (de) * 1976-07-03 1978-01-05 Ibm Deutschland Verfahren zur passivierung und planarisierung eines metallisierungsmusters
US4070501A (en) * 1976-10-28 1978-01-24 Ibm Corporation Forming self-aligned via holes in thin film interconnection systems
US4092442A (en) * 1976-12-30 1978-05-30 International Business Machines Corporation Method of depositing thin films utilizing a polyimide mask

Also Published As

Publication number Publication date
SE434896B (sv) 1984-08-20
CA1123118A (en) 1982-05-04
GB2043345A (en) 1980-10-01
US4244799A (en) 1981-01-13
WO1980000639A1 (en) 1980-04-03
IT1122539B (it) 1986-04-23
GB2043345B (en) 1983-05-18
JPS55500646A (it) 1980-09-11
IE48479B1 (en) 1985-02-06
FR2435819A1 (fr) 1980-04-04
IE791715L (en) 1980-03-11
NL7920069A (nl) 1980-07-31
BE878667A (fr) 1979-12-31
ES483987A1 (es) 1980-04-01
SE8003378L (sv) 1980-05-06
DE2953117A1 (en) 1980-11-27

Similar Documents

Publication Publication Date Title
IT7925589A0 (it) Fabbricazione di circuiti integrati utilizzando configurazioni spesse di alta risoluzione.
IT7831078A0 (it) Struttura d&#39;interconnessione di circuiti integrati.
IT7925850A0 (it) Apparecchiatura per provare circuiti semiconduttori integrati.
IT7922901A0 (it) Dispositivi semiconduttori e circuiti integrati.
IT7829280A0 (it) Processo di fabbricazione di circuiti integrati.
IT8021996A0 (it) Processo di fabbricazione di circuiti integrati.
NL189889C (nl) Geintegreerde halfgeleiderschakeling.
PL212822A1 (pl) Przyrzad polprzewodnikowy
NL7901334A (nl) Halfgeleidersubstraat.
DK71980A (da) Brokonverterkredsloeb
IT8019615A0 (it) Processo per la fabbricazione di circuiti integrati.
NL7901339A (nl) Halfgeleider hoogspanningsschakelaar.
IT8023688A0 (it) Processo di fabbricazione di circuiti semiconduttori.
FR2430039B1 (fr) Circuit integre de multiplication
IT7827014A0 (it) Processo di fabbricazione di circuiti semiconduttori integrati.
EP0022870A4 (en) Semiconductor circuit.
IT1063554B (it) Procedimento per la fabbricazione di circuiti integrati
IT1064171B (it) Procedimento per la fabbricazione di circuiti integrati
SE7901551L (sv) Integrerad krets
IT7923688A0 (it) Circuiti d&#39;alimentazione di potenza.
DK525979A (da) Halvleder-ladnngsoverfoeringsanordning
IT7819249A0 (it) Circuiti integrati.
FR2437112B1 (fr) Circuit logique numerique de verrouillage
NL7803607A (nl) Spanningsreferentieschakeling.
IT7822794A0 (it) Processo di fabbricazione di circuiti integrati.