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IT1244544B - DYNAMIC ACCESS MEMORY CELL WITH MIXED STACKED SLOT TYPE CAPACITORS - Google Patents

DYNAMIC ACCESS MEMORY CELL WITH MIXED STACKED SLOT TYPE CAPACITORS

Info

Publication number
IT1244544B
IT1244544B ITMI910245A ITMI910245A IT1244544B IT 1244544 B IT1244544 B IT 1244544B IT MI910245 A ITMI910245 A IT MI910245A IT MI910245 A ITMI910245 A IT MI910245A IT 1244544 B IT1244544 B IT 1244544B
Authority
IT
Italy
Prior art keywords
memory cell
access memory
stacked
capacitor
slot type
Prior art date
Application number
ITMI910245A
Other languages
Italian (it)
Inventor
Youngtae Kang
Laeku Kang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI910245A0 publication Critical patent/ITMI910245A0/en
Publication of ITMI910245A1 publication Critical patent/ITMI910245A1/en
Application granted granted Critical
Publication of IT1244544B publication Critical patent/IT1244544B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

Sono descritti una cella di memoria ad accesso casuale dinamica avente un condensatore impilato a solchi miscelati ed un processo di formazione di essa. Secondo la presente invenzione, il fenomeno della perforazione viene impedito prevedendo una differenza tra le profondità dei solchi dei condensatori a solchi. Inoltre, l'insufficiente capacità del condensatore avente il solco meno profondo viene compensata rendendo l'area dell'elettrodo del condensatore impilato superiore all'area dell'elettrodo del condensatore impilato della cella di memoria avente un condensatore a solco più profondo. Così, il fenomeno dell'accoppiamento suscettibile di verificarsi tra i condensatori impilati può essere impedito fornendo così una cella DRAM suscettibile di essere applicata a circuiti integrati su scala ultra grande.A dynamic random access memory cell is disclosed having a capacitor stacked with mixed grooves and a process for forming it. According to the present invention, the phenomenon of perforation is prevented by providing for a difference between the depths of the furrows of the furrowed capacitors. Further, the insufficient capacitance of the capacitor having the shallower groove is compensated by making the area of the stacked capacitor electrode greater than the area of the stacked capacitor electrode of the memory cell having a deeper groove capacitor. Thus, the phenomenon of coupling likely to occur between the stacked capacitors can be prevented thereby providing a DRAM cell that can be applied to integrated circuits on an ultra large scale.

ITMI910245A 1990-10-11 1991-02-01 DYNAMIC ACCESS MEMORY CELL WITH MIXED STACKED SLOT TYPE CAPACITORS IT1244544B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900016121A KR930005738B1 (en) 1990-10-11 1990-10-11 MIST type dynamic random access memory cell and manufacturing method thereof

Publications (3)

Publication Number Publication Date
ITMI910245A0 ITMI910245A0 (en) 1991-02-01
ITMI910245A1 ITMI910245A1 (en) 1992-08-01
IT1244544B true IT1244544B (en) 1994-07-15

Family

ID=19304521

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI910245A IT1244544B (en) 1990-10-11 1991-02-01 DYNAMIC ACCESS MEMORY CELL WITH MIXED STACKED SLOT TYPE CAPACITORS

Country Status (6)

Country Link
JP (1) JPH0770622B2 (en)
KR (1) KR930005738B1 (en)
DE (1) DE4103596C2 (en)
FR (1) FR2667984B1 (en)
GB (1) GB2248720B (en)
IT (1) IT1244544B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283726A (en) * 1996-02-16 1997-10-31 Nippon Steel Corp Semiconductor memory device and manufacturing method thereof
KR19990048904A (en) * 1997-12-11 1999-07-05 윤종용 Capacitor Manufacturing Method of Semiconductor Device
DE102005020079A1 (en) * 2005-04-29 2006-06-01 Infineon Technologies Ag Hybrid memory cell for dynamic random access memory (DRAM), containing specified substrate with transistor structure(s) with drain, source, control contact and channel zone between drain and source, etc

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62120070A (en) * 1985-11-20 1987-06-01 Toshiba Corp Semiconductor memory
JPH0815207B2 (en) * 1986-02-04 1996-02-14 富士通株式会社 Semiconductor memory device
JPS63122261A (en) * 1986-11-12 1988-05-26 Mitsubishi Electric Corp Manufacturing method of semiconductor device
JPS63239969A (en) * 1987-03-27 1988-10-05 Sony Corp Memory device
JP2621181B2 (en) * 1987-06-12 1997-06-18 日本電気株式会社 MIS type semiconductor memory device
JPH02106958A (en) * 1988-10-17 1990-04-19 Hitachi Ltd semiconductor equipment
JPH02116160A (en) * 1988-10-26 1990-04-27 Matsushita Electron Corp Semiconductor device and manufacture thereof
KR950000500B1 (en) * 1989-08-31 1995-01-24 금성일렉트론 주식회사 Manufacturing method and structure of dram cell capacitor

Also Published As

Publication number Publication date
KR920008931A (en) 1992-05-28
GB9101316D0 (en) 1991-03-06
FR2667984A1 (en) 1992-04-17
KR930005738B1 (en) 1993-06-24
DE4103596C2 (en) 1994-02-24
ITMI910245A0 (en) 1991-02-01
ITMI910245A1 (en) 1992-08-01
GB2248720A (en) 1992-04-15
GB2248720B (en) 1995-04-19
JPH06342887A (en) 1994-12-13
FR2667984B1 (en) 1993-01-08
DE4103596A1 (en) 1992-04-16
JPH0770622B2 (en) 1995-07-31

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970225