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IN2014CN03747A - - Google Patents

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Publication number
IN2014CN03747A
IN2014CN03747A IN3747CHN2014A IN2014CN03747A IN 2014CN03747 A IN2014CN03747 A IN 2014CN03747A IN 3747CHN2014 A IN3747CHN2014 A IN 3747CHN2014A IN 2014CN03747 A IN2014CN03747 A IN 2014CN03747A
Authority
IN
India
Prior art keywords
divide
frequency divider
signal
circuit
phase
Prior art date
Application number
Inventor
Qiao Dongjiang
Bossu Frederic
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014CN03747A publication Critical patent/IN2014CN03747A/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H03H11/265—Time-delay networks with adjustable delay

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q) that differ from each other in phase by ninety degrees. To divide by three, the frequency divider includes a divide-by-three frequency divider. The divide-by-three frequency divider includes a divide-by-three circuit, a delay circuit, and a feedback circuit. The divide-by-three circuit frequency divides a signal from the VCO and generates therefrom three signals C, A' and B that differ from each other in phase by one hundred twenty degrees. The delay circuit delays signal A' to generate a delayed version A of the signal A'. The feedback circuit controls the delay circuit such that the delayed version A (I) is ninety degrees out of phase with respect to the signal C (Q).
IN3747CHN2014 2008-08-18 2009-08-18 IN2014CN03747A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/193,693 US7825703B2 (en) 2008-08-18 2008-08-18 Divide-by-three quadrature frequency divider
PCT/US2009/054211 WO2010022092A1 (en) 2008-08-18 2009-08-18 Divide-by-three quadrature frequency divider

Publications (1)

Publication Number Publication Date
IN2014CN03747A true IN2014CN03747A (en) 2015-09-25

Family

ID=41170029

Family Applications (1)

Application Number Title Priority Date Filing Date
IN3747CHN2014 IN2014CN03747A (en) 2008-08-18 2009-08-18

Country Status (11)

Country Link
US (1) US7825703B2 (en)
EP (2) EP2327159B1 (en)
JP (1) JP5259823B2 (en)
KR (1) KR101246962B1 (en)
CN (2) CN103944564B (en)
BR (1) BRPI0917342A2 (en)
CA (1) CA2735676C (en)
IN (1) IN2014CN03747A (en)
RU (1) RU2479121C2 (en)
TW (1) TW201015859A (en)
WO (1) WO2010022092A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8344765B2 (en) * 2009-07-16 2013-01-01 Qualcomm, Incorporated Frequency divider with a configurable dividing ratio
WO2012050761A2 (en) 2010-09-30 2012-04-19 Dow Corning Corporation Process for preparing an acryloyloxysilane
US8768994B2 (en) * 2010-10-22 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Filter auto-calibration using multi-clock generator
KR101292767B1 (en) * 2011-09-06 2013-08-02 동국대학교 산학협력단 Pass transistor and odd number frequency devider with 50% duty cycle including it
US8803568B2 (en) * 2011-11-28 2014-08-12 Qualcomm Incorporated Dividing a frequency by 1.5 to produce a quadrature signal
US9065449B2 (en) * 2013-10-28 2015-06-23 Avago Technologies General Ip (Singapore) Pte. Ltd. High-speed divide-by-1.5 circuit with 50 percent duty cycle
CN104734695B (en) 2013-12-24 2018-05-04 澜起科技（上海）有限公司 Signal generator, electronic system and the method for producing signal
US9455716B2 (en) 2014-05-28 2016-09-27 Qualcomm Incorporated Reconfigurable fractional divider
CN105391444B (en) 2014-09-04 2018-07-20 中芯国际集成电路制造(上海)有限公司 A kind of frequency dividing circuit and electronic device
US20160079985A1 (en) * 2014-09-16 2016-03-17 Qualcomm Incorporated Quadrature local oscillator phase synthesis and architecture for divide-by-odd-number frequency dividers
CN104575425B (en) * 2015-01-09 2017-04-12 深圳市华星光电技术有限公司 Scanning driving circuit and NAND logic operation circuit thereof
US9705664B2 (en) 2015-06-18 2017-07-11 Mediatek Singapore Pte. Ltd. Synthesizer module, RF transceiver and method therefor
US10164574B2 (en) * 2015-07-07 2018-12-25 Mediatek Inc. Method for generating a plurality of oscillating signals with different phases and associated circuit and local oscillator
US9973182B2 (en) * 2016-09-14 2018-05-15 Qualcomm Incorporated Re-timing based clock generation and residual sideband (RSB) enhancement circuit
US10374588B2 (en) 2016-10-31 2019-08-06 Mediatek Inc. Quadrature clock generating mechanism of communication system transmitter
US10116290B1 (en) * 2017-12-07 2018-10-30 Speedlink Technology Inc. RF frontend having a wideband mm wave frequency doubler
EP3910793A4 (en) * 2019-01-31 2022-02-09 Huawei Technologies Co., Ltd. BUFFER CIRCUIT, FREQUENCY DIVIDER CIRCUIT AND COMMUNICATION DEVICE
US10454462B1 (en) * 2019-04-18 2019-10-22 Hong Kong Applied Science and Technology Research Institute Company Limited 50% duty cycle quadrature-in and quadrature-out (QIQO) divide-by-3 circuit
US11646919B2 (en) * 2020-01-08 2023-05-09 Mediatek Singapore Pte. Ltd. IQ generator for mixer
US11264995B1 (en) * 2020-10-26 2022-03-01 Qualcomm Incorporated System and method for maintaining local oscillator (LO) phase continuity
RU2752485C1 (en) * 2020-12-03 2021-07-28 Акционерное общество "ПКК МИЛАНДР" Frequency divider with variable division coefficient
CN112787659B (en) * 2020-12-30 2024-08-16 瑞声科技（南京）有限公司 Three frequency divider circuit
CN112994682B (en) * 2021-05-10 2021-08-03 上海灵动微电子股份有限公司 Clock frequency divider, microcontroller and phase-locked loop circuit based on switched capacitor
CN115149943B (en) * 2022-08-31 2022-11-22 上海韬润半导体有限公司 Frequency dividing circuit

Family Cites Families (14)

* Cited by examiner, † Cited by third party
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US4366394A (en) * 1980-09-25 1982-12-28 Rockwell International Corporation Divide by three clock divider with symmetrical output
US4399326A (en) * 1981-01-12 1983-08-16 Bode Harald E W Audio signal processing system
GB9727244D0 (en) 1997-12-23 1998-02-25 Sgs Thomson Microelectronics A dividing circuit and transistor stage therefor
JP2002026726A (en) * 2000-07-07 2002-01-25 Mitsubishi Electric Corp Semiconductor integrated circuit
US6389095B1 (en) * 2000-10-27 2002-05-14 Qualcomm, Incorporated Divide-by-three circuit
US6960962B2 (en) * 2001-01-12 2005-11-01 Qualcomm Inc. Local oscillator leakage control in direct conversion processes
US7508273B2 (en) * 2003-03-19 2009-03-24 Nxp B.V. Quadrature clock divider
RU2273860C2 (en) * 2004-04-12 2006-04-10 федеральное государственное унитарное предприятие "Государственный Рязанский приборный завод" (ФГУП ГРПЗ) Coherent receiver of a radiolocation station with a digital arrangement for amplitude and phase adjusting of quadrature component of a receiving signal
NO323203B1 (en) * 2004-09-24 2007-01-22 Texas Instr Norway As Quadrature parts-by-three frequency parts
JP4687082B2 (en) * 2004-11-30 2011-05-25 セイコーエプソン株式会社 Electronic device and wireless communication terminal
US7123103B1 (en) * 2005-03-31 2006-10-17 Conexant Systems, Inc. Systems and method for automatic quadrature phase imbalance compensation using a delay locked loop
JP2009017528A (en) * 2007-06-05 2009-01-22 Seiko Epson Corp Pulse generation circuit and UWB communication device
RU70059U1 (en) * 2007-08-13 2008-01-10 Открытое акционерное общество "Концерн "Созвездие" DIGITAL FREQUENCY SYNTHESIS
JP4675422B2 (en) * 2009-03-30 2011-04-20 日本電信電話株式会社 Wireless transmitter

Also Published As

Publication number Publication date
CN102124653B (en) 2014-10-08
CN102124653A (en) 2011-07-13
JP5259823B2 (en) 2013-08-07
EP2797234B1 (en) 2018-12-26
EP2327159B1 (en) 2015-01-14
CN103944564A (en) 2014-07-23
KR20110055663A (en) 2011-05-25
KR101246962B1 (en) 2013-03-25
RU2011110168A (en) 2012-09-27
CA2735676C (en) 2014-09-16
EP2797234A8 (en) 2014-12-03
JP2012500596A (en) 2012-01-05
BRPI0917342A2 (en) 2015-11-17
CN103944564B (en) 2017-08-25
EP2327159A1 (en) 2011-06-01
EP2797234A1 (en) 2014-10-29
CA2735676A1 (en) 2010-02-25
TW201015859A (en) 2010-04-16
US20100039153A1 (en) 2010-02-18
RU2479121C2 (en) 2013-04-10
US7825703B2 (en) 2010-11-02
WO2010022092A1 (en) 2010-02-25

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