IE51654B1

IE51654B1 - Method and apparatus for coding and decoding binary data

Info

Publication number: IE51654B1
Application number: IE840/81A
Authority: IE
Original assignee: Telephonie Ind Commerciale
Priority date: 1980-04-15
Filing date: 1981-04-14
Publication date: 1987-02-04
Also published as: SE8102380L; GB2074423B; GB2074423A; ES501297A0; US4399530A; DK169981A; IT8121157A0; PT72859B; BR8102252A; IT1137364B; JPS579145A; ES8203182A1; DE3113766A1; FR2480537A1; IE810840L; FR2480537B1; PT72859A; MX151545A; BE888434A

Abstract

A Coding and decoding method for binary data and associated synchronous clock pulses, wherein the transmission is a half-duplex transmission reception system effected over a single pair of conductors which allows both transmission of the binary data and transmission of the associated clock pulses.

Description

The invention relates both to a method for coding and decoding binary data and associated synchronous clock pulses, and to a device for effecting said method.

Various synchronous data transmission methods are 5 already known. These known methods require two pairs of conductors, one being associated with the transmission of binary data and the other being associated with the clock pulses. It is also necessary to provide both a modulator-demodulator and a baseband converter.

However, the cost of devices using these known methods is relatively high.

The object of the present invention is to provide a method for differential half-duplex synchronous transmission-reception, which enables not only a considerable reduction in the cost of the device to be obtained, but also good immunity to interference induced along the line.

The present invention provides a method of coding and decoding binary data and associated synchronous clock - 3 pulses, said data and pulses symbolically having the values 0 or 1, over a metal pair, characterised in that: for coding, the first line of the metal pair is placed in state 1 when the data and pulses are themselves simultaneously in state 1, otherwise it remains in state 0; and the second line of the metal pair is placed in state 1 when the clock signal is in state 1 whilst the data signal is in state 0, otherwise it remains in state 0; for decoding, the decoded output of the clock signal is placed in state 1 when the lines of the metal pair are simultaneously in a different state, and the state of the decoded output signal is modified when passing from state 1 to state 0 of any one of the coded signals of the lines of the metal pair.

The invention also relates to a device for carrying out the method according to the preceding paragraph, comprising for coding, two AND gates, each connected at its output to a line of the metal pair, the inputs of the AND gate being connected in parallel to the clock signal emission source and the data signal transmission source, the data signal being connected to one of the AND gates via an inverter and comprising for decoding, a NAND gate for decoding the clock signal supplied to the output of the said gate and whose inputs are connected to the metal pair; a memory circuit formed by two NAND gates, the output of each NAND gate being connected to a first 516 5 4 input of the other NAND gate, second inputs of the NAND gate being connected to respective lines of the metal pair, the decoded data signal being generated at the output of the memory circuit.

In the accompanying drawings:Figure 1 is the basic circuit diagram of one form of device for carrying out the method according to the invention; and Figure 2 shows waveforms associated with the circuit of Figure 1.

As shown in Figure 1, a device 1 for coding and decoding binary data and associated synchronous block pulses include a logic processing circuit 2 supplied between the potentials VQ and Vss> A binary signal is fed from the logic processing circuit 2 through line 3 connected both to the input 4 of an inverter 5 and to one input 6 of a first AND gate 7. The output 8 of the inverter 5 is connected to one input 9 of a second AND gate 10. Likewise, from the logic processing circuit 2, clock pulses are fed through line 11 connected both to the second input 12 of the second AND gate 10 and to the second input 13 of the first AND gate 7.

S1654 - 5 The output 14 of the first AND gate 7 is connected through line 15 to the base 15 of a first transistor 17, the emitter 18 of which is connected to the electrical earth 19, and the collector 20 of which is connected to the first conductor 21 of a pair of conductors 22. Likewise, the output 23 of the second AND gate 10 is connected through line 24 to the base 25 of a second transistor 26, the emitter 27 of which ’s connected to the electrical earth 28, and the collector 29 of which is connected to the second conductor 30 of the pair of conductors 22.

For reception, a first differential amplifier 31 is provided, having its positive input 32 connected both to one end 33 of a first resistor 34 and to one end 35 of a second resistor 36.

The other end 37 of the first resistor 34 is connected to the potential 38. The other end 39 of the second resistor 36 is connected both to the line 21 and to one end 40 of a third resistor 41, the other end 42 of which is connected to the electrical earth 43.

The negative input 44 of the first differential amplifier 31 is connected both to the line 30 and to one end 45 of a fourth resistor 46, the other end 47 of which - 6 is connected to the electrical earth 48.

The output 49 of the first differential amplifier 31 is connected both to tne end 50 of a fifth resistor 51, the other ene 52 of which is connected tc the potential 53, and to one input 54 of a first NANO gate 55 and one input 56 of a third NAND gate 57. The output 58 of the first NAND gate 55 is connected to the logic processing circuit 2 to return the received clock pulses 59. The output 60 of the third NAND gate 57 is connected both to the logic processing circuit 2 to return the received data 61, and to one of the inputs 62 of a second NAND gate 63.

In addition, a second differential amplifier 64 is provided having its positive input 65 connected both to one end 66 of a sixth resistor 67 and to one end 68 of a seventh resistor 69. The other end 70 of the sixth resistor 67 is connected to the potential 71. The other end 72 of the seventh resistor 69 is connected both to the line 60 and to the end 45 of the fourth resistor 46.

The negative input 73 of the second differential amplifier 64 is connected both to the line 21 and to the end 40 of the third resistor 41. - 7 The output 74 of the second differential amplifier 64 is connected both to the end 75 of an eighthresistor 76 of which the other end 77 is connected to the potential 78, and to the second input 79 of the second NAND gate 63 and the second input 80 of the first NAND gate 55.

The output 81 of said second NAND gate 63 is connected to the second input 82 of the third NAND gate 57. The gates 57 and 63 are assembled in such a manner as to form a R-S flip-flop.

The operation is as follows: In the case of transmission, there are two signals He, De having two logic states, 0 and 1, and a composite signal is transmitted as follows: (a’) = He De (a) = He De (b*) = He De (b) - He De In the case of reception, a stable state is ensured by unbalance between the input voltages of the differential amplifi er.

The logic state 0 of (a) or of (b) corresponds to a 20 physical state Vb. - 8 S10S4 The logic state 1 of (a) or of (b) corresponds to a physical state Vh.

Thus, by virtue of the coding structure, (a) and (b) are never at the level Vb at the same time.

The result is that the outputs a and b of the differential amplifiers are in the form: a = a = He De b" = b = He De HR = a.b = He De . He.De = He De + He De = He De + 10 He De = He (De + De' from which HR = He Reference will now be made to the in figure 2.

The first line corresponds to The second line corresponds to The third line corresponds to The fourth line corresponds to The fifth line corresponds to The sixth line corresponds to The seventh line corresponds to The eighth line corresponds to The ninth line corresponds to The result is that waveforms shown He De De a1 = He De b' = He De a = a = He De b = b" = He De HR = a.b DR = Q DR = De Various modifications may be made within the scope of the present invention.

Claims

1. A method of coding and decoding binary data and associated synchronous clock pulses, said data and pulses symbolically having the values 0 or 1, over a 5 metal pair, characterised in that: for coding, the first line of the metal pair is placed in state 1 when the data and pulses are themselves simultaneously in state i, otherwise it remains in state 0; and the second line of the metal pair is placed in state 1 when 10 the clock signal is in state I whilst the data signal is in state 0, otherwise it remains in state 0; for decoding, the decoded output of the clock signal is placed in state 1 when the lines of the metal pair are simultaneously in a different state, and the state of the 15 decoded output of the data signal is modified when passing from state 1 to state 0 of any one of the coded signals of the lines of the metal pair.

2. A device for carrying out the method as claimed in claim 1, comprising for coding, two AND gates, 20 each connected at its output to a line of the metal pair, the inputs of the AND gates being connected in parallel to the clock signal emission source and the data signal transmission source, the data signal being connected to one of the AND gates via an inverter, and comprising for 25 decoding, a NAND gate for decoding the clock signal - 11 supplied to the output of the said gate and whose inputs are connected to the metal pair; a memory circuit formed by two NAND gates, the output of each NAND gate being connected to a first input of the other NAND gate, second inputs of the NAND gates being connected to respective lines of the metal pair, the decoded data signal being generated at the output of the memory circuit.

3. A device as claimed in claim 2, characterised in that in the decoding section two differential amplifiers are mounted symmetrically on the lines of the metal pair and are placed upstream of the NAND gate for decoding the clock signal and the memory circuit, the said NAND gate and the said memory circuit respectively having their inputs connected to each of the outputs of the said differential amplifiers.

4. A coding and decoding method for binary data and associated synchronous clock pulses, substantially as hereinbefore described with reference to the accompanying drawings.

5. A device for coding and decoding binary data and associated synchronous clock pulses, substantially as hereinbefore described with reference to the accompanying drawings. 51634