IE47297B1 - Binary data transmission method and corresponding decoding devices - Google Patents

Abstract

The invention relates to a method of coding binary data with a recurrence frequency F, the method being particularly suitable when data is to be transmitted via optical fibres. As described, a binary 1 digit is represented by a pulse in one half of the corresponding binary unit, a binary 0 digit being represented by the absence of any pulse in the corresponding binary unit, except that k 0 digits with defined ranks i.e. positions, in a sequence of m successive 0 digits are each represented by a pulse in the other half of the corresponding binary unit, k being less than m. As shown in Figure 1, k = 1 and m = 4 so that in a sequence of four 0 digits, one 0 digit (the k digit) having a defined rank (in this case the last of the four 0 digits) is represented as above. Suitable arrangements for effecting the required encoding and decoding are also described.

Description

The present invention concerns a binary data transmission method and an encoding device and the associated decoding device. The invention is particularly applicable to the transmission of data signals over a digital trans5 mission link and, more especially, over an optical fibre transmission link.

Data to be transmitted over a digital transmission link is encoded in the form of a series of pulses. The encoding process or the code adopted basically depends on constraints imposed by the transmission line or transmission equipment.

The present invention is intended to provide a twolevel digital signal in accordance with a new encoding law which is particularly suitable for transmission of data over an optical fibre link.

The present invention consists in a binary data transmission method in which the data is embodied in a digital signal at a frequency F with a binary unit duration of 1/P for each binary digit, wherein the method comprises - translating each binary digit with a first value by means of a signal element at a given first level in a first half of the corresponding binary unit and a signal element with a second given level, different from the first level, in the other or second half of the same binary unit, - translating each binary digit with the second value and not forming part of a sequence of m successive binary digits with the second value by a signal element with said second level in the corresponding binary unit, - and translating, within each sequence of m successive binary digits with the second value, k binary digits with respective ranks defined in the sequence, each by means of a signal element with said first level in said second half of the corresponding binary unit and a signal element with said second level in said first half of this unit, each of the m-k digits being translated by a signal element with said second level in the corresponding binary unit, m and k being non-zero integers and k being less than m.

The present invention also consists in a device for encoding binary digitsin the form of a digital input signal at a frequency F under the control of a clock operating at the frequency F and defining a binary unit of duration 1/F for each binary digit, the device comprising - first means for detecting each digit in the received input signal with ε·. first value and representing it by means of a pulse in a first half of the corresponding binary unit, - second means for detecting sequences of m successive digits with the second value in said received input sig5 nal and generating a signal representing k digits with respective ranks defined in each sequence, k and m being non-zero integers and m being greater than k, - third means for representing each of the k binary digits of each sequence of m successive digits with the second value by means of a pulse in a second half of the corresponding binary unit, - summing fourth means connected to said first and third means and providing at its output a two-level signal in two-phase k/m code.

The present invention also consists in a device for decoding a two-phase k/m signal, where k and m are nonzero integers and m is greater than k, produced by encoding data at the frequency F of a coding clock signal H defining a binary unit of duration 1/F for each digit, in which signal a pulse in a first half of a binary unit corresponds to a digit with a first value and a pulse in the second half of a binary unit corresponds to a digit with a second value, with, a rank defined in a sequence of m successive digits with this second value, whereas the absence of a pulse in a binary unit corresponds to all other digits with said second value, the device comprising - a first circuit for detecting at least one of the rising and falling edges of a two-phase k/m signal to be decoded, - a second circuit connected to said first circuit and providing at its output a signal at a frequency to F in phase with the edges detected by the first circuit, the second circuit being followed by a frequency divider with a division ratio of two providing a signal H'r at frequency F, - a circuit for determining the phase of said signal H'r relative to said signal H, comprising a third circuit for detecting two pulses corresponding to two successive binary digits with said first value in said received twophase k/m signal, an output routing logic circuit receiving said signal H'r and the complemented signal H'r and providing at its output one of said received signals constituting the decoding clock signal Hr which is in phase with said coding clock signal H, the logic circuit being controlled by a fourth circuit for detecting coincidence of said signal Hr and the output signal of said third circuit, - and means for outputting said binary digits in accordance with whether said pulses are in one or the other of the two halves of each binary unit defined by the decoding clock signal Hr.

Other features and advantages of the invention will emerge from the following description which is given with reference to the accompanying drawings in which: - figure 1 illustrates a binary data transmission method in accordance with the invention, - figure 2 is a block diagram of an encoding device in accordance with the invention, - figure 3 is a particular embodiment of the encoding 10 device in accordance with the invention, its operation being illustrated in figure 4, - figure 5 is another particular embodiment of the encoding device in accordance with the invention, its operation being illustrated in figure 6, - figure 7 is a diagram illustrating the decoding of a signal encoded in accordance with the invention, - figure δ shows a particular embodiment of a decoding device in accordance with the invention, its operation being illustrated in figure 9, and - figure 10 shows an embodiment of a circuit for recovering the clock signal and which forms part of a decoding device, its operation being illustrated in figures 11, and 13.

Figure 1 illustrates the binary data transmission process in accordance with the invention. Line a) shows a series of binary digits recurring at a frequency F, i.e. with a binary unit duration 1/F. In this example, it has been assumed that the binary data is in the form of a signal in NRZ code as shown in line b).

In NRZ (No Return to Zero) code the signal has two 5 levels and each binary 1 is represented by a signal element with a given non-zero level which is maintained constant throughout the duration of the corresponding binary unit, each binary 0 being represented by a signal element with a different given level which is also maintained constant throughout the duration of the corresponding binary unit.

Line c) shov?s the binary units M, also of duration 1/F, allocated to the binary data in the signal encoded in accordance with the invention and shown in line d). In this particular example, the binary units M of the NRZ signal and of the signal encoded in accordance with the invention coincide and are designated in the same way.

It will be understood that there may be a shift between the sequence of binary units defined by the signal encoded in accordance with the invention and the sequence 2o of binary units of the NRZ signal.

The data shown in line a) is transmitted in the form of the signal shown in line d), which is hereinafter referred to as a two-phase k/m signal.

In the particular example shown in line d) the two25 phase k/m signal has values of k = 1 and m = 4, the general rule being that k and m are two non-zero integers where k is less than m. In this two-phase 1/4 signal, which is a two-level signal: - a binary 1 is represented by a positive pulse or + 1 signal element in the second half of the corresponding binary unit, whereas there is no pulse in the first half of this unit [signal element 0), - a binary 0 which does not form part of a series of 4 successive O's [generally, a series of m successive O's) is translated by the absence of a pulse (signal element 0) throughout the duration of the corresponding unit, and - ir. each series of 4 successive O's, one (k) binary digit with a defined rank in .the sequence (in this case the final of the four O's) is represented by a positive pulse or .+ 1 signal element in the first half of the corresponding binary unit, whereas there is no pulse (signal element 0) in the second half of this unit, each of the three (m-k) other binary digits is translated by the absence of any pulse (signal element 0) throughout the duration of the corresponding unit. & convention relating to the position of the pulses other than that illustrated could be adopted, so that the pulses representing one binary 1 and one (k) particular binary 0 in a sequence of four (m)successive 0's are located in the first and second halves of the corresponding binary units, respectively. These pulses could also be negative pulses. It will be understood that a convention other than that illustrated could be adopted by reversing the encoding procedures for the 0 and 1 digits. Figure .1 shows that the two-phase 1/4 signal generated in this way does not contain any sequence of more than three units without a change of state, the mean power level of this signal being approximately one quarter of its peak value.

Generally speaking, the signal timing can be readily recovered as the two-phase k/m signal does not include more than m binary units without a change of state.

It should also be noted that the content of the twophase k/m signal is readily recognised: it is only necessary to detect the presence of a pulse in one or other half of each binary unit. Errors are also readily detected: in the signal shown in line d) of figure 1, an error will be recognised when a pulse is detected in one of the three units preceding a pulse in the first half of a binary unit and representing the fourth 0 of a sequence of four 0's, Figure 2 is a block diagram of an encoding device for transmission of binary data at the frequency F using the method in accordance with the invention.

The binary data to be transmitted is defined by a digital signal at the frequency F, and is applied to a first input 1 of the device. A clock signal H at the frequency F is applied to a second input 2 of the device. This clock signal H has a given phase relationship with the timing signal of the data in the digital signal at input 1. It defines a binary unit M with a duration 1/F for each binary digit to be transmitted after the encoding process is applied.

The encoding device includes a first circuit 3 for detecting binary I's in the signal received at input 1.

The circuit 3 is controlled by the clock signal H. It also includes a second circuit 4 for detecting sequences of m successive binary 0's in the signal received at input 1; the circuit 4 is controlled by the clock signal H, and is connected to a third circuit 5 which converts k digits with predefined ranks in each sequence of m successive binary 0's detected into k binary I's occupying the same respective rank in the converted sequence. The circuit 5 is also controlled by the clock signal H. The binary signal representing the I's in the input signal obtained at the output of the first circuit 3 is applied to a decision and signal shaping circuit 6 which also receives the clock signal H. In response to each binary 1, the circuit .6 outputs a pulse of determined length at a specific position in time, the rising and falling edges of this pulse coinciding with two successive predefined edges of the clock signal (e.g. the falling and rising edges of the clock signal) . The binary signal representing the 0's in the input signal and modified by conversion of k 0's in each sequence of m successive 0's in the input signal into k l's by the third circuit 5 is applied to another decision and signal shaping circuit 7, which also receives the clock signal H. In response to each binary 1 which it receives ,the circuit 7 outputs a pulse of determined length at a specific position in time, the rising and falling edges of this pulse coinciding with two successi-”-e edges of the clock signal H, taken in the reverse order to those applying to circuit 6.

The two decision and signal shaping circuits 6 and 7 10 are connected to an output circuit 8 which sums the output signals of the circuits 6 and 7. The two-phase k/m signal is obtained at the output 9 of this output circuit. Where necessary, the encoding device includes a delay circuit 10 on the input side of the decision and signal shaping circuit 6, to compensate for the relative shift of the output signals of circuits 3 and 5 representing the binary O's ard l’s, respectively, in the input signal.

Figure 3 shows a specific embodiment of an encoding device for encoding binary data received as an NRZ signal into the form of a two-phase 1/4 signal (k=l, m=4). Reference numeral 1 is retained for the input receiving the signal to be encoded and reference numeral 2 for the input receiving the clock signal H.

In this embodiment, the NRZ signal at input 1 is applied to a first input of a first AND gate 11 and to the forced reset input of two D flip-flops 12 and 13.

The AND gate 11 receives on a second input the complement H of the clock signal, obtained from an inverter 14 to which the clock signal H is applied.

Each of the flip-flops 12 and 13 has its d input connected to its complemented output Q. The clock input h of the first flip-flop 12 receives the complemented clock signal H from inverter 14. The clock input h of the second flip-flop 13 receives the signal at the complemented output Q of flip-flop 12. The two flipflops 12 and 13 form a counter with a capacity of four, simultaneous l's at their Q outputs for a duration of 1/F indicating the detection of a sequence of four successive binary 0's in the NRZ signal at input 1.

A two-input AND gate 15 is connected to the respective Q outputs of the flip-flops 12 and 13. This AND gate converts the fourth binary 0 in a sequenc® of four successive binary 0's into a binary 1, and therefore outputs the converted sequence 0001 in place of the sequence 0000 detected in the NRZ signal.

The output signal from the AND gate 15 is applied to a first input of an AND gate 16 receiving the clock signal H on a second input. The output signals of the two AND gates 11 and 16 are applied to inputs of an OR gate 17 which sums its input signals and provides· at its output 18 the two-phase 1/4 signal corresponding to the NRZ signal at input 1.

As the input signal is an NRZ signal and the flipflops 12 and 13 and the AND gate 15 do not introduce any relative shift between output binary data and the corresponding data in the NRZ signs.1, the NRZ signal at input 1 is applied directly to one of the inputs of the AND gate 11 controlled by the signal H. Tn this specific embodiment, this eliminates the need for a circuit for detecting binary l's in the input signal (circuit 3 in figure 2) and for a delay circuit ensuring correspondence between the signals applied to the first inputs of the AND gates 11 and 16 to observe the relative positions of the binary digits in the NRZ signal (circuit 10 in figure 2).

The operation of the encoding device shown in figure will be described with reference to the diagrams in figure 4, each of which is marked, on the righthand side, with the reference code of the signal or the reference numeral of the circuit at whose output the signal represen20 ted is obtained. Referring to figure 4, line a) shows a series of binary digits identical to that shown in line a) of figure 1, the binary units M also being shown. Line b) shows the corresponding NRZ signal. Line c) shows the clock signal H whose successive periods define binary units which, in this example, coincide with the binary unit M of the NRZ signal and are also designated M.

Lines d) and e) show the output signals at the 0 outputs of the D flip-flops 12 and 13, respectively. Because of the loop connection of each of these flip-flops, each Q output changes state on each rising edge of the signal applied to its clock input h, in the absence of any forced reset signal corresponding to the binary 1's of the NRZ signal. The signal Q12 shows a change of state in the middle of each binary unit for which the input binary digit is 0. Signal Q13 corresponds to the inhibiting of alternate changes of state in signal Q12, in the absence of a forced reset signal. The circuit containing these two flip-flops forms a counter with a capacity of four and which counts successive binary 0's in the NRZ signal. If signals Q12 and Q13 are simultaneously equal to 1 for a duration of 1/P, this signifies the detection of four successive binary 0's in the NRZ signal.

Diagram f) shows the output signal of the AND gate 15 which detects the presence of four successive binary 0's by the coincident 1 states of signals Q12 and Q13. This coincidence occurs during the second half of the binary unit of the third 0 in the sequence and the first half of the binary unit of the fourth 0 in the sequence.

Diagram g) shows the output signal of the AND gate 11 controlled hy the complemented clock signal H. This signal corresponds to the 1 digits in the NRZ signal, each represented by a pulse of defined length equal to 47237 half the duration of the corresponding binary unit M, its rising and falling edges being located at the middle and end respectively of this binary unit M, in other words coinciding with the descending and following rising edge of the clock signal H in this binary unit M. Line h) shows the signal at the output of the AND gate 16 controlled by the clock signal H. This corresponds to the binary l's in the signal at the output of the AND gate 15 (converted fourth 0), each represented as a binary 1 of the NRZ signal but with a phase lead jr provided by the control signal H (rather than the signal H applied to the AND gate 11). Each of the AND gates 11 and 16 forms a decision and signal shaping circuit which outputs pulses of defined length at specific time positions in response to received binary l's. Line i) shows the two-phase 1/4 signal obtained at the output of the OR gate 18 and resulting from the combination of Lhe output signals of the AND gates 11 and 16, Figure 5 shows an alternative specific embodiment of the encoding device, for encoding binary data in the form of an HDB3 signal into a two-phase 1/4 signal (k=l, m=4). In this embodiment, reference numeral 2 is retained for designating the input receiving the clock signal H, and reference numeral 1 is retained and used in conjunction with reference numeral 1' to indicate the input terminals of the device across which the HDB3 signal to be encoded is applied.

The HDB3 code is derived from the bipolar code, and consists of a three-level signal forming part of the family of codes known as the HDBn codes. In HDB3 code: - h binary 1 is represented by a pulse having the opposite polarity to the preceding pulse and located, for example, in the first half of the corresponding binary unit, - a binary 0 is represented by the absence of any pulse in the corresponding binary unit, except that: - each sequence of four (n+1) successive binary O's is represented by one of the two sequences BOOV or 000V (BO....OV or 00....OV), so that two successive bipolar violations, designated V, are always of opposite sign ; in these two sequences, B corresponds to the first of the four successive O's of the sequence and is represented by a binary 1 (i.e. by a positive or negative pulse), and V corresponds to the fourth of the four successive O's in the sequence and is represented by a binary 1 but with a bipolar violation (i.e. by a pulse with the same polarity as the preceding 1 digit).

In the embodiment shown in figure 5, the HDB3 signal is applied to an input transformer 20. The primary winding of this transformer is connected to the two terminals 1 and 1' constituting the input for the HDB3 signal. The secondary winding has an earthed centre tap. 47297 Two D flip-flops 22 and 23 are connected to the terminals 21 and 21' of the secondary winding of the transformer 20, each receiving on a clock input h the complemented clock signal H obtained at the output of an inverter 31 connected to input 2. The d input of flip-flop 22 is connected to terminal 21 of the secondary winding of transformer 20, the d input of flip-flop 23 being connected to terminal 21'. The signal obtained at the Q output of each of the flip-flops 22 and 23 is applied to a respective input of an OR gate 24 and also to a bipolarity violation detector 25 which detects sequences of four successive binary 0's. The OR gate 24 has its output connected to the load input of a shift register 26 which has four stages 27, 28, 29 and 30. The shift register 26 is controlled by the clock signal H at input 2, which is applied to the clock input h. The snift register 26 also receives the signal obtained at the output of the bipolarity violation detector 25, which is applied to the first and third stages 27 and 29 of the shift register 26 so as to force these stages to state 0 each time a.bipolarity violation is detected.

The shift register 26 consists of four D flip-flops, each triggered on the rising edge of the clock signal H applied to its clock input h. The first flip-flop receives the output signal from the OR gate 24 on its d input, and each of the other three flip-flops receives on its d input the signal obtained at the Q output of the preceding flip-flop.

The output signal of the bipolarity violation detector is also applied to the load input d of another shift register 32 which also has four stages and comprises D flip-flops. This shift register receives the clock signal H on its clock input h as a shift control signal.

The output of the shift register 26 (i.e, that of the final stage 30) is connected to one input of an AND gate whose other input receives the complemented clock signal H obtained at the output of the inverter 31 connected to input 2. The output of the shift register 32 (i.e. that of its final stage) is connected to one input of an AND gate 34 whose other input receives the clock signal H from input 2. The outputs of the two AND gates 33 and are connected respective inputs of an OR gate 35 which sums the input signals to provide at its output 36 the two-phase 1/4 signal corresponding to the HDB3 input signal.

The operation of the device shown in figure 5 will now be described with reference to the diagrams in figure 6, each of which is marked, on the righthand side, with the reference code of the signal represented or the reference numeral of the circuit providing the signal represented.

Diagram a) shows a series of binary digits identical to those shown in figures 1 and 4, the binary units M being marked. Diagram h) shows the corresponding HDB3 signal, showing the sequences BOOV and 000V corresponding to four successive binary O's. Diagram c) shows the clock signal II applied to input 2, defining binary units of the same duration as the units M of diagram a), their edges coinciding with those of the binary units M. In practice, there may be a relative shift between the clock signal H and the clock signal defining the frequency of the binary digits in the HDB3 signal.

Diagram d) shows the signal obtained at the Q output of the D flip-flop 22 which is triggered by the rising edges of the complemented clock signal H, its Q output reproducing the positive transitions of the signal at terminal 21 and executing a signal-shaping function.

Diagram e) shows the signal obtained at the Q output of the D flip-flop 23, which operates in the same way as flip-flop 22.

The signal shown in diagram f) is that obtained at the output of the OR gate 24, and corresponds to the logical sum of the signals at Q22 and Q23. Diagram g) shows the bipolarity violation detection signal obtained at the output of circuit 25, by detection of two successive pulses of the same signal Q22 or Q23; the signal at the output of circuit 25 corresponds to the detection of the fourth. 0 of a sequence of four successive 0's of the input HDB3 signal, this being represented in the output signal of the circuit 25 by a pulse of duration 1/F beginning in the middle of the binary unit corresponding to said fourth 0. Diagram h) shows the signal obtained at the Q output of the final flip-flop (i.e. the final stage 30) of the shift register 26, and the effect of the forced resetting of the first and third flip-flops (i.e. stages 27 and 29) by the bipolarity violation detection signal at the output of circuit 25. Each of the flip-flops 27 to 30 is triggered by the rising edge of the signal H, its Q output then going to the level of the signal present at its d input. Because of the convention adopted for the phase of the clock signal applied to input h, the first flip-flop 27 shifts the signal applied to input d by half a unit, the following flip-flops each delaying the signal received at their respective d inputs by a complete unit. The dashed arrows f^ and f’^ and che marked sequences 000V and BOOV show the action of the forced resetting of the first flip-flop 27 by a pulse of the output signal of circuit 25 as shown in diagram g); the dashed arrows fg and f’g show the effect of a reset pulse applied to the third flip-flop 29. Because of the position of the forced reset pulse in question, it acts, as far as the first flip-flop is concerned (arrows fand f', during the binary units corresponding to the 0 and then the V underlined in the sequence 000V or BOOV, and simultaneously acts, as far as the third flip-flop is concerned (arrows f3 and f13) during the binary units corresponding to the 0 or B and then the 0 underlined in the same sequence 000V or B007. The effect of this forced resetting is the cancellation of the pulses which are shown shaded in the signal Q30, which then represents only the 1 digits contained in the input HDB3 signal.

Diagram i) shows the output signal of the AND gate 33 which receives the signals Q30 and H: the pulses representing the 1 bits of the input signal are located in tbe second half of a binary unit defined by the clock signal H. Diagram j) shows the signal obtained at the output of the circuit 32 which applies to its input signal a delay identical to that applied by circuit 26. Diagram k) shows the output signal of the AND gate 34, each part of which represents the fourth 0 bit of a series of four successive 0’s in the HDB3 input signal and is located in the first half of the binary unit of the clock signal H.

Diagram 1) shows the two-phase 1/4 signal ohtained at output 36 by combining the output signals of the AND gates 33 and 34. The binary units are shown on diagram 1) each of which defines one binary digit.

Figures 5 and 6 relate to one specific embodiment of the device. It should be noted that the shift Λ7297 register 26 might be arranged to operate differently, so as to eliminate the pulses B and V corresponding to the first and fourth 0's of a sequence of four successive 0's in the input signal. The shift register 32 would apply to its input signal the same delay as register 26 applies to its input signal.

In figure 7,· diagrams a), b), c] and d) show how a signal in RZ (.Return to Zero) code or in NRZ (No Return to Zero) code from’a two-phase 1/4 code signal. The corresponding decoding devices consist of an AND gate receiving the two-phase 1/4 code signal and controlled by a clock signal Hr at the frequency F, for the reconstitution of a signal in RZ code, or an AND gate followed by a D flip-flop with its d input connected to the output'of the AND gate and its h input connected to receive the signal Hr, for the reconstitution of a signal in NRZ code. These devices are so simple that they have not been shown in a diagram.

Referring to figure 7, diagram a) shows the twophase 1/4 code signal obtained as described above (figures 1, 4 and 6), showing the binary units M. Diagram b) shows the clock signal Hr for reconstitution of the RZ or NRZ code signal, successive clock periods being equal to the duration of each binary unit M and, in this instance, coinciding with the units M of the two-phase 1/4 signal and also designated M. Diagram c) shows the RZ signal obtained from coincidence of the complemented clock signal Hr and the two-phase 1/4 signal. It should be noted that any initial doubt as to the value (1 or 0) of the digits in the two-phase 1/4 signal is resolved by detecting, for example, two consecutive pulses separated by a half-unit and therefore corresponding to two binary l's, or by detecting two successive pulses separated by a period equal to four binary units, the first of those pulses corresponding to a binary 0 and the second to a binary 1. The resolution of this uncertainty defines the correct phase of the signal Hr to he applied, following complementing, to the AND gate.

Diagram d) shows the NRZ code signal obtained at the output of the above-mentioned flip-flop, as derived from the RZ signal and the clock signal Hr.

Figure 8 shows an embodiment of a device for decoding a two-phase 1/4 signal applied to an input 38 in order to reconstitute the signal in HDB3 code. For this embodiment, as for that to which figure 7 relates, it is assumed that the clock signal Hr for reconstitution of the HDB3 code signal has already been generated and is applied to a clock input 39 of the device. This signal Hr is at the frequency F, and is obtained by reconstituting the signal H which, in the encoding device, defines the succession of binary units. Because of the way in which the signal Hr is generated, which will be described below with reference to figures 10 and 11, the changes of state of this signal Hr are in fact slightly delayed relative to those in the two-phase input signal.

' The decoding device shown in this figure includes a first shift register 40 with four cascade-connected stages (D flip-flops) 41, 42, 43 and 44. It also includes a second shift register 45 with five cascadeconnected stages (D flip-flops) 46 to 50. The d input of one flip-flop is connected to the Q output of the preceding flip-flop, in both shift registers 40 and 45.

The d input of the first flip-flop in each shift register (41 and 46) is connected to input 38 and therefore receives the two-phase 1/4 input signal. The first register 40 is controlled'by the complemented clock signal Hr provided by an inverter 51 connected to input 39, the signal Hr being applied to each h input of flip-flops 41 to 44. In the second register 45, the clock signal Hr at input 39 is applied to the h input of the first flip-flop 46 and the signal Hr from inverter 51 is applied to the h input of each of flip-flops 47 to 50.

A two-input AND gate 52 is connected to the Q output of the final flip-flop 44 of shift register 40 and to input 39 receiving the signal Hr. The output of this AND gate 52 supplies a clock signal which is applied to the h input of a D flip-flop 53 whose d input is connected 47237 to its complemented output Q.

Forced resetting of the flip-flop 53 is obtained byusing the output signal of an AND gate 54 which has two inputs, one connected to the Q output of the final flipflop 50 of shift register 45 and the other connected to the input 39 receiving the clock signal Hr.

A two-input AND gate 55 is connected to the complemented output Q of flip-flop 53 and to the Q output of the second flip-flop 47 of register 45. The output of this AND gate 55 and the Q output of the final flipflop 44 of register 40 are connected to the inputs of an OR gate 56. The output of this OR gate 56 is connected to one input of an AND gate 57 which is also connected to receive the clock signal Hr at input 39.

The output signal of this AND gate 57 provides the clock signal to a D flip-flop 58, being applied to its h input. The d inpur of flu-flop 58 is connected to its complemented output Q.

A two-input OR gate 59 has one input connected to the output of the OR gate 56 and the other connected to the Q output of the final flip-flop 50 of register 45, and combines these input signals. The output of the OR gate 59, the complemented output Q of the flip-flop 58 and the input 39 receiving the clock signal Hr are connected to respective inputs of a first AND gate 60, and the output of the OR gate 59, the direct output Q of the flip-flop 58 7 2 3 7 and the input 39 receiving clock signal Hr are connected to respective inputs of a second AND gate 61. The outputs of the AND gates 60 and 61 are connected to respective ends of the primary winding of a transformer 62, this primary winding having an earthed centre tap and the secondary winding having two output terminals 63 and 64 across which is obtained the two-phase input signal converted back into HDB3 code.

The operation of this device is illustrated by the various diagrams in figure 9. These diagrams show various signals obtained within the device, and each is identified on its righthand side by its identifying code or by the reference numeral of the circuit at whose output it is obtained or the terminal at which it is obtained. Diagram a) shows a signal in two-phase 1/4 code which is identical to the signal shown in figures 1, 4 and 6. Diagram a) shows the binary units M, the binary O's corresponding to the fourth 0 in each series of four successive O's in the signal, and the binary l's.

Diagram b) shows the clock signal Hr obtained by reconstituting the signal H which defines the binary units M in the two-phase 1/4 signal. As already mentioned, this signal Hr is in fact very slightly lagging relative to the signal H, the delay being too small to be shown on the diagram.

Diagrams c) and d) respectively show the signal at ,. 47297 the direct output Q of the first and final flip-flops of the shift register 40 controlled by the signal Hr. Diagrams e), f) and g) show the respective signals obtained at the direct outputs of the first, second and final flip-flops of register 45. The first flip-flop in this register is controlled by the signal Hr and the others by the signal Hr. All D flip-flops in the device are triggered by the rising edge of the received clock signals. The dashed arrows show the delay applied by each of the flip-flops relative to one of the preceding flip-tlops of the same shift register. Diagram d) shows that the signal Q at the output of flip-flop 44, i.e. at the output of register 40, reflects the detection of binary l's, these being detected by the first shift register 40. Diagram g) shows that the signal at the Q output of flip-flop 50 reflects the detection of the fourth 0 in each series of four successive 0's, the 0's converted into pulses in the two-phase 1/4 input signal being detected by the second shift register 45.

Diagrams h) and i) show the output signals of the AND gates 52 and 54, combining Q44 and Hr (AND gate 52) and Q50 and Hr (AND gate 53), respectively. Diagram j) shows the signal obtained at the Q output of the looped flip-flop 53 whose clock signal is provided by the AND gate 52, this flip-flop changing state on each rising edge of its clock signal and being forcibly reset 7 297 (Q53 = 1} by the signal obtained at the output of the AND gate 54. Between successive fourth O's converted into pulses, the flip-flop 53 detects the parity of the pulses representing the binary l's in the two-phase signal detected by register 40, taking as reference the forced parity set by any pulse representing a fourth 0 digit. The Q output of flip-flop 53 is forced to 1 on each pulse representing a fourth 0, which must be represented by a bipolarity violation pulse in HDB3 code.

It should be noted that the total shift applied to the signal Q53 by the four flip-flops of register 40 and flip-flop 53 is equal to the total shift applied by the five flip-flops of register 45.

Diagram k) shows the signals obtained at the output of the AND gate 55 controlled by the signal at the Q output of the flip-flop 53 and the signal obtained at the Q output of flip-flop 47. This AND gate 55 generates a so-called padding pulse B which corresponds to the pulse representing signal B of the sequence BOOV in HDB3 code. This B pulse is generated each time that the number of binary l's detected by flip-flop 53 between successive ‘forced resets is 0 or even and a fourth binary 0 in a sequence of four O's is present in flipflop 47. Note that a 1 in flip-flop 47 representing signal element V of one of the sequences 000V and BOOV .47297 in HDB3 code necessarily corresponds to 0's in flipflops 48, 49 and 50 for the two-phase 1/4 code, these four 0's being represented by one of the sequences 000V and BOOV in the HDB3 signal.

Diagram 1) shows the signal obtained at the output of the AND gate 56 which combines the signals representing the 1 digits of the two-phase 1/4 signal and the packing pulses B. Diagram m) shows the signal at the Q output of flip-flop 58 which, by changing state on each rising edge of its clock signal, detects alternate pulses in the signal obtained at the output of the AND gate 57 receiving on its inputs the output signal of the OR gate 56 and the signal Hr. The flip-flop 58 determines the polarity of the pulses in the HDB3 signal to be reconstituted.

Diagram n) shows the signal obtained at the output of the OR gate 59 which combines the pulses representing the l's of the two-phas^ 1/4 signal, the packing pulses B, and the pulses representing the converted 0's of the two-phase 1/4 signal.

Diagrams o) and p) show the signals obtained at the outputs of the the AND gates 60 and 61 which route the pulses in accordance with their polarity. Diagram q) shows the HDB3 code signal obtained across the terminals 63 and 64 of the secondary winding of transformer 62 and obtained by combining the output signals of AND 7 2 9 7 gates 60 and 61, distinguishing between the polarities of the pulses thereof.

Figure 10 shows one embodiment of a circuit for generating the reception clock or decoding clock signal Hr by reconstituting the clock signal H of the encoder. This circuit forms part of a circuit for decoding the two-phase 1/4 signal as described hereinabove.

The circuit comprises an edge detector 65 which, in this example, detects the rising edges of the pulses of the two-phase 1/4 signal at the input 38 (the input of the decoding device). The detector 65 comprises a delay circuit 66 connected to the input 38 followed by an inverter 67 and a two-input AND gate 68 connected to the inverter 67 and to the input 38. The detector 65 controls a circuit 70 for extracting a signal at the frequency 2F. This circuit 70 comprises a filter 71 including an oscillatory circuit preceded by an input transistor 72 connecting it to the output of the AND gate 68 and followed by a signal-shaping and impedance matching circuit 73 providing at an output 74 a squarewave signal at the frequency 2F phase locked to the rising edges of the two-phase 1/4 signal. As each of the circuits 65 and 70 is well known, they will not be described in detail, although they are shown in the figure. Note that an alternativeapproach would be to generate the squarewave signal at the frequency 2F by means of a local oscillator phase locked to the rising and/or falling edges of the two-phase 1/4 signal.

The squarewave signal at frequency 2F obtained at 74 is applied as a clock signal to the h input of a first D flip-flop 75, and also to the h input of a second D flip-flop 76. Input 38 is connected to the d input of flip-flop 75. The d input of the flip-flop 76 is connected to the Q output of flip-flop 75. A NAND gate 77 with three inputs is connected to input 38, the 0 output of the first flip-flop 75 and the Q output or flip-flop 76. An inverter 78 is connected to the output of the NAND gate 77. The two flip-flops 75 and 76, the NAND gate 77 and the inverter 78 together form a detector 79 which detects two successive pulses separated by half the duration of a unit and representing two successive I's of the two-phase 1/4 signal at input 38.

The squarewave signal at frequency 2F obtained at 74 is also applied as a clock signal to the h input of a third flip-flop 80 whose d input is looped to its Q output. This flip-flop 80 halves the frequency of its clock signal, and provides at its Q output a clock signal H'r at frequency F, which is in phase with or in phase opposition to the clock signal H of the twophase 1/4 input signal.

The Q and Q outputs of this flip-flop 80 are connected to respective first inputs of two AND gates 81 and 82 whose respective outputs are connected to an OR gate 83. These gates 81, 82 and 83 form a circuit for routing the signal H'r or the signal H’r, in phase with signal H, to the output of the OR gate 83 which forms the input terminal 39 for the signal Hr for decoding the two-phase 1/4 signal.

A flip-flop 85 controls the two AND gates 81 and 82, and has its d input connected to its Q output, its h input being connected to the output of an AND gate 86.

One input of the AND gate 86 is looped to its output 39, the other being connected to the output of the inverter 78. The respective Q outputs of flip-flops 85 and 80 are connected to the AND gate 81, the Q outputs of these flipflops being connected to the AND gate 82.

The operation of this circuit for extracting the clock signal Hr for decoding the two-phase 1/4 signal will be explained with reference to the diagrams of figures 11 to 13, in which the time scale is twice that used for the diagrams appearing in the preceding figures.

The diagrams of figure 11 show the generation of the squarewave signal at frequency 2F obtained at output 74. Diagram a) shows a two-phase 1/4 signal applied to input 38. To simplify the description, this signal corresponds to the sequence of digits 101100001, which differs from that considered previously. Diagram b) shows the same signal delayed by τ and diagram c) shows the output signal of the AND gate 68 consisting of a short pulse on each rising edge of signal a). Diagram b) shows the same signal delayed by τ and diagram c) shows the output signal of the AND gate 68 consisting of a short pulse on each rising edge of signal a). The circuit 70 is used to extract from the series of pulses shown in diagram o) the squarewave signal at frequency 2F shown in diagram d).

Diagrams e) and f) show the signals H'r and H'r at frequency F obtained from the looped flip-flop 80 operating as a frequency divider with a division ratio of 2, these signals being obtained at the two outputs of flip-flop 80, one being virtually in phase with the clock signal H defining the binary units of the two-phase input signal.

Diagram g) and h) show the signals obtained at the Q outputs of flip-flop 75 and 76, respectively. Each of these flip-flops has a clock signal at the frequency 2F, and delays the signal received on its d input by half a unit 1/2F. Diagram i} shows the signal obtained at the output of the inverter 78, representing the detection of two successive l’s in the two-phase 1/4 input signal. The inverter 78 outputs a pulse corresponding to the second of the two l's.

The diagrams of figures 12 and 13 referred to in the remainder of this explanation of the operation of the circuit shown in figure 10 use the same time scale as figure 11. In figure 12, the signal H'r is assumed to be in phase v/ith the signal H defining the binary units in the two-phase 1/4 signal, whereas in figure 13 it is assumed that signal H’r has a phase shift π relative to signal H, as shown symbolically by the dashed lines joining the diagrams in figures 11, 12 and 13.

In diagram a) in figure 12, it is assumed that the signal H'r is in phase with the signal H; in diagram a) of figure 13, the signal H'r is assumed to be in phase opposition with the signal H. The diagram b) in each of figures 12 and 13 shows the output signal from inverter 78 shown in diagram i} of figure 11.

Diagram c) in figures 12 and 13 shows the signal obtained at the Q output of the flip-flop 85 when taking level 1 as the initial state for the curve shown in full line on the lefthand side of figures 12 and 13, level 0 being taken as the initial state for the curve shown in dashed line on the lefthand side of the figures. Diagram dl and e) show the signals obtained at the outputs of AND gate 81 and 82, respectively, in accordance with the conventions adoptedfor the initial state of flipflop 85.

Thus diagram fl in figure 12 shows that if the initial state of flip-flop 85 is 1, the signal supplied at the output 39 before the first detection of two pulses representing two successive l's in the two-phase 1/4 signal, as shown in diagram b), is H’r. The pulse obtained at the output of the inverter 78 therefore occurs during the 0 level of the signal Hr then at 39: the AND gate 86 output remains at 0, as shown in diagram g) and the state of flip-flop 85 is held at 1. The signal H’r which is in phase with signal H continues to be supplied at output 39.

On the other hand, if the initial state of flip10 flop 85 is 0, the signal supplied at the output 39 before the first detection of two pulses representing two successive l's in the two-phase 1/4 signal (dashed curve), as shown in diagram f), is the signal H'r. The pulse obtained at the output of the inverter 78 therefore occurs when the signal H'r at 39 goes to 1: the AND gate 86 opens briefly, as shown in diagram g), and changes the state of flip-flop 85 from 0 to 1. The gate 82 closes and gate 81 passes the signal H'r which thus appears at the output 39 in place of the signal H'r. The signal at 39 goes back to 0, closing the AND gate 86, as shown in diagram g), Subsequent detection of two other pulses representing two successive l's corresponds to the above-described situation for which the initial state of flip-flop 85 is 1, and therefore is without effect on signal H'r, which continues to be supplied at 39 and forms the signal Hr.

Referring to diagram f) in figure 13, it will be seen that if the initial state of the flip-flop 85 is 1, the signal at output 39 before the first pulse is output by inverter 78 (full line curve) is u'r. The first pulse output by the inverter 78 causes, in conjunction with the signal at 39 which then changes from state 0 to state 1, the appearance of a short pulse at the output of the AND gate 86,-as shown in diagram g), which switches the Q output of flip-flop 85 to state 0. The signal at output 39 changes from Hr to H'r, in phase with signal H.

On the other hand, if the initial state of flip-flop 85 is 0, the signal at output 39 before the first pulse output by inverter 78 is H'r, as shown in dashed outline in diagram f). The pulse output by the inverter 78 has no effect on the AND gate 86 receiving the 0 level of signal H'r, as shown in diagram g): the flip-flop 85 remains in state 0. The signal H'r in phase with signal H continues to be provided at output 39, as shown in diagram f).

Any further pulse output hy the inverter 78 is without effect, the signal Hr at 39 remaining identical to H'r.

Thus it is possible to generate the clock signal Hr in phase with the coding signal H (in practice the signal Hr is very slightly lagging because of the delays introduced by the logic circuits). 47287 The invention has mainly heen described with reference to specific embodiments, but it will be realised that certain modifications may be made to these and that certain of the devices described may be replaced by other, technically equivalent devices.

Claims (7)

1. / A binary data transmission method in which the data is embodied in a digital signal at a frequency F with a binary unit duration of 1/F for each binary digit. Wherein the method comprises 5 - translating each binary digit with a first value by means of a signal element at a given first level in a first half of the corresponding binary unit and a signal element with a second given level, different from the first level, in the other or second half of the same 10 binary unit, - translating each binary digit with the second value and not forming part of a sequence of m successive binary digits with the second value by a signal element with said second level in the corresponding binary unit, 15 - and translating, within each sequence of m successive binary digits with the second value, k binary digits with respective ranks defined in the sequence, each by means of a signal element with said first level in said second half of the corresponding binary unit and a signal 20 element with said second level in said first half of this unit, each of the m-k digits being translated by a signal element with said second level in the corresponding binary unit, m and k being non-zero integers and k being less than m. 4723?

2. / A device fcr encoding binary data in the form cf a digital input signal at a frequency F under the control of a clock operating at the frequency F and defining a binary unit of duration cf 1/F for each binary digit, the 5 device comprising - first means (3, ί ; 11 ; 20, 22-26, 335 for detecting each digit in the received input signal with a first value and representing it by means of a pulse in a first half of the corresponding binary unit, 10 - second means (4, 5 ; 12,- 12, 15 ; 22, 23, 25) for detecting sequences of m successive digits with the second value in said received input signal and generating a signal representing k digits with respective ranks defined in each sequence, k and m being non-zero integers and m being 15 greater than k, - third means (7 ; 16 ; 34) for representing each of the k binary digits of each sequence of m successive digits with the second value by means of a pulse in a second half of the corresponding binary unit, 20 - summing fourth means (8 ; 17 ; 35) connected to said first and third means and providing at its output a twolevel signal in two-phase k-m code.

3. / An encoding device according to claim 2, wherein said digital input signal is in NRZ code and in which the 25 numbers n and m are chosen so that k=l and m-4, and wherein said second means comprise a counter (12, 13) with a capacity of four controlled by said clock signal at frequency F and receiving said input signal and resetting its output state to zero in response to each digit with said first value, and a logic circuit (15) for decoding a digit of specified rank within each sequence of four successive digits with said second value, and in that said first and third means comprise two AND gates (11, 16), one receiving the input signal and the other connected to said decoder logic circuit, the two AND gates being controlled in phase opposition by said clock signal at frequency F.

4. / An encoding device according to claim 2, wherein said digital input signal is in HDB3 code and in which the numbers k and m are chosen such that k=l and m=4 and the digits with the second value are the binary 0 digits, and wherein - said second means comprise two D flip-flops (22, 23) controlled by said clock signal at frequency F and receiving via a transformer (20) said digital input signal applied to their d input, and a bipolarity violation detector (25) connected to the output of each of said flip-flops, - said first means comprising said two flip-flops (22, 23), an OR gate (24) connected to the output of each of said flip-flops, a first shift register (26) with its load input connected to the output of said OR gate, controlled hy said clock signal at frequency F and by the output signal of said bipolarity violation detector, generating an output signal representing only the binary 1 digits of said

5. Input signal, and a first AND gate (33) controlled by said clock signal at frequency F and receiving said output signal of said first shift register, - and said third means comprising a second shift register (32) with its load input connected to the output of 10 said bipolarity violation detector (25), controlled by said clock signal at frequency F and shifting its input signal by an amount identical to that imposed by said first shift register, and a second AND gate (34) controlled by said clock signal, in phase opposition relative to said 15 first AND gate, and receiving said output signal of said second shift register. 5/ A device for decoding a two-phase k/m signal, where k and m are non-zero integers and m is greater than k, produced by encoding data at the frequency F of a coding 20 clock signal H defining a binary unit of duration 1/F for each digit, in which signal a pulse in a first half of a binary unit corresponds to a digit with a first value and a pulse in the second half of a binary unit corresponds to a digit with a second value, with a defined rank in 25 a sequence of m successive digits with this second value, whereas the absence of a pulse in a binary unit corresponds to all other digits with said second value, the device comprising - a first circuit (65) for detecting at least one of the rising and falling edges of a two-phase k/m signal to be decoded, - a second circuit (70) connected to said first circuit and providing at its output a signal at a frequency 2F in phase with the edges detected by the first circuit, the second circuit being followed by a frequency divider (80) with a division ratio of two providing a signal H'r at frequency F, - a circuit for determining the phase of said signal H'r relative to said signal H, comprising a third circuit (79) for detecting two pulses corresponding to two successive binary digits with said first value in said received twophase k/m signal, an output routing logic circuit (81-83) receiving said signal H'r and the complemented signal H'r and providing at its output one of said received signals constituting the decoding clock signal Hr which is in phase with said coding clock signal H, the logic circuit being controlled by a fourth circuit (86) for detecting coincidence of said signal Hr and the output signal of said third circuit, - and means for outputting said binary digits in accordance with whether said pulses are in one or the other of the two halves of each binary unit defined by the decoding clock signal Hr.

6. / A device for decoding a two-phase 1/4 (k=l, m=4) 5 signal, according to claim 5, wherein a pulse in said second half of the binary unit corresponds to the fourth digit of the series of four digits with said second value, the device converting this signal into a signal in HDB3 code, and comprising 10 - means (40) for detecting binary digits with the first value in said received two-phase 1/4 signal and means (45) for detecting the fourth digit with the second value in each sequence in said received two-phase 1/4 signal, under the control of the clock signal Hr, 15 - means (53) for detecting the parity of the digits with said first value from each detected fourth digit with the second value, - means (55) for generating, each time a zero or even number of digits with the first value is detected between 20 successive detections of a fourth digit with the second value, a so-called backing pulse which is in advance of the second detection of a fourth relevant digit by three binary units, - means (58) for determining the polarity to be applied 25 to the pulses of the HDB3 code signal representing the binary digits with the first value and the packing digits, - means (59) for summing the pulses representing the binary digits with the first value, said packing pulses and the pulses representing a fourth digit with the second 5 value, as per their respective binary units, into a second signal, and - a logic output and routing circuit (60, 61, 62) for routing the pulses in accordance with the polarity to be given thereto, connected to said polarity determining 10 means, receiving the signal output by said summing means and controlled by said clock signal, providing at its output said signal in HDB3 code.

7. / A device for encoding binary data substantially as herein described with reference to or as illustrated in the accompanying drawings.