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HK981A - Double master mask process for integrated circuit manufacture - Google Patents

Double master mask process for integrated circuit manufacture

Info

Publication number
HK981A
HK981A HK9/81A HK981A HK981A HK 981 A HK981 A HK 981A HK 9/81 A HK9/81 A HK 9/81A HK 981 A HK981 A HK 981A HK 981 A HK981 A HK 981A
Authority
HK
Hong Kong
Prior art keywords
resistor
base
self
respect
region
Prior art date
Application number
HK9/81A
Inventor
M R Hunt
S T Mastroianni
C A Ladas
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Publication of HK981A publication Critical patent/HK981A/en

Links

Classifications

    • H10P30/204—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P30/212—
    • H10P76/40—
    • H10W10/031—
    • H10W10/30—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/047—Emitter dip
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion

Landscapes

  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Respiratory Apparatuses And Protective Means (AREA)

Abstract

A double master mask process for fabricating semiconductor integrated circuits is provided in which selectively etchable dielectric layers and ion implanted resistors are used to form dense integrated circuits with a minimum number of critical alignments. A first silicon dioxide silicon nitride layer used in conjunction with a first master photomask defines a base region and an isolation region which are self-aligned with respect to each other and with respect to resistor contact regions. After isolation and base diffusion, the first oxide/nitride layer is stripped away and a second oxide/nitride layer is grown. Using a photoresist mask, a predeposition layer for the resistor is then formed using ion implantation through the oxide/nitride layers. A second master photomask allows the formation of collector and emitter regions and base and resistor contact which are self-aligned with respect to each other. The diffusion cycle used to form the collector contact and emitter regions simultaneously anneals the ion implanted resistor region to form a high value resistor of closely controlled tolerances. In conjunction with the use of the first master mask, a base region and isolation region which are self-aligned with respect to each other are formed through the use of a " base washout" process which maintains self-alignment without the use of additional process steps.
HK9/81A 1976-06-28 1981-01-15 Double master mask process for integrated circuit manufacture HK981A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/700,432 US4021270A (en) 1976-06-28 1976-06-28 Double master mask process for integrated circuit manufacture

Publications (1)

Publication Number Publication Date
HK981A true HK981A (en) 1981-01-23

Family

ID=24813479

Family Applications (1)

Application Number Title Priority Date Filing Date
HK9/81A HK981A (en) 1976-06-28 1981-01-15 Double master mask process for integrated circuit manufacture

Country Status (6)

Country Link
US (1) US4021270A (en)
JP (1) JPS532091A (en)
DE (1) DE2729171C2 (en)
FR (1) FR2357063A1 (en)
GB (1) GB1535493A (en)
HK (1) HK981A (en)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151019A (en) * 1974-12-27 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
US4153487A (en) * 1974-12-27 1979-05-08 Tokyo Shibaura Electric Co., Ltd. Method of manufacturing intergrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
US4178190A (en) * 1975-06-30 1979-12-11 Rca Corporation Method of making a bipolar transistor with high-low emitter impurity concentration
US4113512A (en) * 1976-10-28 1978-09-12 International Business Machines Corporation Technique for preventing forward biased epi-isolation degradation
US4135954A (en) * 1977-07-12 1979-01-23 International Business Machines Corporation Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers
US4110126A (en) * 1977-08-31 1978-08-29 International Business Machines Corporation NPN/PNP Fabrication process with improved alignment
US4159915A (en) * 1977-10-25 1979-07-03 International Business Machines Corporation Method for fabrication vertical NPN and PNP structures utilizing ion-implantation
US4155778A (en) * 1977-12-30 1979-05-22 International Business Machines Corporation Forming semiconductor devices having ion implanted and diffused regions
US4118250A (en) * 1977-12-30 1978-10-03 International Business Machines Corporation Process for producing integrated circuit devices by ion implantation
US4228451A (en) * 1978-07-21 1980-10-14 Monolithic Memories, Inc. High resistivity semiconductor resistor device
JPS55138267A (en) * 1979-04-12 1980-10-28 Matsushita Electric Ind Co Ltd Manufacture of semiconductor integrated circuit containing resistance element
US4267012A (en) * 1979-04-30 1981-05-12 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer
US4257826A (en) * 1979-10-11 1981-03-24 Texas Instruments Incorporated Photoresist masking in manufacture of semiconductor device
JPS5685848A (en) * 1979-12-15 1981-07-13 Toshiba Corp Manufacture of bipolar integrated circuit
US4429321A (en) * 1980-10-23 1984-01-31 Canon Kabushiki Kaisha Liquid jet recording device
US4416055A (en) * 1981-12-04 1983-11-22 Gte Laboratories Incorporated Method of fabricating a monolithic integrated circuit structure
US4648909A (en) * 1984-11-28 1987-03-10 Fairchild Semiconductor Corporation Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits
IT1188465B (en) * 1986-03-27 1988-01-14 Sgs Microelettronica Spa PROCEDURE FOR THE MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUITS INCLUDING CMOS DEVICES AND HIGH VOLTAGE ELECTRONIC DEVICES
DE3788470T2 (en) * 1986-08-08 1994-06-09 Philips Nv Method of manufacturing an insulated gate field effect transistor.
US4898837A (en) * 1987-11-19 1990-02-06 Sanyo Electric Co., Ltd. Method of fabricating a semiconductor integrated circuit
US5141881A (en) * 1989-04-20 1992-08-25 Sanyo Electric Co., Ltd. Method for manufacturing a semiconductor integrated circuit
JPH06101540B2 (en) * 1989-05-19 1994-12-12 三洋電機株式会社 Method for manufacturing semiconductor integrated circuit
GB2237445B (en) * 1989-10-04 1994-01-12 Seagate Microelectron Ltd A semiconductor device fabrication process
US5179030A (en) * 1991-04-26 1993-01-12 Unitrode Corporation Method of fabricating a buried zener diode simultaneously with other semiconductor devices
FR2687843A1 (en) * 1992-02-24 1993-08-27 Motorola Semiconducteurs PNP BIPOLAR LATERAL TRANSISTOR AND METHOD FOR MANUFACTURING SAME.
EP0818055A4 (en) * 1995-03-27 1998-05-06 Micrel Inc SELF-ALIGNING TECHNOLOGY FOR SEMICONDUCTOR ARRANGEMENTS
US5702959A (en) * 1995-05-31 1997-12-30 Texas Instruments Incorporated Method for making an isolated vertical transistor
FR2785089B1 (en) * 1998-10-23 2002-03-01 St Microelectronics Sa CONSTRUCTION OF INSULATION WALL
EP1296374B1 (en) * 2001-09-14 2012-09-05 STMicroelectronics Srl Process for bonding and electrically connecting microsystems integrated in several distinct substrates

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3479237A (en) * 1966-04-08 1969-11-18 Bell Telephone Labor Inc Etch masks on semiconductor surfaces
DE1764358B1 (en) * 1967-05-26 1971-09-30 Tokyo Shibaura Electric Co PROCESS FOR PRODUCING A SEMICONDUCTOR COMPONENT
GB1300727A (en) * 1969-04-03 1972-12-20 Motorola Inc Shallow junction semiconductor device and method for making same
US3673679A (en) * 1970-12-01 1972-07-04 Texas Instruments Inc Complementary insulated gate field effect devices
JPS4873085A (en) * 1971-12-29 1973-10-02
DE2314260A1 (en) * 1972-05-30 1973-12-13 Ibm CHARGE-COUPLED SEMI-CONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTURING IT
US3771218A (en) * 1972-07-13 1973-11-13 Ibm Process for fabricating passivated transistors
US3793088A (en) * 1972-11-15 1974-02-19 Bell Telephone Labor Inc Compatible pnp and npn devices in an integrated circuit
US3868274A (en) * 1974-01-02 1975-02-25 Gen Instrument Corp Method for fabricating MOS devices with a multiplicity of thresholds on a semiconductor substrate

Also Published As

Publication number Publication date
DE2729171C2 (en) 1983-03-03
US4021270A (en) 1977-05-03
DE2729171A1 (en) 1977-12-29
GB1535493A (en) 1978-12-13
JPS532091A (en) 1978-01-10
FR2357063B1 (en) 1982-02-19
FR2357063A1 (en) 1978-01-27

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Legal Events

Date Code Title Description
NR Patent deemed never to have been added to the register under section 13(7) of patents (transitional arrangements) rules