HK83795A

HK83795A - Method and system for enciphering and deciphering data transmitted between a transmitting apparatus and a receiving apparatus

Info

Publication number: HK83795A
Application number: HK83795A
Authority: HK
Inventors: Girard Paul
Original assignee: Cp8 Technologies
Priority date: 1984-06-19
Filing date: 1995-05-25
Publication date: 1995-06-01
Also published as: JPH046143B2; FR2566155A1; DE3579073D1; EP0172047B1; FR2566155B1; EP0172047A1; JPS6113724A; ATE55501T1; CA1243738A

Abstract

1. A method of ciphering and deciphering a message transmitted between an emitter device and a receiver device, consisting in ciphering the message (M) by applying to it a reversible ciphering algorithm consisting of an irreversible ciphering algorithm (f) combined with a symmetrization algorithm (s1), and in deciphering the message directly by applying to the ciphered message a reverse deciphering algorithm consisting of the aforesaid irreversible ciphering algorithm combined with a symmetrization algorithm (s2), characterized in that it consists in splitting up the message (M) into two portions (M1, M2), in storing the first portion (M1) of the message in a first register (X1), storing the second portion (M2) of the message in a second register (X2), and performing n times the following successive operations : - storing the contents of the second register (X2) in a garage register (RG) ; - executing upon the contents of the second register (X2) the irreversible algorithm (f) which takes into account an element i of at least one secret code (S) decomposed into p elements ; - storing the result of the execution of the irreversible algorithm (f) in the second register (X2) ; - adding modulo 2 binary digit to binary digit, the contents of the first and second registers (X1, X2) ; - storing the result of this addition in the second register (X2) ; and - storing the contents of the garage register (RG) in the first register (X1) ; and - recommencing the aforesaid n operations p times with i varying from 1 to p, the ciphered or deciphered message consisting of the association in an output register (X3) of the contents of the second register (X2) and of the garage register (RG).

Description

The invention relates to the transmission of information in general and in particular to a process and system for encrypting and decrypting information transmitted between a transmitting and a receiving device.

The invention applies in particular to the transmission of confidential information.

Many applications now use portable media such as cards to access a service delivered by a server.

The provision of this service usually requires a dialogue or exchange of information between the card and the server.

This dialogue usually involves the transmission of at least one message which must be kept confidential to prevent attempts at fraud by the sender and the receiver of the message and by a third party who may intercept the message on the transmission line.

For these reasons, the encryption technique is used so that an encrypted message can only be decrypted by the person to whom it is intended.

The encryption technique consists of processing the message by an algorithm whose degree of complexity depends on the desired degree of security.

However, given that the memory capacity available in a portable object is limited and that an invertible algorithm, for a minimum level of security, takes up relatively little memory space, the encryption and decryption operations are performed in circuits located outside the portable object.

This solution is acceptable only in applications where the messages transmitted contain only so-called passive information, i.e. information which does not enable a protected operation to be carried out. On the contrary, there are applications where the messages transmitted contain so-called active information, i.e. information from which a protected operation can be carried out. In this case, the decrypted message must not be directly accessible from outside for obvious security reasons.

This problem is particularly acute when trying to write certain information (for example, a credit card) into a portable object.

The order of the writing is first decoded by the decoding circuits and then transmitted to the card to carry out the writing operation. Since it is possible to read the order of the writing at the card's input, it is sufficient to re-enter this order in clear form to recode the card at will.

It is therefore desirable to have portable objects that can perform decryption operations directly, without having to use circuits outside the card, i.e. these objects contain the decryption circuits.

Since a non-reversible algorithm takes up less memory space than an inversible algorithm for the same degree of security, the invention provides a process that enables information to be encrypted and decrypted from a non-reversible algorithm by giving this algorithm the inversible property so that it can directly perform decryption operations inside a portable object in accordance with the system proposed by the invention.

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The invention therefore provides for a process according to claim 1, a system according to claim 6 and a certain according to claim 12 to encrypt and decrypt a message transmitted between a transmitting device and a receiving device.

As will be explained later, the invention allows for applications not envisaged so far, in particular for ensuring security in networks and for performing televalorisation operations, i.e. allowing the cardholder to re-credit the card remotely.

Further advantages, characteristics and details will be shown in the explanatory description below, with reference to the accompanying drawings given for example only.

Figure 1 shows a schematic representation of a system conforming to the invention.

Figure 2 shows the details of the encryption/decryption circuits included in a portable media such as a card.

As shown in Figure 1, the system consists of an emission part (E) and an input part (R).

The transmission part (E) consists of a terminal (3E) and a first portable object (1) such as a card temporarily or permanently coupled to that terminal. The reception part (R) consists of a terminal (3R) and a second portable object (2) such as a card temporarily coupled to that terminal. The terminals (3E, 3R) are connected to each other by a conventional transmission line (L).

The cards (1, 2) have, for example, a structure which is in accordance with that described in the applicant's French patent No 2 461 301.

The memory set (12) includes, for example, non-volatile memory (12A) and volatile memory (12B). The memory (12A) itself is divided into at least two areas: a secret area (12A1) inaccessible from the outside in writing/reading and an area (12A2) accessible from the outside in reading/writing.

The encryption/decryption circuits (11) access the memory assembly (12) by a bus (b10).

The terminal (3E) shall, for example, comprise at least one card reader (21) and a data input (22) device such as a keyboard and, as an accessory, a display unit (23).

The card (1) is coupled to the terminal (3E) by an interface (V) as described in the applicant's French patent application No 2 483 713.This interface is connected to the encryption/decryption circuits (11) of the card (1) by a link (b11) and to the write/read device (21) of the terminal (3E) by a link (b24).

The terminal (3R) is identical to the terminal (3E) and the card (2), similar to the card (1), is coupled to this terminal (3R) by the above interface (V). The two terminals (3E, 3R) are connected by a telecommunications interface (T) including the transmission path (L). This interface is connected to the devices (21) of the terminals (3E, 3R) by a link (b25).

The contents of the memory set (12) and the details of the encryption/decryption circuits (11) of the cards (1, 2) are described below.

The following information shall be recorded in the secret area (12A1) of the memory of each card (1, 2): - a confidential code (C) - a secret code (S), - at least one identifier (1), and - an algorithm (f).

In the memory areas (12A2) and (12B) (12) of each card (1, 2) permanent information and temporary information specific to the intended applications are recorded respectively.

As shown in Figure 2, the encryption/decryption circuits (11) comprise two types of circuits (11a, 11b).

The first circuits (11a) are conventional processing circuits capable of executing the algorithm (f) recorded in the cards (1, 2).

These first circuits (11a) are connected in input to output by two intermediate registers (RS, RI) whose inputs are connected to the secret memory area (12A1) of the card.

The second circuits (11b) are designed to complete the first circuits (11a) in the case where algorithm (f) is a non-reversible algorithm. - a first register (X1) whose input is connected to the memory area (12B) and the output of a garage register (RG), and whose output is connected to an input of an adding machine (A) modulo 2 binary digit to binary digit,- a second register (X2) whose input is connected to the memory area (12B), to the output of the adding machine (A) and to the output of the first circuits (11a), and whose output is connected to both the second input of the adding machine (A), to the input of the garage register (RG) and to an input of the first additions (11a), and- a third register (X3) or output register whose input is connected to the outputs of the adding machine (A) and the garage register (GR).

The encryption/decryption circuits (11) divided into two parts (11a, 11b) can be advantageously included in the circuits of a microprocessor designed for this purpose. It should be noted that the algorithm (f) is not necessarily recorded in the memory of the card, it can be implanted in the card in the form of a wired logic.

The operation of the encryption/decryption circuits (11) is described below with reference to Figures 1 and 2, assuming the use of a non-reversible algorithm (f).

The operation of encrypting a message is equivalent to applying simultaneously to that message a non-reversible algorithm (f) and a symmetry algorithm (s1), the set of these two algorithms ultimately returning to applying an inversible algorithm on the message.

The operation of decrypting this message is to apply simultaneously to the encrypted message the same non-reversible algorithm (f) and a symmetry algorithm (s2), the combination of these two algorithms returning to apply an inverse algorithm on the encrypted message.

If the algorithms (s1 and s2) are identical, the algorithm (F-1) is an inverse decryption algorithm identical to the encryption algorithm (F). Otherwise, the algorithm (F-') is an inverse decryption algorithm different from the encryption algorithm (F).

Either a message (M) to be transmitted from terminal (3E) to terminal (3R). - be pre-recorded in the memory area (12B) of the card (1), or - be entered on the terminal keyboard (22) of the terminal (3E), or - be originating from a device (not shown) or a central unit (not shown).

Regardless of its origin, the message (M) is in all cases stored in the memory area (12B) of the card (1).

This message (M) is divided into two parts (M1, M2), the part (M1) of the message is stored in the register (X1) and the part (M2) of the message is stored in the register (X2).

It is important to note that the algorithm (f) takes into account the secret code (S) broken down into p Si elements. In the example, the algorithm (f) also takes into account the identifier (I) broken down into q Ij elements and which personalizes the cardholder (2) for a particular application.

The message (M) is encrypted by performing the following operations n times (n being a positive integer): - the contents of the register (X2) are stored in the garage register (RG) which will then contain the part (M2) of the message (M), - the processing circuits (11a) run the algorithm (f) on the contents of the register (X2), i.e. on the part (M2) of the message (M) to give a result: which is stored in the register (X2) (with i greater than or equal to 1 and less than or equal to p, and j greater than or equal to 1 and less than or equal to q), - the additor (A) of the processing circuits (11 b) adds modulo 2 binary digit to binary digit the contents of the registers (X1, X2) to give a result R2: The data in the register (X2) is stored in the register (X1) and the contents of the garage register (RG) are stored in the register (X1) which will then contain the part (M2) of the message (M). - the contents of the register (X2) are stored in the garage register (RG) which will then contain the result R2 mentioned above: - the processing circuits (11a) run algorithm (f) on the register content (X2), i.e. on the result R2 to give a result R3: which is then stored in the register (X2),- the additor (A) adds modulo 2 binary digit to binary digit the contents of the registers (X1) and (X2) to give a result R4: which is then stored in the register (X2).The above operations that have just been performed for an i and a given are performed (p.q) times with i varying from [1 to p] and j from [1 to q). Once these operations are completed, the encrypted message (M') is obtained in the output register (X3) by putting the contents of the additor (A) and the register (RG) end to end such as: in the example described where n=2.

This encrypted message (M') produced at the transmitting (E) side is sent to the receiving (R) side by the transmission (L) side. The encrypted message (M') once received by the terminal (3R) is stored in the memory area (12B) of the card (2) which is coupled to that terminal (3R).

The decryption circuits (11) of the card (2) will run algorithm (f) to decrypt the message (M). The decryption operation is to apply to the message (M') the same operations as those performed when encrypting the message (M) with one possible variant depending on whether one wishes to obtain a reverse decryption algorithm that is generally identical or not to the encryption algorithm.

The encrypted message (M') is therefore divided into two parts (M'1, M'2):

The part (M'2) of the message (M') is stored in the register (X2) and the part (M'1) of the message (M') is stored in the register (X1).

As for the encryption operation given for purely indicative purposes, the following operations will be performed twice (n=2), which gives: - the contents of the register (X2) are stored in the garage register (RG), - the decryption circuits (11a) run the algorithm (f) on the contents of the register (X2) to give a result (R'1): which is stored in the register (X2) (with i greater than or equal to 1 and less than or equal to p, and j greater than or equal to 1 and less than or equal to q)― the additor (A) adds modulo 2 binary digit to binary digit the contents of the registers (X1, X2) to give a result R'2: which is stored in the register (X2).- the contents of the garage register (RG) are stored in the register (X1) which then contains the part (M'2) of the message (M),- the contents of the register (X2) are stored in the garage register (RG) which then contains the result R'2 above which is equal to the part (M2) of the message,- the decryption circuits (11a) run algorithm (f) again on the contents of the register (X2) to give a result (R'3): which is stored in the register (X2), and- the additor (A) adds modulo 2 binary digit to binary digit the contents of the registers (X1 and X2) to give a result R'4:

As with encryption, the above operations performed for a given i and j are performed (p.q) times with i varying from [1 to p] and j varying from [1 to q].

The invention provides two solutions, namely: - combine the contents of the additor (A) and the garage register (RG) so as to find in the output register (X3) the original message M=(M1, M2), or- combine the contents of the additor (A) and the garage register (RG) in the output register (X3) to obtain a different decrypted message from the original message, e.g. M'=(M2, M1).

If the output register (X3) contains the message (M1, M2) i.e. the original message (M), then the decryption algorithm is identical to the encryption algorithm (s1 equals s2).

If the output register contains a different decrypted message from the original message, for example M'=(M2, M1 the decryption algorithm is not identical to the encryption algorithm (s1 different from s2).

This asymmetry obtained, for example at the end of processing, by a simple reversal of the contents of the additor (A) and the garage register (RG) has been given for purely indicative purposes. More generally and always within the framework of the invention, this asymmetry can be achieved at any stage of the decryption.

The operation of the system as described above was envisaged with the use of a non-reversible algorithm (f) as the starting assumption.

In the case where the chosen algorithm (f) is an inversible algorithm, the above operation differs only in the level of the encryption and decryption operations which are no longer performed by the processing circuits (11a) alone, since it is no longer necessary to call on the processing circuits (11b) responsible for executing the symmetry algorithms (s1, s2) which are used only when the algorithm (f) is a non-reversible algorithm.

In particular, the encryption operation may be limited to applying the algorithm (f) to the entire message (M) to give an encrypted message (M') such that:

This message (M') is directly decrypted by the decryption circuits (11a) of the card (2) by applying to this message the inverse algorithm (f-') as follows:

The interest of the invention will be highlighted in the two applications described below.

A first application is a network in which several people can all communicate with each other via portable objects such as cards. This enablement is achieved by giving these people cards that all contain the same secret code S, the same identifier and the same encryption/decryption algorithm (f). In this case, the decryption algorithm is identical to the encryption algorithm.

A second application is the example of a banking application and in particular an operation which allows the cardholder, once his credit has been exhausted, to re-credit his card remotely in a secure way for the banker.

In the system shown in Figure (1), the terminal (3E) is located in the banker's house, while the terminal (3R) is installed either in a public place or at the cardholder's home (2) by being combined with a telephone exchange, for example.

The operation of crediting the card (2) for X francs was broken down into a series of basic steps:

- first stage:

The cardholder (2), hereinafter referred to as the applicant, calls the banker to notify him of the requested transaction.

- second stage:

If so, the applicant shall connect his card (2) to the terminal (3R) and type his personal identification code (C) into the terminal (3R) keyboard (22) in the usual way. The card (2) or terminal (3R) shall verify that this code (C) corresponds to the code (C) pre-recorded in the memory area (12A1) of the card (2). If there is no coincidence, the requested operation shall not be carried out.

- the third stage:

otherwise, the banker enters a message (M) on the keyboard (22) of his terminal (3E), which translates into an order to recredit the card (2) for an amount of X francs, i.e. gives an order to write the X data to a specific address in the memory area (12A2) of the card (2).

- the fourth stage:

the message (M) is transmitted to the card (1) of the banker to undergo an encryption operation as described above to obtain an encrypted message (M').

- the fifth stage:

the encrypted message (M') is transmitted to the terminal (3R), via the transmission route (L) e.g. a telephone line, and then to the card (2) of the applicant.

- sixth stage:

the encrypted message (M') undergoes a decryption operation as described above with the variant where the decryption algorithm is not identical to the encryption algorithm.

This decrypted message is a writing order which can be understood by the card (2), unless the applicant's card (2) does not contain the same parameters (S, 1) as the banker's card (1). It is essential that the decrypted message is decrypted inside the card (2) and not outside it to prevent the applicant from being able to read the decrypted message, otherwise it would be possible for him to recredit his card himself without receiving a prior order from the banker.

In this application, it is important that the encryption and decryption algorithms are not identical, to prevent the applicant from imitating the banker's card with another card.

Finally, an additional precaution must be taken as the applicant may be able to read the encrypted message, which will then be tempted to re-enter the encrypted message into his card in order to re-credit it without receiving the prior order from the banker.

Claims

1. A method of ciphering and deciphering a message transmitted between an emitter device and a receiver device, consisting in ciphering the message (M) by applying to it a reversible ciphering algorithm consisting of an irreversible ciphering algorithm (f) combined with a symmetrization algorithm (s1), and in deciphering the message directly by applying to the ciphered message a reverse deciphering algorithm consisting of the aforesaid irreversible ciphering algorithm combined with a symmetrization algorithm (s2), characterized in that it consists in splitting up the message (M) into two portions (M1, M2), in storing the first portion (M1) of the message in a first register (X1), storing the second portion (M2) of the message in a second register (X2), and performing n times the following successive operations:

- storing the contents of the second register (X2) in a garage register (RG);

- executing upon the contents of the second register (X2) the irreversible algorithm (f) which takes into account an element i of at least one secret code (S) decomposed into p elements;

- storing the result of the execution of the irreversible algorithm (f) in the second register (X2);

- adding modulo 2 binary digit to binary digit, the contents of the first and second registers (X1, X2);

- storing the result of this addition in the second register (X2); and

- storing the contents of the garage register (RG) in the first register (X1); and

- recommencing the aforesaid n operations p times with i varying from 1 to p, the ciphered or deciphered message consisting of the association in an output register (X3) of the contents of the second register (X2) and of the garage register (RG).

2. A method as in Claim 1, characterized in that it consists in applying two identical symmetrization algorithms (s1, s2) in order that the deciphering algorithm shall be a reverse algorithm identical with the ciphering algorithm (f).

3. A method as in Claim 1, characterized in that it consists in applying two different symmetrization algorithms (s1, s2) in order that the deciphering algorithm shall be a reverse algorithm different from the ciphering algorithm (f).

4. A method as in one of the Claims 1 to 3, characterized in that it consists in directly deciphering the message (M) inside a portable object (1) such as a card connected to the emitter device.

5. A method as in one of the Claims 1 to 4, characterized in that it consists in directly ciphering the message (M) inside a portable object (1) such as a card connected to the emitter device.

6. A system for putting into effect the method as in Claims 1 to 5 for ciphering and deciphering a message transmitted between an emitter device (E) and a receiver device (R); the emitter device (E) comprising at least ciphering circuits (11) for executing a ciphering algorithm (F) and the receiver device (R) comprising at least deciphering circuits (11) for executing a deciphering algorithm (F-'), characterized in that the processing circuits for the ciphering and for the deciphering comprise a first register (X1), a second register (X2), a garage register (RG) and an output register (X3), a modulo 2 binary digit to binary digit adder (A), a memory for recording an irreversible algorithm (f) and at least one symmetrization algorithm (s) as well as a secret code (S), and in that the input to the register (X2) is connected to means enabling the irreversible algorithm (f) to be effected as well as to the output from the adder (A), the output from the register (X2) is connected both to one input to the means of effecting the irreversible algorithm (f), to one input to the adder (A) and to the input to the garage register (RG), the output from the register (X1) is connected to the other input to the adder (A), and the outputs from the adder (A) and garage register (RG) are connected to the input to the output register (X3).

7. A system as in Claim 6, characterized in that the deciphering circuits (11) are included in a portable object (2) such as a card connected to the receiver device (R).

8. A system as in Claim 7, characterized in that the deciphering circuits (11) comprise first circuits (11a) for processing an irreversible algorithm (f) applied to the ciphered message, combined with second circuits (11b) for processing a symmetrization algorithm (s2) for deciphering the message.

9. A system as in one of the Claims 6 to 8, characterized in that the aforesaid algorithms (f, s2) for the deciphering are recorded in one memory of the card (2) connected to the receiver device (R).

10. A system as in one of the Claims 6 to 9, characterized in that the first and second circuits (11 a, 11 b) for the ciphering and for the deciphering are integrated into one microprocessor.

11. A system as in one of the Claims 6 to 10, characterized in that the ciphering circuits (11) of the emitter device (E) are included in a portable object (1) such as a card connected to the emitter device (E).

12. A card for putting into effect the method as in Claim 1 to 5 in the system as in Claims 6 to 11, characterized in that it comprises processing circuits which comprise both for the ciphering and for the deciphering at least one first register (X1), one second register (X2), one garage register (RG) and one output register (X3), one modulo 2 binary digit to binary digit adder (A), one memory for recording an irreversible algorithm (f) and at least one symmetrization algorithm (s) as well as a secret code (S), and in that the input to the register (X2) is connected to means enabling the irreversible algorithm (f) to be effected as well as to the output from the adder (A), the output from the register (X2) is connected both to one input to the means of effecting the irreversible algorithm (f), to one input to the adder (A) and to the input to the garage register (RG), the output from the register (X1) is connected to the other input to the adder (A), and the outputs from the adder (A) and from the garage register are connected to the input to the output register (X3).