HK40100917A - High capacitance tunable multilayer capacitor and array - Google Patents

Description

High-capacitance adjustable multilayer capacitors and arrays

This application is a divisional application of Chinese Patent Application No. 201880077505.4, filed on September 17, 2018, entitled "High-capacitance adjustable multilayer capacitor and array".

Cross-references to related applications

This application claims priority to U.S. Provisional Patent Application Serial No. 62/566,848, filed October 2, 2017, and U.S. Provisional Patent Application Serial No. 62/569,757, filed October 9, 2017, the entire contents of which are incorporated herein by reference.

Background Technology

Adjustable capacitors have been proposed for various applications that rely on the variable dielectric properties of the dielectric. For such capacitors, the capacitance at zero bias is typically close to its maximum value, and the capacitance decreases with the applied voltage. This capacitance variation allows these units to be used in filters, matching networks, resonant circuits, and other applications ranging from audio to RF and microwave frequencies to create adjustable circuits. Despite these advantages, the use of such capacitors is relatively limited, partly due to the relatively low capacitance values required at high power and high voltage. Therefore, there is a current need for a voltage-adjustable capacitor with improved characteristics that can be used in a wider range of possible applications.

Summary of the Invention

According to one embodiment of this disclosure, an adjustable multilayer capacitor array is disclosed. The adjustable multilayer capacitor includes a plurality of adjustable multilayer capacitors connected in parallel. The adjustable multilayer capacitor has an initial capacitance greater than about 0.1 microfarads at an operating voltage greater than about 10 volts. The adjustable multilayer capacitor is configured to have adjustable capacitance by applying a DC bias voltage to the adjustable multilayer capacitor array. The adjustable multilayer capacitor has an operating voltage greater than about 10 volts.

According to another embodiment of this disclosure, an adjustable multilayer capacitor is disclosed, comprising a first active electrode in electrical contact with a first active terminal and a second active electrode in electrical contact with a second active terminal. The capacitor also includes a first DC bias electrode in electrical contact with a first DC bias terminal and a second DC bias electrode in electrical contact with a second DC bias terminal. The capacitor further includes a plurality of dielectric layers disposed between the first and second active electrodes and the first and second bias electrodes. At least a portion of the dielectric layers comprises an adjustable dielectric material exhibiting a variable dielectric constant when an applied DC voltage is applied across the first and second DC bias electrodes. The adjustable multilayer capacitor can have an initial capacitance greater than about 0.1 microfarads at an operating voltage greater than about 10 volts.

According to another embodiment of this disclosure, a partially adjustable multilayer capacitor array is disclosed. The partially adjustable multilayer capacitor array includes adjustable multilayer capacitors configured to have adjustable capacitance by applying a DC bias voltage to the array. The partially adjustable multilayer capacitor array also includes non-adjustable multilayer capacitors connected in parallel with the adjustable multilayer capacitors. The capacitance value of the non-adjustable multilayer capacitors is not adjustable when a DC bias voltage is applied to the partially adjustable multilayer capacitor array.

According to another embodiment of this disclosure, a partially tunable multilayer capacitor is disclosed. The partially tunable multilayer capacitor includes a first active electrode in electrical contact with a first active terminal and a second active electrode in electrical contact with a second active terminal. The partially tunable multilayer capacitor also includes a first DC bias electrode in electrical contact with a first DC bias terminal and a second DC bias electrode in electrical contact with a second DC bias terminal. The partially tunable multilayer capacitor further includes a plurality of dielectric layers disposed between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layers comprises an tunable dielectric material that exhibits a variable dielectric constant when an applied DC voltage is applied across the first and second DC bias electrodes. The non-tunable portions of the plurality of dielectric layers do not exhibit variable capacitance when an applied DC voltage is applied across the first and second DC bias electrodes.

According to another embodiment of this disclosure, an adjustable multilayer capacitor array is disclosed. The adjustable multilayer capacitor array may include a plurality of adjustable multilayer capacitors connected in parallel. The adjustable multilayer capacitor array may have a horizontally stacked configuration. The thickness of each of the plurality of adjustable multilayer capacitors may extend along the length of the adjustable multilayer capacitor array. The adjustable multilayer capacitors may be configured to have adjustable capacitance by applying a DC bias voltage to the adjustable multilayer capacitor array.

Other features and aspects of the invention are set forth in more detail below.

Attached Figure Description

In the remainder of this specification, a full and practical disclosure of the invention, including its preferred mode, is set forth in more detail for those skilled in the art, and with reference to the accompanying drawings, wherein:

Figure 1 shows, as a graph, the capacitance variation that can be achieved using the currently disclosed subject matter within a certain range of normalized bias voltage variation;

Figures 2A, 2B, and 2C show cross-sectional views, exploded plan views, and exploded perspective views of exemplary embodiments of a four-terminal biased multilayer capacitor according to the currently disclosed subject matter, respectively.

Figure 2D shows a general side view, top view, and end perspective view of the assembled device according to the exemplary embodiments of Figures 2A to 2C;

Figures 2E and 2F respectively show representative diagrams of the shunt and cascade configurations of the exemplary embodiments of Figures 2A to 2D;

Figures 3A, 3B, and 3C show cross-sectional views, exploded plan views, and exploded perspective views of exemplary embodiments of a four-terminal adjustable cascaded multilayer capacitor according to the currently disclosed subject matter.

Figures 3D and 3E respectively show representative diagrams of the shunt and series configurations of the exemplary embodiments of Figures 3A to 3C;

Figures 4A and 4B show a perspective view and an exploded plan view, respectively, of an exemplary embodiment of a multilayer capacitor with a four-terminal adjustable partial bias configuration according to the currently disclosed subject matter.

Figure 4C shows a representative diagram of an exemplary embodiment of Figures 4A and 4B;

Figure 5 illustrates an exemplary embodiment of the Chip Manufacturing Automation Process (CMAP) according to the currently disclosed subject matter, which can be used in exemplary embodiments of manufacturing apparatuses as disclosed herein;

Figure 6 shows a cross-sectional view of an exemplary embodiment of a biased asymmetric multilayer capacitor according to the subject matter currently disclosed;

Figures 7A and 7B show a cross-sectional view and a partially enlarged perspective view, respectively, of an exemplary embodiment of a 1:1 scale overlapping symmetrical design of a biased multilayer capacitor according to the subject matter currently disclosed.

Figures 7C and 7D show a cross-sectional view and a partially enlarged perspective view, respectively, of another exemplary embodiment of a 1:1 scale overlapping symmetrical design of a biased multilayer capacitor according to the subject matter currently disclosed.

Figure 8A shows a cross-sectional view of an exemplary embodiment of an 11:1 scale unshielded asymmetric design of a biased multilayer capacitor according to the subject matter currently disclosed.

Figure 8B shows a cross-sectional view of an exemplary embodiment of an 11:1 scale shielded asymmetric design of a biased multilayer capacitor according to the subject matter currently disclosed.

Figures 9A and 9B show a cross-sectional view and a schematic diagram, respectively, of an exemplary embodiment of a partially adjustable multilayer capacitor according to the subject matter currently disclosed.

Figure 10 shows a cross-sectional view of an exemplary embodiment of a biased multilayer capacitor with mixed components according to the currently disclosed subject matter;

Figures 11A-11C respectively illustrate various symmetry orientations that can be used for active terminals and biased terminals in certain embodiments of the present invention;

Figures 12A-12C show side views, front views and perspective views of embodiments of an adjustable multilayer capacitor array according to aspects of the currently disclosed subject matter;

Figures 13A-13C respectively show a side view, a front view, and a perspective view of an embodiment of a partially adjustable multilayer capacitor array according to aspects of the currently disclosed subject matter; and

Figures 14A-14C respectively show a side view, a front view, and a perspective view of an embodiment of an adjustable multilayer capacitor array according to aspects of the currently disclosed subject matter; and

Figure 15 shows a perspective view of an embodiment of an adjustable multilayer capacitor array according to aspects of the currently disclosed subject matter.

Reference numerals are used repeatedly throughout this specification and the accompanying drawings to indicate the same or similar features, elements or steps.

Detailed Implementation

Those skilled in the art will understand that this discussion is merely a description of exemplary embodiments and is not intended to limit the broader aspects of the invention, which are embodied in the exemplary construction.

In general, the present invention relates to a multilayer capacitor comprising a plurality of dielectric layers interposed between alternating active electrode layers. At least a portion of the dielectric layers comprises an adjustable material that exhibits a variable dielectric constant when an applied voltage is applied. More particularly, such material also has a “voltage adjustability factor” ranging from about 10% to about 90%, from about 20% to about 80% in some embodiments, and from about 30% to about 70% in some embodiments, wherein the “voltage adjustability factor” is determined according to the following general formula:

T = 100 × ( _ε₀ - _ε₀ ) / _ε₀

in,

T is the voltage adjustability coefficient;

ε _₀ is the static dielectric constant of the material without an applied voltage; and

_εV is the variable dielectric constant of a material after an applied voltage (DC) is applied.

The static dielectric constant of a material typically ranges from about 100 to about 25,000, in some embodiments from about 200 to about 10,000, and in some embodiments from about 500 to about 9,000, for example, at operating temperatures ranging from about -55°C to about 150°C (e.g., 25°C) and frequencies ranging from about 100 Hz to about 1 GHz (e.g., 1 kHz), as determined according to ASTM D2149-13. It should be understood, of course, that the specific value of the static dielectric constant is typically chosen based on the specific application using the capacitor. The dielectric constant typically decreases within the aforementioned range when an increased DC bias is applied. The adjustment voltage applied to induce the desired change in dielectric constant typically varies relative to the voltage at which the dielectric components begin to conduct after the application of an electric field (“breakdown voltage”), and can be determined according to ASTM D149-13 at a temperature of 25°C. In most embodiments, the maximum applied DC bias voltage is about 50% or less of the breakdown voltage of the dielectric component, in some embodiments about 30% or less, and in some embodiments from about 0.5% to about 10%.

As is known in the art, any variety of tunable dielectric materials can generally be used. Particularly suitable materials are dielectrics whose base components include one or more ferroelectric phases, such as perovskites, tungsten bronze materials (e.g., barium sodium niobate), and layered materials (e.g., bismuth titanate). Suitable perovskites may include, for example, barium titanate and related solid solutions (e.g., barium strontium titanate, calcium barium titanate, barium zirconium titanate, barium strontium zirconium titanate, barium calcium zirconium titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconium titanate, lead lanthanum zirconium titanate), sodium bismuth titanate, etc. In a particular embodiment, for example, barium strontium titanate (“BSTO”) with the chemical formula Ba _x Sr _1-x TiO ₃ can be used, where x ranges from 0 to 1, from about 0.15 to about 0.65 in some embodiments, and from about 0.25 to about 0.6 in some embodiments. Other electrically tunable dielectric materials may partially or wholly replace strontium titanate. For example, one example is _{BaxCa 1-x TiO3} , where x ranges from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6. Other suitable perovskites may include _{PbxZr 1-x TiO3} (“PZT”), where x ranges from about 0.05 to about 0.4, lanthanum lead titanate (“PLZT”), lead titanate ( _PbTiO3 ), calcium barium zirconate titanate ( _{BaCaZrTiO3 )} , sodium nitrate ( _NaNO3 ), _KNbO3 , _LiNbO3 , _LiTaO3 , _PbNb2O6 , _PbTa2O6 , KSr( _NbO3 ) _, and _NaBa2 ( _NbO3 ) _5KHb2PO4 . Other composite perovskites may include A[B1 _1/3 B2 _2/3 ] _O3 material, where A is _{BaxSr 1-x} (x can be a value from 0 to 1); B1 is _{MgyZn 1-y} (y can be a value from 0 to 1); and B2 is _{TazNb 1-z} (z can be a value from 0 to 1). Potential dielectric materials of interest can be formed by combining two end-member components in alternating layers, as illustrated in the exemplary embodiment of FIG10. Such end-member components can be chemically similar, but as mentioned above, the proportion of dopant at the A site differs. For example, component 1 (132 in Figure 10) can be a perovskite compound with the general formula ( _A1x , A2 _(1-x) ) _BO3 , and component 2 (134) can be a perovskite with the general formula ( _A1y , A2 _(1-y) ) _BO3 , where A1 and A2 are derived from Ba, Sr, Mg, and Ca; potential B-site members are Zr, Ti, and Sn, and “x” and “y” represent the mole fraction of each component. Specific examples of compound 1 could be ( _Ba0.8Sr0.2 ) _TiO3 , and compound ₂ could be ( _Ba0.6Sr0.4 ) _{TiO3 .} These two compounds can be combined in alternating layers in a sintered multilayer capacitor with an adjustable electrode structure, as shown in Figure 10, such that the dielectric properties of each material are superimposed. If desired, perovskite materials may also be doped with rare earth oxides (“REO”), for example, in an amount less than or equal to 5.0 mole percent, more preferably from 0.1 to 1 mole percent. For this purpose, suitable rare earth oxide dopants may include, for example, scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and ytterbium.

Regardless of the specific material used, the use of an tunable dielectric material allows the capacitance of the resulting capacitor to be adjusted by applying a DC bias voltage from the bias terminals. More specifically, the capacitor includes a set of first active electrodes in electrical contact with a first active terminal (e.g., an input terminal) and a set of second active electrodes in electrical contact with a second active terminal (e.g., an output terminal). The capacitor also includes a set of first DC bias electrodes in electrical contact with a first DC bias terminal and a set of second DC bias electrodes in electrical contact with a second DC bias terminal. When arranged in a circuit, a DC power supply (e.g., a battery, a constant voltage power supply, a multi-output power supply, a DC-DC converter, etc.) can provide DC bias to the capacitor through the first and second bias terminals (which are typically bipolar because they have opposite polarities). The electrodes and terminals can be formed from any of a variety of different metals known in the art, such as noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, etc.), and various combinations thereof. A dielectric layer is interposed between the respective active and bias electrodes.

I. Adjustable multilayer capacitor

Regardless of the specific configuration employed, the inventors have discovered that by selectively controlling the thickness and number of dielectric layers, compact, adjustable capacitors can be achieved that exhibit excellent adjustability over a high capacitance range within a medium to high operating voltage range, while also providing extremely low equivalent series resistance. In some embodiments, the capacitors can be arranged in an array, as described in more detail later. In other embodiments, these capacitors can be used as individual components. Individual adjustable multilayer capacitors can be used in applications requiring high capacitance, such as values of 0.1 microfarads (“μF”) or higher, about 1 μF or higher in some embodiments, about 10 μF or higher in some embodiments, and 200 μF or higher in some embodiments. For example, such capacitors can provide adjustment capabilities with initial capacitance values ranging from 0.1 to 100 μF, from about 0.5 μF to about 50 μF in some embodiments, from about 1 μF to about 40 μF in some embodiments, and from about 2 μF to about 30 μF in some embodiments. The degree of capacitance adjustability can be varied as needed. For example, the capacitance can be adjusted from about 10% to about 100% of the initial capacitance of the capacitor (i.e., without the application of a DC bias voltage), in some embodiments from about 20% to about 95%, and in some embodiments from about 30% to about 80% of the initial capacitance.

As described above, individual adjustable capacitors can exhibit low ESR. In some embodiments, the equivalent series resistance (ESR) of an individual adjustable capacitor can range from about 50 milliohms (mΩ) or less, in some embodiments about 20 mΩ or less, and in some embodiments about 10 mΩ or less. For example, in some embodiments, the ESR of the adjustable capacitor can range from about 1 mΩ to about 50 mΩ, in some embodiments from about 5 mΩ to about 40 mΩ, and in some embodiments from about 5 mΩ to about 20 mΩ.

As described above, individual adjustable capacitors can operate at medium or high operating voltages. The operating voltage can be referred to as the DC bias voltage (i.e., the voltage across the bias electrode) and/or the signal voltage (i.e., the voltage across the active electrode). The operating voltage typically varies relative to the voltage at which the dielectric component begins to conduct after an electric field is applied (i.e., the "breakdown voltage"), and can be determined according to ASTM D149-13 at a temperature of 25°C. In most embodiments, the operating voltage is about 50% or less of the breakdown voltage of the dielectric component; in some embodiments, about 30% or less; and in some embodiments, from about 0.5% to about 10%.

For example, the adjustable capacitor can operate at an AC voltage greater than about 10V (e.g., peak-to-peak amplitude), greater than about 50V in some embodiments, and greater than about 100V in some embodiments. For example, in some embodiments, the adjustable capacitor can operate at a voltage ranging from about 10V to about 300V, from about 15V to about 150V in some embodiments, and from about 20V to about 100V in some embodiments. In some embodiments, the adjustable capacitor can operate at a DC voltage greater than about 10V, greater than about 50V in some embodiments, and greater than about 100V in some embodiments. For example, in some embodiments, the adjustable capacitor can operate at a voltage ranging from about 10V to about 300V, from about 15V to about 150V in some embodiments, and from about 20V to about 100V in some embodiments. In some embodiments, the adjustable capacitor can operate at a voltage having both AC and DC components.

Similarly, the adjustable capacitor can be adjusted using a range of medium to high applied DC bias voltages. For example, in some embodiments, the DC bias voltage can be greater than about 10V, in some embodiments greater than about 50V, and in some embodiments greater than about 100V. For example, in some embodiments, the range of the DC bias voltage can be from about 10V to about 300V, in some embodiments from about 15V to about 150V, and in some embodiments from about 20V to about 100V.

In some embodiments, the thickness of the dielectric layer can range from about 0.5 micrometers (μm) to about 50 μm, from about 1 μm to about 40 μm in some embodiments, and from about 2 μm to about 15 μm in some embodiments. The thickness of the electrode layer can range from about 0.5 μm to about 3.0 μm, from about 1 μm to about 2.5 μm in some embodiments, and from about 1 μm to about 2 μm in some embodiments, for example, about 1.5 μm.

The total number of active electrode and bias electrode layers can vary. For example, in some embodiments, the total number of active electrode layers can range from 2 to about 1,000, in some embodiments from about 10 to about 700, and in some embodiments from about 100 to about 500. For example, in some embodiments, the total number of bias electrodes can range from 2 to about 1,000, and in some embodiments from about 10 to about 500. It should be understood that the number of electrode layers and bias layers depicted in the accompanying drawings and described herein are illustrative only.

In some embodiments, the capacitor may be compact, enabling it to provide high capacitance while occupying a small volume and/or surface area on the surface on which it is mounted. Therefore, for example, the capacitor may be well-suited for mounting on a printed circuit board. The length of an individual capacitor may range, for example, from about 1 mm to about 50 mm, from about 2 mm to about 35 mm in some embodiments, from about 3 mm to about 10 mm in some embodiments, and from about 3 mm to about 7 mm in some embodiments. The width of an individual capacitor may range, for example, from about 1 mm to about 50 mm, from about 2 mm to about 35 mm in some embodiments, from about 3 mm to about 10 mm in some embodiments, and from about 3 mm to about 7 mm in some embodiments.

Similarly, capacitors can have a low profile, for example, suitable for mounting on a circuit board. The thickness of an individual capacitor can range, for example, from about 1 mm to about 50 mm, from about 2 mm to about 35 mm in some embodiments, from about 3 mm to about 10 mm in some embodiments, and from about 2 mm to about 4 mm in some embodiments.

In alternative embodiments, the initial capacitance value of the adjustable multilayer capacitor may be about 100 picofarads (“pF”) or higher, in some embodiments about 10,000 pF or higher, in some embodiments from about 100,000 pF to about 10,000,000 pF, in some embodiments from about 200,000 pF to 5,000,000 pF, and in some embodiments from about 400,000 pF to about 3,500,000 pF. In some embodiments, the initial capacitance value of a portion of the adjustable multilayer capacitor may range from 0.5 to 50,000,000 pF, in some embodiments from about 100,000 pF to about 10,000,000 pF, in some embodiments from about 200,000 pF to 5,000,000 pF, and in some embodiments from about 400,000 pF to about 3,500,000 pF. Similarly, in other embodiments, the capacitor can be used in applications requiring low capacitance, such as values less than 100 pF, about 50 pF or less in some embodiments, from about 0.5 to about 30 pF in some embodiments, and from about 1 to about 10 pF in some embodiments. The adjustable multilayer capacitor can be configured to have any suitable initial capacitance value.

II. Partially Adjustable Multilayer Capacitors

Furthermore, aspects of this disclosure relate to partially adjustable individual multilayer capacitors. Compared to an equivalent fully adjustable multilayer capacitor, a partially adjustable multilayer capacitor can be adjusted with improved resolution or accuracy. In some embodiments, the partially adjustable multilayer capacitor can provide a smaller capacitance change per unit change in the applied voltage, thereby achieving more precise adjustment.

Compared to an equivalent fully adjustable multilayer capacitor, a partially adjustable multilayer capacitor can be adjusted over a smaller range of capacitance values. For example, a fully adjustable capacitor can be adjustable from, for instance, about 10% to about 95% of its initial capacitance value. This can be accomplished by applying a DC bias voltage to a fully adjustable capacitor that ranges from 0% to 100% of its maximum DC bias voltage. In contrast, a comparable partially adjustable multilayer capacitor can only be adjusted from about 50% to about 95% of its initial capacitance value over the same applied DC bias voltage range. Therefore, for every unit change in the applied voltage, the partially adjustable multilayer capacitor can provide a smaller capacitance change. In some embodiments, the partially adjustable multilayer capacitor can be adjusted from about 20% to about 95% of its initial capacitance value, from about 30% to about 95% in some embodiments, from about 40% to about 95% in some embodiments, from about 50% to about 95% in some embodiments, from about 60% to about 95% in some embodiments, from about 70% to about 95% in some embodiments, and from about 80% to about 95% in some embodiments.

In some embodiments, the partially adjustable multilayer capacitor can be used in applications requiring high capacitance, such as values of 0.1 μF or higher, about 1 μF or higher in some embodiments, about 10 μF or higher in some embodiments, and 200 μF or higher in some embodiments. For example, such a capacitor can provide adjustment capability with an initial capacitance value ranging from 0.1 to 100 μF, from about 0.5 μF to about 50 μF in some embodiments, from about 1 μF to about 40 μF in some embodiments, and from about 2 μF to about 30 μF in some embodiments.

Alternatively, in other embodiments, the initial capacitance value of the partially adjustable multilayer capacitor may be about 100 picofarads (“pF”) or higher, about 10,000 pF or higher in some embodiments, from about 100,000 pF to about 10,000,000 pF in some embodiments, from about 200,000 pF to 5,000,000 pF in some embodiments, and from about 400,000 pF to about 3,500,000 pF in some embodiments. In some embodiments, the initial capacitance value of the partially adjustable multilayer capacitor may range from 0.5 to 50,000,000 pF, from about 100,000 pF to about 10,000,000 pF in some embodiments, from about 200,000 pF to 5,000,000 pF in some embodiments, and from about 400,000 pF to about 3,500,000 pF in some embodiments. Similarly, in some alternative embodiments, the capacitor can be used in applications requiring low capacitance, such as values less than 100 pF, about 50 pF or less in some embodiments, from about 0.5 to about 30 pF in some embodiments, and from about 1 to about 10 pF in some embodiments. Partially adjustable multilayer capacitors can be configured to have any suitable initial capacitance value.

As described above, in some embodiments, adjustable capacitors can provide adjustability over a high capacitance range within a compact component. The combination of high initial capacitance and small overall size can result in high volumetric efficiency. For example, an adjustable multilayer capacitor can have an initial volumetric efficiency associated with its initial capacitance value. Initial volumetric efficiency can be calculated as the initial capacitance of the array (i.e., without a DC bias voltage applied) divided by the volume of the array. In some embodiments, the initial volumetric efficiency can be greater than about 10 microfarads (“μF/cc”), greater than about 40 μF/cc in some embodiments, greater than 100 μF/cc in some embodiments, and greater than 300 μF/cc in some embodiments. For example, in some embodiments, the range of initial volumetric efficiency can be from about 10 μF/cc to about 500 μF/cc, from about 20 μF/cc to about 300 μF/cc in some embodiments, and from about 40 μF/cc to about 250 μF/cc in some embodiments.

III. Adjustable multilayer capacitor array

This disclosure also relates to adjustable multilayer capacitor arrays. Regardless of the specific configuration, the inventors have found that by selectively controlling the thickness of the dielectric layer in individual capacitors, the number of dielectric layers in individual capacitors, the physical configuration of the capacitors in the array, and the number of capacitors in the array, compact and adjustable capacitors can be achieved that exhibit excellent adjustability over a high capacitance range in the medium to high operating voltage range, while also providing extremely low equivalent series resistance. Therefore, adjustable capacitor arrays can be used in applications requiring high capacitance, such as values of 0.1 μF or higher, about 1 μF or higher in some embodiments, 10 μF or higher in some embodiments, and 1000 μF or higher in some embodiments. For example, such capacitors can provide adjustment capabilities with initial capacitance values ranging from 0.1 to 1000 μF, from about 1 μF to about 500 μF in some embodiments, from about 5 μF to about 300 μF in some embodiments, and from about 50 μF to about 250 μF in some embodiments. The degree of capacitance adjustability can be varied as needed. For example, the capacitance can be adjusted from about 10% to about 100%, from about 20% to about 95% in some embodiments, and from about 30% to about 80% of its initial value in some embodiments.

As described above, adjustable capacitor arrays can provide extremely low equivalent series resistance (ESR). For example, in some embodiments, the ESR of the adjustable capacitor array can be about 10 mΩ or less, in some embodiments about 8 mΩ or less, and in some embodiments about 4 mΩ or less. For example, in some embodiments, the ESR of the adjustable capacitor array can range from about 0.01 mΩ to about 10 mΩ, in some embodiments from about 0.1 mΩ to about 8 mΩ, and in some embodiments from about 1 mΩ to about 4 mΩ.

As described above, in some embodiments, the adjustable capacitor array can operate at medium to high operating voltages. For example, the adjustable capacitor array can operate at voltages greater than about 10V, greater than about 50V in some embodiments, and greater than about 100V in some embodiments. For example, in some embodiments, the adjustable capacitor array can operate at voltages ranging from about 10V to about 300V, from about 15V to about 150V in some embodiments, and from about 20V to about 100V in some embodiments.

Similarly, the adjustable capacitor array can be adjustable over a medium to high voltage range. For example, in some embodiments, the DC bias voltage can be greater than about 10V, in some embodiments greater than about 50V, and in some embodiments greater than about 100V. For example, in some embodiments, the DC bias voltage can range from about 10V to about 300V, in some embodiments from about 15V to about 150V, and in some embodiments from about 20V to about 100V.

In some embodiments, the adjustable capacitor stack may have a “horizontal stack” configuration, as explained in more detail below. This can provide components with a low profile that offer adjustability over a range of high capacitance values. Additionally, the “horizontal stack” configuration can provide improved mechanical stability and heat dissipation.

The combination of high capacitance and small overall size can result in high volumetric efficiency. For example, an adjustable multilayer capacitor array can have an initial volumetric efficiency associated with an initial capacitance value. The initial volumetric efficiency can be calculated as the array's initial capacitance (i.e., without a DC bias voltage applied) divided by the array's volume. In some embodiments, the initial volumetric efficiency can be greater than about 10 μF/cc per cubic centimeter, greater than about 40 μF/cc in some embodiments, greater than 100 μF/cc in some embodiments, and greater than 300 μF/cc in some embodiments. For example, in some embodiments, the initial volumetric efficiency can range from about 10 μF/cc to about 500 μF/cc, from about 20 μF/cc to about 300 μF/cc in some embodiments, and from about 40 μF/cc to about 250 μF/cc in some embodiments.

In some embodiments, the capacitor array can be compact, providing high capacitance while occupying a small surface area on the surface on which it is mounted. Therefore, for example, the capacitor array can be ideally suited for mounting on a printed circuit board. For example, the length of the capacitor array can range from about 5 millimeters (mm) to about 50 mm, and in some embodiments from about 10 mm to about 30 mm. The width of the capacitor array can range from, for example, from about 3 mm to about 15 mm, and in some embodiments from about 5 mm to about 10 mm.

Similarly, the capacitor array can have a low profile, for example, suitable for mounting on a circuit board. In some embodiments, the height of the capacitor array can range from, for example, from about 3 mm to about 15 mm, and in some embodiments from about 4 mm to about 10 mm.

In some embodiments, the adjustable capacitor array may include 2 to 24 capacitors, 3 to 12 capacitors in some embodiments, and 4 to 6 capacitors in some embodiments. In other embodiments, the adjustable capacitor array may include more than 24 capacitors.

IV. Partially Adjustable Multilayer Capacitor Array

Furthermore, in some embodiments, a partially adjustable multilayer capacitor array can provide improved adjustment resolution or accuracy in a manner similar to that described above for partially adjustable multilayer capacitors. In some embodiments, a partially adjustable multilayer capacitor array may, for example, include adjustable and non-adjustable capacitors connected in parallel. This can provide an array with a high initial capacitance value that is adjustable with higher accuracy than a non-adjustable multilayer capacitor in a manner similar to that described above. For example, in some embodiments, a partially adjustable multilayer capacitor array can be adjusted from about 20% to about 100% of the initial capacitance value (without applying a DC bias voltage), from about 30% to about 95% in some embodiments, from about 40% to about 90% in some embodiments, from about 50% to about 85% in some embodiments, from about 60% to about 85% in some embodiments, from about 70% to about 85% in some embodiments, and from about 80% to about 85% of the initial capacitance value in some embodiments.

In some embodiments, the partially adjustable multilayer capacitor array can be used in applications requiring high capacitance, such as values of 0.1 μF or higher, about 1 μF or higher in some embodiments, about 10 μF or higher in some embodiments, about 100 μF or higher in some embodiments, and 1000 μF or higher in some embodiments. For example, such capacitors can provide adjustment capabilities with initial capacitance values ranging from 0.1 to 1000 μF, from about 0.5 μF to about 500 μF in some embodiments, from about 1 μF to about 50 μF in some embodiments, and from about 2 μF to about 40 μF in some embodiments.

Alternatively, in other embodiments, the initial capacitance value of the partially adjustable multilayer capacitor array may be about 100 picofarads (“pF”) or higher, about 10,000 pF or higher in some embodiments, from about 100,000 pF to about 10,000,000 pF in some embodiments, from about 200,000 pF to 5,000,000 pF in some embodiments, and from about 400,000 pF to about 3,500,000 pF in some embodiments. In some embodiments, the initial capacitance value of the partially adjustable multilayer capacitor array may range from 0.5 to 50,000,000 pF, from about 100,000 pF to about 10,000,000 pF in some embodiments, from about 200,000 pF to 5,000,000 pF in some embodiments, and from about 400,000 pF to about 3,500,000 pF in some embodiments. Similarly, in other embodiments, the capacitor array can be used in applications requiring low capacitance, such as values less than 100 pF, about 50 pF or less in some embodiments, from about 0.5 to about 30 pF in some embodiments, and from about 1 to about 10 pF in some embodiments. A partially adjustable multilayer capacitor array can be configured to have any suitable initial capacitance value.

In some embodiments, the partially adjustable capacitor array may include 2 to 24 capacitors, 3 to 12 capacitors in some embodiments, and 4 to 6 capacitors in some embodiments. In other embodiments, the partially adjustable capacitor array may include more than 24 capacitors.

V. Discussion of Specific Implementations

Various embodiments of the invention will now be described in more detail.

Figure 1 illustrates, in graph form, the achievable capacitance variation within a certain range of normalized bias voltage variations. Specifically, the horizontal axis plots the normalized bias voltage as a percentage of the device's rated voltage, for example, from 0% to 150%. As shown, the corresponding change in the device's effective capacitance is plotted on the vertical axis as a percentage change from the capacitance value without any bias. As the graph in Figure 1 shows, along the relative straight lines, a 150% increase in the normalized bias voltage approaches an 80% decrease in the unbiased capacitance value, as illustrated. In this way, the voltage-adjustable capacitor device according to the currently disclosed subject matter helps to maximize efficiency under a range of operating conditions.

Referring now to Figures 2A-2D, a particular embodiment of a capacitor 10 that may be formed according to the invention will now be described in more detail. As shown, the capacitor 10 comprises a plurality of dielectric layers 12 that are alternately stacked relative to two sets of separate active electrodes 14 and 20 and two sets of separate bias electrodes 22 and 26. The capacitor may be hexahedral, such as rectangular. In the illustrated embodiment, a first active terminal 16 is electrically connected to a first active electrode 14, and a second active terminal 18 is electrically connected to a second active electrode 20. A first bias electrode 22 is electrically connected to a first DC bias (+) terminal 30 via an extension member 24 (e.g., a tab) extending to the side of the capacitor 10. Similarly, a second bias electrode 26 is electrically connected to a second DC bias (-) terminal 32 via an extension member 28. Thus, the resulting capacitor 10 comprises four (4) separate terminals. In some embodiments, the active terminals 16, 18 may be wrapped around the respective ends of the capacitor 10 to provide larger terminals 16, 18 for electrically connecting the capacitor 10 to a circuit. DC bias terminals 30, 32 may be configured as strips that do not extend across the entire side of capacitor 10. However, in other embodiments, DC bias terminals 30, 32 may alternatively be wrapped around the side of capacitor 10, and active terminals 16, 18 may be configured as strips that do not extend along the entire end of capacitor.

Figures 2E and 2F show representative diagrams of shunt and series configurations of the exemplary embodiments of Figures 2A to 2D, respectively. As shown, a ground 34 relative to the bias input is also provided for the shunt configuration.

In the above embodiments, stacking active electrodes connects each alternating electrode to an opposite terminal. In some embodiments, alternating layers can be connected to the same terminal using a “cascaded” configuration, in which each set of active electrodes is laterally spaced rather than stacked. An embodiment of such a cascaded capacitor 49 is shown in Figures 3A-3C. As shown, the capacitor 49 includes a plurality of dielectric layers 44 arranged relative to two separate sets of active electrodes 36 and 40 and two separate sets of bias electrodes 46 and 50. In the illustrated embodiment, in this example, a first active terminal 38 is electrically connected to a first active electrode 36, and a second active terminal 42 is electrically connected to a second active electrode 40. The first bias electrode 46 is electrically connected to a first DC bias (-) terminal 54 via an extension member 48 extending to the side of the capacitor 49. Similarly, the second bias electrode 50 is electrically connected to a second DC bias (+) terminal 56 via an extension member 52. Figures 3D and 3E show representative diagrams of shunt and series configurations of the exemplary embodiments of Figures 3A to 3C, respectively. As shown, a ground 58 relative to the bias input is also provided for the shunt configuration.

Figures 4A-4C illustrate another embodiment of a capacitor 59 that can be formed in a partially cascaded configuration according to the invention. The capacitor 59 is considered “partially cascaded” because only a localized region 60 of the total active capacitance region is biased (see Figure 4A). As shown, the addition of the bias floating electrodes allows an external voltage to be applied to change the dielectric properties of the total capacitance, which are determined by other factors and characteristics. As shown in these figures, dielectric layers 62 can be alternately stacked relative to a first set of active electrodes 64 and a second set of active electrodes 66, a first set of bias electrodes 68 and a second set of bias electrodes 72, and a plurality of floating electrodes 76. The first active electrode 64 is electrically connected to a first active terminal 78, while the second active electrode 66 is electrically connected to a second active terminal 80. The first bias electrode 68 is electrically connected to a first DC bias (+) terminal 82 via an extension member 70 extending to the side of the capacitor 59. Similarly, the second bias electrode 72 is electrically connected to a second DC bias (-) terminal 84 via an extension member 74. It should be understood that the number of electrode layers shown in Figure 4A is merely illustrative.

Figures 7A and 7B illustrate yet another embodiment according to aspects of this disclosure. In this embodiment, the first set of active electrodes 114 and the second set of active electrodes 120 are stacked with the first set of bias electrodes 122 and the second set of bias electrodes 126 in an alternating 1:1 scale pattern. Referring to Figure 7B, in some embodiments, the leads 124, 128 of the bias electrodes 122, 126 may be configured as protruding tabs. The leads 124, 128 may contact the DC bias terminals 30, 32 in the manner shown in Figure 2D. It should be understood that the number of electrode layers shown in Figures 7A and 7B is merely illustrative.

Another embodiment according to aspects of this disclosure is illustrated in Figures 7C and 7D. In this embodiment, the active electrodes 114, 120 may include corresponding leads 125 and 127, which may be configured as protruding tabs. The leads 125, 127 may be electrically connected to the corresponding active terminals 16, 18 shown in Figure 7D. This can provide improved lamination between the edges of the capacitor layers, particularly at the corners of the layers, which can result in a more robust capacitor. Furthermore, this configuration can reduce the occurrence of delamination problems during manufacturing.

Furthermore, the respective widths of the tabs 124, 125, 126, and 127 can be selected to provide greater electrical contact (e.g., with lower resistance) with the respective electrodes 114, 120, 122, and 126. Additionally, the widths of the tabs 124 and 128 associated with the DC bias electrodes 122 and 126, and the widths of the terminals 30 and 32, can be selected to avoid contact between the bias electrode terminals 30 and 32 and the signal electrode terminals 16 and 18. For example, in some embodiments, the tabs 124, 125, 126, and 127 may extend 10% or more along the edge of the capacitor, in some embodiments 30% or more, and in some embodiments 60% or more. It should be understood that the number of electrode layers shown in Figures 7A-7D is merely illustrative.

In the above embodiments, the electrodes are typically arranged in a “symmetrical” configuration because the distance (or dielectric thickness) between the first and second active electrodes is approximately the same as the distance between the first and second bias electrodes. However, in some embodiments, it may be desirable to vary this thickness to achieve an “asymmetrical” configuration. For example, the distance between the first and second active electrodes may be smaller than the distance between the first and second bias electrodes. In other still embodiments, the distance between the first and second active electrodes may be greater than the distance between the first and second bias electrodes. This may increase the DC field applied for a given level of applied DC bias, which will increase the level of adjustability of a given DC bias voltage, among others. Such an arrangement may also allow for relatively large adjustability for a relatively moderate DC voltage and allows for the use of materials with moderate adjustability (with potentially lower losses and temperature/frequency variability). While this asymmetrical configuration can be implemented in various ways, it is generally desirable to use an additional “floating” bias electrode between each pair of active electrodes. For example, referring to FIG6, an embodiment of such an asymmetric capacitor is shown, which includes a corresponding first active electrode 114 and a second active electrode 120, which are coupled to a first bias electrode 122 and a second bias electrode 126, respectively.

Figure 8A illustrates another embodiment of the asymmetric capacitor, where every 11th electrode is an active electrode rather than a bias electrode (11:1 ratio design). In this case, each such corresponding active electrode (e.g., an AC electrode) can be defined by a pair of DC bias electrodes with opposite polarities. Therefore, a bias field can be generated across each AC electrode. This configuration provides capacitive coupling between the two polarities of the AC signal and the DC bias voltage, and vice versa. Each AC electrode 214, 220 can be positioned between a pair of bias electrodes 222, 226 with opposite polarities. The first set of bias electrodes 222 can all have the same polarity, and the second set of bias electrodes 226 (shown in dashed lines) can all have a corresponding polarity opposite to that of the first set of bias electrodes 222. This configuration provides capacitive coupling between each AC electrode 214, 220 and the two DC bias polarities.

Figure 8B shows a cross-sectional view of an exemplary embodiment of an 11:1 scale shielded asymmetric design of a biased multilayer capacitor according to the subject matter currently disclosed. This is similar to the example shown in Figure 8, except that each AC electrode 314, 320 is defined by a pair of DC electrodes (322 or 326) of the same polarity. One set of bias electrodes 322 may all have the same polarity, and the other set of bias electrodes 326 (shown in dashed lines) may all have opposite polarities. While the material between the two DC electrodes (322 or 326) of the same polarity does not provide adjustment, it can potentially provide shielding for the AC signal, reducing associated noise. Such a configuration also provides coupling between each of the first set of AC electrodes 314 having only a single DC bias polarity. Similarly, such a configuration can provide capacitive coupling only between the second set of AC electrodes 320 and the opposite DC bias polarity. It should be understood that the number of electrode layers shown in Figures 8 and 9 is merely illustrative.

Figure 9A shows a cross-sectional view of an exemplary embodiment of a partially adjustable multilayer capacitor 400 according to aspects of the currently disclosed subject matter. The partially adjustable multilayer capacitor 400 may include a first set of AC electrodes 402 electrically connected to a first active terminal 404 and a second set of AC electrodes 406 electrically connected to a second active terminal 408. The partially adjustable multilayer capacitor 400 may also include a DC bias electrode 410 configured to apply a DC bias voltage across one or more variable dielectric regions 412, such that the dielectric constant of the variable dielectric regions 412 varies as discussed in more detail above. The partially adjustable multilayer capacitor 400 may also include a non-adjustable region 414 that is not adjustable by applying a DC bias voltage. For example, in some embodiments, the non-adjustable region 414 may not contain any DC bias electrode 410. Alternatively, in other embodiments, the non-adjustable region 414 may contain electrodes not connected to any terminal, such that no DC bias voltage can be applied within the non-adjustable region 414. Therefore, in some embodiments, the capacitance of the dielectric material in the non-adjustable portion 402 may be unaffected by the DC bias voltage applied across the DC bias electrode 410.

Figure 9B shows a schematic diagram of the partially adjustable multilayer capacitor shown in Figure 9A. In this embodiment, the non-adjustable region 414 is connected in parallel with one or more variable dielectric regions 412. Applying a DC bias voltage across the DC bias terminal can change the capacitance of the adjustable region(s) 412(s) but not the capacitance of the non-adjustable region 414. This results in the partially adjustable multilayer capacitor being adjustable over a smaller range of capacitance values compared to an equivalent fully adjustable multilayer capacitor. Therefore, for every unit change in the applied DC bias voltage, the change in capacitance can be smaller than that of an equivalent fully adjustable multilayer capacitor. Thus, the partially adjustable multilayer capacitor can provide greater adjustment resolution or accuracy.

In some embodiments, the active and DC bias terminals are arranged symmetrically about the axis of the capacitor. For example, in one embodiment, the capacitor may include opposing first and second end regions spaced apart in the longitudinal direction, and second and second side regions spaced apart in the transverse direction. In some embodiments, the active terminals may be located at the respective end regions of the capacitor, while the DC bias terminals may be located at the respective side regions of the capacitor. When arranged symmetrically, the active terminals and/or DC bias terminals may be equidistant from the longitudinal and/or transverse axes extending through the geometric center of the capacitor. For example, referring to FIG11(a), an embodiment of capacitor 1000 is shown, which includes a longitudinal axis “x” and a transverse axis “y” that are perpendicular to each other and extend through the geometric center “C”. In this particular embodiment, capacitor 1000 includes corresponding first active terminals 1100 and second active terminals 1120, which are located at the end regions of capacitor 1000 and centered about the axes “x” and “y”. Similarly, capacitor 1000 includes a first bias terminal 1140 and a second bias terminal 1160, which are located in the side region of capacitor 1000 and are also centered about the axes “x” and “y”.

In some embodiments, it may be desirable to position two or more terminals on the same side of the capacitor. For example, in Figure 11(b), an embodiment of capacitor 2000 is shown, which includes a first active terminal 2100 and a second active terminal 2140 located in the same side region. Capacitor 2000 also includes a first bias terminal 2160 and a second bias terminal 2120, both located in the opposite side region to the active terminals. Although active terminals 2100 and 2140 are located only in the side regions, they can still be arranged symmetrically because they are both positioned equidistant from axes “x” and “y”. Similarly, bias terminals 2160 and 2120 are also positioned equidistant from axes “x” and “y”. In the above embodiments, the first active terminal and the first bias terminal are positioned opposite the corresponding second active terminal and the second bias terminal. Of course, this is not necessary. For example, in Figure 11(c), a capacitor 3000 is shown, which includes corresponding first active electrode terminals 3100 and second active electrode terminals 3160, which are located in an offset configuration in opposite side regions. Nevertheless, the first active terminals 3100 and second active terminals 3160 are still arranged symmetrically because they are both positioned equidistant from axes “x” and “y”. Similarly, the capacitor 3000 also includes a first bias terminal 3120 and a second bias terminal 3140, which are located in an offset configuration in opposite side regions, but are equidistant from axes “x” and “y”. In other embodiments, the terminals (e.g., bias terminals and/or active electrode terminals) may be configured asymmetrically about the “x” and “y” axes as described above.

The subject matter disclosed herein also includes related and/or corresponding methods for improving voltage-adjustable devices, such as the production of such devices and their combined use with associated circuitry. As another example, Figure 5 illustrates a Chip Manufacturing Automation Process (CMAP) 86, which can be used in conjunction with exemplary embodiments of the manufacturing apparatus disclosed herein. As shown, process 86 may include multiple successive stages, and in some cases, three ovens with interceding ceramic stations or other steps/aspects, such as using sieves or elevator and conveyor features, as schematically illustrated. Those skilled in the art will understand that the exact provision of successive steps will depend on which (or a modification thereof) of the exemplary apparatus embodiments disclosed herein is being manufactured. Furthermore, the individual steps indicated are intended only to indicate the type of step indicated and do not imply the need for other aspects beyond the general nature of the indicated step. For example, a sieve step may involve screen bonding a stainless steel wire mesh together with an electrode paste for an electrode layer, or other techniques may be practiced for this step. For example, more conventional steps of alternating stacking and lamination (using tape) may be practiced. In any process (or other process), those skilled in the art will recognize that the chosen steps can be practiced to produce a particular design chosen for a given application of the subject matter currently disclosed.

Referring to Figures 12A-12C, an adjustable multilayer capacitor array 4000 can be formed by arranging individual capacitors 10 in a "horizontally stacked" configuration. Individual capacitors can be configured, for example, with reference to the descriptions in Figures 2 and 7. Compared to a single capacitor 10, the stacked capacitor array 4000 can provide increased capacitance and reduced ESR. Furthermore, the stacked capacitor array 400 can allow for the fabrication and mounting of more capacitors, for example, on a printed circuit board. Additionally, the stacked capacitor array 400 can provide improved mechanical stability and heat dissipation.

In some embodiments, the capacitors 10 of the capacitor array 4000 can be connected in parallel. For example, a first lead frame 4002 can connect to each first active terminal 16, and a second lead frame 4004 can connect to each second active terminal 18. A first single lead 4006 can connect to each first DC bias terminal 30, and a second single lead 4008 can connect to each second DC bias terminal 32. In some embodiments, the DC bias terminals 30, 32 can be wound around the sides of the capacitors, as shown in Figures 12B and 12C. This configuration can provide improved mechanical and/or electrical connections between the DC bias terminals 30, 32 and the corresponding bias electrodes to which each bias terminal 30, 32 is connected. Furthermore, such a configuration can provide improved electrical connections between the respective first DC bias terminals 30 and the respective second DC bias terminals 32 of adjacent capacitors 10. This can provide a more flexible array 4000.

In other embodiments, DC bias terminals 30, 32 may be disposed only on the side surface of capacitor 10, as shown in FIG12A. Such a configuration allows capacitor 10 to be arranged more closely in array 4000, resulting in, for example, a more compact array 4000.

A DC bias voltage can be applied to each capacitor 10 within the array 4000 by applying a DC bias voltage across the first single lead 4006 and the second single lead 4008. For clarity, the single leads 4006, 4008 are omitted from Figures 12A and 12B. Each of the first lead frame 4002 and the second lead frame 4004 may include a plurality of leads 4010 extending from the capacitor array 4000 for connection to circuitry, such as a printed circuit board. In some embodiments, the leads 4010 may be straight, as shown in Figure 12A, while in other embodiments, the leads 4010 may be bent outwards in a “J” configuration, as shown in Figure 12B. In still other embodiments, the leads 4010 may be bent inwards or have any other suitable configuration for mounting.

The adjustable multilayer capacitor array 4000 may have a length 4012 in the length direction 4014, a width 4016 in the width direction 4018, and a height 4020 in the height direction 4022. Each capacitor 10 may be arranged in a "horizontally stacked" configuration such that the thickness of each of the plurality of adjustable multilayer capacitors 10 extends in the length direction 4014 of the array 4000. As shown in Figures 12A and 12B, the height 4020 of the array 4000 may include a gap distance 4021 (shown in dashed lines) between the array 4000 and the surface on which the array 4000 is mounted. The gap distance 4021 may be measured between the bottom surface of the array 400 (including terminal 32) and the surface on which the array 4000 is mounted. Lead frames 4002, 4004 may support the array 4000 on the surface. The gap distance 4021 may help to thermally insulate the array 4000 from the surface and/or decouple the array 4000 from strain mechanics in the surface.

Referring to Figures 13A-13C, a partially adjustable multilayer capacitor array 5000 can be formed by arranging adjustable multilayer capacitors 10 and non-adjustable capacitors 5002 (i.e., capacitors without adjustment capability) in a "horizontally stacked" configuration. Similar to the embodiment shown in Figures 12A-12C, the partially adjustable multilayer capacitor array 5000 may include a first lead frame 4002 connecting each first active terminal 16 of the adjustable multilayer capacitors 10 and a second lead frame 4004 connecting each second active terminal 19 of the adjustable multilayer capacitors 10. Furthermore, a first single lead 4006 may connect to each first DC bias terminal 30 of the adjustable multilayer capacitors 10, and a second single lead 4008 may connect to each second DC bias terminal 32 of the adjustable multilayer capacitors 10. For clarity, the single leads 4006 and 4008 are omitted from Figures 13A and 13B. Similar to the array 4000 described with reference to Figures 12A-12C, the adjustable capacitor 10 of the partially adjustable array 5000 may include DC bias terminals 30, 32, which are wrapped around the sides of the capacitor 10, as shown in Figures 13B and 13C. In other embodiments, the DC bias terminals 30, 32 may be deposited only on the side surfaces of the adjustable capacitor, for example, as shown in Figure 13A.

The partially adjustable multilayer capacitor array 5000 can provide improved adjustment resolution or accuracy in a manner similar to the partially adjustable multilayer capacitor 400 described above with reference to Figures 9A and 9B. The non-adjustable capacitor 5002 can increase the minimum capacitance of the array 5000 when the maximum DC bias voltage is applied across the array's DC bias electrodes 30, 32 using a single lead 4006, 4008.

Referring to Figures 14A-14C, in some embodiments, the bottom-terminated array 6000 may be configured to have a first DC bias terminal 30 and a second DC bias terminal 32 arranged along the bottom surface of the array 6000. For example, each capacitor 10 may have a corresponding first DC bias terminal 30 and second DC bias terminal 32 arranged along the same side. In other embodiments, the DC bias terminals 30, 32 may both be disposed along the top surface of the array 4000. However, the DC bias terminals 30, 32 may have any suitable configuration.

The configurations shown in Figures 14A-14C offer several advantages, including, for example, ease of installation and improved mechanical durability. For instance, DC bias terminals 30, 32 can be more easily connected to corresponding terminals on the surface on which the array 400 is mounted (e.g., a printed circuit board). In some embodiments, a single lead 4006, 4008 can connect the corresponding DC bias terminals 30, 32 to the corresponding terminals on the mounting surface. However, in other embodiments, the DC bias terminals can be directly connected to the corresponding terminals on the mounting surface, for example, by soldering, without using a single lead 4006, 4008.

Furthermore, the bottom-terminated configuration described above can be used to form a partially adjustable capacitor array in a manner similar to the embodiments described with reference to Figures 13A-13C. For example, in some embodiments, the combination of bottom-terminated adjustable capacitors 10 can be connected in parallel with non-adjustable capacitors 5002 in a manner similar to the partially adjustable array 5000 described above with reference to Figures 13A-13C.

In other embodiments, a first set of adjustable capacitors 10 (having DC bias terminals 30, 32 arranged on opposing side surfaces, as shown in Figures 12A-12C) can be used to form an array with a second set of adjustable capacitors 10 (having DC bias terminals 30, 32 arranged on the same side surfaces (e.g., on the bottom surface), as shown in Figures 14A-14C). This configuration allows a first DC bias voltage to be applied to the first set of adjustable capacitors 10 and allows a second DC bias voltage, different from the first DC bias voltage, to be applied to the second set of adjustable capacitors 10. This can provide an adjustable array 4000 that can be adjusted based on two different DC bias voltages. In yet another embodiment, for example, the first set of adjustable capacitors 10 (having DC bias terminals 30, 32 arranged on the bottom surface) can be connected in an array with the second set of adjustable capacitors 10 (having DC bias terminals 30, 32 arranged on the top surface). This configuration also allows a first DC bias voltage to be applied to the first set of adjustable capacitors 10 and a second DC bias voltage, different from the first DC bias voltage, to be applied to the second set of adjustable capacitors 10. This can provide an adjustable array 4000 that can be adjusted based on two different DC bias voltages.

Those skilled in the art will understand that other combinations of adjustable capacitors having the various configurations described and shown herein can form arrays other than those specifically described herein. Similarly, other combinations of adjustable and non-adjustable capacitors having the configurations described and shown herein are also possible.

Referring to FIG. 15, in some embodiments, the capacitor array 4000 may have a vertically stacked configuration. The vertically stacked capacitor array 4000 may similarly have a first lead frame 4002 connected to some or all of the first active terminals 16, and a second lead frame 4004 connected to some or all of the second active terminals 18. A first single lead 4006 may connect to some or all of the first DC bias terminals 30, and a second single lead 4008 may connect to some or all of the second DC bias terminals 32. Therefore, the vertically stacked capacitor array 4000 may be configured as a fully adjustable capacitor array in some embodiments and as a partially adjustable capacitor array in other embodiments. In some embodiments, the vertically stacked array may be formed with two bias terminals 30, 32 on the same side, for example using an adjustable capacitor 10 configured to bottom-terminate the capacitor 10 described in the adjustable array as shown above with reference to FIGS. 14A-14C. Similarly, combinations of different adjustable and/or non-adjustable capacitors can be combined into a vertical stacked array 4000, as described above with reference to horizontal stacked arrays 4000 and 5000.

The horizontal stacking configuration described above with reference to Figures 12-14 can provide improved mechanical stability for capacitor arrays comprising a large number of capacitors. For example, for arrays comprising more than five capacitors, the height of a vertically stacked array may become unsuitable for mounting, for example, to a surface on a printed circuit board. Furthermore, the height of such an array may make the array mechanically unstable. However, for arrays with a small number of capacitors, such as five or fewer, a vertically stacked array can provide a smaller footprint and a lower profile.

VI. Application

The capacitor of this invention can be used in a variety of applications, including, for example, power conversion circuits. Adjustability at high capacitance and voltage allows for optimization of circuit performance. Other applications may include smoothing capacitors in point-of-load filter circuits and variable-load circuits. Other suitable applications may include, for example, waveguides, RF applications (e.g., delay lines), antenna structures, matching networks, resonant circuits, and others.

Test methods

capacitance

Capacitance can be measured according to MIL-STD-202 Method 305 using a Keithley 3330 Precision LCZ instrument with a DC bias of 0.0V, 1.1V, or 2.1V (1V RMS sine wave). The operating frequency is 1kHz, and the temperature is approximately 25°C. The relative humidity can be 25% or 85%.

Equivalent series resistance (ESR)

Equivalent series resistance can be measured using a Keithley 2400, 2602, or 3330 Precision LCZ meter with DC bias of 0.0V, 1.1V, or 2.1V (0.5V peak-to-peak sinusoidal signal) and operating frequencies of 10kHz, 50kHz, or 100kHz. Various temperature and relative humidity levels can be measured. For example, temperatures can be 23°C, 85°C, or 105°C, and relative humidity can be 25% or 85%.

Example

Examples of adjustable multilayer capacitor arrays according to aspects of this disclosure are provided in Table 1:

Table 1: Example of an adjustable multilayer capacitor array

The initial capacitance listed in Table 1 can be the capacitance of the array without an applied DC bias voltage. The array can be adjusted from approximately 10% to approximately 95% of the initial capacitance.

These and other modifications and variations of the invention can be practiced by those skilled in the art without departing from the spirit and scope of the invention. Furthermore, it should be understood that aspects of the various embodiments can be interchanged in whole or in part. Moreover, those skilled in the art will understand that the above description is merely exemplary and is not intended to limit the invention further described in the appended claims.

Claims (35)

1. An adjustable multilayer capacitor array comprising a plurality of adjustable multilayer capacitors connected in parallel, wherein the adjustable multilayer capacitor array has an initial capacitance value greater than about 0.1 microfarads at an operating voltage greater than about 10 volts, and wherein the adjustable multilayer capacitors are configured to have adjustable capacitance by applying a DC bias voltage to the adjustable multilayer capacitor array. 2. The adjustable multilayer capacitor array of claim 1, wherein the applied DC bias voltage ranges from about 10 volts to about 300 volts. 3. The adjustable multilayer capacitor array of claim 2, wherein the applied DC bias voltage ranges from about 100 volts to about 300 volts. 4. The adjustable multilayer capacitor array of claim 1, wherein the adjustable multilayer capacitor has an initial volumetric efficiency associated with the initial capacitance value, and the initial volumetric efficiency is greater than about 10 microfarads per cubic centimeter. 5. The adjustable multilayer capacitor array of claim 1, wherein the initial volumetric efficiency ranges from about 10 microfarads per cubic centimeter to about 500 microfarads per cubic centimeter. 6. The adjustable multilayer capacitor array of claim 1, wherein the initial capacitance value of the adjustable multilayer capacitor array is greater than about 1 μF. 7. The adjustable multilayer capacitor array of claim 1, wherein the capacitance of the adjustable multilayer capacitor is adjustable from about 10% to about 95% of the initial capacitance value. 8. The adjustable multilayer capacitor array of claim 1, wherein the equivalent series resistance of the adjustable multilayer capacitor array is less than about 10 mΩ. 9. The adjustable multilayer capacitor array of claim 1, wherein the adjustable multilayer capacitor array has a horizontally stacked configuration, and the thickness of each of the plurality of adjustable multilayer capacitors extends in the length direction of the adjustable multilayer capacitor array. 10. The adjustable multilayer capacitor array of claim 1, wherein the plurality of adjustable multilayer capacitors comprises five or more adjustable multilayer capacitors. 11. The adjustable multilayer capacitor array of claim 1, further comprising at least one multilayer capacitor not configured to be adjustable by an applied voltage. 12. The capacitor of claim 1, wherein the length of the adjustable multilayer capacitor array is from about 5 mm to about 50 mm. 13. The capacitor of claim 1, wherein the width of the adjustable multilayer capacitor array is from about 3 mm to about 15 mm. 14. The capacitor of claim 1, wherein the height of the adjustable multilayer capacitor array is from about 3 mm to about 15 mm. 15. The adjustable multilayer capacitor array of claim 1, wherein each of the plurality of adjustable multilayer capacitors comprises: The first active electrode that is in electrical contact with the first active terminal; The second active electrode is in electrical contact with the second active terminal; The first DC bias electrode is in electrical contact with the first DC bias terminal; and The second DC bias electrode is in electrical contact with the second DC bias terminal; and Multiple dielectric layers are disposed between the first active electrode and the second active electrode and between the first bias electrode and the second bias electrode. At least a portion of the dielectric layer comprises an tunable dielectric material that exhibits a variable dielectric constant when an applied DC voltage is applied across the first DC bias electrode and the second DC bias electrode. 16. The adjustable multilayer capacitor array of claim 15, further comprising: The first lead frame connected to each first active terminal; and A second lead frame connected to each second active terminal. 17. The adjustable multilayer capacitor array of claim 15, further comprising a first single lead connected to each first DC bias terminal and a second single lead connected to a second DC bias terminal. 18. The adjustable multilayer capacitor array of claim 15, wherein the thickness of the plurality of dielectric layers of at least one of the plurality of adjustable multilayer capacitors ranges from about 0.5 micrometers to about 50 micrometers. 19. The adjustable multilayer capacitor array of claim 15, wherein the number of dielectric layers included in at least one of the plurality of adjustable multilayer capacitors ranges from about 10 to about 700. 20. The capacitor of claim 15, wherein the total number of the first active electrode and the second active electrode of at least one of the plurality of adjustable multilayer capacitors ranges from about 100 to about 500. 21. The capacitor of claim 15, wherein at least one of the plurality of adjustable multilayer capacitors comprises a dielectric material having a voltage adjustability factor from about 10% to about 95%, wherein the voltage adjustability factor is determined according to the following general formula: T = 100 × ( _ε₀ - _ε₀ ) / _ε₀ in, T is the voltage adjustability coefficient; ε _₀ is the static dielectric constant of the material without an applied voltage; and _εV is the variable dielectric constant of the material after the applied voltage (DC) is applied. 22. The capacitor of claim 21, wherein at least one of the plurality of adjustable multilayer capacitors comprises a dielectric material having a static dielectric constant from about 100 to about 10,000, as determined according to ASTM D2149-13 at an operating temperature of 25°C and a frequency of 1 kHz. 23. The capacitor of claim 21, wherein at least one of the plurality of adjustable multilayer capacitors comprises a dielectric material comprising one or more ferroelectric phases. 24. The capacitor of claim 21, wherein at least one of the plurality of adjustable multilayer capacitors comprises a perovskite, tungsten bronze, layered structure material, or a combination thereof as the dielectric material. 25. A circuit comprising an adjustable multilayer capacitor array as claimed in claim 15 and a power supply providing a DC bias voltage to the capacitors via a first DC bias terminal and a second DC bias terminal. 26. An adjustable multilayer capacitor, comprising: The first active electrode that is in electrical contact with the first active terminal; The second active electrode is in electrical contact with the second active terminal; The first DC bias electrode is in electrical contact with the first DC bias terminal; The second DC bias electrode is in electrical contact with the second DC bias terminal; and Multiple dielectric layers are disposed between the first active electrode and the second active electrode and between the first bias electrode and the second bias electrode. At least a portion of the dielectric layer comprises a tunable dielectric material that exhibits a variable dielectric constant when an applied DC voltage is applied across the first DC bias electrode and the second DC bias electrode. Furthermore, the adjustable multilayer capacitor described herein has an initial capacitance greater than approximately 0.1 microfarads at an operating voltage greater than approximately 10 volts. 27. The capacitor of claim 26, wherein the applied DC voltage is greater than about 100 volts. 28. The capacitor of claim 26, wherein the non-adjustable portion of the plurality of dielectric layers does not exhibit variable capacitance when an applied DC voltage is applied across the first DC bias electrode and the second DC bias electrode. 29. The capacitor of claim 26, wherein the non-adjustable portion of the plurality of dielectric layers does not include any bias electrodes. 30. The capacitor of claim 26, wherein the non-adjustable portion of the plurality of dielectric layers includes a bias electrode not connected to any bias terminal. 31. An adjustable multilayer capacitor array comprising a plurality of adjustable multilayer capacitors connected in parallel, wherein the adjustable multilayer capacitor array has a horizontally stacked configuration, wherein the thickness of each of the plurality of adjustable multilayer capacitors extends in the length direction of the adjustable multilayer capacitor array, and wherein the adjustable multilayer capacitors are configured to have adjustable capacitance by applying a DC bias voltage to the adjustable multilayer capacitor array. 32. The adjustable multilayer capacitor array of claim 31, further comprising: At least one non-adjustable multilayer capacitor is connected in parallel with the plurality of adjustable multilayer capacitors. 33. The adjustable multilayer capacitor array of claim 31, wherein each of the plurality of adjustable multilayer capacitors comprises: The first active electrode that is in electrical contact with the first active terminal; The second active electrode is in electrical contact with the second active terminal; The first DC bias electrode is in electrical contact with the first DC bias terminal; The second DC bias electrode is in electrical contact with the second DC bias terminal; and Multiple dielectric layers are disposed between the first active electrode and the second active electrode and between the first bias electrode and the second bias electrode. At least a portion of the dielectric layer comprises an tunable dielectric material that exhibits a variable dielectric constant when the applied DC voltage is applied across the first DC bias electrode and the second DC bias electrode. 34. The adjustable multilayer capacitor array as described in claim 33, wherein: The first DC bias electrode of each of the plurality of adjustable multilayer capacitors is disposed along the bottom surface of the adjustable multilayer capacitor array; and The second DC bias electrode of each of the plurality of adjustable multilayer capacitors is disposed along the top surface of the adjustable multilayer capacitor array. 35. The adjustable multilayer capacitor array as described in claim 33, wherein: The first DC bias electrode of each of the plurality of adjustable multilayer capacitors is disposed along the bottom surface of the adjustable multilayer capacitor array; and The second DC bias electrode of each of the plurality of adjustable multilayer capacitors is disposed along the bottom surface of the adjustable multilayer capacitor array.