HK40048128B - Method and system for integrated circuit (ic) layout migration integrated with layout expertise - Google Patents

Description

Methods and systems for integrated circuit (IC) layout migration that integrate professional layout design experience.

[Technical Field]

This invention relates to computer-aided design (CAD), and more particularly to a layout process migration tool.

[Background Technology]

A schematic diagram of a circuit or a larger system can be transformed into a physical device by creating a layout of the physical device defined by that schematic diagram. This layout includes rectangles and other shapes that define transparent and opaque areas on a photomask. The photomask is used to transfer the layout onto a substrate to be fabricated into the physical device. During semiconductor device fabrication, multiple photomasks are created for the multiple layers that need to be added and etched.

In the past, layouts were hand-drawn by layout engineers or technicians on computer-aided design (CAD) terminals. To reduce layout time, standard cells or macros were first drawn manually, and then placement and routing software was used to place them in the appropriate positions and interconnect them. Hand-drawn cells were copied multiple times. Standard layout stream formats such as GDSII (Graphics Design System 2, originally created by Calma) allow for layered layouts in binary stream formats.

Sometimes, hand-drawn cells of different sizes are required. Parametric cells or P-cells are designed where the size of the hand-drawn cells can be scaled using parameters such as transistor channel width W or length L.

This standard cell layout is very useful for digital circuits with large tolerances. However, analog circuits have very tight tolerances, often requiring layout engineers to hand-draw cells and possess specialized knowledge. P-cells are sometimes also used in analog designs to allow for analog transistors with different w/l ratios.

Each semiconductor manufacturing process has a set of design rules. These design rules specify limitations on the layout. These limitations can include minimum widths of layers such as metals, polysilicon gates, contacts, and vias, as well as minimum spacing between adjacent lines within a layer and between different layers. Because the cost of integrated circuits (ICs) is proportional to their size, layout engineers tend to use minimum spacing to produce the smallest possible cell layout.

As semiconductor manufacturing technology advances, the minimum width and spacing in design rules tend to decrease or shrink for newer processes. This reduction in size and migration to more advanced, smaller-functional-size processes lowers the manufacturing cost per device. Therefore, layouts created using design rules from older processes are sometimes adapted to accommodate a new set of design rules for newer processes.

The original layout can be scaled down or down to a smaller size for use in newer processes. However, uniformly scaling all polygons in the layout by a fixed factor (e.g., 0.8, or a 20% reduction) may violate certain design rules in the new process. These violations occur because the design rules are not uniformly scaled. For example, the length and width of a polysilicon gate can be scaled by 0.8, but the width and spacing of metal lines can only be scaled by 0.9, resulting in a violation of metal design rules when the original design is uniformly scaled down by a factor of 0.8.

In layout migration scenarios, specialized knowledge from layout engineers is typically required. For smaller processes, design rules tend to become increasingly numerous and complex, demanding greater skills, expertise, and effort from layout engineers. During layout migration processes, cell layouts or original design plans often require extensive manual adjustments by layout engineers before they can be reused.

Automated layout migration software may require the use of P-cells or the introduction of constraints that take into account both the original and new design rules. These constraints are defined as a specific set of target design rules. The goal is to migrate layouts to several sets of target design rules for several semiconductor processes. Having multiple target processes allows circuits to be sourced from alternative suppliers (second-sourced) or manufactured by multiple foundries, reducing costs by introducing price competition among these foundries.

The desired goals are: to migrate layouts across multiple processes with multiple sets of design rules; to provide a reusable layout that automatically adapts to different design rules; to enable one-to-many layout migrations; to provide a software toolkit that allows layout engineers to add their expertise to create reusable layouts; and to enable layout migrations from standard hierarchical layout databases such as GDSII, without P-cells and constraints.

[Attached Image Description]

Figure 1 is a flowchart of a one-to-many layout migration using a reusable layout database (integrated with the expertise of layout engineers).

Figure 2 shows the GDSII layout resolver in more detail.

Figure 3 is an example of a text entry in a layout database file created by the layout parser.

Figure 4 is a schematic diagram of the simulated layout design toolkit.

Figures 5A-5B show layout engineers modifying lines of text in a layout database file to generate a reusable layout database.

Figures 6A-6C show the placement of the unit in the reusable layout database.

Figure 7 shows the wiring in the reusable layout database.

Figures 8A-8C show the layout migration from a reusable layout database to two target layouts with two sets of target design rules.

Figures 9A-9C show how the simulated layout generator uses placement functionality embedded by layout engineers into a reusable layout database to create cell layouts.

Figures 10A-10D show the simulation layout generator using routing functionality embedded by layout engineers into a reusable layout database to create cell layouts.

Figure 11 shows a portion of the reusable code that generates the 3-input NAND layout of Figure 10D.

Figure 12 shows how to control IC manufacturing by writing to a photomask after generating a target layout file from a reusable layout database using a simulated layout generator.

【Detailed Implementation Methods】

This invention relates to improvements in layout migration tools. The following description is intended to enable those skilled in the art to make and use the invention in the context of specific applications and their requirements. Various modifications to the preferred embodiments will be apparent to those skilled in the art, and the general principles defined in the invention can be applied to other embodiments. Therefore, the invention is not limited to the specific embodiments shown and described, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Figure 1 is a flowchart of a one-to-many layout migration using a reusable layout database (integrating layout engineer expertise). The existing layout is defined in the binary GDSII format commonly used in semiconductor process chip manufacturing plants. The existing layout design GDSII file 502 flows in and is converted and parsed by the layout parser 504. The layout parser 504 reads a locally converted copy of the binary stream GDSII file 502 and extracts polygons on different layers to create text entries specifying these polygons in a text-based format in the layout database file 506. The layout parser 504 preserves the hierarchy specified in the GDSII file 502 when generating the layout database file 506. Therefore, reusable standard cells only need to be specified once in the GDSII file 502 and the layout database file 506.

The simulation layout design toolkit 510 allows layout engineers to obtain the x and y positions of these polygons in the layout database file 506. The layout engineer can then write code to better specify the devices formed by these polygons and better allow migration to different design rule sets. The layout engineer uses the keyboard or other input 512 to override text lines in the layout database file 506, using reusable code describing these polygons to specify them.

The simulated layout expertise integrator 508 uses reusable code from input 512 to replace or overwrite text entries in the layout database file 506 to integrate the expertise of layout engineers. The simulated layout expertise integrator 508 uses the reusable code input by layout engineers to modify the layout database file 506 to form a reusable layout database 514.

The reusable layout database 514 contains reusable code from input 512 and the remaining text entries from layout database file 506. Reusable code, derived from the expertise of layout engineers, activates functionality in the analog layout generator 516 or device generator 518. Engineers can use design toolkit 510 to customize their own P-cells of any geometry. Such customized P-cells can be single devices, such as test keys, or embedded in circuitry, generating device layouts specified by the reusable code.

During layout compilation, the simulation layout generator 516 combines the device layout created by the device generator 518 with polygons specified by text entries in the reusable layout database 514, which are initially located in the layout database file 506. Then, using design rules 520 for multiple semiconductor processes, the compiled layout is converted to target processes 1, 2, 3, ..., N. The simulation layout generator 516 then outputs multiple converted layouts as target layouts 1, 2, 3, ..., N. These target layouts are converted from text format to GDSII binary format to generate target layout GDSII files 522.

Figure 2 shows the GDSII layout resolver in more detail. The layout resolver 504 receives a GDSII file 502 (Figure 1), which specifies the original layout using the original design rules. The binary stream is parsed by the GDSII resolver 120 into identifiers of records in GDSII format. These record type identifiers describe four types of GDSII data items. The SREF resolver 102 searches for SREF record type identifiers for references to standard cells or other cells in the layered layout. These SREF identifiers specify the x, y positions of cells in other locations. SREF can also mirror or rotate cells.

Boundary resolver 104 searches for records of polygon boundaries. Boundary (B) record type has a list of x, y coordinates of the vertices of the closed polygon. These polygons may have a specified processing layer.

Path parser 106 searches for path data items in a copy of the streaming GDSII file 502. The path record type is suitable for a single line or a series of line segments whose width can be extended. Paths are particularly useful for forming metal interconnects.

The text parser 108 searches for records of text data items. Text is typically added to the layout to mark transistors, logic gates, cells, and metal lines. Text helps layout engineers understand the layout and its correspondence with the schematic. The text is removed before the photomask is created in the manufacturing process so that it does not appear on the final physical device.

Multiple polygons or other structures can be combined to form a container structure or unit using the Start Structure (BEGSTR) and End Structure (ENDSTR) GDSII record types. The name of this structure or unit can be defined within the container structure using the Structure Name (STRNAME) record type.

The layout data integrator 110 rearranges the records parsed by the SREF parser 102, boundary parser 104, path parser 106, and text parser 108 to reflect the hierarchy of the structure or unit. The layout data integrator 110 creates a text line for each data item found by the GDSII parser 120. These text lines are output by the layout parser 504 as a layout database file 506 (Figure 1).

Figure 3 is an example of a text entry in a layout database file created by the layout parser. The second line is an example of a text data item from the GDSII file 502 when the text parser 108 locates a text record and the layout parser 504 creates the layout database file 506.

The path is a line that begins with "P", such as lines 3, 4 and 9-15. These path lines have the x and y coordinates of the two path endpoints, as well as path properties such as width (180) and layer such as second metal (102,1).

Boundaries are lines that begin with "B", such as lines 5-7 and 16-18. In this example, each boundary has 5 x, y coordinates, and for a closed rectangular polygon, the first and last coordinates are the same. Boundaries may have more than 5 points.

The SREF parser 102 (Figure 2) identifies instance references for standard cells or other blocks. These instance references are converted into text lines starting with "I" in the layout database file 506, such as lines 19-25. Each instance line has an x, y coordinate, at which the cell instance is placed and the cell's name is invoked.

Figure 4 is a schematic diagram of the Simulated Layout Design Toolkit. The Simulated Layout Design Toolkit 510 allows layout engineers to integrate their expertise into a reusable layout database 514 (Figure 1). Layout engineers use the functions in the Simulated Layout Design Toolkit 510 to rewrite lines of text in the layout database file 506 to include reusable code that facilitates the migration of the reusable layout database 514 to multiple processes with different sets of design rules.

The simulation layout design toolkit 510 includes a location function 130, a placement function 132, and a routing function 134. Layout engineers can use the location function 130 to find the positions or x, y coordinate positions of devices and polygons on various layers. Original design rules are used to build a reusable layout database and replicate existing layouts. The target design rules are then used to generate new GDSII structures through the reusable database. The location function 130 can use a system algorithm to describe the relative positions between elements, such as top, bottom, left, and right. With such definitions, detailed evaluation can be performed when engineers specify element numbers in the reusable database, as explained later in Figure 5B. Elements can be any polygon, device, or instance defined by the engineer. For example, I3[T, (CommonSD, I1, r)] specifies that element I3 will be located to the right of element I1. Here, the right side is defined by the location function "r". I1 and I3 are specified as instances of MOSFET cells.

Layout engineers use placement function 132 to place elements and polygons at locations within the reusable layout database 514. These locations can be specified as absolute x, y coordinates or as relative positions to other elements or polygons. Relative positions can be specified as a function of a design rule, such as 1.5 times the minimum spacing design rule, where the value of the design rule has not yet been specified. Placement function 132 can also include symmetrical placement functions, such as placing polygons along a common line or arranging elements in one or two dimensions.

Routing function 134 connects cells using two or more layers of interconnect metal, vias, and contacts. The path data item in GDSII file 502 is typically used to specify interconnects. After adjusting the placement of transistors and cells for different design rules, interconnects can be rerouted between path endpoints. Layout engineers can specify various routing methods, such as direct routing, maze routing, star-search routing, routing using reinforcement learning algorithms, or routing using artificial intelligence (AI). Layout engineers can recognize that using a certain routing method instead of others can better route certain paths, and can use routing function 134 to specify the optimal routing method for a path based on the engineer's past experience and expertise.

Using the Simulated Layout Design Toolkit 510, layout engineers can integrate their expertise into the reusable layout database 514, thereby allowing the reusable layout database 514 to be reused for multiple target layouts with different sets of target design rules.

Figures 5A-5B show layout engineers modifying text lines in a layout database file to generate a reusable layout database. In Figure 5A, a portion of the layout database file 506 (Figure 1) shows six instance lines. The first, third, and fourth lines each call for an instance p25, which can be a complementary metal-oxide-semiconductor (CMOS) p-channel transistor (PMOS) with a maximum signal voltage limit of 2.5 volts. The second, fifth, and sixth lines call for an instance n25, which can be an n-channel transistor (NMOS) with a maximum voltage of 2.5 volts. Layout engineers can specify the channel width of these p25 and n25 transistors using other attributes.

Each row also provides the x and y coordinates for each instance. All p25 devices are at Y = 6290, while all n25 devices are at Y = 290. The first pair of p and n devices is at X = 335, the second pair at X = 875, and the third pair at X = 1415. Therefore, these six transistors are arranged such that the PMOS devices are above the NMOS devices, with a center-to-center spacing of 6000 units, and adjacent transistors on the left and right are 540 units apart center-to-center.

Layout engineers can view lines 506 in the layout database file, as shown in Figure 5A. These six lines in Figure 5A require six independent transistors: three PMOS and three NMOS transistors.

Engineers may recognize that adjacent transistors can share their source/drain regions instead of having separate sources/drains. Engineers can use placement function 132 to rewrite line 3 using the CommonSD common source/drain placement function. This is a relative placement function that allows transistors to be placed very close to adjacent transistors, thus sharing their source/drain regions and contacts. Line 3 in layout database file 506:

I[(875,6290)][p25,0,0]

The rows replaced with the rewritten portion of the reusable layout database 514 (using the CommonSD function to specify instance I3):

I3[T,(CommonSD,I1,r)][p25,0,0]

Remove the absolute coordinates (875, 6290) from the layout database file 506 and replace them with the relative placement function CommonSD, which has no x and y coordinates, specifying that the source/drain is shared with instance I1.

Similarly, delete the absolute coordinates of transistor p25 in line 4 and transistor n25 in lines 5 and 6, replacing them with the CommonSD function. Instances I4 and I3 share source/drain, instances I5 and I2 share source/drain, and instances I6 and I5 share source/drain. The parameter r indicates that the right-hand source/drain is shared, not the left-hand source/drain.

Layout engineers can manually edit layout database file 506 and type in CommonSD functions and their parameters to generate a reusable layout database 514. The simulation layout design toolkit 510 can define functions, parameters, and syntax, allowing layout engineers to perform actions such as selecting placement functions 132, such as CommonSD, to define the relative placement of other n25 and p25 transistor cell instances.

Figures 6A-6C show the placement of cells in the reusable layout database. In Figure 6A, block 170 is placed at an absolute x, y position in the planar view of the layout. Block 170 can be a cell with multiple polygons on multiple layers, a single polygon, or a parameterized cell. The center (0, 0) of block 170 is placed at an absolute x, y position using the absolute placement function, as shown in the first two rows of Figure 5B.

In Figure 6B, a series of three blocks 170, 171, and 172 are placed horizontally in sequence. The first block 170 is placed at absolute positions X0 and Y0 using the absolute placement function. However, blocks 171 and 172 are placed relative to the first block 170, not at absolute positions. The distance between the center of block 171 and the center of the first block 170 is S1, and the distance between the center of block 172 and the center of the second block 171 is S2. Therefore, the first block 170 is located at X0 and Y0, the second block 171 is located at X1 and Y0, where X1 = X0 + S1, and the third block 172 is located at X2 and Y0, where X2 = X1 + S2.

The spacing values S1 and S2 can be functions of a design rule, allowing the spacing to be adjusted for different design rules. For example, when blocks 170, 171, and 172 are all minimum-width metal lines with minimum spacing, S1 and S2 can be the minimum spacing of the target design rule. When blocks 170, 171, and 172 are more complex cells, S1 can be the cell width plus the minimum spacing between cells, which can be set through metal spacing design rules. Alternatively, layout engineers can use larger spacing between cells to achieve more interconnects and easier routing.

In Figure 6C, the cells are aligned along the vertical axis. The centers of blocks 171 and 173 are aligned so that their centers have the same X coordinate, X3 = X1. Since the width L of block 173 is greater than the width of block 171, the bottom corner of block 173 can be calculated as X3L = X1 - L2 and X3R = X1 + L2.

The centers of blocks 171 and 173 are spaced apart by a distance S3 in the vertical direction, such that when block 171 is centered at X1, Y1, then block 173 is centered at X1, Y1-S3. Similarly, the spacing S3 can be a function of the target design rule plus an additional amount added by the layout engineer, for example, for better routing or for circuit performance, such as for latch-up resistors. The value of the design rule is reserved as a parameter rather than specified as a numerical value, thus allowing the selection of a design rule from a variety of target design rule sets. This allows the cell placement in the reusable layout database 514 to be reused for multiple processes.

The Simulated Layout Design Toolkit 510 includes the CommonCentre function in placement function 132. This CommonCentre function places one block (such as block 173) at a relative position to another block along its common center. Spacing S3 can be specified in the function call, such as the minimum spacing allowed by design rules. Similarly, the CommonCentre function can also be specified for horizontal (Figure 6B) or vertical (Figure 6C) alignment and symmetry.

Figure 7 shows the routing in the reusable layout database. Blocks 171-176 are six cells arranged in two rows, three in each row. The internal structure of the cells may differ, and one row may be a mirror image of the other.

The cell connections are established through connection points on the cell boundaries. In this example, connection points are defined for both the first and second metal layers. For example, block 171 has connection points X1L, Y1D and X1R, Y1D on its lower boundary. Block 174 has connection points X4L, Y4U and X4R, Y4U on its upper boundary.

Connections between blocks 171 and 174 can be defined using routing function 134 or via path data items in layout database file 506. The routing routine implements the connection using layer-1 metal 182 by creating a rectangle between connection points X1L, Y1D and X1R, Y1D in block 171, and connection points X4L, Y4U and X4R, Y4U in block 174. In this example, X1L = X4L, X1R = X4R.

The reusable layout database 514 also includes a line call to the Z-shaped routing function in routing function 134. The routing function generates a Z-shaped polygon using layer-2 metal 184 to achieve the connection by creating a layer-2 metal polygon between the connection points X3L, Y3D and X3R, Y3D of block 173 and the connection points X5L, Y5U and X5R, Y5U of block 175.

Figures 8A-8C illustrate the layout migration of two target layouts from a reusable layout database to two sets of target design rules. In Figure 8A, an original layout 190 is created using the original design rules and converted into a reusable layout database 514, specifying that block 177 is positioned below the center of the space between blocks 171 and 172. Blocks 171 and 172 are horizontally spaced with a spacing of SH between their edges, while block 177 is located below blocks 171 and 172 with a spacing of SV between its edges.

Once the expertise of layout engineers has been integrated into the reusable layout database 514 using the simulated layout design toolkit 510, the reusable layout database 514 can be used to convert the original layout 190 into two target layouts 192 and 194, which use design rules DR1 and DR2.

In Figure 8B, the simulated layout generator 516 (Figure 1) transforms the reusable layout database 514 used for the original layout 190 into a first target layout 192 using the first design rule DR1. The simulated layout generator 516, or an engineer, can compare the original design rule with the first design rule to obtain the horizontal and vertical scaling factors SF_H and SF_V, as well as the block scaling factor BSF. The block scaling factor BSF can be limited by the design rule that has the minimum shrinkage between the two sets of design rules used for multiple polygonal layers in a typical cell. The spacing scaling factor may depend on the ratio of the metal layer design rules that determine the spacing between blocks.

The block scaling factor (BSF) is used to scale the size of blocks or cells. For the first target layout 192, the BSF is 1.0, so the sizes of blocks 171, 172, and 177 are not reduced. However, the spacing scaling factors (SF_H and SF_V) are both 0.5, so when the original layout 190 is migrated to the first target layout 192, the spacing between cells is reduced by 50%. Although the block size is not reduced, the reduced block spacing allows the first target layout 192 to be slightly smaller than the original layout 190.

The reusable layout database 514 can also be converted into a second target layout using the second design rule DR2. The second design rule DR2 is better than the first design rule DR1 because the block scaling factor BSF is 0.5, and the vertical scaling factor SF_V is even further reduced to 0.25, although the horizontal scaling factor SF_H remains at 0.5 for both design rules DR1 and DR2.

For the second target layout 194, the BSF is 0.5, so before placement, blocks 171, 172, and 177 are scaled down by 50% in both the horizontal and vertical directions. The spacing scaling factor SF_H is 0.5, so the horizontal spacing between the edges of the scaled-down blocks 171 and 172 is reduced to SH*SF_V, where SH is the original horizontal spacing from the original layout 190.

The vertical spacing SF_V was further reduced to 0.25, thus reducing the vertical spacing between blocks 171 and 177 by 75%. The sizes of blocks 171, 172, and 177 were reduced, and the spacing between blocks was also reduced, resulting in the second target layout 194 being significantly smaller than the original layout 190.

Figures 9A-9C show the analog layout generator using placement functionality embedded by the layout engineer into the reusable layout database to create cell layouts. When processing the code in Figure 5B within the reusable layout database 514, the second line calls the analog layout generator 516 to generate an instance of the n25 cell, which is an NMOS transistor:

I2[(335,290)][n25,0,0]

This row enables the analog layout generator 516 to generate an n-channel transistor by creating a polysilicon layer rectangular gate 30, a diffusion rectangle including source/drain regions 20, 22, source contact 10, and drain contact 12. The intersection of the polysilicon and the diffusion rectangle forms the active gate region of the transistor. The center of the transistor is located at absolute positions 335, 290. This first transistor is shown in Figure 9A.

The fifth line of reusable code,

I5[T,(CommonSD,I2,r)][n25,0,0]

The requirement is to generate another n25 cell, but the absolute x and y positions are not given. Instead, the CommonSD function is called using I2 and r as function call arguments. This function causes the analog layout generator 516 to generate a new transistor whose source/drain regions are shared with the right-hand source/drain regions of the transistor created by instance I2.

In Figure 9B, the gate 30 of the I2 transistor still has the source contact 10 in the source/drain region 20, but the drain contact 12 and the source/drain region 20 are shared with the gate 32 of the I5 transistor. The analog layout generator 516 also generates the shared contact 14 and the source/drain region 24 to the right side of the gate 32 of the I5 transistor. The diffusion rectangle has been extended to the right to include the gate 32 of the I5 transistor and the source/drain region 24.

Next, the simulated layout generator 516 processes the reusable code in line six:

I6[T,(CommonSD,I5,r)][n25,0,0]

It requests the generation of a third n25 cell, without specifying the absolute x and y positions. Instead, it calls the CommonSD function using I5 and r as function call arguments. This function causes the analog layout generator 516 to generate a new transistor whose source/drain regions are shared with the right-side source/drain regions of the transistor created by instance I5.

In Figure 9B, the contact 14 and source/drain region 24, which were shared with the right side of the gate 32 of transistor I5, are now shared with the gate 34 of transistor I6. Analog layout generator 516 generates contact 16 and source/drain region 26 to the right side of the gate 34 of transistor I6. The diffusion rectangle extends again to the right to include the gate 36 of transistor I6 and the source/drain region 26.

For the other rows in Figure 5B, PMOS transistors can be generated in a similar manner to that described in Figures 9A-9B:

I1[(335,6290)][p25,0,0]

I3[T,(CommonSD,I1,r)][p25,0,0]

I4[T,(CommonSD,I3,r)][p25,0,0]

In Figure 9C, the analog layout generator 516 extends the gate 30 upwards to add metal contacts 40 at sufficient intervals to meet target design rules. This interval distance is parameterized by the design rules. A first layer of metal 50 is added over the metal contacts 40 and extends vertically over the cells.

Similarly, the analog layout generator 516 extends the polysilicon gates 32, 34 upwards and adds metal contacts 42, 44 and a first layer of metal 52, 54.

Since source/drain regions 22 and 24 are shared with both transistors, the overall size of the three transistors in examples I2, I5, and I6 is reduced compared to individual transistors (each with its own unshared source/drain regions). Using the CommonSD functions of the analog layout design toolkit 510, the expertise that layout engineers believe can be used to share source/drain regions for these transistors is added to the reusable layout database 514. Layout migration to multiple target processes is improved.

Figures 10A-10D show the analog layout generator using routing functions embedded by layout engineers into a reusable layout database to create cell layouts. In Figure 10A, transistor gates 30, 32, and 34 share source/drain regions 22 and 24 and metal contacts 40, 42, and 44, shown at the bottom. These are the I2, I5, and I6 NMOS transistors shown in Figure 9C.

The top shows transistor gates 31, 33, and 35, with shared source/drain regions 23 and 25, non-shared source/drain regions 21 and 27 at both ends, and contacts 11, 13, 15, and 17. These can be code segments generated for instances I1, I3, and I4, as shown in the reusable layout database 514 in Figure 5B.

Metal contacts 41, 43, and 45 are also created to connect to the polysilicon gates 31, 33, and 35. These metal contacts 41, 43, and 45 are created at the bottom of the PMOS transistor gates 31, 33, and 35, rather than at the top as in the NMOS transistor gates 30, 32, and 34.

These metal contacts can be created using the CommonCenter function in placement function 132. The CommonCenter function aligns the metal contact 43 with its polysilicon gate. For example, line 13 of the code segment in the reusable layout database 514 shown later in Figure 11:

13I11[T,(CommonCentre,I3,d)][M1_PO,0]

The simulation layout generator 516 generates a metal-1 to polysilicon contact (M1_PO) at the bottom of instance I3 (I3, d) and shares a common center with I3.

Since instances I1 and I2 have the same absolute X coordinate, the PMOS gate 31 is aligned with the NMOS gate 30.

In Figure 10B, the layout engineer has used a routing function 134 to generate the interconnect. The rectangular routing function is used to generate a simple rectangle to connect I1 and I2 using the first layer of metal (101). This is shown in row 20 of Figure 11, where boundary B6 is listed:

20B6[T,(Rect,I1.PO_Down._l,I1.PO_Down._r,I1.PO_Down._d,I2.PO_Up._u)][101,1]

This reusable line of code generates the first layer of metal 60, connecting metal contacts 40 and 41 to transistor gates 30 and 31. The first two points in the `rect` function are relative to the lower left (`I1.PO_Down_l`) and lower right (`I1.PO_Down_r`) of the I2 polysilicon. The other two points in the `rect` function, `I1.PO_Down._d` and `I2.PO_Up._u`, are the upper and lower edges of metal 60. `I1.PO_Down._d` is the lower edge of PO contact 41, and `I2.PO_Up._u` is the upper edge of PO contact 40.

Similarly, other lines of reusable code are generated using the rect wiring function to connect metal contacts 42, 43 to the first layer of metal 62 of transistor gates 32, 33, and to connect metal contacts 44, 45 to the first layer of metal 64 of transistor gates 34, 35.

In Figure 10C, additional rect wiring function 134 is used to generate VDD metal 66 and VSS metal 68 on the first metal layer. VDD metal 66 is connected to contacts 11 and 15 in source/drain regions 21 and 25, which serve as PMOS sources connected to power supplies. VSS metal 68 is connected to contact 16 in source/drain region 26, which serves as a grounded NMOS source.

In Figure 10D, the second metal layer 70 is generated by the analog layout generator 516. The second metal layer 70 is connected to the cell output (not shown) and to contact 10 in the source-drain region 20, to contact 13 in the source/drain region 23, and to contact 17 in the source/drain region 27, forming a 3-input NAND gate.

The second layer of metal 70 is generated by the simulation layout generator 516 processing line 23 in the reusable code section of the reusable layout database 514 shown in Figure 11. This line uses the Z-routing function to generate Z-shaped metal lines using the second metal (parameter 102).

23P1[T,(Zshape,I4.AA_Right._r+90,I4.AA_Right._u,I2.AA_Left._l-90,I2.AA_Left._d,4000,180)][102,1]

This line of reusable code defines a Z-shaped polygonal second metal (102,1) with a center of Y = 4000 and a width of 180nm. The right edge extends 90nm beyond the non-shared source/drain region 27 (I4.AA_Right._r+90). The left edge extends 90nm beyond the non-shared source/drain region 20 (I2.AA_Left._l-90). The upper edge is the non-shared source/drain region 27 (I4.AA_Right._u), and the lower edge is the non-shared source/drain region 20 (I2.AA_Left._d).

Figure 11 shows a portion of the reusable code that generates the 3-input NAND layout of Figure 10D. The portion of the reusable code in Figure 11 is part of the reusable layout database 514, where lines 5-23 were written by the layout engineer, and lines 1 and 2 were almost unchanged except for the addition of instance names (I1, I2) for further reference.

Lines 5-8 use the CommonSD placement function to generate transistors with shared source/drain regions. Lines 4, 7, and 8 generate NMOS transistor gates 30, 32, and 34, as well as contacts and source/drain terminals, as shown in Figure 9B. The metal contacts 40, 42, and 44 shown in Figure 9C are added using the CommonCenter placement function by adding metal 1-to-polysilicon contacts (M1_PO) in lines 9-11, while the metal contacts 41, 43, and 45 shown in Figure 10A are added using the CommonCenter placement function in lines 12-14.

The complex shape VDD metal 66 was generated by using the rectangle routing function in lines 15, 17, and 18, resulting in 3 rectangles. VSS metal 68 was generated by using the rectangle routing function in lines 16 and 19, resulting in 2 rectangles.

The first layer of metals 60, 62, and 64 are generated using the rectangular routing function in rows 20, 21, and 22, respectively. Finally, the second layer of metal 70 is generated using the Z-shaped routing function in row 23 of Figure 11.

Figure 12 illustrates the use of a simulated layout generator to generate a target layout file from a reusable layout database, controlling IC manufacturing by writing to a photomask. The simulated layout generator 516 generates a target layout file 522 from a reusable layout database 514 by processing reusable commands from a simulated layout design toolkit 510. These reusable commands are inserted into the reusable layout database 514 by layout engineers. The target layout file 522 is in GDSII format, or is converted to GDSII format, for use by photomask manufacturers in the physical layout 76.

Physical layout 76 specifies the physical x and y positions on each die, where various components will be located on the finished integrated circuit (IC) die. Physical layout 76 is converted into multiple patterning layers, which specify the locations of gates, metal lines, vias, connections between layers, and oxide and diffusion regions on the substrate. Mask image 78 typically includes an image for each patterned layer.

A mask manufacturing machine reads a mask image 78 or another design file and then physically writes or burns these images onto a photomask 82. The photomask 82 is a tangible product, a result of layout migration software or routines generating a target layout file 522, which is ultimately converted by software into a mask image 78 of the actual transistor gates and wiring. While layout migration software can be executed on a general-purpose computer, creating the photomask 82 requires specialized equipment, such as a light or electron beam, to write layout data onto individual masks. This light or electron beam is turned on and off via the layout data while simultaneously scanning an unexposed photoresist polymer layer in a rasterized pattern on a blank photomask glass plate. The photoresist is exposed in some locations by the light or electron beam, while remaining unexposed in others. The exposure plate can then be washed in a chemical developer bath to remove the exposed or unexposed areas, thus forming the photomask 82.

During photomask fabrication 80, a photomask machine produces multiple photomasks 82, each used for each semiconductor process layer. The photomasks 82 are then sent to a semiconductor fab (wafer fab or chip factory) and loaded into a photomask machine for IC manufacturing process 84, where light from the photomasks 82 exposes the photoresist resin on the semiconductor wafer. After multilayer exposure processes via the photomasks 82, as well as other processes (e.g., ion implantation, diffusion, oxide growth, polysilicon and metal deposition, via and contact etching, and metal and polysilicon etching), IC manufacturing process 84 produces a wafer 86. Wafer 86 is a silicon, GaAs, or other semiconductor substrate with patterned layers formed on its surface. Multiple chips are produced on each wafer 86. After initial wafer sorting and testing, wafer 86 is diced into smaller pieces and packaged to produce ICs 88.

Therefore, the target layout file 522 generated from the reusable layout database 514 controls a series of steps in the manufacturing process, ultimately resulting in the photomask 82 and the IC 88. Highly specialized machines and the computers that control these machines are ultimately controlled or guided by the data in the target layout file 522 to produce the specific IC 88 chip.

IC 88 can be an ASIC or module assembled into an end-user device such as a smartphone 90. The smartphone 90 may include a camera 92, which captures images, which are then processed by IC 88. IC 88 can be manufactured by two or more chip manufacturers and implement existing designs, but using two different sets of design rules. Each design rule creates a different target layout file 522, which generates different sets of photomasks 82 for manufacturing IC 88 using a specific semiconductor process.

[Alternative Embodiments]

The inventors designed several other embodiments. For example, the absolute coordinates in the original layout can be adjusted or scaled. For instance, the absolute x and y positions in the original layout 190 (FIG. 8A) can be scaled by 0.5 to x/2 and y/2 to produce corresponding absolute positions in the first target layout 194 (FIG. 8B). The original plan view can be used, but it can be scaled according to new design rules. Path widths, contact via areas, etc., can be changed to generate scaled individual devices.

Layout engineers can manually edit the lowest-level units in the hierarchy to include parameters from design rules, such as spacing and width. Design rules can be stored in a separate file, which can be loaded by the simulation layout design toolkit 510. Layout engineers can directly change values in the design rule file. A graphical interface can also be developed for users to input such parameters. This change to the design rules causes the simulation layout generator 516 to automatically adjust the converted layout output by the simulation layout generator 516, because the reusable layout database 514 is relative to the parametric design rules. For example, if only the design rule for the contact via area is changed, all contacts in the target layout will be changed without altering the relative positions of the diffusion spacing.

Some design rules may include special rules, such as those for high-voltage transistors with increased size and spacing. Special layouts, such as donut-shaped or ring-shaped transistor gates, may be used. Guard rings or other structures may be added to cells marked for high voltage or other special purposes. Reusable code may include functionality to activate these special layouts and design rules for certain cells. Even on the same IC, transistors operating in analog circuitry may have different layout requirements than those used in digital circuitry.

As described, reusable code is input into the reusable layout database 514 by layout engineers and processed by both the simulation layout generator 516 and the device generator 518. The device generator 518 handles arrangement functions, while the simulation layout generator handles other functions. The division of functions can be adjusted so that either the device generator 518 or the simulation layout generator 516 can handle all functions from the simulation layout design toolkit 510. The device generator 518 and the simulation layout generator 516 can also be combined.

Although the syntax of the reusable code is shown in Figures 5B and 11, various modifications to the syntax and parameters can be made. The code shown is merely an example of one possible code syntax. Similarly, the layout parser 504 can create the layout database file 506 using a different syntax than that shown in Figure 3. Extensions can be supported for P-cells and other structures.

The layout engineer's overwrite of layout database file 506 does not need to be 1:1. A line in layout database file 506 can be replaced by the layout engineer using multiple lines of reusable code from reusable layout database 514, or multiple lines in layout database file 506 can be replaced by the layout engineer using a single line of reusable code from reusable layout database 514. Some lines may be 1:1, others may be 1:N or N:1, depending on the functionality and layout.

Compared to digital layout design, this invention is more beneficial for analog layout design. For digital circuit layout, layout engineers do not need to design modules themselves. Chip manufacturers provide a standard cell library as basic gate-level modules from which layouts can be built. Furthermore, since digital circuit performance is insensitive to placement and routing, mature CAD tools can perform automatic placement and routing. However, for analog circuit layout design, engineers typically do not have standard cells provided by chip manufacturers, thus requiring more effort from layout engineers than for digital layout design. Moreover, the performance of analog circuits is much more sensitive to the layout planarity than that of digital circuits, therefore analog layouts require significant designer expertise to handle unintended effects. These unintended effects include signal mismatch caused by asymmetry, larger parasitic capacitances, and resistances. Therefore, analog layout design can benefit more from this invention than digital layout design.

Layout engineers or other engineers or programmers can write search and replace routines or other macros to search for certain data items in the layout database file 506 and rewrite these data items using reusable code, instead of manually overwriting each data item with reusable code. For example, interconnections between cells can be searched in the layout database file 506 and replaced with a routing function in routing function 134, thereby allowing the simulated layout generator 516 to reroute the layout without using existing interconnections.

A graphical user interface can be developed to present the simulated layout design toolkit 510 to layout engineers, allowing them to select data items from the layout database file 506 and then paste reusable code to generate a reusable layout database 514. Existing layouts can be displayed graphically to layout engineers for reference, and engineers can be allowed to select the x and y coordinates of targets on the displayed layout to paste into the reusable code.

Other programs can be used for further processing, such as design rule checkers or schematic verification tools. These programs can flag errors for layout engineers to fix manually, or they can modify the layout database file to correct errors.

There may be multiple IC semiconductor manufacturing processes. A variety of specialized machines and processes can be used to fabricate the photomask 82, including direct writing to burn away the metallization layer instead of the photoresist. Multiple combinations of diffusion, oxide growth, etching, deposition, ion implantation, and other manufacturing steps can produce patterns on the IC controlled by the photomask 82.

Various combinations of software, hardware, firmware, routines, modules, functions, etc., can be used to implement the simulation layout generator 516, simulation layout design toolkit 510, device generator 518, and other components using various technologies. Modules, blocks, components, routines, subroutines, processes, functions, etc., may have multiple divisions and can be replaced. The syntax, functions, and files of reusable code may have multiple variations. Multiple file formats and variations can be used. Some embodiments may not use all components. Additional components can be added.

The layout parser can also parse a local copy of the GDSII file 502 for cell definitions or cell delimiters, which determine cell content. Cell definitions can include polygon boundaries, paths, text, and other cell instances. Layout engineers can use cell definitions to create custom P-cells. Instances can call P-cells provided by the chip manufacturer or custom P-cells. SREF is an inherent element of the GDSII stream format that describes the position of one structure relative to another.

Terms like up, down, left, right, above, below, etc., are relative and depend on the viewer's position or viewpoint. Planes, layouts, units, and data items can be rotated, flipped, mirrored, and otherwise transformed. Numerous variations are possible.

The background section of this invention may include background information about the problems or circumstances surrounding the invention, rather than a description of prior art by others. Therefore, the material included in the background section is not an admission of prior art by the applicant.

Any methods or processes described herein, whether machine-implemented or computer-implemented, are intended to be performed by machines, computers, or other devices, and not by humans alone without machine assistance. Tangible results may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio generating devices, and related media devices, and may include hard-copy printouts that are also machine-generated. Computer control of other machines is another tangible result.

Any advantages and benefits described may not apply to all embodiments of the invention. When the word "means" appears before a claim element, the applicant intends to bring that claim element to fall under the provisions of Section 112, Paragraph 6 of 35 USC. Typically, one or more words precede the word "means." The words preceding "means" are labels intended to facilitate reference to the claim element and are not intended to express structural limitations. Such device-plus-function claims are intended to cover not only the structures described herein for performing that function and their structural equivalents, but also the equivalent structures. For example, although nails and screws have different constructions, they both have equivalent structures because they both serve a fastening function. Signals are typically electronic signals, but can also be optical signals, for example, transmitted via fiber optic cables.

For illustrative and descriptive purposes, embodiments of the invention have been presented for the foregoing. This is not intended to be exhaustive or to limit the invention to the exact forms disclosed. Various modifications and variations are possible in light of the foregoing teachings. The scope of the invention is not limited to this detailed description but rather to the appended claims.

Claims (20)

1. A computer-implemented method for migrating an existing layout of an integrated circuit (IC) to a target layout of the IC, comprising: Receive an existing layout file, which specifies the existing layout; Parse the data items in the existing layout file, including polygon boundaries, paths, and cell instances, where a cell contains one or more boundaries, paths, or another cell instance; The data items are written to a layout database file in a text-based format; Display the data items in the text format to the layout engineer and receive updated reusable lines of code from the layout engineer; Replace some data items in the layout database file with the updated reusable code lines to generate a reusable layout database, wherein the reusable code specifies reusable data items; Compile the reusable layout database, and adjust the layout size and spacing of the reusable data items in the reusable layout database using the first set of target design rules to meet the first set of target design rules, so as to generate a first target layout file; Compile the reusable layout database, and use the second set of target design rules to adjust the layout size and spacing of the reusable data items in the reusable layout database to meet the second set of target design rules, so as to generate a second target layout file; Wherein, the second target layout specified in the second target layout file does not conform to the first set of target design rules, but conforms to the second set of target design rules; The reusable layout database is reused to generate the first target layout file and to generate the second target layout file. 2. The computer implementation method according to claim 1 further includes: The size and spacing of data items in the reusable layout database are scaled by a first scaling factor to generate scaled data items in the first target layout file; Wherein, the first scaling factor is a ratio of the first set of target design rules to the corresponding design rules in the existing design rules of the existing layout; The first scaling factor includes a block scaling factor for scaling units and an interval scaling factor for scaling the interval between units. 3. The computer implementation method according to claim 1, wherein the existing layout file is in binary format; The layout database file is in a text format that is readable and editable by layout engineers. 4. The computer implementation method according to claim 3 further includes: A layout engineer is provided with a layout design toolkit from which the layout engineer selects functionality, including functionality selected in the updated reusable code lines; wherein the reusable code includes functionality from the layout design toolkit. 5. The computer implementation method according to claim 4 further includes: The layout engineer receives functions selected from the reusable code, including placement and routing functions. The placement function specifies the position of the reusable data item relative to other data items, and the routing function specifies the routing method for generating metal interconnects to interconnect the cells. 6. The computer implementation method according to claim 3 further includes: A series of cells are generated from reusable code in the reusable layout database using a device generator. 7. The computer implementation method according to claim 3 further includes: Wherein, when the reusable code includes a CommonSD function, the layout generator generates a layout of a pair of transistors, the pair of transistors sharing source/drain regions between the pair of transistors specified in the first target layout file. 8. The computer implementation method according to claim 3, wherein the existing layout file is in Graphical Design System II (GDSII) format; further comprising: Convert the first target layout file to GDSII format. 9. The computer-implemented method according to claim 3, further comprising: The first target layout file is used to control the generation of photomasks for use by a first chip factory when manufacturing ICs using the first set of target design rules; The second target layout file is used to control the generation of photomasks for use by a second chip factory when manufacturing ICs using the second set of target design rules. 10. A map migration system, comprising: One input receives an existing layout file using a first set of design rules for the first layout of an integrated circuit IC of a first process. A layout parser is used to parse the existing layout file to identify data items, the data items including polygon boundaries, cell instances, and cell definitions, wherein the cell definitions include polygon boundaries and other cell instances; A layout data item integrator that generates a layout database file, the layout database file including the data items identified by the layout parser from the existing layout file; a layout design toolkit having a placement function that specifies the placement position of a data item relative to other data items, the placement position being a function of a set of design rules; Expert knowledge input is used to receive reusable code containing the placement functionality; A layout expertise integrator that puts the reusable code into the layout database file to generate a reusable layout database, wherein the reusable layout database has the reusable code and some data items from the layout database file, wherein other data items from the layout database file are replaced by the reusable code; A layout generator is used to compile the reusable layout database and convert the data items into a data item layout with dimensions and spacing conforming to a second set of design rules. It also compiles the reusable code and places the data items in a second relative position according to the placement function in the reusable code. The second relative position also conforms to the second set of design rules, so as to generate a second layout file using the second set of design rules, for the second layout of an IC of a second process. 11. The layout migration system of claim 10, wherein the layout generator further compiles the reusable layout database and converts the data items into data item layouts with dimensions and spacing conforming to a third set of design rules, and compiles the reusable code and places the data items in a third relative position according to the placement function in the reusable code, the third relative position also conforming to the third set of design rules, to generate a third layout file using the third set of design rules for the third layout of an IC of a third process. 12. The layout migration system according to claim 11, further comprising: A device generator that generates a series of cells based on reusable code containing arrangement functionality. The device generator sends the series of units to the layout generator for further processing. 13. The layout migration system according to claim 11, wherein the layout database file is in text format; The reusable layout database mentioned above is a text file; The reusable code is in text format and can be typed by a layout engineer and sent to the expertise input. 14. The layout migration system of claim 13, wherein the layout design toolkit further includes location functionality and routing functionality; The location function reports the x and y positions of the data items to the layout engineer; The routing function specifies the routing method used by the layout generator to generate the layout of interconnect metals in the second and third layout files, the interconnect metals being used to connect units. 15. The layout migration system according to claim 14, wherein the placement function further includes: The CommonSD function specifies a transistor cell that shares a common source/drain region with a referenced transistor cell referenced by the CommonSD function. The placement functionality also includes a common center function, which specifies that a data item shares a common center with a referenced data item referenced by the common center function; The wiring function also includes a rectangle function that generates a metal layer rectangle to interconnect two data items referenced by the rectangle function; The wiring function also includes a Z-shaped function that generates Z-shaped polygons in the metal layer to interconnect two data items referenced by the Z-shaped function. 16. The layout migration system according to claim 11, further comprising: A format converter for generating the second layout file in a binary stream format for use by a photomask manufacturer who uses the second process to manufacture photomasks for a semiconductor chip factory; The format converter is also used to generate the third layout file in a binary stream format for use by another photomask manufacturer, which uses the third process to manufacture photomasks for another semiconductor chip factory. The first layout of the IC is migrated to the second layout file for the semiconductor chip manufacturer to use the second process for manufacturing, and is also migrated to the third layout file for the other semiconductor chip manufacturer to use the third process for manufacturing. 17. A non-transitory computer-readable medium for storing computer-executable instructions that, when executed by a processor, implement a method comprising: It accepts an existing layout file that specifies an existing layout; Parse the data items in the existing layout file, the data items including polygon boundaries, paths and cell instances, where a cell contains one or more boundaries, paths or another cell instance; Write the data items into a layout database file; Receive updated reusable lines of code; Replace some data items in the layout database file with the updated reusable code lines to generate a reusable layout database, wherein the reusable code specifies reusable data items; Compile the reusable layout database, and adjust the layout size and spacing of the reusable data items in the reusable layout database using the first set of target design rules to satisfy the first set of target design rules, so as to generate a first target layout file; Compile the reusable layout database, and use the second set of target design rules to adjust the layout size and spacing of the reusable data items in the reusable layout database to meet the second set of target design rules, and generate a second target layout file; Wherein, the second layout specified in the second target layout file does not conform to the first set of target design rules, but conforms to the second set of target design rules; The reusable layout database is reused to generate the first target layout file and to generate the second target layout file. 18. The non-transitory computer-readable medium of claim 17, wherein the method further comprises: The size and spacing of data items in the reusable layout database are scaled by a first scaling factor to generate scaled data items in the first target layout file; Wherein, the first scaling factor is a ratio of the corresponding design rule in the first set of target design rules and the existing design rules of the existing layout; The first scaling factor includes a block scaling factor for scaling units and an interval scaling factor for scaling the interval between units. 19. The non-transitory computer-readable medium of claim 18, wherein the method further comprises: Provide layout engineers with a layout design toolkit from which they can select features, including selecting features in updated reusable lines of code. The map database file mentioned above is in a text-based format; The data items are written to the layout database file in the text-based format. Display data items to the layout engineer in the text format, and receive updated reusable lines of code from the layout engineer; The layout engineer receives function selections contained in the reusable code, including placement and routing functions. The placement function specifies the relative position of the reusable data item with respect to other data items, and the routing function specifies a routing method for generating metal interconnects to interconnect the cells. 20. The non-transitory computer-readable medium of claim 18, wherein the method further comprises: A series of cells are generated from reusable code in the reusable layout database using a device generator.