HK40013924B - Silicon-on-insulator with crystalline silicon oxide - Google Patents

Description

Silicon-on-insulator with crystalline silicon oxide

Background Technology

Silicon-on-insulator (SOI) structures can be used as substrates and building blocks for various types of semiconductor devices, such as MOSFETs and other types of transistors, as well as other types of microelectronic components and circuits, and silicon photonic components.

The quality of the SOI structure is crucial to the performance of devices formed on that substrate. In many applications, crystalline, high-quality SOI structures result in optimal device performance.

Traditionally, SOI layer structures have been fabricated via ion implantation, which involves bombarding an existing silicon surface with oxygen ions followed by annealing. This results in the formation of an amorphous silicon oxide layer within the silicon substrate. One drawback is that ion bombardment adversely affects the quality of the remaining silicon layer above the silicon oxide.

A method is disclosed in US 20060003500A1 in which an atomic layer of oxygen is first self-limitedly deposited on an existing silicon surface to form a molecular layer of crystalline silicon dioxide. A covering silicon layer can then be epitaxially formed on the silicon dioxide.

Summary of the Invention

The summary is provided to introduce, in a brief form, some conceptual choices further described in the detailed embodiments below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

On one hand, a method for forming a semiconductor structure is disclosed, the semiconductor structure comprising a silicon-on-insulator structure using crystalline silicon oxide (SiO₂ ₎ as an insulating material. The method includes: providing a crystalline silicon substrate having a sufficiently clean deposition surface in a vacuum chamber; heating the silicon substrate to an oxidation temperature _To in the range of 550 to 1200°C; supplying the vacuum chamber with an oxygen dose Do of molecular oxygen _O₂ in the range of 0.1 to 1000 Langmuir (L) while maintaining the silicon substrate at the oxidation temperature, wherein the oxidation pressure _Po in the vacuum chamber is in the range of ^1.10⁻⁸ to ^1.10⁻⁴ mbars; wherein at least a portion of the oxygen supplied to the vacuum chamber is adsorbed onto the deposition surface and diffused into the silicon substrate, and a crystalline silicon oxide layer with a thickness of at least two molecular layers is formed in the silicon substrate between a crystalline silicon base layer and a crystalline silicon top layer. In some embodiments, the oxidation temperature may be in the range of 550 to 1000°C, or in the range of 550 to 850°C.

On the other hand, a semiconductor structure is disclosed, comprising a silicon-on-insulator (SiO₂) structure using crystalline silicon oxide ( _SiO₂x) as the insulating material. The semiconductor structure includes: a crystalline silicon base layer; a crystalline silicon oxide layer on the base layer having a thickness of at least two molecular layers; and a crystalline silicon top layer on the crystalline silicon oxide layer, wherein the crystalline silicon oxide layer can be formed by the method described above. The semiconductor structure can be formed by the method described above.

The many accompanying features can be better understood by referring to the following detailed description taken in conjunction with the accompanying drawings, which will make these features easier to comprehend.

Attached Figure Description

This specification can be better understood from the following detailed description, which is read in conjunction with the accompanying drawings, in which:

Figures 1, 3, and 5 show flowcharts of methods for fabricating semiconductor structures including silicon-on-insulator (SOI) layer structures;

Figures 2 and 6 schematically illustrate semiconductor structures including SOI layer structures;

Figure 4 shows a scanning tunneling microscope image of a semiconductor structure including an SOI layer; and

Figure 7 schematically illustrates the band structure of a semiconductor structure including an SOI layer.

Figures 8 and 9 show the capacitance-voltage (C-V) curves measured for a metal-oxide-semiconductor (MOS) capacitor sample including an SOI layer structure and a MOS capacitor reference without an SOI layer structure.

The accompanying figures in Figures 2 and 6 are not to scale.

Detailed Implementation

The detailed description provided below with reference to the accompanying drawings is intended as a description of some embodiments and is not intended to represent the only form in which the embodiments can be constructed, implemented or utilized.

At least some of the embodiments and examples discussed below can provide, for example, a simple, substantially single-step method for forming a high-quality SOI structure using crystalline silicon oxide as an insulating layer. Furthermore, at least some of the embodiments and examples discussed below can provide, for example, a high-quality SOI layer structure suitable for incorporation as part of various semiconductor devices. For example, the SOI layer structure can be used as a deposition surface for depositing semiconductor device layers thereon.

The method 100 of Figure 1 can be used to form a semiconductor structure comprising a silicon-on-insulator (SOI) layer structure using a crystalline silicon oxide ( _SiO₂ ) layer as the insulating layer. The semiconductor substrate can be the semiconductor substrate shown in Figure 2. The method is discussed below with reference to Figures 1 and 2.

The method includes providing a crystalline silicon substrate 201 with a sufficiently clean deposition surface 202 in a vacuum chamber during operation 120.

The crystalline silicon substrate can be in the form of a conventional silicon wafer having any suitable diameter and thickness. Alternatively, the silicon substrate can be formed in any other suitable configuration, shape, and size. For example, it can be diced from or etched onto a silicon wafer. The silicon substrate can be a self-supporting structure or it can be a structure or load structure attached to or formed on a carrier substrate. The silicon substrate can also be part of a larger structure or assembly that also includes parts, structures, and components not formed of silicon.

A deposition surface is a surface of a silicon substrate on which additional materials can be introduced and/or adsorbed. Regarding crystal orientation, the deposition surface can be, for example, a silicon {100} surface, a silicon {111} surface, or a silicon {110} surface.

Sufficient cleanliness means that the deposited surface is substantially free of any native silicon oxide or any other type of impurity atoms. "Substantially free" means that the concentration of foreign atoms and molecules on the silicon surface does not exceed 3 × ^{10¹³ cm⁻²} . This sufficiently clean deposited surface can be provided as clean beforehand (i.e., prior to the method). Optionally, its cleaning can be included in the method, as shown in optional cleaning operation 110 in the method of Figure 1. This cleaning can be performed by any suitable cleaning process.

The vacuum chamber can be the vacuum chamber of any suitable type of system capable of generating a pressure of ^1.10⁻⁴ mbar or lower, preferably at least as low as ^1.10⁻⁸ mbar. Any suitable type of carrier or holding member can be present, on which or attached to the silicon substrate. Any suitable type of heating and cooling system can be connected to the carrier or holding member to heat and cool the silicon substrate thereon.

The method also includes heating the silicon substrate already provided in the vacuum chamber in operation 130 to an oxidation temperature To in the range of 550 to 1200°C, for example, in the range of 550 to 1000°C, 550 to 850°C, _or 550 to 750°C.

In step 140, the method includes supplying molecular oxygen O2 to a vacuum chamber having an oxidation pressure _Po in the range of ^1.10⁻⁸ to ^1.10⁻⁴ _mbar , for example, in the range of ^1.10⁻⁷ to ^1.10⁻⁸ mbar, while maintaining the substrate at the oxidation temperature. Oxygen is continuously supplied until an oxygen dose in the range of 0.1 to 1000 L, for example, in the range of 5 to 300 L, has been supplied to the vacuum chamber.

The aforementioned range defines the parameter space within which actual process parameters can be selected. Therefore, this method can be performed using different combinations of actual process parameters (i.e., oxidation temperature, oxidation pressure, and oxygen dosage). For example, the actual process parameters can be selected from any of the following parameter subspaces: _To = 550 to 700 °C, _Po = ^1.10⁻⁷ to ^1.10⁻⁴ mbar, _Do = 10 to 50 L; _To = 650 to 700 °C, _Po = ^1.10⁻⁷ to ^1.10⁻⁶ mbar, _Do = 50 to 100 L; _To = 650 to 750 °C, _Po = ^1.10⁻⁷ to ^5.10⁻⁷ mbar, _Do = 50 to 300 L; _To = 700 to 750 °C, _Po = ^1.10⁻⁵ to ^5.10⁻⁵ mbar, _Do = 5 to 50 L; _To = 550 to 600 °C, _Po = 1.10⁻⁷ to ^5.10⁻⁷ mbar, _Do = 5 to ⁷⁵ L; and _To =700 to 750℃, P _o =5· ^10⁻⁶ to 1· ^10⁻⁵ mbar, D _o =10 to 100 L.

The duration of oxygen supply can vary depending on, for example, oxygen pressure and the target oxygen dose. Oxygen pressure, in turn, is affected, for example, by the detailed performance of the vacuum chamber and the oxygen supply device. To ensure precise control of the oxygen dose, molecular oxygen can be supplied to the vacuum chamber for at least 0.5 seconds, for example, at least about 1 second, preferably an oxidation duration of at least 10 seconds. Increasing the oxidation duration allows for better control of the oxygen dose.

As a result of the oxygen supply and the oxidation pressure, oxidation time, and oxidation temperature of the silicon substrate, the oxygen supplied to the vacuum chamber is at least partially adsorbed onto the deposition surface and diffuses into the silicon substrate. Therefore, a crystalline silicon oxide layer with a thickness of at least two molecular layers is formed within the silicon substrate between the crystalline silicon base layer and the crystalline silicon top layer. In other words, an SOI structure with a crystalline silicon oxide SiO_{_x} layer as a dielectric layer is formed below the crystalline silicon top layer. Thus, this method involves forming a crystalline silicon oxide layer within an existing silicon crystal without requiring any additional deposition steps, such as forming an additional crystalline silicon top layer. The top layer can then have a diamond cubic crystal structure that is substantially or largely the same as the base layer. "Substantially" and "largely" refer to the fact that the crystalline silicon oxide layer may have a crystal structure deviating from the diamond cubic crystal structure, and this may also have some influence on the crystal structure of the silicon top layer, at least near the Si/SiO_{_x} interface. On the other hand, the (2x1)+(1x2) reconstruction of the free surface of the crystalline silicon top layer affects the crystal structure of the top layer near its free surface.

Based on the established understanding in the art, when crystalline silicon is oxidized using known methods, the oxygen binding sites in the crystal are located on the deposition surface; see, for example, Miyamoto et al., Physical Review B 43, 9287, 1991.

However, the above method is based on a surprising observation that, through a novel combination of appropriately chosen oxidation parameters, oxygen adsorbed on the deposition surface can diffuse through the surface or top layer of the silicon substrate, thereby allowing crystalline oxide to form within the bulk silicon crystal significantly below the deposition surface. Simultaneously, due to oxygen atoms binding to the silicon substrate, silicon atoms from the bulk crystal of the substrate can diffuse towards the outermost surface. This diffused silicon atoms can form new structures on the deposition surface. The crystal structure of the _SiO₂ layer can differ from the diamond lattice of the bulk silicon.

The semiconductor structure 200, including a silicon-on-insulator (SOI) structure, shown in Figure 2, can be fabricated using the method discussed above with reference to Figure 1. In this case, as shown in Figure 2, the fabrication begins with a crystalline silicon substrate 201 having a sufficiently clean deposition surface 202 thereon. The semiconductor structure 200 includes a crystalline silicon base layer 203, a crystalline silicon oxide (SiO₂ ₎ layer 204 extending on the silicon base layer to a thickness of more than one molecular layer; and a crystalline silicon top layer 205 on the crystalline silicon oxide layer. The crystalline silicon top layer 205 may have a diamond cubic crystal structure that is substantially or largely the same as that of the crystalline silicon base layer 203.

The precise thickness of the crystalline SiO _x layer can vary and can be several nanometers thick. When formed using the methods discussed above with reference to Figure 1, the thickness can be affected by, for example, oxidation temperature, oxidation pressure, and/or oxygen dosage. The choice of thickness can be used to adjust the band gap of the SiO _x layer. For example, increasing the band gap can advantageously provide an increase in the effective insulating barrier thickness of the oxide layer. Appropriately adjusting the thickness of the crystalline SiO _x layer can be used, for example, to adjust the tunneling effect through the SiO _x layer in a semiconductor structure. This will be discussed in more detail below.

In semiconductor structures fabricated using the method discussed above with reference to FIG1, it has been found that the silicon-silicon oxide interface between the silicon oxide layer and the silicon substrate and silicon top layer is formed hierarchically rather than abruptly due to diffusion. This can advantageously result in a bent energy band at the SiO _x /Si interface between the silicon oxide layer and the silicon substrate, driving charge carriers away from the interface region, which can, for example, reduce unwanted surface recombination of charge carriers.

The method 300 in Figure 3 differs from the method in Figure 1 in that it includes an additional annealing operation 350, wherein, after supplying molecular oxygen, the silicon substrate with adsorbed oxygen is annealed in a vacuum chamber at a post-heating temperature in the range of 650 to 750°C to remove any excess oxygen that may not contribute to the formation of the crystalline silicon oxide layer. The annealing can have a duration of 30 seconds to 60 minutes, for example, 5 to 20 minutes. A pressure below ^10⁻⁸ mbar can be used in the vacuum chamber during the annealing process.

Prior to annealing, the semiconductor structure formed during operations at 310 or 320 to 340 degrees Celsius can be cooled to a temperature significantly lower than both the oxidation and post-heating temperatures. Alternatively, the temperature of the silicon substrate/semiconductor structure can be directly adjusted from the oxidation temperature to the post-heating temperature. If the oxidation temperature is equal to the post-heating temperature, no adjustment is necessary.

The feasibility of the above method was tested through an oxidation step example.

In the first embodiment, a 5 mm x 10 mm rectangular Si sample was cut from an n-type Si(100) wafer and used as a crystalline silicon substrate with a Si(100) deposited surface. The Si sample was attached along its short side to a sample holder made of Mo that allowed DC current to be fed through the Si sample. The sample holder was transferred to a manipulator located in a vacuum chamber of a multi-chamber vacuum system, and the Si sample was repeatedly and rapidly heated to a cleaning temperature of 1100 to 1200 °C to remove native oxides and carbon contaminants from the Si(100) deposited surface. X-ray photoelectron spectroscopy (XPS) was used to determine the effective removal/desorption of oxygen and carbon contaminants from the deposited surface. Furthermore, low-energy electron diffraction (LEED) analysis showed sharp (2x1) + (1x2) reconstructions caused by the inherent double-domain surface structure. Scanning tunneling microscopy (STM) images captured after surface cleaning supported the presence of double-domain reconstructions on large two-dimensional terraces.

Following the cleaning stage, the Si sample with a clean Si(100) deposited surface was oxidized in the same vacuum system using _O2 gas introduced into the vacuum chamber through a leak valve. Before opening the leak valve, the temperature of the Si sample was increased to a heating temperature of 670°C. Then, the _O2 pressure in the vacuum chamber was increased to ^1.10⁻⁷ mbar (pressure measured by an ion pressure gauge), and the Si sample was oxidized at the heating temperature for 500 seconds, producing an oxidation amount of 50 Langmuirs (L). Afterward, the leak valve was closed, and silicon heating was stopped.

The STM images in Figure 4 show the surface development of the Si sample during the oxidation process. In the top image, the deposited surface exhibits a stepped or ladder-like microstructure. As oxidation proceeds, oxygen atoms bind (incorporate) into the Si crystal, causing Si atoms to diffuse from the host crystal to the deposited surface, where they begin to form new islands or rows with an initial (2x1) dimer-row structure, as shown in the middle and bottom images.

After oxidation of the Si sample, the LEED image of the Si sample still showed a sharp (2x1)+(1x2) pattern, indicating that the outermost surface layer of the sample was formed by crystalline silicon. On the other hand, the O1s intensity measured by XPS clearly revealed the bonding of oxygen atoms in the bulk silicon crystal beneath the top silicon layer.

In the second embodiment, a Si sample was prepared and cleaned in a manner similar to the first embodiment discussed above. Oxidation was performed in a substantially similar manner to the first embodiment, but at a temperature of 600°C, with an oxygen pressure of ^1.10⁻⁶ mbar and an oxygen supply time of 75 s, resulting in an oxygen dose of 75 L. Similar to the first embodiment, sharp (2x1) + (1x2) LEED patterns were observed, and the O1s intensity was measured using XPS, indicating that a crystalline SOI structure was also formed using these oxidation parameters.

In the third embodiment, essentially similar to the first and second embodiments, oxidation was performed at an oxidation temperature of 700°C, with an oxygen pressure of ^1.10⁻⁴ mbar and an oxygen supply time of 1 s, producing an oxygen dose of approximately 100 to 200 L. After oxidation, the LEED image of the sample showed only a weak (1x1), indicating the presence of excess oxygen at the deposition surface that had not been incorporated into the Si host crystal and formed crystalline _SiO₂ . The sample was then annealed at a post-heating temperature of 700°C for 10 minutes. Annealing resulted in a sharp (2x1) + (1x2) LEED pattern, similar to Figure 7b, and the O₁s intensity measured by XPS again indicated the formation of a crystalline silicon oxide layer beneath the crystalline silicon top layer.

Method 500 of Figure 5 includes an oxidation stage, which can be performed according to any of the methods discussed above with reference to Figures 1 and 3. This method includes operations 520, 530, and 540 of providing a crystalline silicon substrate in a vacuum chamber, heating the crystalline silicon substrate to an oxidation temperature, and supplying molecular oxygen to the vacuum chamber to oxidize the silicon substrate. Furthermore, the method may include one or both of optional operations 510 and 550 of cleaning the deposited surface of the silicon substrate and annealing the silicon substrate in which a silicon oxide layer is formed.

Furthermore, in operation 560, the method includes depositing a capping layer on the top silicon layer. The capping layer may include, for example, an oxide or a nitride, and may be amorphous or crystalline. The additional oxide layer may include, for example, silicon dioxide (SiO2 ₎ , aluminum oxide ( _{Al2O3 )} , hafnium dioxide (HfO2 ₎ , or titanium dioxide (TiO2 ₎ . In other embodiments, it may include, for example, a mixture of hafnium dioxide and titanium dioxide HfO2 _{- TiO2} , zirconium oxide _ZrO2 , cerium oxide _CeO2 , yttrium oxide _Y2O3 , zirconium silicate _ZrSiO4 , _hafnium silicate _HfSiO4 , aluminum oxide _Al2O3 , silicon oxynitride hafnium HfSiON, silicon nitride _hafnium , lanthanum oxide _La2O3 , _bismuth silicate _Bi4Si2O12 , _{tantalum oxide Ta2O5 ,} tungsten oxide _WO3 , _lanthanum aluminum oxide _LaAlO3 , barium strontium oxide _{Ba1 - xSrxO3} , lead(II) titanate _PbTiO3 , barium _{titanate BaTiO3} , strontium titanate _SrTiO3 , or any suitable mixture thereof. The capping layer can have a thickness, for example, in the range of 1 to 500, 1 to 400, or 3 to 300 nm.

The capping layer can be deposited, for example, by atomic layer deposition (ALD) or chemical vapor deposition (CVD). Therefore, the entire method 500 can be performed by forming an SOI structure using any of the methods discussed above with reference to Figures 1 and 3, and then depositing a capping layer thereon by ALD or CVD.

The semiconductor structure 600 of Figure 6 can be manufactured, for example, by the method 500 of Figure 5. The semiconductor structure 600 includes an SOI configuration, which can be any of the semiconductor structures discussed above with reference to Figures 2 and 4. The SOI configuration includes a crystalline silicon substrate 603, a crystalline silicon oxide (SiO₂ ₎ layer 604 with a thickness of at least two molecular layers on the silicon substrate, and a crystalline silicon top layer 605 on the crystalline silicon oxide layer. The semiconductor structure 600 also includes a capping layer 606 on the crystalline silicon top layer 605. The capping layer can include, for example, silicon dioxide (SiO₂ ₎ , aluminum oxide ( _{Al₂O₃ )} , hafnium dioxide (HfO₂ ₎ , or titanium dioxide (TiO₂ ₎ . In other embodiments, it may include _{, for example, a mixture of hafnium dioxide and titanium dioxide HfO2-TiO2, zirconium oxide ZrO2, cerium oxide CeO2, or yttrium oxide Y2O3 , zirconium silicate ZrSiO4 , hafnium silicate HfSiO4, aluminum oxide Al2O3 , silicon} oxynitride hafnium _HfSiON , silicon nitride hafnium, _lanthanum oxide _La2O3 , _bismuth silicate _Bi4Si2O12 , tantalum oxide _Ta2O5 , tungsten oxide _WO3 , lanthanum aluminum oxide _LaAlO3 , barium strontium oxide _{Ba1 -xSrxO3 ,} lead( _II ) titanate _PbTiO3 , barium titanate BaTiO3, strontium titanate _{SrTiO3 ,} or any suitable mixture thereof. The capping layer can have a thickness, for example, in the range of 1 to 500, 1 to 400, or 3 to 300 nm.

It has been found that for semiconductor structures fabricated using any of the methods discussed above with reference to Figures 1, 3, and 5, the tunnel gaps of the semiconductor structures measured by scanning tunneling spectroscopy (STS) are significantly higher than those measured for the clean surface of the Si host sample. For example, STS analysis has shown that oxidizing the Si(100)(2x1) surface at 600 °C with a low oxygen dose of 10 L can result in a tunnel gap width that is four times wider than that of a clean, unoxidized Si(100)(2x1) reference surface. Due to the inherent property of STS being most sensitive to the outermost atomic layer of the sample under test, it can be assumed that the measured tunnel gap does not represent the SiO _x gap. This assumption has been confirmed by STM analysis of the sample, showing the absence of any oxygen on its surface. Instead, it can be assumed that oxygen bound to the host beneath the outermost Si surface causes bending of the valence and conduction bands, increasing the band gap between the minimum conduction band (CBM) and maximum valence band (VBM) of the outermost surface layer of the oxidized Si sample, including the SOI structure. This effect is illustrated in Figure 7a.

The effect of this band bending on the band structure in a semiconductor structure 600, including a capping layer on a crystalline silicon top layer, as shown in Figure 7b, is illustrated. As is known in the art, in structures with an insulating oxide layer on a crystalline Si substrate, interface defects are typically present at the insulator/Si interface. These interface defects can cause undesirable surface recombination of charge carriers. In the structure according to Figure 6, the increase in the SiO₂ _x⁻ -induced band gap (and band bending) may “repel” charge carriers from the most defect-rich regions of the structure, as shown in Figure 7b, where charge carriers are represented by spheres and the repulsive effect is indicated by arrows.

The existence of the hypothetical effect schematically illustrated in Figures 7a and 7b was investigated using a surface recombination velocity (SRV) instrument from Aalto University with a test sample and a reference sample based on semiconductor structure 600 of Figure 6. The test sample was fabricated at an oxidation temperature of 600 °C according to the method in Figure 5, and the reference sample was fabricated by oxidizing a Si substrate at room temperature. The reference sample was covered with a similar _{amorphous Al₂O₃} film as a capping layer, as with the test sample. The test sample exhibited a significantly higher lifetime than the reference sample, thus confirming the hypothetical effect explained above with reference to Figures 7a and 7b.

In the embodiments discussed above with reference to Figures 1 to 7, a planar silicon substrate with a single planar deposition surface and a planar semiconductor structure with an SOI layer structure were discussed. However, the methods discussed above can also be used to oxidize silicon substrate structures with multiple deposition surfaces, which can be of different orientations and can have different crystal orientations. Therefore, a three-dimensional SOI layer structure can be formed. Accordingly, the structures discussed above with respect to the planar semiconductor structures shown in Figures 2 and 6 can also be implemented as semiconductor structures with a three-dimensional SOI layer structure.

The semiconductor structures fabricated as described above with reference to Figures 1, 3, and 5, and the semiconductor structures fabricated as described above with reference to Figures 2, 4, and 6, can be used in any kind of application where the SOI structure is useful. For example, these semiconductor structures can be used in field-effect transistors (FETs), solar cells, and various elements or barrier structures designed to guide current flow in semiconductor devices. Furthermore, these semiconductor structures have been found to potentially be used for passivating various semiconductor surfaces.

As shown in Figure 6, a semiconductor structure with a capping layer on a top layer of crystalline silicon can be used, for example, as a surface passivation and/or anti-reflective coating for solar cell structures, or as a gate stack for field-effect transistors (FETs). Favorable surface recombination rate characteristics can improve the performance of this semiconductor structure and device. Similar semiconductor structures can also be used, for example, for the electro- and/or chemical passivation of three-dimensional structures (such as nanostructures formed by etching) to prevent changes caused by environmental conditions around the structure.

In the fourth embodiment, two 5mm x 10mm rectangular slices are cut from an n-type Si(100) wafer to serve as a Si sample substrate and a Si reference substrate. Then, the substrates are vacuum-cleaned in the vacuum chamber of a multi-chamber vacuum system by repeatedly and rapidly heating them to a cleaning temperature of 1100°C.

Following this cleaning step, the Si sample substrate is subjected to a heating temperature of 650°C, and the outer surface of the sample is oxidized under an _O2 pressure of ^1.10⁻⁷ mbar to produce an oxidation dose of 50 L to generate the SOI layer structure according to the invention. Subsequently, _HfO₂ films with a thickness of 25 nm are grown on the oxidized sample substrate and the reference substrate by ALD using water and tetra(dimethylamino)hafnium(IV) (TDMAH) as precursors.

After depositing _HfO2 , circular gate metal pads with a diameter of 100 micrometers were deposited on the _HfO2 film by sputtering 10 nm of chromium followed by 50 nm of gold through a shadow mask to fabricate two metal-oxide-semiconductor (MOS) structures: a MOS capacitor sample and a MOS capacitor reference, each comprising a sample substrate and a reference substrate as semiconductors, respectively. The MOS capacitor structures were then removed from the vacuum system and connected to an LCR meter, with back contacts formed using conductive silver paste.

Figure 8 shows capacitance-voltage (CV) curves measured for two different MOS capacitor structures according to the fourth embodiment. The CV curves in Figures 8a and 8b correspond to measurements performed on the MOS capacitor sample and the MOS capacitor reference, respectively. Based on Figure 8, it can be seen that the depletion region capacitance step of the MOS capacitor reference, occurring under near-short-circuit conditions, is more structured (e.g., with shoulders and/or flattened) than the corresponding step in the MOS capacitor sample when transitioning from a negative voltage to a positive voltage. This depletion region characteristic may indicate that the defect density in the MOS capacitor reference is higher than that in the MOS capacitor sample because the crystalline SiO_{_x} layer is embedded inside the Si sample substrate. Furthermore, based on these results, the cleaning step performed at 1100°C may have caused band bending in both the sample and reference substrates, thus affecting the shape of the CV curves.

In the fifth embodiment, a MOS capacitor sample and a MOS capacitor reference were fabricated similarly to those in the fourth embodiment described above and connected to an LCR measuring instrument. However, compared to the fourth embodiment, the step of cleaning the sample substrate and reference substrate in vacuum was replaced with a standard RCA cleaning procedure. The sample substrate and reference substrate also underwent additional post-metallization annealing at 400°C before silver paste was applied to form the back contacts.

Figure 9 shows capacitance-voltage (CV) curves measured for two different MOS capacitor structures according to the fifth embodiment. The CV curves in Figures 9a and 9b correspond to measurements performed on the MOS capacitor sample and the MOS capacitor reference, respectively. In Figure 9b, the inversion capacitance of the reference sample is seen to increase under negative voltage. This is likely caused by an unfavorable hole-inversion layer in the MOS capacitor reference, see, for example, O'Connor et al., Journal of Applied Physics 111, 124104, 2012. The hole-inversion layer may be caused by the inherent fixed negative charge in _HfO2 ; see, for example, Foster et al., Physical Review Letters 89, 225901, 2002. The hole-inversion layer that hinders the turn-off of the MOS capacitor reference can be removed by providing an SOI layer structure, as shown in Figure 9a, because it compensates for the fixed positive charge of _SiOx , see, for example, Schmidt et al., Applied Physics A 86, 187, 2007. This fixed positive charge in crystalline SiO_{_x} can also be used in semiconductor devices (such as solar cells) to design various elements or barrier structures for guiding current flow (such as induced pn junctions or hole diffusion barriers in p-type silicon).

Although the subject matter has been described in language specific to structural features and/or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as embodiments for implementing the claims.

It is understood that the benefits and advantages described above may apply to one implementation scheme or to multiple implementation schemes. The implementation scheme is not limited to an implementation scheme that solves any or all of the described problems or has any or all of the described benefits and advantages. It is also understood that references to "an" project refer to one or more of those projects.

In this specification, the term "comprising" means including the features or actions that follow, without excluding the presence of one or more other features or actions.

It should be noted that the embodiments of the claims are not limited to those discussed above, but other embodiments may exist within the scope of the claims.

Claims (12)

1. A method for forming a semiconductor structure, said semiconductor structure comprising a silicon-on-insulator layer structure using crystalline silicon oxide (SiO₂ ₎ as an insulating material, said method comprising: A crystalline silicon substrate with a clean deposition surface is provided in a vacuum chamber; The crystalline silicon substrate is heated to an oxidation temperature T _{_o} in the range of 550 to 1200°C; The vacuum chamber is supplied _with molecular oxygen _O2 in the range of 0.1 to 1000 Langmuirs, while the crystalline silicon substrate is kept at the oxidation temperature, wherein the oxidation pressure _Po in the vacuum chamber is in the range of ^1.10⁻⁸ to ^1.10⁻⁴ mbar. At least a portion of the oxygen supplied to the vacuum chamber is adsorbed onto the deposition surface and diffuses into the crystalline silicon substrate, and a crystalline silicon oxide layer with a thickness of at least two molecular layers is formed between the crystalline silicon base layer and the crystalline silicon top layer in the crystalline silicon substrate. 2. The method of claim 1, wherein the oxidation temperature _To is in the range of 550 to 750°C, the oxidation pressure _Po is in the range of ^1.10⁻⁷ to ^1.10⁻⁴ mbar, and the oxygen dose _Do is in the range of 5 to 300 Langmuirs. 3. The method of claim 2, wherein the oxidation temperature, the oxidation pressure, and the oxygen dosage are within one of the following parameter spaces a) to f): a) _To = 550 to 700 °C, P _{_o} = 1.10^{^-7} to 1.10^{^-4} mbar, _Do = 10 to 50 Langmuir; b) _To = 650 to 700 °C, P _o = ^1.10⁻⁷ to ^1.10⁻⁶ mbar, _Do = 50 to 100 Langmuir; c) _To = 650 to 750 °C, P _o = ^1.10⁻⁷ to ^5.10⁻⁷ mbar, _Do = 50 to 300 Langmuir; d) T _{_o} = 700 to 750 °C, P _{_o} = 1.10^{^-5} to 5.10^{^-5} mbar, D _{_o} = 5 to 50 Langmuir; e)T _{_o} = 550 to 600 °C, P _{_o} = 1.10^{^-7} to 5.10^{^-7} mbar, D _{_o} = 5 to 75 Langmuir; f)T _{_o} = 700 to 750 °C, P _{_o} = 5.10^{^-6} to 1.10^{^-5} mbar, D _{_o} = 10 to 100 Langmuir. 4. The method according to any one of claims 1 to 3, wherein the molecular oxygen is supplied to the vacuum chamber for an oxidation duration of at least 0.5 s. 5. The method of any one of claims 1 to 3, further comprising cleaning the deposition surface by removing possible native oxides and/or other impurities on the deposition surface before supplying the molecular oxygen to the vacuum chamber. 6. The method of any one of claims 1 to 3, wherein the deposited surface is a silicon {100} surface, a silicon {111} surface, or a silicon {110} surface. 7. The method of any one of claims 1 to 3, further comprising, after supplying the molecular oxygen, annealing the crystalline silicon substrate at a post-heating temperature in the range of 650 to 750°C for 30 seconds to 60 minutes to remove any excess oxygen that may be present not contained in the crystalline silicon oxide. 8. The method of any one of claims 1 to 3, further comprising depositing a capping layer on the top layer of the crystalline silicon, the capping layer comprising silicon dioxide (SiO2 ₎ , aluminum oxide ( _{Al2O3 )} , hafnium dioxide ( _HfO2) , or titanium dioxide (TiO2 ₎ . 9. The method of claim 8, wherein the capping layer is deposited to have a thickness of 1 to 500 nm. 10. A semiconductor structure formed by the method according to any one of claims 1 to 9, said semiconductor structure comprising a silicon-on-insulator structure using crystalline silicon oxide (SiO₂ ₎ as the insulating material, said semiconductor structure comprising: Crystalline silicon substrate; A crystalline silicon oxide layer on the silicon substrate has a thickness of at least two molecular layers; and A top layer of crystalline silicon on the crystalline silicon oxide layer. 11. The semiconductor structure of claim 10, further comprising a capping layer on the top layer of the crystalline silicon, the capping layer comprising silicon dioxide (SiO2 ₎ , aluminum oxide ( _{Al2O3 )} , hafnium dioxide (HfO2 ₎ , or titanium dioxide (TiO2 ₎ . 12. The semiconductor structure of claim 11, wherein the capping layer has a thickness of 1 to 500 nm.