HK1235608B - Integrated circuit to control a power supply that supplies power to plurality of light-emitting diode strings - Google Patents

Description

Integrated circuit for controlling power supply to multiple light-emitting diode strings

This application is a divisional application of the invention patent application with application date of December 6, 2012, application number 201280069410.0, and invention name “Serial Lighting Interface with Embedded Feedback”.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Provisional Application No. 61/568,545, filed December 8, 2011, which is incorporated herein by reference in its entirety.

This application is related to the following applications, each of which is incorporated herein by reference in its entirety: Application No. 13/346,625, filed January 9, 2012, entitled Low Cost LED Driver with Integral Dimming Capability; and Application No. 13/346,647, filed January 9, 2012, entitled Low Cost LED Driver with Improved SerialBus.

Technical Field

The present invention relates to semiconductor devices and circuits and methods for driving LEDs in lighting and display applications.

Background Art

LEDs are increasingly being used to replace lamps and bulbs in lighting applications, including providing white light as backlighting in color liquid crystal displays (LCDs) and high-definition televisions (HDTVs). To backlight color LCD panels, LED strings can include white LEDs or a combination of red, green, and blue LEDs tuned with a controllable color temperature to produce white light. While these LEDs can be used to uniformly illuminate an entire display, the performance, contrast, reliability, and power efficiency of the display are improved by using multiple strings of LEDs, each driven to a different current and brightness level corresponding to the portion of the display illuminated by that particular LED string. The term "local dimming" refers to backlight systems with such non-uniform backlight brightness. Compared to LCDs using uniform backlighting, power savings can be as high as 50%. Using local dimming, LCD contrast ratios can approach those of plasma TVs.

In order to control the brightness and uniformity of the light emitted from each LED string, special electronic driver circuits must be used to precisely control the LED current and voltage. For example, a string of "m" white LEDs connected in series requires a voltage equal to approximately 3.1 to 3.5 (usually 3.3) times "m" to operate consistently. Providing this required voltage to the LED string typically requires a step-up or step-down voltage converter and a regulator called a DC-to-DC converter or switch mode power supply (SMPS). When powering multiple LED strings from a single SMPS, the output voltage of the power supply must exceed the highest voltage required by any one LED string. Because the required highest forward voltage cannot be known a priori, the LED driver IC must be smart enough to use feedback to dynamically adjust the supply voltage. If two or more supply voltages are required, more than one feedback signal is required.

In the case of RGB backlighting, voltage feedback requirements are even more complex because red, green, and blue LEDs have significantly different forward voltages and cannot share a common power rail. Instead, an RGB LED string requires three different supply voltages: + _VRLED , + _VGLED , and + _VBLED , each with a separate feedback signal to dynamically adjust its respective supply voltage to the appropriate level. For example, a string of 30 red LEDs in series requires a supply voltage exceeding 66V to operate properly, while 30 blue LEDs may require a supply voltage exceeding 96V, and 30 green LEDs may require a supply voltage exceeding 108V.

In addition to providing the proper voltage to the LED strings, the backlight driver must also precisely control the current _ILED conducted in each string to a tolerance of ±2%. Accurate current control is necessary because the brightness of an LED is proportional to the current flowing through it, and any substantial string-to-string current mismatch will manifest as variations in the LCD's brightness. In addition to controlling current, local dimming requires precise pulse control of the LED illumination, both in terms of timing and duration, to synchronize the brightness of each backlight area, zone, or tile with the corresponding image on the LCD screen.

Another complication is that the color temperature of white LEDs varies with current. As an example, a string of white LEDs conducting 30mA 100% of the time would ideally be equivalent in brightness to the same string carrying 60mA pulsed on and off at a 50% duty cycle. However, even at the same brightness, the color temperature will not be the same. Therefore, accurately setting and maintaining the current in each string is crucial to achieving uniform white backlighting for color LCD panels.

In the case of RGB backlighting, balancing current is even more complex because the luminosity, or light output, or brightness, of red, blue, and green LEDs is very different. For example, a red LED produces less light than a blue LED for the same LED current. This difference is understandable because the semiconductor materials and manufacturing processes used to make LEDs of different colors are substantially different.

As will be shown in this background section, known solutions for local dimming limit display brightness and suffer from high solution costs. For example, early attempts to integrate LED driver control circuitry with multiple channels of high-voltage current sink transistors were problematic because mismatches in the forward voltages of the LED strings resulted in excessive power dissipation and overheating. Attempts to minimize power dissipation by reducing the LED current and limiting the number of LEDs in the string (for better channel-to-channel voltage matching) proved uneconomical, requiring more LEDs and a greater number of LED driver channels. Consequently, fully integrated approaches to LED backlight drivers have been limited to small display panels or very expensive "high-end" HDTVs.

Subsequent attempts to reduce overall display backlight costs using a multi-chip approach have sacrificed necessary features, functionality, and even safety.

For example, the multi-chip solution for driving LEDs shown in FIG1 includes an interface IC 6 that drives multiple discrete current sinks, DMOSFETs 4, and a high-voltage protection device 3. The backlight system includes sixteen LED strings 2A-2Q (collectively, LED strings 2), where each LED string 2A-2Q contains "m" series-connected LEDs, ranging in length from 2 to 16 LEDs. (Note that the letter "O" has been omitted from strings 2A-2Q to avoid confusion with the number 0.) Each LED string has a current controlled by one of the discrete current sinks, DMOSFETs 4A-4Q. Interface IC 6 sets the current in each LED string in response to commands from a backlight microcontroller (μC) 7, transmitted via a high-speed, expensive SPI bus interface 11. Microcontroller μC 7 receives video and image information from a scaler IC 8 to determine the appropriate lighting level required for each LED string.

As shown, each LED string 2A-2Q is powered by a common LED power rail 12 generated by a switch mode power supply (SMPS) 9 having a voltage + _VLED generated in response to a fed-back current sense feedback (CSFB) signal 1 from an interface IC 6. The supply voltage varies with the number of LEDs in series, "m", and can range from 35 volts for 10 LEDs up to 150 volts for a string of 40 LEDs. The SMPS 9 can be powered from the AC mains or, alternatively, from another input such as a +24V input.

The SMPS 9 typically includes a flyback converter operating in hard switching or quasi-resonant mode. Forward and Cuk converters, while applicable, are generally too expensive and unnecessarily complex to serve the cost-sensitive display and TV markets. In the case where the SMPS 9 is powered from a +24V input, its operation depends on the number of LEDs connected in series. If the forward voltage of the LED string is less than 24V, for example, if fewer than 7 LEDs are connected in series, a step-down (buck) switching regulator can be used to implement the SMPS 9. Conversely, if the forward voltage of the LED string is greater than 24V, for example, if more than 8 LEDs are connected in series, a step-up switching regulator can be used to implement the SMPS 9.

Proper generation of the CSFB signal 10 is crucial for achieving reliable operation of the display's LED backlight, regardless of its input voltage. If the feedback signal is incorrect, the LED supply voltage +VLED may be too high or too low. If the LED supply voltage is too high, excessive power dissipation will occur in the current sink DMOSFETs 4A-4Q. If the LED supply voltage is too low, the LED string requiring the highest current may not illuminate at the specified level, if at all.

To implement the CSFB functionality, accurate monitoring of the LED string forward voltage requires electrical access to the drains of the current sink DMOSFETs 4A-4Q, which can be particularly problematic for multi-chip implementations, resulting in additional package pins and added component cost.

Current sinks DMOSFETs 4A-4Q are implemented using discrete DMOSFETs to avoid overheating. Additional discrete DMOSFETs 3A-3Q, typically high voltage discrete DMOSFETs, are optionally employed to clamp the maximum voltage appearing across current sink DMOSFET 4, especially for higher voltage operation, eg, over 100V.

Each of the components 3A-3Q is a discrete device in a separate package, requiring its own unique pick-and-place operation to position and mount it on its printed circuit board. The current sink DMOSFET, clamp MOSFET (if any), and its associated LED string are collectively referred to as a "channel."

Each set of discrete MOSFETs 3A-3Q and DMOSFETs 4A-4Q and its corresponding white LED string is repeated "n" times for an n-channel LED driver system. For example, a 16-channel backlight system requires 34 components, in addition to the SMPS module 9, namely, a microcontroller, a high-pin-count LED interface IC, and 32 discrete MOSFETs to facilitate local dimming in response to video information generated from the scaler IC 8. This solution is complex and expensive.

In some cases, it's desirable to split LED power across more than one power supply, for example to reduce power consumption in any one power supply and its components. However, existing LED interface ICs cannot support multiple independent feedback signals. In the case of RGB backlighting displays, the solution is even more complex and expensive. Because current and prior art LED drivers and controllers include only a single CSFB signal per integrated circuit, independently regulating three different power supplies requires three separate LED interface ICs and three separate power supplies, making today's RGB backlighting solutions prohibitively expensive.

In either case, the assembly of a large number of discrete components, i.e., a high bill of materials (BOM) count, results in expensive PCB assembly, further exacerbated by the high packaging cost of the high pin count package 6. The need for such a large number of pins is illustrated in FIG2A , which illustrates further circuit details for each channel of the LED driver system. As shown, each channel includes a string of "m" series-connected LEDs 21, a cascode-clamp MOSFET 22 with an integrated high-voltage diode 23, a current sink MOSFET 24, and a current-sensing, I-accurate gate driver circuit 25.

Active current sink MOSFET 24 is a discrete power MOSFET, preferably a vertical DMOSFET, having gate, source, and drain connections. An I-precision gate driver circuit 25 senses the current in current sink MOSFET 24 and provides the required gate drive voltage to conduct a precise amount of current. In normal operation, current sink MOSFET 24 operates in its saturation mode, controlling a constant level of current independent of its drain-to-source voltage. Due to the simultaneous presence of drain voltage and current, power is dissipated in MOSFET 24.

The drain voltage of current sink MOSFET 24 needs to be continuously measured for two purposes—to detect the occurrence of a shorted LED in LED fault circuit 27, and to facilitate feedback to the system's SMPS via CSFB circuit 26. The signal generated by CSFB current 26 is crucial for dynamically adjusting +VLED to an appropriate voltage, high enough to ensure that each LED string is illuminated and low enough to avoid excessive voltage across current sink DMOSFET 24, which would cause undesirable power dissipation. With only one CSFB signal, the LEDs cannot be powered from more than one source, i.e., the power requirement cannot be split in two to reduce size, cost, and heat generation in the SMPS.

The current sink MOSFET 24 requires three connections to the control IC, specifically to the source for current measurement, the gate for device bias, and the drain for fault and feedback sensing. These three connections for each channel are depicted intersecting a discrete to-IC interface 28. Even in FIG2B , where the cascode clamp MOSFET 22 is removed and the current sink MOSFET 24 must maintain a high voltage, as illustrated by the HV integrated diode 23, each channel still requires three pins per channel to intersect the interface 28. This requirement for three interfaces per channel explains the need for the high pin count interface IC 6 shown in FIG1 . For a sixteen-channel driver, the need for three pins per channel uses 48 pins for outputs. Including the SPI bus interface, analog functions, power supplies, and more, requires a costly 64- or 72-pin package. Furthermore, many TV printed circuit board assembly shops cannot solder packages with any pin pitch less than 0.8 or 1.27 mm. A 72-pin package with a 0.8mm pin pitch requires a 14x14mm plastic body to accommodate the peripheral linear edges required to fit all the pins.

A significant problem with the multi-chip architecture shown in FIG1 is that the temperature sensing circuitry in interface IC 6 can only detect the temperature of the interface IC itself, where no significant power consumption occurs. Unfortunately, extremely high heat is generated in discrete current sink DMOSFET 4, where temperature sensing is impossible. Without temperature sensing, any of current sink MOSFETs 4A-4Q could overheat without the system being able to detect or remedy the situation.

In summary, today's implementations of LED backlighting for LCD panels with local dimming capabilities suffer from a number of fundamental limitations in terms of cost, performance, features, and safety.

Highly integrated LED driver solutions require expensive, large die packaged in expensive, high pin count packages, and concentrate the heat in a single package, limiting the driver to lower currents due to power dissipation caused by linear operation of the current sink MOSFETs, and lower voltages due to power dissipation caused by LED forward voltage mismatch, which is further exacerbated for larger numbers of LEDs in series.

Multi-chip solutions that combine LED controllers with discrete power MOSFETs require a BOM and an even higher pin-count package. Almost three times the pin count of a fully integrated LED driver, a sixteen-channel solution may require 33 to 49 components and a 72-pin package measuring 14mm x 14mm. Furthermore, discrete MOSFETs do not provide thermal sensing or protection against overheating. Using only one feedback signal, these LED drivers cannot power two or more LEDs without including an additional interface IC, which adds cost and complexity.

Similarly, extending the use of these existing LED driver and interface ICs to RGB backlighting requires an even higher BOM count, including three large high-pin-count packages and all the associated discrete MOSFETs.

What is needed for a cost-effective and reliable backlight system for TVs with local dimming is a new semiconductor chipset that eliminates discrete MOSFETs, provides low overall packaging cost, minimizes heat concentration within any component, facilitates over-temperature detection and thermal protection, protects low-voltage components from high voltages and protects against shorted LEDs, flexibly scales to accommodate different sized displays, and maintains precise control of LED current and brightness.

Ideally, a flexible solution would be scalable to accommodate varying numbers of channels, feedback signals, power supplies, and display panels of varying sizes without the need for custom integrated circuits.

Summary of the Invention

The system according to the present invention includes an interface integrated circuit (IC) that transmits a current sense feedback (CSFB) signal to a switch mode power supply (SMPS) for setting a single supply voltage for multiple light-emitting diode (LED) strings. Multiple LED driver ICs control the current in the LED strings and provide other functions for the LED strings.

Each LED driver IC controls at least two LED strings (channels) and includes a serial lighting interface (SLI) bus shift register functionally linked to a latch in the LED driver IC. The latch is used to store digital data that controls the current in the LED string and can be used to control or monitor other functions related to the LED string, such as detecting short circuits and open circuits in the LED string and excessive temperature in the LED driver IC.

According to the present invention, each LED driver IC includes circuitry for periodically sampling the forward voltage drop across each controlled LED string, and a CSFB sampling latch for storing a digital representation of such samples. The CSFB latch can store a digital representation of the highest forward voltage drop in any LED string controlled by the LED driver IC. Each CSFB latch is coupled to a register within the LED driver IC's SLI bus shift register. In some embodiments, the forward voltage drop across the LED string is detected by sensing the voltage at a current sink MOSFET that controls the current through the LED string.

The individual SLI bus shift registers in the LED driver IC are connected together in series via the SLI bus in a "daisy-chain" arrangement, thereby forming an SLI bus that originates at and terminates at the interface IC. Thus, in the process of serially pushing data bits previously stored in the SLI bus registers back to the interface IC, data bits removed from the interface IC are serially shifted through the SLI bus shift registers and the SLI bus connecting them and back to the interface IC.

In some embodiments, the SLI bus shift register includes a dedicated CSFB register that stores CSFB data received from the CSFB latch within the LED driver IC. Similarly, the SLI bus shift register may include other dedicated registers that are linked in a one-to-one relationship with other functions and sampling latches within the LED driver IC.

Alternatively, in a preferred embodiment, the SLI bus shift register in each LED driver IC includes a prefix register and a data register. That is, there is a one-to-one relationship between the SLI bus registers and the latches in the LED driver IC. The CSFB latch and other latches in the LED driver IC are identified by a digital word (address) in the prefix register, allowing data stored in the CSFB latch to be copied to the data register. This structure conserves valuable semiconductor "real estate" on the LED driver IC, significantly reducing costs.

In either embodiment, a digital word representing the highest forward voltage of any LED string controlled by an LED driver IC can be read and stored into a register within the driver IC's SLI bus shift register.

The interface IC contains circuitry that receives the CSFB data stored in the SLI bus shift register and selects the CSFB word representing the highest forward voltage drop of any LED string controlled by that LED. This word is then used by the interface IC to generate the CSFB signal that the SMPS module uses to set the appropriate supply voltage for all controlled LED strings.

Sampling of the CSFB data in the LED driver IC is performed at predetermined intervals, after each interval the data is again shifted to the interface IC which then sends a new SCFB signal to the SMPS module, allowing the supply voltage to be adjusted appropriately based on the new highest forward voltage drop between the controlled LED strings.

This arrangement allows flexibility and scalability to systems including different numbers of LED strings and other parameters.

This arrangement allows the LED drive system to be easily divided into different groups of LED strings powered by different SMPS modules at different supply voltages. For example, this is useful when displaying separate strings of red, green, and blue LEDs, which typically require different supply voltages. In this case, the interface IC includes circuitry capable of separating the CSFB words associated with the red, green, and blue LED strings, respectively, and sending the appropriate CSFB signals to the separate SMPS modules providing the supply voltages for the different LED strings. In embodiments where the SLI bus shift register includes a dedicated SCFB register, separation processing can be performed by counting the number of bits received to identify which LED string the CSFB data is associated with. In embodiments where the SLI shift register includes a prefix and data register, the prefix can be used to identify which LED string the CSFB data is associated with.

According to one aspect of the present invention, an integrated circuit for controlling a power supply that supplies power to a plurality of LED strings is provided, the integrated circuit comprising: an interface circuit coupled to a plurality of serial shift registers coupled in a daisy-chain manner, the interface circuit being configured to receive a plurality of digital values from the plurality of serial shift registers and identify a lowest digital value from the plurality of digital values, each of the plurality of digital values corresponding to a voltage level at one end of one of the plurality of LED strings; and a converter coupled to the interface circuit, the converter being configured to convert the lowest digital value into a control signal and provide the control signal to the power supply to adjust an output voltage of the power supply, the converter comprising a digital-to-analog converter (DAC) and an operational transconductance amplifier, the DAC being configured to convert the lowest digital value into an analog voltage signal, the operational transconductance amplifier being coupled to the DAC and configured to convert the analog voltage signal into an analog current signal and provide the analog current signal to the power supply.

According to another aspect of the present invention, an integrated circuit for controlling a power supply for supplying power to a plurality of LED strings is provided, the integrated circuit comprising: an interface circuit coupled to a plurality of serial shift registers coupled in a daisy-chain manner, the interface circuit being configured to receive a plurality of digital values from the plurality of serial shift registers and identify a lowest digital value from the plurality of digital values, each of the plurality of digital values corresponding to a voltage level at one end of one of the plurality of LED strings, the interface circuit comprising a register storing digital values and a comparator coupled to the register and configured to compare the incoming digital values from the plurality of serial shift registers with the digital values stored in the register to identify a lower digital value; and a converter coupled to the interface circuit, the converter being configured to convert the lowest digital value into a control signal and provide the control signal to the power supply to adjust the output voltage of the power supply.

According to another aspect of the present invention, an integrated circuit for controlling a first power source and a second power source for supplying power to a first plurality of LED strings and a second plurality of LED strings, respectively, is provided. The integrated circuit includes: an interface circuit coupled to a plurality of serial shift registers coupled in a daisy-chain manner, the interface circuit being configured to receive a first plurality of digital values from the plurality of serial shift registers, receive a second plurality of digital values from the plurality of serial shift registers, identify a first lowest digital value from the first plurality of digital values, and identify a second lowest digital value from the second plurality of digital values, each of the first plurality of digital values corresponding to a voltage level at one end of one of the first plurality of LED strings, each of the second plurality of digital values corresponding to a voltage level at one end of one of the second plurality of LED strings, and the interface circuit being configured to receive a first plurality of digital values from the plurality of serial shift registers, receive a second plurality of digital values from the plurality of serial shift registers, identify a first lowest digital value from the first plurality of digital values, and identify a second lowest digital value from the second plurality of digital values, wherein each of the first plurality of digital values corresponds to a voltage level at one end of one of the first plurality of LED strings, and each of the second plurality of digital values corresponds to a voltage level at one end of one of the second plurality of LED strings. The circuit includes a first register configured to store a first digital value and a second register configured to store a second digital value, the interface circuit configured to compare a first incoming digital value of the first plurality of digital values with the first digital value stored in the first register to identify a first lower digital value, and to compare a second incoming digital value of the second plurality of digital values with the second digital value stored in the second register to identify a second lower digital value; and a converter coupled to the interface circuit, the converter configured to convert the first lowest digital value into a first control signal, convert the second lowest digital value into a second control signal, provide the first control signal to the first power supply to adjust the output voltage of the first power supply, and provide the second control signal to the second power supply to adjust the output voltage of the second power supply.

BRIEF DESCRIPTION OF THE DRAWINGS

1 is a diagram of a prior art multi-channel LED driving system for LCD backlighting using discrete DMOSFETs as integrated circuit sinks and protection voltage clamps.

FIG2A is a schematic diagram of a separate LED driver channel using discrete current sink DMOSFETs and a protective high voltage cascode clamp DMOSFET.

FIG2B is a schematic diagram of a separate LED driver channel using discrete high voltage current sink DMOSFETs without a cascode clamp MOSFET.

3A is a schematic diagram of a dual-channel high-voltage smart LED driver with serial bus control having protective high-voltage cascode clamped DMOSFETs and a wide (fat) SLI bus interface.

3B is a schematic diagram of a dual-channel high-voltage intelligent LED driver with serial bus control using high-voltage current sink MOSFETs without cascode clamp MOSFETs and a wide SLI bus interface.

3C is a schematic diagram of a dual-channel high voltage intelligent LED driver with serial bus control using high voltage current sink MOSFETs without cascode clamp MOSFETs and including a prefix multiplexed SLI bus interface.

4A and 4B illustrate diagrams of a multi-channel LED backlight system using a smart LED driver without cascode clamped MOSFETs and including SLI serial bus control.

FIG. 5 is a simplified schematic diagram of the system shown in FIG. 4 illustrating the significant reduction in component material.

FIG. 6 is a schematic diagram illustrating SLI bus-based control of an intelligent backlight system with embedded SLI bus control.

7A is a block diagram of a dual-channel LED driver with embedded CSFB feedback and using a wide SLI bus interface and protocol, with corresponding digital control and timing (DC&T) and analog control and sensing (AC&S) circuits.

7B is a block diagram of a dual-channel LED driver with embedded CSFB feedback and using a prefix-multiplexed SLI bus with corresponding digital control and timing (DC&T) and analog control and sensing (AC&S) circuits.

8 is a block diagram illustrating a multi-function prefix multiplexed SLI bus register with a corresponding three-tiered register-latch architecture including preload and valid latches and embedded CSFB capability.

FIG. 9 is a simplified diagram illustrating the communication path of the SLI bus embedded CSFB signal from the LED driver IC to the interface IC.

10A is a schematic diagram of a dual-channel high voltage smart LED driver with SLI bus embedded CSFB and serial bus control with protective high voltage cascode clamped DMOSFETs and a wide SLI bus.

10B is a schematic diagram of a dual-channel high voltage smart LED driver with SLI embedded CSFB and serial bus control using high voltage current sink MOSFETs without cascode clamp MOSFETs and including a wide SLI bus.

10C is a schematic diagram of a dual-channel high voltage smart LED driver with SLI bus embedded CSFB and serial bus control using high voltage current sink MOSFETs without cascode clamp MOSFETs and including a prefix multiplexed SLI bus.

11A and 11B illustrate a multi-channel LED backlight system using an intelligent LED driver with cascode clamped MOSFETs and an SLI bus embedded CSFB signal.

FIG12 illustrates an embodiment of an analog CSFB circuit.

FIG13 illustrates an embodiment of an analog-to-digital CSFB converter.

FIG14 illustrates an embodiment of a digital-to-analog CSFB converter.

15 is a schematic diagram illustrating SLI bus-based control of an intelligent backlight system with embedded SLI bus control for dual power supplies.

16 is a block diagram of an interface IC for controlling dual power supplies using the wide SLI bus protocol.

17 is a block diagram of an interface IC for controlling dual power supplies using prefix-multiplexed SLI bus protocol and prefix-specific CSFB signals.

18 is a block diagram of a quad CSFB SLI bus protocol and decoding system using a single SLI bus prefix.

19 is a block diagram of an interface IC for controlling multiple power supplies using an alternative quadruple CSFB encoded prefix multiplexed SLI bus protocol.

FIG. 20 is a schematic diagram illustrating SLI bus-based control of an intelligent RGB backlight system with embedded SLI bus control of three power supplies divided into one color for each driver IC.

FIG. 21 is a schematic diagram illustrating SLI bus-based control of an intelligent RGB backlight system with embedded SLI bus control of three power supplies divided into three colors for each driver IC.

FIG22 illustrates an eight-channel LED driver that integrates eight current sink DMOSFETs and four independent CSFB detection circuits for providing independent feedback control to generate four different supply voltages.

DETAILED DESCRIPTION

As described in the Background section, existing backlighting solutions for TVs and large-screen LCDs are complex, expensive, and inflexible. To reduce the cost of backlighting systems for LCDs with local dimming without sacrificing safe and reliable operation, a completely new architecture is clearly needed that at least eliminates the discrete MOSFETs, minimizes heat concentration within any component, facilitates over-temperature detection and thermal protection, and protects low-voltage components from high voltages. While achieving these goals alone may not be enough to achieve a truly cost-effective solution that can meet the demanding cost targets of the home consumer electronics market, such improvements are the first steps toward achieving such goals in order to achieve low-cost local dimming.

The invention described herein enables a new cost-effective and scalable architecture for implementing a safe and economically viable LED backlighting system for large-screen LCDs and TVs with energy-efficient local dimming capabilities. The new LED driver system, functional partitioning, and architecture disclosed herein completely eliminate the aforementioned problems in terms of cost, functionality, and the need for high pin count packages. The new architecture is based on certain fundamental premises, including:

1. Analog control, sensing, and protection of current sink MOSFETs should be functionally integrated with their associated current sink MOSFETs rather than separated into another IC.

2. Basic dimming, phase delay functions, LED current control and channel-specific functions should be functionally integrated with the current sink MOSFETs they control, rather than separated into another IC.

3. System timing, system μC host negotiation and other global parameters and functions that are not unique to a specific channel should not be functionally integrated with the current sink MOSFET.

4. The number of integrated channels, ie, current sink MOSFETs, per packaged device should be optimized for thermal management to avoid overheating while meeting the specified LED current, supply voltage, and LED forward voltage mismatch requirements.

5. Communication with and control of multi-channel LED drivers should employ a low-pin-count approach, ideally requiring no more than three package pins total on an interface IC and on each LED driver IC. This communication approach should only constitute a small fraction of the driver IC’s die area and cost.

6. The level of functional integration in the interface and driver ICs should be balanced to facilitate low-cost and low-pin-count packaging compatible with single-layer PCB assembly.

7. Ideally, the system should be flexible enough to scale to any number of channels without requiring a major redesign of the IC.

The traditional architecture of Figure 1, a centralized controller for driving multiple discrete power MOSFETs, fails to meet even one of these goals, primarily because it requires a central point of control, or "command center," for all digital and analog information processing. Essentially, the command center IC must communicate with its μC host and directly sense and drive each current sink MOSFET. This high degree of component connectivity requires a large number of input and output lines, necessitating a high-pin-count package.

Overview of Distributed LED Driver Architecture

In stark contrast to the prior art, the above design criteria (if not commands) describe a "distributed" system, i.e., a system without the need for central control. In the disclosed distributed system, an interface IC translates information received from a host μC into a simple serial communication protocol, digitally sending instructions to any number of intelligent LED driver "satellite" ICs connected to the serial bus.

An implementation of an LED driver that facilitates the above standards is described in Williams et al., application Ser. No. 13/346,625, entitled “Low Cost LED Driver with Integral Dimming Capability,” which is incorporated herein by reference in its entirety. An alternative version of the LED driver is described in Williams et al., application Ser. No. 13/346,647, entitled “Low Cost LED Driver with Improved Serial Bus,” which is also incorporated herein by reference in its entirety.

The key concepts of these applications are reiterated here, including a hardware description of the interface and LED driver ICs, as well as the operation of several versions of the invented "Serial Lighting Interface," or SLI bus—a serial communication protocol containing parameters specifically related to controlling LED lighting. Each driver ID, in response to its SLI bus digital instructions, locally performs all required LED driver functions, such as dynamic precision LED current control, PWM brightness control, phase delay, and fault detection, without assistance from the interface IC. When "daisy-chained" back to the interface IC, fault conditions such as open LEDs, shorted LEDs, or over-temperature faults occurring in any driver IC can also be communicated back to the interface IC, and ultimately to the host μC.

While the basic architectures disclosed in the two referenced applications are similar, their implementations of the SLI bus protocols and physical interfaces differ. In the "fat" SLI bus protocol described in the first application, long digital words are used to load all control parameters into each LED driver in a single SLI bus broadcast, i.e., all data for each register of each driver IC is removed from the interface IC onto the SLI bus at once. In an alternative version described in the second application, the inventive "prefix-multiplexed" SLI bus protocol, multiple SLI bus broadcasts are used to direct smaller digital words to specific function latches.

Regardless of the SLI bus protocol used, each LED driver IC includes analog current sense feedback (CSFB) input and output pins (CSFBI and CSFBO). These are daisy-chained with the CSFBI and CSFBO of other driver ICs and interface ICs to provide feedback to the high-voltage switch-mode power supply (SMPS), dynamically adjusting the voltage supplying the LED string. The analog CSFB signal requires two package pins on each LED driver IC. Regardless of the number of integrated channels, each LED driver IC outputs only a single CSFB signal.

Each satellite LED driver IC communicates with a central companion interface IC via the SLI bus, interpreting SPI bus commands from the video/graphics processor or scaler IC and translating the SPI bus messages it receives into SLI bus commands. Along with its translated responses, this interface IC provides reference voltages to all LED driver ICs required to ensure good current matching, generates Vsync and grayscale clock (GSC) pulses to synchronize their operation, and monitors each LED driver IC for potential faults. It also facilitates the voltage-to-current conversion of the analog voltage CSFB signal to an analog current CSFB signal using an on-chip operational transconductance amplifier (OTA). The analog CSFB signal requires two package pins on the interface IC (CSFBI and ICSFB): the CSFBI pin is used to receive the voltage CSFB signal from the LED driver IC, and the ICSFB pin is used to transmit the current CSFB signal to the SMPS.

Therefore, by redistributing the functions of the LED backlight system so that precise current control and dimming, fault detection and CSFB sensing and feedback are integrated with the high-voltage current sink MOSFET instead of in the system interface IC, high pin count packages can be eliminated and a scalable distributed system can be achieved.

LED driver with integrated dimming, fault detection and CSFB feedback

An implementation of the present invention's LED driver IC 51 with SLI bus communication is shown in FIG3A and includes a dual-channel driver with integrated current sink DMOSFETs 55A and 55B, cascode clamp DMOSFETs 57A and 57B with integrated high-voltage diodes 58A and 58B, I-accurate gate driver circuits 56A and 56B for accurate current control, analog control and sensing circuitry 60, and digital control and timing circuitry 59. An on-chip bias supply and regulator 62 provides power to the IC.

LED driver IC 51 provides complete control of two channels of 250mA LED drivers with 150V blocking capability and ±2% absolute current accuracy, 12-bit PWM brightness control, 12-bit PWM phase control, 8-bit current control, fault detection for open LED and short LED conditions, and over-temperature detection, all controlled via a high-speed SLI bus and synchronized with other drivers via common Vsync and grayscale clock (GSC) signals. While the specific example shown illustrates cascode clamped DMOSFETs 57A and 57B rated at 150V blocking capability, these devices can be sized for operation from 100V to 300V as needed. The driver IC's 250mA current rating is set by the power dissipation and forward voltage mismatch of the packages in the two LED strings 52A and 52B.

In operation, the LED driver IC 51 receives a data stream on its serial input SI pin, which is fed to the input of the SLI bus shift register 61. The data is clocked at a rate set by the serial clock SCK signal provided by the interface IC (not shown). The maximum clock rate of this data depends on the CMOS technology used to implement the shift register 61, but operation at 10 MHz is achievable even using 0.5 μm linewidth processes and wafer fabrication. As long as the SCK signal continues to run, the data will shift into the shift register 61 and eventually exit the serial output pin SO on its way to the next LED driver IC in the serial daisy chain.

After the data intended for the driver IC 51 arrives in the shift register 61, the SCK signal is temporarily stopped by the interface IC sending the data. Using the "wide" SLI bus protocol, all serial data used to control the parameters of the LED driver ICs is shifted into the SLI bus shift register 61 at once, that is, the data is shifted into the shift register 61 in each driver IC in the daisy chain. Even if only one parameter must be changed, all the data is rewritten to the shift register 61. Thereafter, a Vsync pulse latches the data from the shift register 61 into the latches contained within the digital timing and control (DC&T) circuit 59 and the latches contained within the analog control and sensing AC&S circuit 60, which may include flip-flops or static RAM. Also at the time of the Vsync pulse, any data previously written to the fault latch within the AC&S circuit 60 is copied to the appropriate bit of the SLI bus shift register 61.

Restoration of the serial clock SCK signal shifts the read and write bits within shift register 61 through the daisy chain to the next IC. In a preferred embodiment, the daisy chain forms a loop that connects back to the interface IC. Sending new data into the daisy chain ultimately pushes the existing data in the shift register through the loop and ultimately back to the interface IC. In this way, the interface IC can communicate with the individual LED driver ICs that set the brightness and timing of the LED string, and the individual driver ICs can communicate their respective fault conditions back to the interface IC.

Using this clocking scheme, data can be shifted at high speed through a large number of driver ICs without affecting LED current or causing flicker, because the current and timing control of current sink DMOSFETs 55A and 55B only change with each new Vsync pulse. Vsync can be varied from 60Hz to 960Hz, with the grayscale clock frequency scaling proportionally, typically 4096 times the Vsync frequency. Because Vsync is low, below 1kHz, when compared to the SLI bus clock SCK frequency, the interface IC has the flexibility to modify and resend data, interrogating the fault latch multiple times within a given vertical sync pulse duration.

Starting with the Vysnc pulse, DC&T circuit 59 generates two PWM pulses to switch the outputs of I precision gate driver circuits 56A and 56B, turning them on and off after the appropriate phase delay and for the appropriate pulse width duration, or duty cycle, D. I precision gate driver circuits 56A and 56B sense the current in current sink MOSFETs 55A and 55B, respectively, and provide the appropriate gate drive voltage to maintain the target current during the time that each current sink MOSFET is enabled by the PWM pulse provided by each I precision gate driver circuit. The operation of the I precision gate driver circuit is thus that of a "gated" amplifier that is digitally pulsed on and off, but controls the current in the LED to an analog parameter.

The peak current is set globally for all LED driver ICs by the Vref signal and by the value of the Iset resistor 54. In a preferred embodiment, the Vref signal is generated by the interface IC, or it can be provided as an auxiliary output from the SMPS.

The specific current in any one LED string can be further controlled via the SLI bus using an 8- to 12-bit word-based Dot latch, which adjusts the current in the current sink MOSFET to a percentage of the peak current value in 256 to 4096 distinct steps, from 0% to 100%. In this way, using the newly disclosed architecture, precise digital control of LED current is possible, emulating the functionality of a current-mode digital-to-analog converter, or "current DAC." In LCD backlighting applications, this feature can be used to calibrate backlight brightness, improve backlight uniformity, or operate in 3D mode.

As shown, the current flowing through LED string 52A is controlled by current sink DMOSFET 55A and corresponding I-accurate gate driver circuit 56A. Similarly, the current flowing through LED string 52B is controlled by current sink DMOSFET 55B and corresponding I-accurate gate driver circuit 56B. The maximum voltage applied to current sink DMOSFETs 55A and 55B is limited by cascode clamp DMOSFETs 57A and 57B. As long as the number of LEDs "m" is not too large, the voltage +VLED will not exceed the breakdown voltage of PN diodes 58A and 58B, and the maximum voltage across the current sink MOSFETs will be limited to approximately 10V, a threshold voltage below the gate bias applied to cascode clamp DMOSFETs 57A and 58B by bias circuit 62. Bias circuit 62 also generates a 5V Vcc supply to operate its internal circuitry from a 24V VIN input using a linear voltage regulator and filter capacitor 53.

The drain voltage on current sink DMOSFETs 55A and 55B is also monitored by AC&S circuit 60 and compared to the overvoltage value stored in its SLED register from SLI bus shift register 61. If the drain voltage is below the programmed value, the LED string is operating normally. However, if the voltage rises above the specified value, one or more LEDs are shorted, and a fault is detected and recorded for that particular channel. Similarly, if the I Precision gate driver circuit cannot maintain the required current, that is, the LED string is operating in "undercurrent," this means that the LED has failed open and circuit continuity is lost. The channel is then turned off, its CSFB signal is ignored, and a fault is reported. This "undercurrent" can be sensed by monitoring the current sink DMOSFET for a saturated condition, meaning that the I Precision gate driver circuit is driving the gate of the current sink DMOSFET as "fully on" as possible, or alternatively by monitoring the voltage drop across the input terminals of the I Precision gate driver circuit. When the voltage at the input of the I precision gate driver circuit drops too low, an undercurrent condition occurs, thereby indicating an open LED fault.

If an overtemperature condition is detected, a fault is reported, and the channel is left on and conducting until the interface IC sends a command to shut down the channel. However, if the temperature continues to rise to a dangerous level, the AC&S circuit 60 will independently disable the channel and report the fault. Regardless of the nature of the fault—a shorted LED, an open LED, or overtemperature—as soon as a fault occurs, the open-drain MOSFET within the AC&S circuit 60 will activate and pull the FLT pin low, signaling to the host μC that a fault condition has occurred.

AC&S circuit 60 also includes an analog current sense feedback (CSFB) signal, which reflects the voltages at the drains of the two current sink DMOSFETs 55A and 55B and at the CSFBI input pin to determine which of the three voltages is lowest and pass that voltage to the CSFBO output pin. In this way, the lowest current sink MOSFET source voltage, and therefore the LED string with the highest forward voltage drop, is passed to the input of the next driver IC and ultimately back to the interface IC, which responsively generates the CSFB signal used by the SMPS to provide the correct +V _LED to the power rail for that LED string. The integrated current sense feedback function uses two pins (CSFBI and CSFBO) on each LED driver IC and outputs only one analog signal on the CSFBO pin, regardless of the number of channels integrated into LED driver IC 51.

In the manner described above, an LED driver IC 51 with integrated dimming and fault detection capabilities can be implemented without the need for a central interface IC.

An alternative implementation of an LED driver 65 that meets the above criteria is shown in FIG3B . Integrated into LED driver IC 66, LED driver 65 is a dual-channel driver with integrated current sink DMOSFETs but no cascode clamping OSFETs. Instead, current sink DMOSFETs 72A and 72B include integrated high-voltage diodes 73A and 73B, designed to maintain a high voltage when DMOSFETs 72A and 72B are in the off condition. Typically, such a design is best suited for operation below 100V, but can be extended to 150V if needed. As in LED driver IC 51 of FIG3A , I-accurate gate driver circuits 71A and 71B facilitate accurate current control, controlled by analog control and sensing circuitry 70 and digital control and timing circuitry 74. An on-chip bias supply and voltage regulator 69 powers LED driver IC 66, in this case from Vcc rather than the 24V input as in driver IC 51. Driver IC 66 operates similarly to driver IC 50 , except for the lack of the cascode clamp DMOSFET, being controlled via its SLI bus 75 .

The LED driver IC 66 includes an integrated current sensing feedback function using two pins and outputs only one analog signal CSFBO regardless of the number of integrated channels.

An implementation of the inventive LED driver 80 using a prefix-multiplexed SLI bus is shown in FIG3C . LED driver 80 is a dual-channel driver and is implemented on an LED driver IC 81. The LED driver includes current sink DMOSFETs 87A and 87B with integrated high-voltage diodes 88A and 88B, I-accurate gate driver circuits 86A and 86B, analog control and sensing (AC&S) circuitry 85, and digital control and timing (DC&T) circuitry 89. An on-chip bias supply and voltage regulator 84 powers LED driver IC 81 from the Vcc input.

The LED driver 80 provides complete control of two channels of 250mA LED drivers with 150V blocking capability and ±2% absolute current accuracy, 12-bit PWM brightness control, 12-bit PWM phase control, 8-bit current control, fault detection for open LED and short LED conditions, and over-temperature detection, all controlled via a high-speed SLI bus and synchronized with other drivers via common Vsync and grayscale clock (GSC) signals. While the specific example shown illustrates current sink DMOSFETs rated for 150V blocking capability, these devices can be sized for operation from 100V to 300V as needed. The device's 250mA current rating is set by the package's power dissipation and forward voltage mismatch in the two LED strings being driven. Above the 100V rating, it is advantageous to integrate a high voltage cascode clamp DMOSFET (not shown) in series with current sink DMOSFETs 87A and 87B, whereby current sink MOSFETs 87A and 87B do not need to operate above the clamp voltage, ie, above 12V.

In operation, LED driver IC 81 receives a stream of data on its serial input SI pin and feeds it to the input of prefix-multiplexed SLI bus shift register 90. This data is clocked at a rate set by a serial clock SCK signal provided by an interface IC (not shown). The maximum clock rate of this data depends on the CMOS technology used to implement shift register 90, but operation at 10 MHz is achievable even using 0.5 μm linewidth processes and wafer fabrication. As long as the SCK signal continues to operate, the data will shift into shift register 90 and eventually exit to serial output pin SO on its way to the next device in the serial daisy chain.

After the data corresponding to a particular driver IC arrives in shift register 90, the SCK signal is temporarily deasserted by the interface IC sending the data. Decoder 91 interprets the function latch and channel to be controlled and directs multiplexer 92 to connect the data registers within SLI bus interface 90 to the appropriate function latches within digital control and timing (DC&T) circuitry 89 or analog control and sensing (AC&S) circuitry 85.

Thereafter, the Vsync pulse latches the data from the data shift register in the SLI bus 90 into latches, which may comprise flip-flops or static RAM, contained within the DC&T circuit 89 or the AC&S circuit 85. In the event that the decoder instructs the SLI bus to interrogate the fault latch within the AC&S circuit 85, then any data previously written to the fault latch within the AC&S circuit 85 will be copied to the appropriate bits of the SLI bus shift register 90 at the time of the Vsync pulse.

The restoration of the serial clock SCK signal shifts the read and write bits within the shift register 90 through the daisy chain to the next IC. In a preferred embodiment, the daisy chain forms a loop that connects back to the interface IC that sent the data. Sending new data into the daisy chain ultimately pushes the existing data in the shift register through the loop and ultimately back to the interface IC. In this way, the interface IC can communicate with each LED driver IC to set the LED string brightness and timing, and each driver IC can communicate its own fault conditions back to the interface IC.

Using this clocking scheme, data can be shifted through a large number of driver ICs at high speed without affecting the LED current or causing flicker, because the current and timing control of the current sink DMOSFETs 87A and 87B only change with each new Vsync pulse. Vsync can be varied from 60Hz to 960Hz, with the grayscale clock frequency scaling proportionally, which is typically 4096 times the Vsync frequency. Because Vsync is low, below 1kHz, when compared to the frequency of the serial clock SCK signal, the interface IC has the flexibility to modify and resend data, as well as to interrogate the fault latch multiple times in the interval between consecutive Vsync pulses.

Because the data registers within the SLI data bus 90 are not large enough to write to all the functional latches within the DC&T circuit 89 and AC&S circuit 85 from a single SLI bus word or data packet in the prefix-multiplexed or "narrow" SLI bus protocol, the interface IC must send multiple SLI bus packets to the driver IC to load all the latches. This situation arises at startup when all the functional latches are first initialized, or when the data in more than one functional latch must be changed simultaneously. If the data controlling the I-precision gate driver circuits 86A and 86B were allowed to change gradually in multiple steps over several Vsync periods—for example, first changing the Φ latch, then the D latch, and so on—a viewer might be able to discern the step changes as flicker or noise in the video image. Several inventive solutions to this potential problem are disclosed in the aforementioned application Ser. No. 13/346,647 to Williams et al., entitled "Low Cost LED Driver with Improved Serial Bus," in the section "Simultaneously Loading Multiple Functional Latches."

After the function latch data has been loaded, starting with the next Vysnc pulse, DC&T circuit 89 generates two PWM pulses to switch the outputs of I precision gate driver circuits 86A and 86B on and off after the appropriate phase delay and for the appropriate pulse width duration, or duty cycle, D. I precision gate driver circuits 86A and 86B sense the current in current sink MOSFETs 87A and 87B, respectively, and provide the appropriate gate drive voltage to maintain the target current during the time that current sink MOSFETs 87A and 87B are enabled by the PWM pulses from I precision gate driver circuits 86A and 86B. The operation of the I precision gate driver circuit is thus similar to that of a "gated" amplifier, which pulses on and off digitally, but controls the current in the LED as an analog parameter.

The peak current in all LED driver circuits is set globally by the Vref signal and by the value of the Iset resistor 82. In a preferred embodiment, the Vref signal is generated by the interface IC, or it can be provided as an auxiliary output from the SMPS. In an alternative embodiment, the channel-specific Dot correction can be removed, and Vref can be modulated to facilitate global current control of the LED current.

In a driver capable of channel-specific Dot correction, the current in any one LED string can be controlled via the SLI bus by a Dot latch, preferably consisting of an 8- to 12-bit word. This Dot latch adjusts the current in the current sink MOSFET to a percentage of the peak current value in 256 to 4096 distinct steps, from 0% to 100%. In this way, using the newly disclosed architecture, precise digital control of the LED current is possible, emulating the functionality of a current-mode digital-to-analog converter, or "current DAC." In LCD backlighting applications, this feature can be used to calibrate backlight brightness, improve backlight uniformity, or operate in 3D mode.

The structure and operation of I-accurate gate driver circuits 86A and 86B and AC&S circuit 85 are discussed in detail in the above-referenced application Ser. No. 13/346,625 to Williams et al., entitled “Low Cost LED Driver with Integral Dimming Capability.”

As shown, the current flowing through LED string 83A is controlled by current sink DMOSFET 87A and corresponding I-accurate gate driver circuit 86A. Similarly, the current flowing through LED string 83B is controlled by current sink DMOSFET 87B and corresponding I-accurate gate driver circuit 86B. Without the cascode clamping MOSFET, the maximum voltage applied to current sink DMOSFETs 87A and 87V is limited to operate below the breakdown voltage of high voltage diodes 88A and 88B. Bias circuit 84 generates internal chip bias from the 5V Vcc input.

The drain voltage on current sink DMOSFETs 87A and 87B is also monitored by AC&S circuit 85 and compared to the overvoltage value stored in its SLED register from SLI bus 90. If the drain voltage is below the programmed value, the LED string is operating normally. However, if the voltage rises above the specified value, one or more LEDs are shorted, and a fault is detected and recorded for that particular channel. Similarly, if the I Precision gate driver circuit cannot maintain the required current, that is, the LED string is operating in "undercurrent," this means that the LED has failed open and circuit continuity has been lost. The channel is then shut down, its CSFB signal is ignored, and a fault is reported. This "undercurrent" can be sensed by monitoring the current sink DMOSFET for a saturated condition, meaning that the I Precision gate driver circuit is driving the gate of the current sink DMOSFET as "fully on" as possible, or alternatively by monitoring the voltage drop across the input of the I Precision gate driver circuit. When the voltage at the input of the I Precision gate driver circuit drops too low, an undercurrent condition occurs, thereby detecting an open LED fault.

If an overtemperature condition is detected, a fault is reported, and the channel is left on and conducting until the interface IC sends a command to shut down the channel. However, if the temperature continues to rise to a dangerous level, the AC&S circuit 85 will independently disable the channel and report the fault. Regardless of the nature of the fault—a shorted LED, an open LED, or overtemperature—as soon as a fault occurs, the open-drain MOSFET within the AC&S circuit 85 will activate and pull the FLT pin low, signaling to the host μC that a fault condition has occurred.

AC&S circuit 85 also includes an analog current sense feedback (CSFB) signal, which reflects the voltages at the drains of the two current sink DMOSFETs 87A and 87B and at the CSFBI input pin to determine which of the three voltages is lowest and pass that voltage to the CSFBO output pin. In this way, the LED string with the lowest current source voltage, and therefore the highest forward voltage drop, is passed to the input of the next LED driver and ultimately back to the SMPS to power the +V _LED rail. The integrated current sense feedback function within LED driver IC 81 uses two pins and outputs only one analog signal, CSFBO, regardless of the number of integrated channels.

In the manner described above, a two-channel LED driver 81 with integrated dimming and fault detection capabilities can be implemented without the need for a central interface IC.

SLI bus interface IC and system applications

The system 100 in Figure 4 illustrates an application of a distributed system for LED backlighting with local dimming implemented in the manner specified in this disclosure. The figure illustrates an interface IC 101 driving a series of LED driver ICs 81A-81H with integrated dimming and fault detection powered by a common SMPS 108.

Each of the LED driver ICs 81A-81H (sometimes individually referred to herein as LED driver IC 81) can include a device utilizing the prefix-multiplexed SLI bus protocol as shown in FIG3 , or alternatively, can include a device utilizing a wide bus protocol such as the device shown in FIG3A and 3B . Each driver IC 81 can similarly incorporate a high-voltage current sink DMOSFET as shown in FIG3B and 3C , or alternatively can integrate a current sink DMOSFET with cascode clamp protection such as that shown in FIG3A . In system 10 , LED driver IC 81 is illustrated without multiplexer 92 and decoder 91 (shown in FIG3C ), with the understanding that such functionality is embedded within SLI bus interface 90 when desired, i.e., whenever the prefix-multiplexed SLI bus protocol is utilized.

Five common signal lines 107, including three digital clock signals, a digital fault signal, and an analog reference voltage, connect the interface IC 90 to each driver IC 81. A timing and control circuit 124 generates Vsync and GSC signals synchronized with data received from the A-host μC (not shown) via the SPI bus interface 122. The timing and control circuit 124 also monitors the FLT interrupt line to immediately detect potential problems. A reference voltage source 125 provides a global reference voltage to the system to ensure good channel-to-channel current matching. A bias supply circuit 126 powers the interface IC 101 from the VIN voltage supplied by the fixed +24V power rail 110 generated by the SMPS 108. The bias supply circuit 126 also generates a regulated supply voltage, Vcc, to power the LED drivers 81A-81H. The Vcc supply voltage is filtered by a capacitor 102.

In this example, each LED driver 81A-81H includes two channels of high voltage current control including current sink MOSFETs 87A-87Q with integrated HV diodes 88A-88Q, I-accurate gate driver circuits 86A-86Q, DC&T circuits 89A-89H, AC&S circuits 85A-85H, and serial SLI bus interface shift registers 90A-90H. Although LED driver IC 81 is similar to driver IC 66 shown in FIG3B and lacks the cascode clamp circuit, this system configuration works just as well as LED driver IC 51 shown in FIG3A, except that the 24V VIN supply is used to power the LED driver IC and bias the gates of the cascode clamp DMOSFETs instead of Vcc.

In the example shown, the SLI bus 113, including lines 113A-113I connecting LED drivers 81, comprises a daisy chain in which the SO serial output of SLI circuitry 123 within interface IC 101 is connected via line 113A to the SI input of LED driver 81A, the SO output of LED driver 81A is connected via line 113B to the SI input of LED driver 81B (not shown), etc. SLI bus 113H is connected to the SI input of the last LED driver 81H shown in system 100. The SO output of LED driver 81H is in turn connected via line 113I to the SI input of SLI circuitry 123 within interface IC 101. In this manner, SLI buses 113A-113I (collectively, SLI bus 113) form a complete loop originating from interface IC 101, traveling through each of LED driver ICs 81A-81H (collectively, LED driver ICs 81), and back to itself. Data is shifted out of the SO pin of interface IC 101 while a bit string of equal length is returned to the SI pin of interface IC 101 .

SLI circuitry 123 generates the required SLI bus serial clock SCK signal. Because LED driver IC 81 does not have a chip address, the number of bits clocked via SLI bus 113 must be appropriately correlated to the number of devices being driven. The number of devices being driven, and therefore the number of bits clocked via SLI bus 113, can be adjusted via software programming the data exchange within SPI bus interface 112 or via hardware modifications to interface IC 101. In this way, the number of channels within system 100 can be flexibly varied to match the size of the display. The number of bits shifted across SLI bus 113, i.e., broadcasted on bus 113, depends on the SLI bus protocol employed and the total number of bits in SLI bus shift registers 90A-90H. For example, a "wide" SLI bus protocol requires 72 to 88 bits per two-channel LED driver, while a prefix-multiplexed SLI bus requires significantly less, for example, a fixed 32 bits per LED driver IC, regardless of the number of channels integrated into each driver IC.

When a hardware interface IC 101 is used to control SLI bus communications, modifying registers in the SLI bus circuitry 123 to shift out fewer or more bits requires modifications in the manufacture or design of the interface IC 101. An alternative approach involves replacing the interface IC 101 with a programmable interface IC that uses software to adjust the drivers to accommodate fewer or more LED drivers in the daisy chain.

The current sense feedback (CSFB) signal delivered to SMPS 108 is generated by analog daisy chaining. The CSFBI input pin on LED driver IC 81H is connected to Vcc via line 112I. The CSFBO output pin of LED driver IC 112H is connected to the CSFBI input pin of LED driver 81G via line 113H, and so on. Each driver IC includes one CSFBI input pin and one CSFBO output pin. Finally, line 112B connects the CSFBO output pin of LED driver IC 81B to the CSFBI input pin of LED driver IC 81A, which in turn connects its CSFBO output pin to the CSFBI input pin of interface IC 101 via line 112A. The CSFB signal drops in voltage whenever it passes through a driver IC driving an LED string with a higher forward voltage drop, Vf, than the previous string.

As a daisy chain, there is no common line with a specific voltage. Instead, the CSFB voltage cascades from the first LED driver IC to the last LED driver IC in the chain, with the final CSFB voltage on line 112A representing the LED string with the highest Vf in the entire LED array. Operational transconductance amplifier OTA 127 converts the final CSFB signal on line 112A into a current sense feedback (CSFB) signal at the ICSFB pin of interface IC 101, which is passed to SMPS 108 via line 111. In response to this CSFB signal, SMPS 108 drives the +V _LED voltage on power rail 109 to the optimal voltage for flicker-free lighting without excessive power consumption.

In system 100, only a single value of CSFB signal 111 is generated by interface IC 101 and CSFB daisy chains 112A-112I to drive SMPS 108. In systems requiring more than one +V _LED supply voltage, such as in larger displays with higher current illumination or displays with RGB backlighting, more than one interface IC 101 is needed to power more than one SMPS. For example, by duplicating the entire system 100 for different LED colors—i.e., one system for red LEDs, one for blue LEDs, and a third for green LEDs—this architecture can be expanded to multiple SMPS solutions, albeit at a relatively higher cost. Thus, three instances of interface IC 101 would collectively communicate with a common backlight μC and scaler IC via a shared SPI bus, which would otherwise operate independently. Unfortunately, this approach also triples the number of interconnect wires, significantly complicating the PCB design.

FIG5 is a simplified block diagram of system 100, illustrating the significantly reduced construction materials achieved by using intelligent LED drivers with SLI serial bus control and eliminating high-pin-count interface ICs. As shown, sixteen strings of LEDs 83A-83Q are driven by only eight small LED drivers 81A-81H, all of which are controlled by interface IC 101 and SLI bus 113A-113I in response to host μC 7 and scaler IC 8. Compared to FIG1 , which includes 32 discrete MOSFETs and a 72-pin interface IC, the new architecture significantly reduces system cost. Utilizing significantly fewer components also enhances system reliability.

System 100 is also easy to deploy because the SLI bus protocol is used only between interface IC 101 and satellite LED drivers 81A-81H. Communication between μC 7 and interface IC 101 or scaler IC 8 still uses the more complex, higher-overhead SPI bus. In some systems, interface IC 101, microcontroller 7, and the intermediate SPI bus interface can be eliminated, and algorithm control can instead be moved into scaler 8 to facilitate a fully scalable system under complete software control.

As shown, only two analog signals are present in system 100: a common Vref on one of lines 107, and a daisy-chained CSFB signal on lines 113A-113I. The analog feedback voltage CSFB, or optionally the analog feedback current ICSFB signal, controls + _VLED of SMPS 108. In cases where SMPS 108 requires an analog current rather than a voltage for its feedback input, interface IC 101 is required to convert the analog feedback voltage at its CSFBI pin into the analog feedback current ICSFB signal on line 111. An operational transconductance amplifier, or OTA,—a specialized precision analog circuit integrated within mixed-signal interface IC 101—performs this function. With few analog signals and no discrete DMOSFETs with high-impedance inputs, system 100 is relatively immune to noise.

The SMPS 108 in the system 100 is controlled using a single CSFB signal provided via the interface IC 101, derived from the CSFB signals on lines 112A-112I, which is limited to operating with a single SMPS 108. With only a single power supply and feedback signal, the maximum power of the backlight module is limited to the power handling capabilities of the SMPS 108. At high power levels, it becomes desirable to "split" the power supply into multiple supplies in order to maintain higher converter efficiency and cooler operation. In the configuration shown, multiple CSFB signals cannot be provided without increasing the number of interface ICs 101 to equal the number of switch-mode power supplies used.

Furthermore, limited to a single +V _LED supply, the statistical range of LED string voltage mismatch increases with the number of strings, resulting in higher power dissipation in the LED driver ICs 81A-81H, higher delivered power required by the SMPS 108, higher heat generation, and lower overall backlight system efficiency.

The single CSFB signal in system 100 also prevents its application in an RGB backlight module unless the entire system is tripled, with one system for driving strings of red LEDs, another system for driving strings of green LEDs, and a third system for blue LEDs.

Even with a single CSFB line 11 to the SMPS 108, each LED driver IC 81A-81H must still dedicate two of its sixteen pins to the analog CSFBI and CSFBO signals, which reduces the number of package pins that could otherwise be used to increase the number of LED driver channels, to incorporate new features, or to use to reduce the thermal resistance of the package.

What is needed is a means of supporting multiple CSFB signals that eliminates the need for, and benefits from, the two pins dedicated to the CSFB function on each LED driver IC.

LED backlighting system with SLI bus embedded CSFB

To reiterate, the system 100 shown in Figure 5 illustrates current sense feedback signals on lines 112A-112I connecting the LED driver IC 81 to the interface IC 101 and ultimately to the SMPS 108 via line 111. The function of the current sense feedback or CSFB is to measure the voltage across each LED string 82, determine which string has the highest forward voltage, and control the + _VLED output of one power rail 109 that powers all of the LED strings to ensure that + _VLED is sufficient for each string to operate at a specified and constant level of current.

One disadvantage of this approach is that the analog CSFB signal requires two pins on each LED driver IC, which wastes one-eighth of the pins on a 16-pin package—pins that could be invested in improving thermal resistance, adding functionality, or increasing the number of channels in the driver. Another disadvantage of using analog CSFB signals is that there is no convenient means to facilitate support for several CSFB signals for RGB and multiple SMPS backlight systems.

Because the signals on SLI bus 113 also interconnect the same LED driver IC to interface IC 101, the CSFB signal can be digitally embedded in the SLI bus signal, eliminating the need for analog CSFB signals on lines 112A-112H. The benefits of doing so are disclosed herein.

FIG6 illustrates an LED backlight system 170 with embedded CSFB. Compared to the previously described system 100, the only components that need to be changed to embed the CSFB signal into the SLI bus are the LED driver ICs 174H-174H (sometimes referred to herein as driver ICs 174) and the interface IC 171. Thus, the LED driver ICs 174 include analog-to-digital converters to convert the voltage feedback into a digital equivalent and embed this information within the SLI bus data stream 161. This embedded CSFB signal within the digital SLI bus protocol is then converted back to an analog signal by a DAC, or digital-to-analog converter, contained within the interface IC 171. Thus, the CSFB functionality embedded within the SLI bus protocol and interface advantageously eliminates the need for an analog CSFB signal and dedicated package pins.

As described, the embedded CSFB function is implemented to control a single SMPS and +V _LED power rail. The invented embedded CSFB method can be easily modified to control multiple power supplies for higher power backlight systems or for RGB backlighting applications. This alternative embodiment of the invention is described later in this application.

It should be noted that in other embodiments of the present invention, interface IC 171 can be eliminated and its functionality redistributed to other components within the system. For example, the digital functions of dimming, phase control, dot correction, and fault management can be performed within μC 7 or within scaler IC 8, while the analog Vref can be generated within SMPS 108, added to μC 7, or provided by a small discrete IC. Similarly, the conversion of the digital representation of the CSFB signal on SLI bus 161 to the analog CSFB feedback signal on line 160 can be integrated into SMPS 108, added to μC 7, or provided by a small discrete IC, possibly within the same small IC, such as an operational transconductance amplifier and Vref integrated into an 8-pin package.

To embed CSFB signals into the SLI bus 161, various SLI bus protocols can be employed. One such protocol, the so-called "wide" SLI bus protocol and hardware, involves relatively long digital words containing all parameter information for each channel and each function in the SLI bus transmission. A second SLI bus protocol, referred to herein as "prefix multiplexed," reduces the size of SLI bus commands to a fixed size of 32 bits and facilitates updating only those parameters that change without rebroadcasting all parameter data for each channel and function each time a specific update is required. The following sections describe these two SLI bus protocols and the implementation of the SLI bus-embedded CSFB functionality in each version.

Implementing embedded CSFB into wide SLI bus protocols & interfaces

One implementation of an LED driver with SLI bus embedded CSFB functionality is shown in FIG7A . Included in LED driver IC 200 is an SLI bus shift register 201 comprising shift registers 220A, 221A, 222A, 220B, 221B, 222B, 223, 224, and 225, a digital control and timing (DC&T) circuit 202, and an analog control and sensing (AC&S) circuit 203. The example shown is a two-channel driver, but other numbers of channels can be implemented in a similar manner.

The LED driver IC 200 is mixed signal, combining digital and analog signals, and includes a digital SLI shift register 201 connected to a digital DC&T circuit 202 via several parallel data buses, typically 12 bits wide, and also connected to an analog AC&S circuit 203 via various parallel data buses ranging from 4 bits to 12 bits wide.

The output of DC&T circuit 202 digitally switches I-accurate gate driver circuits 206A and 206B and current sink DMOSFETs 205A and 205B on and off with precise timing synchronized by Vsync and the GSK grayscale clock signal. Current sink DMOSFETs 205A and 205B control the currents I _LEDA and I _LEDB in two LED strings (not shown) in response to analog signals from AC&S circuit 203, which in turn control the gate drive signals output by I-accurate gate driver circuits 206A and 206B. The gate drive signals are analog, using amplifiers with feedback to ensure that the conduction current in each of current sink DMOSFETs 205A and 205B is a fixed multiple of a reference current I ref , also provided by AC&T circuit 203.

Although the LED driver IC system 200 includes only current sink DMOSFETs 205A and 205B, the circuit is compatible with either a cascode-clamped LED driver output as shown in FIG3A or a high-voltage current sink version as illustrated in FIG3B and FIG3C . To implement the cascode-clamped version, two high-voltage N-channel DMOSFETs are connected in series with the current sink DMOSFETs 205A and 205B, with their source terminals connected to the drain terminals of the current sink DMOSFETs and their drain terminals connected to the anodes of the corresponding driven LED strings.

Both the drain and source voltages of current sink DMOSFETs 205A and 205B are used to monitor the status of the LED string via LED detection circuit 215. Specifically, the source voltage is used to detect an open LED string, while the drain voltage is used to detect a shorted LED. A fault-set latch 224 can be used to program the voltage level for detecting a shorted LED.

The drain voltages of current sink DMOSFETs 205A and 205B are also used by CSFB circuit 218A to determine the channel with the highest LED voltage drop, i.e., the DMOSFET with the lowest drain voltage. CSFB circuit 218A outputs a voltage equal to the lower of the drain voltages of current sink DMOSFETs 205A and 205B to analog-to-digital (A/D) converter 218B, and A/D converter 218B converts this lower drain voltage to its equivalent digital value, which is stored in CSFB shift register 223 within SLI bus shift register 201. While the CSFB voltage can be continuously updated, this is not normally necessary for controlling the relatively low-bandwidth SMPS powering the LED strings. In many cases, one sample per Vsync pulse is sufficient.

In operation, data is clocked into the SI shift register 201 at a clock rate of SCK via the serial input pin SI. This includes shifting data into 12-bit data registers 220A and 220B for PWM on-time data for channels A and B, 12-bit data registers 221A and 221B for phase-delayed data for channels A and B, 12-bit data registers 222A and 222B for "dot" current data for channels A and B, and 12 bits for fault information, including an 8-bit register 224 for Flt setting and a 4-bit register 225 for Flt status. Additionally, for drivers with embedded CSFB, the SLI bus shift register 201 also includes a 4-bit register 223 containing the word output by the A/D converter 218A, representing the CSFB voltage output of the LED driver IC 200. Data within these register periods is clocked out of the SO pin as new data is clocked in. Pausing the SCK signal holds the data statically within the shift register.The terms "channel A" and "channel B" are arbitrary and are used only to identify the outputs and their corresponding data in the SLI data stream.

After receiving a Vsync pulse, data from PWM A register 220A is loaded into D latch 211A, and data from Phase A register 221A is loaded into Φ latch 212A of Latch & Counter A circuit 210A. Simultaneously, data from PWM B register 220B is loaded into D latch 211B, and data from Phase B register 221B is loaded into Φ latch 212B of Latch & Counter B circuit 210B. After receiving a subsequent clock signal on the GSC grayscale clock, both counters count the number of pulses in their Φ latches 212A and 212B, respectively, and then enable current to flow in I-accurate gate driver circuits 206A and 206V, respectively, illuminating the LED string connected to that particular channel. The channel remains enabled and conductive for the duration of the number of pulses stored in D latches 220A and 220B. The output is then switched off and awaits the next Vsync pulse to repeat the process. The DC&T circuit 202 thus synchronizes the two PWM pulses according to the SLI bus data.

Also synchronized with the Vsync pulse, the data stored in Dot A and Dot B latches 222A and 222B is copied to D/A converters 213A and 213B, setting the current in DMOSFETs 205A and 205B. As shown, D/A converters 213A and 213B are discrete circuits that provide an accurate fractional portion of Iref to set the current in the LED string. Alternatively, in a preferred embodiment, Iaccurate gate driver circuits 213A and 213B incorporate adjustable current mirrors using binary weighting and are capable of setting a fractional portion of the desired maximum current. The reference current Iref, representing the maximum channel current, is set by Rset resistor 204 and the Vref input in bias circuit 217.

Fault detection involves the LED integrated circuit 215 comparing the source and drain voltages of current sink DMOSFETs 205A and 205B with the values stored in the fault latch 214. These values are copied from the Flt setting register 224 at each Vsync pulse. The temperature detection circuit 216 monitors the temperature of the LED driver IC. Any fault immediately triggers the open-drain MOSFET 219 to turn on and pull the Flt line low, generating an interrupt. This fault information is also written from the fault latch 214 to the Flt status register 225 at the next Vsync pulse.

For LED drivers with embedded SCFB, digital data representing the CSFB value for the LED driver IC 200 is copied from the output of the A/D converter 218 to the CSFB register 223 in the SLI bus shift register 201, synchronized with the Vsync pulse. Although the CSFB data can be refreshed more frequently than once per Vsync pulse, there is no specific convenient timing pulse for using the wide SLI bus protocol to indicate the copying of data from the A/D converter 218B to the CSFB register 223. Without an additional dedicated control pin, a timer must be used for CSFB write operations, but because the GSC and SCK clock signals can start and stop during normal operation, there is no simple way to perform oversampling of the CSFB value.

The implementation of the dimming function and digital-to-analog conversion is further detailed in the above-referenced application Ser. No. 13/346,625 to Williams et al., entitled “Low Cost LED Driver with Integral Dimming Capability.” This application also includes detailed circuit implementation examples for the fault and LED integrated circuits 214 and 215, the reference current source 217, and the current sense feedback (CSFB) circuit 218. Therefore, the details of these components will not be repeated here.

In the manner described, a serial data bus is used to control the amplitude, timing, and duration of current in multiple LED strings, as well as to control the detection of fault conditions in the LED strings and report the occurrence of fault conditions, and to control the +V _LED supply voltage using embedded CSFB information. The SLI protocol is flexible, requiring only that the data sent over the serial bus match the hardware being controlled, specifically that the number of bits sent to each LED driver IC match the bits required by that LED driver IC (typically, each LED driver IC in a given LED driver system requires the same number of bits), and that the total number of bits sent during each Vsync period equals the number of bits required by each LED driver IC multiplied by the number of LED driver ICs.

For example, in FIG7A , a wide SLI bus protocol for one channel, including dot correction, fault setting and fault reporting, and CSFB information, includes 88 bits per dual-channel driver IC, or 44 bits per channel or LED string. If eight dual-channel driver ICs controlling 16 strings of LEDs are connected via a single SLI bus loop, the total number of bits shifted out of the interface IC and across the SLI bus during each Vsync period equals 8 times 88, or 704 bits, which is less than a thousand bits. If the SLI bus is clocked at 10 MHz, the entire data stream can be clocked through each driver IC and to each channel ground in 70.4 microseconds, or 4.4 microseconds per channel.

Although the serial data bus communicates at an "electronic" data rate, i.e., a rate using a MHz clock and megabits of data per second, the Vsync or "frame" rate used to control changes in the image on the LCD display panel occurs at a much slower pace because the human eye cannot perceive changes in the image at any rate approaching the electronic data rate. Although most people are unaware of flicker at a 60Hz frame rate, i.e., 16 image frames per second, a 120Hz TV image looks "clearer" to many people than a 60HZ TV, simply using a direct comparison, in the case of A vs. B comparison. At even higher Vsync rates, such as 240Hz and higher, only "gamers" and video display "experts" claim to see any improvement, primarily in the form of reduced motion blur. There is such a large difference between the electronic data rate and the relatively slow video frame rate that makes serial bus communication possible for backlight drivers.

For example, at 60Hz, each Vsync period consumes 16.7 milliseconds, which is orders of magnitude longer than the time required to send all data to all driver ICs. Even in most advanced TVs running at 8X scan rate and in 960Hz 3D mode, each Vsync/period consumes 1.04 milliseconds, meaning up to 236 channels can be controlled in real time. This number of channels far exceeds the LED driver system requirements for even the largest HDTVs.

The 88-bit "wide" protocol for each dual channel, shown in shift register 201 of FIG7A , enables the interface IC to write or read all the data in each register of each channel at once during each Vsync period. The term "wide" refers to the content of the data word used to control each channel. The wide protocol requires that the data for every variable and every register in a given LED driver IC be included in every packet of data transmitted from the interface IC to that LED driver IC, even if nothing has changed from the previous data packet for that LED driver IC.

If a reduced data protocol is used, that is, one requiring fewer bits per channel, sending data to each channel takes even less time. Because the wide protocol has no timing constraints due to the relatively slow Vsync refresh rate, there is no data rate benefit. However, using fewer bits in the serial communication protocol does reduce the size of the digital shift register and data latch in the LED driver IC, reducing the area of the LED driver IC and lowering the overall system cost.

For example, an alternative two-channel data protocol for the SLI bus with embedded CSFB using a 64-bit data set rather than the 88-bit data set shown for the LED driver IC 200 in FIG7A is also possible. Such a data set may include 12 bits for PWM brightness duty cycle, 12 bits for phase delay, 8 bits for fault settings, 4 bits for fault status, and 4 bits for one channel of CSFB data, thereby not including 12 bit point correction data. Thus, in this implementation, individual channel current settings and brightness calibration for each LED string are not available.

In LCD panel manufacturing, many manufacturers believe that electronically calibrating the display for uniform brightness is too expensive and therefore commercially impractical. Global display brightness can still be calibrated by adjusting the panel's current setting resistors, such as the value of setting resistor 204 shown in LED driver IC 200, but brightness uniformity in backlight brightness cannot be controlled by the microcontroller or interface IC. Instead, panel manufacturers manually "sort" their LED supply into bins of LEDs with similar brightness and color temperature.

It should be noted that removing Dot data from the SLI bus protocol does not prevent overall display brightness control or calibration. Adjusting the system's global reference voltage, Vref, still allows for global dimming or global current control. For example, in LED driver IC 200, adjusting the value of Vref affects the reference current Iref generated by Iref generator 217. If the Vref voltage is shared by all LED driver ICs, adjusting this voltage will uniformly affect each driver IC and the overall brightness of the panel, independent of PWM dimming control.

Embedding CSFB functionality into the SLI bus is not limited to the wide SLI bus protocol. Instead, using prefix-multiplexed SLI bus protocols and interfaces facilitates greater flexibility and higher CSFB feedback sample rates.

Thus, the limitations and drawbacks of sending long digital words or instructions over a serial bus can be overcome by using a "register address" or "prefix" that is added to the Serial Lighting Interface bus protocol and embedded in each SLI bus communication. When combined with circuitry for decoding and multiplexing SLI bus data, the embedded prefix information enables data to be routed only to the function latch of a specific destination.

Implementing embedded CSFB in prefix-multiplexed SLI bus protocols and interfaces

By specifically sending data only to the latches that need to be updated, the "prefix multiplexed" or "narrow" SLI bus architecture avoids the need to repeatedly and unnecessarily resend digital data, especially redundant data that remains constant or changes infrequently. In operation, after an initial setup, only the latches that are changing are overwritten.

Registers containing fixed data are written only once when the system is first initialized, and no subsequent communication from the interface IC over the SLI bus is required. Because only the latches that are changing are updated, the amount of data sent across the SLI bus is greatly reduced. This inventive method offers several advantages over the wide SLI bus approach, namely:

The number of bits required to integrate the SLI bus shift register is greatly reduced, saving die area and reducing cost, especially in smaller (e.g., two channel) LED driver ICs.

• The effective bandwidth of the SLI bus at any given clock rate is increased because redundant data is not sent repeatedly.

• The SLI bus protocol can be standardized with fixed word lengths and functions without loss of commonality.

An example of a prefix-multiplexed SLI bus is shown in the embodiment of an LED driver IC 230 shown in the schematic circuit diagram of FIG7B . In addition to the alternative LED driver IC 230, FIG7B also shows an SLI bus shift register 231 containing a 16-bit prefix register 232 and a 16-bit data register 233, as well as a prefix decoder and multiplexer (mux) circuit 234. The data in the data register 231 is routed to D latches 211A and 211B and Φ latches 212A and 212B in latch & counter A 210A and latch & counter B 210B, respectively; one of the D/A converters 213A and 213B in the digital control and timing (DC&T) circuit 203; or the fault latch circuit 214 in the analog control and sensing (AC&S) circuit 203. These data transfers are made through the prefix decoder and multiplexer circuit 234, depending on the routing direction contained in the prefix register 232. The prefix decoder & multiplexer circuit 234 therefore decodes the 16-bit data word stored in the prefix register 232 and multiplexes the 16-bit data 223 stored in the data register 233 into the appropriate D, Φ or Dot latch DC&T circuit 202 or AC&S circuit 203.

In the case of the fault latch circuit 214, the multiplexer 234 operates bidirectionally, allowing the data stored in the data register 233 to be written to the fault latch circuit 214, or conversely, allowing the data stored in the fault latch circuit 214 to be written to the data register 233. Similarly, the CSFB data contained in the A/D converter 218B is directed by the multiplexer 234 to be written to the data register 233, depending on the prefix code stored in the prefix register 232.

Although data is copied between the function latches and the SLI bus registers in synchronization with the Vsync pulse in the case of the wide SLI bus protocol, in a prefix-multiplexed SLI bus, some functions do not need to be synchronized with the Vsync pulse, particularly when reading back fault information from the fault latch 214 and CSFB data from the A/D converter 218B. Instead, data can be "pulled" from the LED driver IC into the SLI bus as needed and checked by the interface IC, even at data rates higher than once per Vsync pulse.

In a preferred embodiment, the prefix-multiplexed SLI bus protocol comprises 32-bit words, i.e., 4 bytes in length, which provides a well-balanced compromise between the flexibility of addressing a large number of function latches and maintaining a short wordline length and a small SLI bus shift register size. In the example shown, the SLI bus prefix register 232 is 16 bits in length and the SLI bus data register 233 is also 16 bits in length, which facilitates variables having up to 65,536 combinations to be uniquely written to or read from one of the 65,536 different function latches.

For flexibility and scalability, the SLI bus protocol is designed with a 32-bit prefix multiplexing. While this facilitates a large number of combinations, not all data stored in the SLI bus registers needs to be used. If fewer latches and channels are needed, only a few bits of the prefix need to be decoded to address the required number of function latches. Similarly, if less than 16 bits of precision are required, a smaller number of bits can be used in the data registers within the SLI bus and multiplexed to the target function latches. For example, if the data contained in SLI bus data register 233 represents the PWM brightness duty cycle, 12 bits of data can be multiplexed and loaded into D latch 211A. Meanwhile, if the data contained in SLI bus data register 233 represents the LED current "Dot" setting, the Dot latch within D/A converter 213A only requires 8 bits. The CSFB data read from the A/D converter and latch 218B and written to SLI bus data register 233 can consist of only 4-bit words.

Thus, in a prefix-multiplexed SLI bus, data is repeatedly written by the interface IC into the SLI bus shift register 231 and then multiplexed into one of several function latches 211-214 in a sequential manner, one word at a time. Similarly, data is copied from latches 214 and 218B whenever requested by the interface IC, shifted sequentially through the shift registers in the daisy chain, and returned to the interface IC. In the LED driver IC 200 shown in FIG7B , one SLI bus data register 233 fans out to seven different function latches, and data is read back from two function latches.

The prefix-multiplexed SLI bus 230 is in stark contrast to the wide SLI bus shown in FIG7A , where each register in the SLI bus shift register 201 has a one-to-one correspondence with a functional latch in the LED driver IC, e.g., the SLI bus PWM A register 220A corresponds to the D latch 211A, the SLI bus Phase A register 221A corresponds to the Φ latch 212A, etc. This one-to-one correspondence makes scaling the wide SLI wordline architecture to LED driver ICs with more channels problematic and costly.

The fan-out capability of the prefix-multiplexed SLI bus thus provides a more versatile, lower-cost approach to implementing multi-channel LED drivers than the wide SLI bus protocol. For this and other reasons that will be considered later in this disclosure, the invented prefix-multiplexed SLI bus represents an improved serial lighting interface bus protocol, architecture, and physical interface.

The prefix decoder and multiplexer 234 can be implemented in various ways, as described in the above-referenced application Ser. No. 13/346,647 to Williams et al., entitled "Low Cost LED Driver with Improved Serial Bus." One implementation is shown in the block diagram of FIG8 , in which the 16-bit prefix register in the SLI bus shift register 231 is subdivided into two 8-bit registers, namely, a channel register 232C and a function register 232F. The data register 233 remains unchanged. As shown, the prefix decoder 251 has two output lines, including a channel select output line 254 for selecting which LED channel 255 is being controlled, and a function select output line 252 for controlling which function latch is being interrogated, i.e., written to or read from.

In the example shown, the prefix decoder 251 uses the channel select signal on line 254 to select one of the multiple channels 255, and then uses the function select signal on line 252 to select the function to be controlled. To change the operation of function 256, the multiplexer 253 then writes data from the data register 233 to the preload latch 258. The data is retained in the preload latch 258 until a Vsync pulse occurs, at which time the data is copied from the preload latch 258 to the valid latch 257, thereby changing the operating condition of the analog or digital function 258, such as D, Φ, Dot, etc. The data in the valid latch 257 remains unchanged until the next Vsync pulse occurs.

The operating conditions of the selected channel can be changed in a similar manner by writing data to the preload latch 261 and copying the data to the valid latch 260 in synchronization with the Vsync pulse. Alternatively, the data in the latch 260 can be written from the control function 259 and loaded, i.e., sampled, into the preload latch 216 at regular intervals. The data contained in the preload latch 261 is then copied into the data register 233 of the SLI bus shift register 231 as the decoder 251 selects the corresponding channel and function.

In this way, any number of channels within the LED driver IC, i.e., any number of LED strings, can be independently controlled in real time, which facilitates precise adjustment of each control function 256, 259, as well as other functions, via the shared SLI bus shift register 231 without the need for large shift registers or long digital words.

As shown in FIG8 , the CSFB function can be embedded using the same SLI bus shift register 231 and prefix-multiplexed SLI bus protocol. The CSFB signal 262, i.e., the digital output of the A/D converter, is sampled at regular intervals and written to a sampling latch 263. In some embodiments, the A/D converter and the sampling latch are part of the same unit, as in the case of A/D converter 218B shown in FIG7B . In this way, the most current value of CSFB for a given channel and LED driver IC is always present in the sampling latch 263. Whenever the decoder 251 selects the corresponding channel and the CSFB function is selected, the data contained in the sampling latch 263 is then copied to the data register 233 of the SLI bus shift register 231. Like any other function, the CSFB data is selected by an appropriate and corresponding prefix code. The prefix codes in Table 1 are included as examples for decoding:

Table 1

After data is written to the SLI bus shift register 231, it must be shifted into the interface IC using a corresponding number of SCK pulses. The number of SCK pulses required to shift the data completely through the SLI bus is equal to the number of bits in each SLI bus shift register multiplied by the number of SLI bus shift registers in the SLI bus. Assuming the fixed-length 32-bit protocol shown in Figure 8, and one SLI bus shift register per LED driver IC, the total number of SCK pulses required to shift data from the driver IC furthest from the interface IC in the daisy chain to the CSFBI input of that interface IC is 32 times the number of LED driver ICs.

During shifting, a prefix code is selected to prevent overwriting of data in the SLI bus shift register 233. In a preferred embodiment, this protection can be achieved by using a dedicated prefix function code 251, such as hexadecimal 0E, for loading the SLI bus data register 233 from its corresponding CSFB sampling latch 263. On subsequent broadcasts, as the data from the sampling latch 263 is shifted through the SLI bus daisy chain and into the interface IC to update the feedback signals that control the SMPS, a different prefix code, such as hexadecimal 0F, is used to prevent any reads or writes to or from the SLI bus shift register 233 (this step is referred to as "Execute CSFB" in Table 1 above).

Embedding CSFB functionality within the SLI bus is further illustrated by the schematic block diagram of LED driver system 270 shown in FIG9 . LED driver ICs 272A and 272H, an interface IC 273, LED strings 274A, 274B, 274P, and 274Q, and a switch-mode power supply (SMPS) 293 are shown. In connection with embedded CSFB operation, LED driver IC 272A includes current sink MOSFETs 275A and 275B driving LED strings 274A and 274B, respectively, a CSFB circuit 291A, an analog-to-digital (A/D) converter 275A, a sampling latch 277A, and SLI bus communication using an SLI bus shift register 282A including a prefix register 281A and a data register 280A, a decoder 279A, and its associated multiplexer 278A. For clarity, other functionality within LED driver IC 272A, such as PWM dimming control, dot correction, and fault detection, is not included.

Similarly, LED driver IC 272H includes current sink MOSFETs 275P and 275Q that drive LED strings 274P and 274Q, respectively, a CSFB circuit 291H, an A/D converter 275H, a sampling latch 277H, and SLI bus communication using an SLI bus shift register 282H comprising a prefix register 281H and a data register 280H, a decoder 279H, and its associated multiplexer 278H. Other LED driver ICs 272B-272G (not shown) have the same configuration. Interface IC 273 digitally connects to LED driver ICs 272A-272H in a daisy-chain fashion via SIL bus 294, with each SLI bus output SO connected to the SLI bus input SI of the next IC in the daisy chain. The last LED driver IC 272H in the chain has its SO output connected to the SLI input SI of interface IC 273. The first LED driver IC 272A in the chain has its input connected to the SO output of the interface IC 273 (the output portion of the interface IC 273 is not shown), or alternatively, to any other source of SLI bus data for controlling LED driver ICs.

Interface IC 273 includes an SLI bus shift register 283 including a prefix register 285 and a data register 284, a decoder 287 and its associated multiplexer 286, a digital amplitude comparator 288, a register 289 for storing a digital DCSFB signal, a digital-to-analog (D/A) converter 290, and an operational transconductance amplifier 291 connected to the feedback input of an SMPS 293 in the LED driver system 270 shown in FIG9 using the ICSFB signal, which is a sample of the lowest current CSFB obtained from the LED driver ICs 272A-272H. Interface IC 273 can provide two analog outputs: a current feedback signal ICSFB output by OTA 291, or alternatively, a voltage feedback signal CSFBO output by D/A converter 290 for connection to an SMPS module that requires a voltage rather than a current feedback signal.

Both the ICSFB signal and the CSFBO signal represent the analog equivalent of the digital current sense feedback signal DCSFB. This digital DCSFB signal, sampled at regular intervals, represents the lowest current sense (drain) voltage across the current sink MOSFETs 275A-275Q and is used to detect the LED string 274A-274Q with the highest forward voltage drop. The CSFB signal (whether in the form of ICSFB or CSFBO) in turn controls the voltage + _VLED of the SMPS 293 on power line 271 to generate a voltage + _VLED sufficient to power all LED strings 274, including any string with the highest forward voltage drop.

In operation, interface IC 273 clocks a prefix command into prefix register 281 via the SLI bus daisy chain to each of the eight LED driver ICs 272-272H, instructing each driver IC's multiplexer 278 to copy the current sample contents of sampling latch 277 to data register 280 of its SLI bus shift register 282. For example, in driver IC 272A, the prefix command in prefix register 281A, interpreted by decoder 279A, instructs multiplexer 278A to copy the current sample contents of sampling latch 277A to data register 280A of SLI bus shift register 282A. The same processing and procedures occur in the other LED driver ICs.

Prior to or concurrently with data transfer from sampling latch 277A to SLI bus data register 280A, CSFB circuit 291A measures the drain voltages across current sink MOSFETs 275A and 275B, determines which MOSFET has the lower drain voltage, and passes the lower drain voltage to A/D converter 276A, which converts the voltage to its digital equivalent. The result is temporarily stored in sampling latch 277A. The CSFB voltage can be sampled when data is requested via a prefix code in prefix register 281A, or it can be sampled at regular intervals more frequently than SLI bus communication. Therefore, the data contained in sampling latch 277A represents the most current information regarding the lowest current sink voltage for the two channels integrated within LED driver IC 272A.

Voltage sampling should occur at least once per Vsync period, and can occur at a higher rate. Preferably, it should occur two to three times per Vsync period to improve the accuracy and transient response of the SMPS 293. Sampling more than three times per Vsync period provides reduced return, and excessive sampling, such as ten times per Vsync period, occupies the interface IC with unnecessary tasks. Once the CSFB data provided by the A/D converters 277A-277H of the LED drivers 272A-272H has been loaded into their corresponding SLI bus data registers 280A-280H, the CSFB data must be clocked out of the data registers and into the interface IC 273. The number of SCK pulses required to accomplish this is equal to the number of LED driver ICs 272 in the daisy chain multiplied by the number of bits in each SLI bus shift register 282 in the protocol, which in this case is 32 bits multiplied by 8 driver ICs, or 256 clock pulses.

During or after shifting driver IC CSFB data into SLI bus 283 within interface IC 273, interface IC 273 performs the task of determining which CSFB value is the lowest. It then uses this data to pass a CSFBO or ICSFB signal to SMPS 293, which in turn uses this signal to set the voltage + _VLED on power rail 271. While this data can be stored and analyzed at the end of the SLI bus shift register data transfer, it can also be performed in real time. In one embodiment of the present invention, each CSFB value shifted into SLI bus data shift register 284 by interface IC 273 is compared to the previous value by amplitude comparator 288 and overwritten to register 289 only if it represents a lower voltage than the data preceding it. After all CSFB data from all driver ICs has been compared within one SLI broadcast cycle, the digital data DCSFB within register 289 represents the lowest CSFB value in system 270.

In another aspect of the present invention, a special prefix code in prefix register 285, for example, hexadecimal code "0F" (binary "00001111"), can be used during the SLI bus shift operation to prevent LED driver IC 272 from overwriting CSFB data while shifting data through the SLI bus daisy chain. The same prefix code can be chosen to instruct interface IC 273 to perform a sequential comparison of data arriving during the shift, i.e., during sequential SCK clock pulses, to determine the lowest CSFB signal in the data stream. During this comparison operation, decoder 287 directs multiplexer 286 to the input of digital amplitude comparator 288. This circuit compares the data in SLI bus register 284 with the data in register 289 and overwrites register 289 only if the new data is lower. This process is repeated until CSFB data from each LED driver IC has been shifted into interface IC 273. In other words, in one embodiment of the present invention, a special prefix code can be assigned that never allows the multiplexer to overwrite CSFB data already present in the SLI bus data stream during the shift.

Interface IC 273 then converts this digital representation of the lowest CSFB voltage into an analog voltage CSFBO or an analog current ICSFB, collectively referred to as feedback signal 292, which controls SMPS 293. The characteristics of the analog feedback signal depend on the type of feedback required by SMPS 293. If an analog voltage is required, the CSFBO voltage output of D/A converter 290 can be used, with or without a buffer, to directly drive SMPS 293. If a current feedback signal is required, operational amplifier OTA 291 is used to convert the CSFBO voltage signal into a current signal ICSFB.

Regardless of whether the feedback to the SMPS 293 includes current or voltage, in closed-loop operation, the output voltage of the D/A converter 290 reacts to, i.e., becomes a dynamic function of, the digital CSFB signal DCSFB provided by the digital amplitude comparator 288. In this manner, real-time feedback can be provided digitally to the SMPS 293 via the SLI bus 294, facilitating control of the LED power supply output voltage + _VLED to ensure a suitable voltage for proper illumination of the LED strings 274A-274Q at the desired level of LED current.

LED driver IC with SLI bus embedded CSFB

FIG10A shows an LED driver system 300 with SLI bus communication and embedded CSFB control according to the present invention. Similar to the LED driver IC 51 shown in FIG3A, the LED driver system 300 includes a dual-channel driver IC 301 with integrated current sink DMOSFETs 55A and 55B, cascode clamp DMOSFETs 57A and 57B with integrated high-voltage diodes 58A and 58B, I-accurate gate driver circuits 56A and 56B for accurate current control, digital control and timing (DC&T) circuits 59, and an on-chip bias supply and voltage regulator 62. However, unlike the previously described driver IC 51, the analog control and sense (AC&S) circuits 310 and the wide SLI bus shift register 311 have been modified to embed current sense feedback CSFB information within the SLI bus protocol. Because the SLI bus shift register is "wide," it contains a CSFB register (equivalent to register 223 in FIG. 7A ) dedicated to receiving CSFB data from a sampling latch within AC&S current 310 (equivalent to latch 277 in FIG. 9 ).

Thus, LED driver IC 301 provides complete control of two channels of 250mA LED drivers with 150V blocking capability and ±2% absolute current accuracy, 12-bit PWM brightness control, 12-bit PWM phase control, 8-bit current control, fault detection for open LED and short LED conditions, and over-temperature detection, all controlled via a high-speed SLI bus and synchronized with other drivers via common Vsync and grayscale clock (GSC) signals. While the specific example shown illustrates cascode clamped DMOSFETs rated at 150V blocking capability, these devices can be sized for operation from 100V to 300V as needed. The 250mA current rating of the device is set by the power dissipation and forward voltage mismatch of the package in the two LED strings being driven.

AC&S circuitry 310 within LED driver IC 301 also includes analog current sense feedback, or CSFB, which monitors the signals of the two current sink DMOSFETs 55A and 55B. This signal is converted by an integrated analog-to-digital A/D converter into a digital version of the CSFB voltage, preferably four or more bits in length. This digital CSFB signal, or DCSFB, represents the lowest current source voltage within driver IC 301 and, therefore, the LED string with the highest forward voltage drop. This signal is copied to the CSFB register within the SLI bus shift register 311 and passed across the SLI bus to the interface IC and ultimately back to the system SMPS, supplying the +V _LED power rail.

Unlike the previously described LED driver IC 51, which requires CSFBO and CSFBI pins for outputting and inputting CSFB signals, respectively, LED driver IC 301 embeds its CSFB data within the SLI bus data stream and does not require additional pins to facilitate current sense feedback, regardless of the number of channels integrated into the driver. Consequently, the CSFBO and CSFBI pins are not present in the package containing LED driver IC 301. Consequently, the analog control and sensing circuitry 310 and the wide SLI bus interface 311 have been modified to embed the current sense feedback CSFB information within the SLI bus protocol.

An alternative LED driver 315 with SLI bus communication and embedded CSFB control according to the present invention is shown in FIG10B . Dual-channel LED driver IC 316 includes current sink DMOSFETs 72A and 72B, but omits the cascode clamp MOSFETs. Instead, DMOSFETs 72A and 72B include integrated high-voltage diodes 73A and 73B designed to maintain a high voltage in the off-state condition. Typically, this design is best suited for operation below 100V, but can be extended to 150V if necessary. As in LED driver 301, I-accurate gate driver circuits 71A and 71B facilitate accurate current control controlled by analog control and sensing circuitry 320 and digital control and timing circuitry 74. An on-chip bias supply and voltage regulator 69 powers LED driver IC 316, in this case from Vcc rather than 24V as in LED driver IC 301. LED driver IC 316 operates similarly to LED driver IC 301, except for the lack of a cascode clamp DMOSFET, controlled through its SLI bus shift register 325 which includes a digital CSFB signal embedded within the SLI bus interface and protocol.

Unlike the previously described LED driver IC 66 ( FIG. 3B ), which required CSFBO and CSFBI pins for output and input CSFB signals, respectively, LED driver IC 316 embeds its CSFB data within the SLI bus data stream and does not require additional pins to facilitate current sense feedback, regardless of the number of channels integrated into the driver. Consequently, the CSFBO and CSFBI pins are not present in the package containing LED driver IC 316. Consequently, the analog control and sense circuitry 320 and the wide SLI bus interface 325 have been modified to embed the current sense feedback CSFB information within the SLI bus protocol.

An LED driver 330 with embedded CSFB using prefix-multiplexed SLI bus communication, made in accordance with the present invention, is shown in FIG10C . A dual-channel LED driver IC 331 includes integrated current sink DMOSFETs 87A and 87B with integrated high-voltage diodes 88A and 88B, I-accurate gate driver circuits 86A and 86B for accurate current control, analog control and sensing circuitry 335, and digital control and timing circuitry 89. An on-chip bias supply and voltage regulator 84 powers the IC from the Vcc input.

Unlike the previously described LED driver IC 80 ( FIG. 3C ), which required CSFBO and CSFBI pins for output and input CSFB signals, respectively, LED driver IC 331 embeds its CSFB data within the SLI bus data stream and does not require additional pins to facilitate current sense feedback, regardless of the number of channels integrated into the driver. Consequently, the CSFBO and CSFBI pins are not present in the package containing LED driver IC 80. Consequently, the analog control and sense circuitry 335 and the prefix-multiplexed SLI bus interface 340 have been modified to embed the current sense feedback CSFB information within the SLI bus protocol.

Otherwise, the LED driver IC 331 provides complete control of two channels of 250mA LED drivers with 150V blocking capability and ±2% absolute current accuracy, 12-bit PWM brightness control, 12-bit PWM phase control, 8-bit current control, fault detection for open LED and short LED conditions, and over-temperature detection, all controlled via the high-speed SLI bus and synchronized with other drivers via common Vsync and grayscale clock (GSC) signals. While the specific example shown illustrates current sink DMOSFETs rated at 150V blocking capability, these devices can be sized for operation from 100V to 300V as needed. The device's 250mA current rating is set by the power dissipation and forward voltage mismatch of the package in the two LED strings being driven. Above a nominal 100V, it is advantageous to integrate a high voltage cascode clamp DMOSFET (not shown) in series with current sink DMOSFETs 87A and 87B, whereby current sink MOSFETs 87A and 87B do not need to operate above the clamp voltage, ie, above 12V.

LED driver system and interface with SLI bus embedded CSFB

System 350 in FIG11 illustrates the application of a distributed power system for LED backlighting with local dimming, including SLI bus-embedded current sensing feedback, according to the present invention. The figure illustrates interface IC 351 driving a series of LED drivers 316A-316H with integrated dimming and fault detection, powered by a common SMPS 353. This figure is similar to system 100 in FIG4 , except that the analog CSFB daisy chain has been completely eliminated and functionally replaced by DCSFB signals embedded within the SLI bus protocol and network interface. While analog-to-digital conversion is not explicitly shown in LED driver ICs 316A-316H, interface IC 315 does illustrate the addition of D/A converters 3665 required to reconstruct the analog feedback signals from the SLI bus-embedded DCSFB digital words.

Each of the LED driver ICs 316A-316H can utilize a prefix-multiplexed SLI bus protocol, as shown in LED driver IC 331 of FIG. 10C , or alternatively, can utilize a wide-bus protocol, as shown in LED driver ICs 301 and 316 of FIG. 10A and 10B . Each of the driver ICs 316A-316H can incorporate a high-voltage current sink MOSFET, similar to that shown in FIG. 10B and 10C , or alternatively, can integrate a cascode clamp MOSFET to protect the current sink MOSFET, as shown in FIG. 10A . In system 350 , the LED driver ICs 316A-316H are illustrated without multiplexer 92 and decoder 91 , though it should be understood that such devices can be included within the driver ICs 316A-316H as needed, i.e., whenever a prefix-multiplexed SLI bus protocol is utilized. Five common signal lines 357, including three digital clock lines, one digital fault line, and one analog reference voltage line, connect the interface IC 351 to each driver IC. Timing and control circuitry 363 generates Vsync and GSC signals synchronized with data received from a host μC (not shown) via SPI bus interface 360. Timing and control circuitry 363 also monitors the FLT interrupt line to immediately detect potential problems. Reference voltage source 362 provides a global reference voltage, Vref, to the system to ensure good channel-to-channel current matching. Bias supply 361 powers interface IC 351 from supply voltage VIN on a fixed +24V power rail 354 generated by SMPS 353. Bias circuitry 361 also generates a regulated supply voltage, Vcc, to power LED drivers 316A-316H. This supply voltage, Vcc, is preferably 5V. The Vcc supply voltage is filtered by capacitor 362.

In this example, each of the LED driver ICs 316A-316H includes two channels, including: high voltage current sink DMOSFETs 72A-72Q with integrated HV diodes 73A-73Q, I-accurate gate driver circuits 71A-71Q, DC&T circuits 74A-74H, AC&S circuits 320A-320H including current sense feedback detection and A/D conversion to digital DCSFB, and SLI bus shift registers 325A-325H. Although the LED driver ICs 316A-316H shown in FIG11 lack cascode clamp MOSFETs, the system 350 can also be constructed in the manner of the LED driver IC 300 shown in FIG10A, except that the 24V VIN supply can be used instead of Vcc to power the LED driver IC and bias the gates of the cascode clamp DMOSFETs.

Any of the three versions 10A, 10B, or 10C may be inserted into the driver IC block 316 of FIG. 11 .

The SLI bus 356 connecting the LED driver ICs 316A-316H includes SLI bus shift registers 325A-325H connected together in a daisy chain via SLI buses 356A-356I, wherein the SO serial output of the SLI circuit 364 within the interface IC 351 is connected via SLI bus 356A to the SI input of LED driver 316A, the SO output of LED driver 316A is connected via SLI bus 356B to the SI input of LED driver 316B (not shown), and so on. SLI bus 356H is connected to the SI input of the last LED driver 316H shown in the system 350. The SO output of LED driver 316H is in turn connected via SLI bus 356I to the SI input of the SLI circuit 364 within the interface IC 351. In this manner, the SLI bus 356 forms a complete loop originating at the interface IC 351, passing through each of the LED driver ICs 316A-316H (sometimes collectively referred to as LED driver ICs 316), and back to itself. Data is shifted out of the SO pin of interface IC 350 , while a bit string of equal length is returned to the SI pin of interface IC 350 .

SLI circuitry 364 generates the SLI bus clock signal SCK as needed. Because LED driver ICs 316A-316H do not have chip addresses, the number of bits clocked through SLI bus 356 is related to the number of LED driver ICs being driven. The number of bits clocked through SLI bus 356 can be adjusted by modifying the software controlling data exchange in SPI interface 360 or by hardware modifications to interface IC 351. In this way, the number of channels within system 350 can be flexibly varied to match the size of the display. The number of bits shifted through SLI bus 356, i.e., broadcast on bus 356, depends on the SLI bus protocol used and the total number of bits in the SLI bus shift register. For example, the wide SLI bus protocol requires 72 to 88 bits per two-channel LED driver, while the prefix-multiplexed SLI bus is significantly smaller, requiring, for example, a fixed 32 bits per LED driver IC, regardless of the number of channels integrated into each driver IC.

When a hardware controller within interface IC 351 is used to control SLI bus communications, modifying registers in SLI bus circuitry 364 to shift out fewer or more bits requires modifications in the manufacture or design of interface IC 351. An alternative approach involves replacing interface IC 351 with a programmable interface IC that uses software to adjust the drivers to accommodate fewer or more LED drivers in the daisy chain.

The current sense feedback to SMPS 353 comprises a digital current sense feedback, or DCSFB, signal embedded within SLI bus 356. Data is shifted through SLI bus 356, ultimately returning this embedded DCSFB signal to SLI bus circuitry 364 of interface IC 351. In the manner previously described, SLI bus circuitry 364 in turn outputs the DCSFB word representing the lowest CSFB word in SLI bus 356, and D/A converter 365 converts this DCSFB word into an analog CSFB feedback voltage. Operational transconductance amplifier 366 then converts this CSFB feedback voltage into a current feedback ICSFB signal on line 358 to control the +V _LED output of SMPS 353. Alternatively, the CSFB feedback voltage itself can be used as the feedback signal to control SMPS 353. Digitally embedding the CSFB data contrasts system 350 with system 100 of FIG. 4 , where connecting each LED driver IC to the interface IC via an analog daisy chain requires two dedicated pins per driver IC.

In system 350, unlike system 100, interface IC 351 generates only a single value for CSFB feedback signal CSFBO or ICSFB. In applications requiring more than one SMPS, such as in larger displays with higher current backlighting or displays with RGB backlighting, the interface IC can be modified to output more than one CSFB output voltage to control multiple SMPS units. The SLI bus data stream itself carries the information necessary to independently control multiple LED supply voltage rails, but the interface IC needs to be configured to appropriately separate the channel information to take advantage of this feature. A multi-feedback, multi-output embodiment of the present invention is described below.

Analog and digital data conversion

9 , the voltage present across current sink MOSFET 275 is dynamically measured and used to control the output voltage of SMPS 293. Although both the measured voltage and the feedback signal comprise analog signals, the SLI bus embedded CSFB method according to the present invention includes a digitally encoded feedback path from LED driver IC 272 to interface IC 273. Such a system requires analog-to-digital conversion within LED driver IC 272 to sense the voltage across current sink MOSFET 275, and digital-to-analog conversion within interface IC 273 to generate the feedback signal for SMPS 293.

Converting analog signals to digital words, and vice versa, relies on data conversion. While the design of A/D and D/A converters is well known to those skilled in the art, a wide variety of converters exist and must be selected to meet, but not exceed, the performance requirements of the digital CSFB function. Data converter designs that respond too slowly to load transients or suffer from instabilities and long settling times can result in flickering and inconsistent displayed images and, in extreme cases, can even damage electronic components in the display. Conversely, accurate, high-performance converters are often too large and expensive for the TV market.

FIG12 illustrates a circuit for sensing and digital encoding within an LED driver IC, in which the voltage at the drain connections of MOSFETs 275A and 275B driving LED strings 274A and 274B is connected to the positive inputs, V _inA + and V _inB +, of a CSFB circuit 275, which includes an operational amplifier. The output of the operational amplifier is connected to its negative input, V _inB− , which operates as a unity-gain amplifier or voltage follower, with the most negative of the amplifier's positive inputs, V _inA + and V _inB +. The output of CSFB circuit 275 also feeds the input of an A/D converter 276. Note that for clarity, the I-accurate gate driver circuit for current sink MOSFETs 275A and 275B is not shown in FIG12 .

In one embodiment of CSFB circuit 275, the operational amplifier includes a differential input with matched input P-channel MOSFETs 401A, 401B, and 401C and a current source 403. A current mirror comprising matched N-channel MOSFETs 402A and 402B reflects the current in the negative input P-channel MOSFET 401A. The current in N-channel MOSFET 402B is summed with the currents in P-channel MOSFETs 401B and 401C, driving a second amplifier stage comprising N-channel MOSFET 404 and an active load 405 comprising a current source. Along with negative feedback from its output to the negative input MOSFET 401A, a compensation network comprising capacitor 406 and resistor 407 is provided to set the pole-zero response of the amplifier and maintain stability over the entire range of operation.

In operation, the most negative input present at the amplifier's _VinA + and _VinB + inputs turns on P-channel MOSFET 401B or 401C more than its parallel counterpart and causes the amplifier's output to go to the lower of the two drain voltages of MOSFETs 401B and 401C. This output is then digitized by A/D converter 276 and loaded into the SLI bus shift register when requested.

Although CSFB circuit 275 in FIG12 is shown for a two-channel LED driver IC, any number of channels can be integrated simply by adding a positive input connected to a P-channel MOSFET matched to MOSFETs 401B and 401C. For example, if the third positive input is connected to P-channel MOSFET 401D, CSFB circuit 275 will output the lowest of its three input values, either Channel A, Channel B, or Channel C. In this way, CSFB circuit 275 detects and outputs the lowest drain voltage of any current sink MOSFET in a particular LED driver IC.

As previously described, the CSFB circuit 275 determines the lowest voltage present across the current sink MOSFET within a given LED driver IC. This analog voltage is input to the analog-to-digital converter 276. The analog-to-digital converter 276 can be readily implemented using methods well known to those skilled in the art. A 4-bit D/A converter 276 is shown in FIG13 and includes a voltage divider comprising resistors 417A-417P (collectively, resistors 417), a corresponding number of analog comparators 418A-418P, a stable reference voltage source Vref 416, and a binary-to-decimal (BCD) digital encoder 420.

As shown, the reference voltage Vref is divided into sixteen linearly uniform steps, ranging from one-sixteenth of Vref to Vref. These sixteen reference voltages are connected to the negative inputs of analog comparators 418A-418P. For example, the more positive terminal of resistor 417A, i.e., the side not connected to ground, is connected to the negative input of comparator 418A. Similarly, the more positive terminal of resistor 417G is connected to the negative input of comparator 418G, and so on. The input to comparator 418P is directly connected to the reference voltage Vref. The positive inputs of analog comparators 418A-418P are connected to the input of A/D converter 276, which is in turn connected to the output of CSFB circuit 475. Because comparator 418A measures the lowest voltage of serial resistor chain 417, its output can be considered the least significant bit, or LSB, of the converter. Conversely, because comparator 418P measures the highest voltage, ie, the input above Vref, it can be considered the most significant bit, or MSB, of A/D converter 276 .

In operation, the analog voltage output by CSFB circuit 275 is compared to sixteen reference voltages at the negative inputs to analog comparators 418A-418P. Powered by Vref 416, each reference voltage is generated using a series string of resistors 417. For any given input voltage, the A/D converter input may exceed the reference voltage on some comparators and fall below the reference voltage on others. For those comparators where the CSFB input exceeds the reference voltage, the output of the corresponding comparator will assume a logic "high" state. For those comparators where the reference voltage exceeds the CSFB input, the output of the corresponding comparator will assume a logic "low" state. For example, when the input voltage to A/D converter 276 only slightly exceeds the reference voltage input to comparator 418G, all outputs of comparators 418A-418G will be high, while all outputs of comparators 418H-418P will remain low.

In this manner, the outputs of the sixteen comparators 418A-418P generate bits, i.e., unique digital combinations of "1's" and "0's," that represent a digital approximation of the analog CSFB voltage output of the CSFB circuit 275. The sixteen outputs of the comparators 418A-418P are fed into a BCD decoder 420, which in turn outputs a four-bit binary-to-decimal encoding or BCD code that is subsequently stored in the sampling latch 277 as digital CSFB data. The BCD encoder 420 converts the sixteen possible combinations of the comparator 418 outputs into sixteen four-bit words in a one-to-one correspondence. One possible conversion is shown below in Table 2:

Table 2

As needed, the 4-bit DCSFB data in sampling latch 277 is passed to SLI bus register 280, where it is subsequently shifted across the SLI bus and into the interface IC in the manner previously described. Sampling latch 277, which contains the DCSFB data, is referred to as a "sampling latch" because the process of converting analog data to digital data takes a finite amount of time, i.e., the A/D conversion is not instantaneous, such that the voltage data is only "sampled" on a periodic basis. Furthermore, as described above, there is normally no compelling need or benefit to sampling the CSFB feedback voltage in a video backlight system at a frequency significantly higher than the frame rate, i.e., at a rate faster than five times the Vsync frequency.

In the case of a prefix-multiplexed SLI bus, in response to the corresponding prefix code for reading the DCSFB data, the DCSFB data in the sampling latch 277 is passed through the multiplexer 278 to the SLI bus data register 280, where the prefix is decoded and the data is copied from the sampling latch to the data field of the SLI bus shift register. In a preferred embodiment of a prefix-multiplexed SLI bus, where the SLI bus data register is 16 bits wide, the 4-bit DCSFB word generated from the LED driver IC is preferably loaded into the 4 least significant bits of the data register as shown in Table 3:

Table 3

DCSFB sampling latch SLI bus data register wxyz 0000 0000 0000wxyz

In contrast, in the wide SLI bus protocol, the data in the sampling latch 277 is directly mapped to the corresponding 4-bit word in the SLI bus protocol without the need for an intermediate multiplexer 278. In this way, each LED driver IC regularly generates at least one DCSFB word per IC and loads this information into the SLI bus data register on a regular basis or upon request.

Because each driver IC generates its own DCSFB signal, which represents the lowest drain voltage of the current sink MOSFET in that particular IC, the interface IC must be sorted by a digital code to identify the value of the lowest CSFB voltage for all channels and driver ICs. As shown in Figure 14, this lowest CSFB voltage, stored in digital register 289, is then converted back to an analog feedback signal by D/A converter 290 and output as analog feedback signal 292. The voltage output of D/A converter 290, CSFBO, can be used directly to drive the feedback input of the SMPS, or alternatively, an operational transconductance amplifier OAT 291 can be used to convert this voltage into a feedback current ICSFB.

The four-bit digital-to-analog converter 290 can be readily implemented using methods well known to those skilled in the art. One such method, shown in FIG14 , employs an R/2R ladder design comprising resistors 431-438. Each digital input D0-D3 is biased in a logic "high" state at Vcc or in a logic "low" state at ground. These inputs are connected to a resistor "ladder," generating a voltage _VR across the resistor network. By changing the binary bit combinations in register 289, the resistor ladder voltage _VR can be dynamically varied. Specifically, if register 289 comprises a 4-bit word, the sixteen possible digital combinations create sixteen unique equivalent circuits, each with a different and unique _VR voltage. To avoid interaction with varying load impedances, voltage follower 439 buffers the ladder output voltage. By using binary weighting of the resistors, D/A converter 290 produces a linear, monotonic conversion of the digital code to an analog voltage.

Supports multiple SLI buses embedded with CSFB signals

As mentioned previously, one of the limitations of analog current sensing feedback is its inflexibility to support multiple independent feedback signals. When more than one SMPS is required per system, multiple feedback signals are needed to support higher power levels or to drive multiple strings of LEDs with different colors. For example, in larger, brighter displays where a single power supply is too large and energy inefficient, two SMPS modules are needed to generate independent +V _LED supplies. In RGB backlighting, at least three separate power supplies are required, one for powering the red LED string, one for powering the green LED string, and another for powering the blue LED string. In some cases, in RGBG backlighting, four power supplies are employed because two strings of green LEDs are required instead of one to achieve optimal color balance. Regardless, in today's systems, supporting multiple power supplies with different output voltages requires doubling or tripling the entire LED backlight system, making the solution costly, complex, and sensitive to noise coupling into the multiple analog feedback signals.

Modifying the SLI bus embedded CSFB approach to support multiple DCSFB signals addresses the problematic aspects of multiple analog current sense feedback signals without changing the BOM system cost beyond the additional SMPS module, without changing the SLI bus architecture, without changing the LED driver IC, and with minimal changes to the interface IC. Thus, a single backlight system made in accordance with the present invention can be adapted to support multiple power supplies in a straightforward manner.

As shown in FIG15 , a multi-power LED driver system 450 according to the present invention includes a single interface IC 451 and a single SLI bus daisy chain 161. It uses the disclosed SLI bus embedded CSFB method adapted for multiple DCSFB signals to control an array of eight LED driver ICs 174 and two SMPS modules 453 and 456, utilizing independent feedback lines 452 and 455 for each SMPS module. In this way, a single scaler video processor IC 153 and microcontroller 152 can drive separate LED backlight arrays from two high-voltage power supplies, with each SMPS module 453 and 456 operating at the optimal voltage for the LED string it is driving. For precise current matching, all LED driver ICs 174A-174H share a common Vref analog reference voltage on line 155.

In the dual-power backlight system 450 shown, LED strings 156A-156H are powered from a common high-voltage rail 454, +V _LED1 , which is dynamically regulated to a voltage as a function of digital feedback signal DCSFB1. Interface IC 451 determines the value of DCSFB1 by interrogating the SLI bus embedded CSFB data retrieved from LED driver ICs 174A-174D and selecting the lowest value in the data stream. This digital value is then converted into an analog feedback signal on line 452 for controlling SMPS1 module 453, either as voltage feedback signal CSFBO1 or as current feedback signal ICSFB1. Similarly, LED strings 156I-156Q are powered from a common high-voltage rail 457, +V _LED2 , which is dynamically regulated to a voltage as a function of digital feedback signal DCSFB2. The interface IC 457 determines the value of DCSFB2 by interrogating the SLI bus embedded CSFB data retrieved from the LED driver ICs 174E-174H and selecting the lowest value in the data stream. This digital value is then converted to an analog feedback signal on line 455 for controlling the SMPS2 module 456 as either a voltage feedback signal CSFBO2 or a current feedback signal ICSFB2.

Both DCSFB1 and DCSFB2 data are derived from interrogating the data stream on SLI bus 161, which is shifted into interface IC 451 via SLI bus 161I, and sorting the incoming data bits to determine which LED driver IC constitutes each word of CSFB data, as well as the driver IC from which it originates. In the case of a wide SLI bus protocol, this sorting function can be implemented using counters or programmable logic to determine which LED driver IC is associated with the data arriving on line 161I. This method of encoding CSFB data into the SLI bus protocol facilitates controlling multiple power supplies from LED driver ICs, each embedding a single CSFB feedback signal. While driver IC 174 does not need to be modified from those previously described and used in single-power supply applications, such as system 170 shown in FIG6 , interface IC 451 in FIG15 must be modified to interrogate its incoming CSFB data and parse it into two channels of feedback for independent control of multiple power supplies.

The method for separating the CSFB data associated with LED driver ICs 174A-174D from the CSFB data associated with LED driver ICs 174E-174H is functionally illustrated in FIG16. The SLI bus data stream 473 entering the SLI bus shift register 474 includes eight CSFB signals 473A-473H generated from and within eight individual LED driver ICs (not shown), each of which sends its own unique CSFB feedback value to the interface IC for processing. The SLI bus shift register 474 that interprets the incoming CSFB feedback data resides within the aforementioned interface IC, which outputs feedback signals 487 and 488 as shown to control the two power supplies, for example, within the interface IC or its equivalent.

Because the wide SLI bus protocol 471, which contains CSFB data 472, does not contain information about which driver IC generated a particular CSFB signal, counters or programmable logic must be used to identify the source of the data as it is shifted into the SLI bus shift register 474. In the example shown, CSFB data words 473A-473D generated by LED driver ICs 174A-174D control the output voltage of voltage supply SMPS1, while CSFB data words 473E-473H generated by LED driver ICs 174E-174H control the output voltage of voltage supply SMPS2. Structurally, data word 471 representing each of words 473A-473H includes CSFB packets 472 representing CSFB data embedded within bits that constitute non-CSFB data. In the example shown, data words 473E through 473H for controlling SMPS2 are shifted into the SLI bus shift register 474 first, followed by the words for controlling SMPS1. This sequence is arbitrary and may vary between different systems. In fact, the conceivable scattering of the data for controlling SMPS1 and SMPS2 would further complicate the classification process.

To parse the incoming SLI bus data into the different words 473A-473H, isolate the CSFB data packet 472 within each word, and identify which LED driver IC channel sent the data, a counter 477 counts the number of SCK pulses, and a decoder 478 interprets what to do with the corresponding data, loading it from the SLI bus registers into the valid latch as CSFB1 data, CSFB2 data, or discarding it. Specifically, a multiplexer 475 directs the SLI bus data for channels A, B, C, and D to a compare 1 register 478, and the data for channels E, F, G, and H to a compare 2 register 479. Although the SLI bus shift register 474 contains the entire wide SLI bus protocol word, which is either 66 or 88 bits in length, only the 4-bit wide CSFB packet 472 is loaded into the compare register 478 or 479. All other bits are discarded or used by other registers and functions within the interface IC.

When Channel 1 CSFB data packet 472 has been loaded into Compare 1 register 478, the incoming data is compared with the data in "Lowest CSFB1" register 480, overwriting register 480 only if the new data has a numerically lower magnitude. Otherwise, the data in "Lowest CSFB1" remains unchanged. Upon completion of the SLI bus shift operation or upon the next Vsync pulse, the DCSFB1 data is then loaded into the valid latch and D/A converter 482, and the output voltage of SMPS 1 changes. Analog feedback signal 487 may include a voltage output CSFB1 or a current ICSFB1, where operational transconductance amplifier OTA 484 converts the CSFB1 feedback voltage into the ICSFB1 feedback current. Similarly, when Channel 2 CSFB data 472 is loaded into Comparator 2 register 479, the incoming data is compared with the data in "Lowest CSFB2" register 481, overwriting register 481 only if the new data has a numerically lower magnitude. Otherwise, the data in "Lowest CSFB2" remains unchanged. Upon completion of the SLI bus shift operation or upon the next Vsync pulse, the DCSFB2 data is then loaded into the valid latch and D/A converter 483, and the output voltage of SMPS 2 changes. The analog feedback signal 488 may include a voltage output CSFBO2 or a current ICSFB2, where the operational transconductance amplifier OTA 486 converts the CSFBO2 feedback voltage into the ICSFB2 feedback current.

In this manner, counter 477, decoder 476, and multiplexer 475 are able to interpret and classify SLI bus data stream 473, extracting the SLI bus-embedded digital CSFB signal 472 from each LED driver IC to dynamically control both SMPS outputs via analog CSFB signals 487 and 488. This concept can be extended to three or more power supplies by modifying decoder 476 and adding additional compare registers and D/A converters. As shown, data stream 473 groups all LED driver IC data controlling SMPS2 into sequential words 473H-473E, followed by all LED driver IC data controlling SMPS1, which comprises sequential SLI bus words 473D-473A. In other embodiments of the present invention, the CSFB feedback data for two or more SMPS modules can be interspersed in an alternating or random manner. Therefore, decoder 476 can comprise reconfigurable logic, a field programmable gate array, or a small microcontroller core to flexibly adapt the classification process to varying sequences. Note that at startup, the CSFB register is initially loaded with the highest value. After that, the most recent CSFB data is updated in the SLI bus data, permanently and dynamically adjusting the power supply voltage.

In an alternative embodiment according to the present invention, the information required to separate the SLI bus's embedded CSFB data and distribute it to one of several supply voltages can be built into the protocol itself. One method for extracting and distributing embedded CSFB data using separate prefix codes within a prefix-multiplexed SLI bus protocol and hardware interface is shown in Figure 17. In this example, a prefix code identifying the SMPS to be controlled by the digital CSFB data and its associated CSFB data are embedded in the SLI bus data stream generated by each LED driver IC. By reading and decoding this prefix code, the interface IC can then easily distribute the feedback data to the appropriate SMPS.

As an example, SLI bus data stream 493 embeds two types of CSFB signals, specifically, an SLI bus word 491 having a prefix code "Prefix 1" corresponding to data CSFB1 for controlling SMPS1, and an SLI bus word 492 including "Prefix 2" corresponding to CSFB2 data for controlling SMPS2. In this embodiment, SLI bus data stream 493 includes four words 493H-493E for controlling SMPS2 and four words 493D-493A for controlling SMPS1. SLI bus data stream 493 is sequentially shifted into SLI bus serial shift register 494 under the control of the SCK signal, whereby the prefix code is interpreted by prefix decoder 495, and multiplexer 496 directs the data to the appropriate function latch.

In the event that the prefix code identifies CSFB1 data, prefix decoder 495 directs multiplexer 496 to load the CSFB data from the data field of SLI bus register 494 into "Compare 1" register 478, including CSFB data for LED driver ICs A, B, C, and D as shown. Compare 1 function 478 then overwrites the data in lowest CSFB1 latch 480 only if the incoming data in SLI bus 494 has a lower digital magnitude than the data currently present in "Lowest CSFB1" register 480; otherwise, the data in register 480 remains unchanged. After all words in SLI bus data stream 493 have been shifted into SLI bus shift register 494 and interpreted, the data in "Lowest CSFB1" register 480 represents the current digital representation of the CSFB1 data, i.e., DCSFB1. At this time or in synchronization with the next Vsync pulse, the DCSFB1 data is copied into the valid latch and D/A converter 482, generating analog feedback outputs 486 including voltage output CSFBO1 or current output ICSFB1 after conversion by OTA 484.

In a similar manner, when the prefix code identifies CSFB2 data, prefix decoder 495 directs multiplexer 496 to load the CSFB data from the data field of SLI bus register 494 into compare 2 register 479, including the CSFB data for LED driver ICs E, F, G, and H as shown. Compare function 479 then overwrites the data in "Lowest CSFB2" latch 481 only if the incoming data in SLI bus 494 has a lower digital magnitude than the data currently present in "Lowest CSFB2" register 481; otherwise, the data in register 481 remains unchanged. After all words in SLI bus data stream 493 have been shifted into SLI bus shift register 494 and interpreted, the data in lowest CSFB2 register 481 represents the current digital representation of the CSFB2 data, i.e., DCSFB2. At this time or in synchronization with the next Vsync pulse, the DCSFB2 data is copied into the valid latch and D/A converter 483, generating analog feedback output 487 including voltage output CSFBO2 or current output ICSFB2 after conversion by OTA485.

In the example shown, the first four words shifted into the SLI bus shift register 494 are those associated with the control of SMPS2, i.e., LED driver ICs H, G, F, and E. These are followed by the four words controlling SMPS1, in the same order as LED driver ICs D, C, B, and A. However, with a prefix-multiplexed SLI bus, the data stream is not limited to a specific sequence. Rather, the data sequence can be any alternating or random sequence, mixing the feedback data for SMPS1 and SMPS2. Furthermore, any number of CSFB signals can be embedded into the SLI bus data stream using a different prefix code for each CSFB signal.

For example, the format can be easily adapted to support three power supplies that are compatible with driving an RGB backlighting system, or to support four separate feedback signals useful in RGBG or RGBY backlighting methods. An RGBG backlighting solution uses a red LED string powered by one SMPS, a blue LED string powered by another SMPS, and twice the number of green LED strings powered by two SMPS modules to compensate for the lower brightness of today's green LEDs. In RGBY backlighting, yellow LEDs are included to extend the range of color temperatures. The same system can also be used in logo pattern applications where RGB, RGBG, or RGBY are used to generate actual images rather than white backlight.

In summary, FIG17 illustrates that a single prefix code can be used to embed multiple different CSFB signals into the SLI bus data stream to create a flexible solution for managing multiple power supplies without the need for an analog feedback network. An alternative approach is to embed up to four CSFB signals into the data field of a single prefix-multiplexed SLI bus word, dividing a 16-bit SLI bus data field into four CSFB 4-bit "tuples." This alternative method of embedding CSFB data into the SLI bus protocol is illustrated in FIG18 , where an SLI bus word 501 using a 32-bit prefix-multiplexed or "narrow" ZLI bus protocol includes a 16-bit prefix code 502E and four 4-bit CSFB signals 502A-502D.

In the data field of SLI bus word 501, CSFB1 word 502A includes: the four least significant bits in the SLI bus data field, bits 0 to 3; CSFB2 word 502B includes: the next four more significant bits in the SLI bus data field, bits 4 to 7; CSFB3 word 502C includes: the next four more significant bits in the SLI bus data field, bits 8 to 11; and CSFB4 word 502D includes: the four most significant bits in the SLI bus data field, bits 12 to 15.

Prefix decoder 502 decodes prefix 502E, which instructs multiplexer 504 to transfer all four CSFB words 502A-502D into compare register 505. Compare register 505 then compares the 4-bit CSFB data 502A from the SLI bus with the CSFB1 data in the lowest CSFB register 506, overwriting the data in register 506 only if the new data in 502A is lower. Compare register 505 simultaneously compares the 4-bit CSFB2 data 502B from the SLI bus with the CSFB2 data in the lowest CSFB register 560, overwriting the data in register 506 only if the new data in 502B is lower. Concurrently, compare function 505 compares the data in 502C with the CSFB3 data in the "lowest CSFB" register 506, and compares the data in 502D with the CSFB4 data in the "lowest CSFB" register 506. After the data is shifted into serial shift register 501, the "lowest CSFB" register 506 contains the most current CSFB value.

The data within register 506 is then used to generate CSFB feedback outputs 511-518 using D/A converters 507A-510 and transconductance amplifiers 511-514, either in real time or synchronously with the next Vsync pulse. The four least significant bits in register 506 represent DCSFB1 data, which is processed by D/A converter 507 and OTA 511 to generate the CSFB01 and ICSFB1 outputs for controlling SMPS1. Similarly, in consecutive 4-bit combinations, register 506 contains DCSFB2 data for controlling SMPS2, DCSFB3 data for controlling SMPS3, and DCSFB4 data for controlling SMPS4. As described in accordance with the present invention, one multi-CSFB instruction on SLI bus 501 independently and dynamically controls up to four SMPS output voltages in real time.

An example of an SLI bus application with multiple CSFB embedded to independently control three SMPS outputs is shown in FIG19 , whereby an SLI bus data stream 523 comprises a sequence of nine SLI bus words 523I-523A, each following a quadruple CSFB protocol represented by prefix-multiplexed SLI bus word 521, with a corresponding data field "wxyz". The data for CSFB1 is encoded in the four least significant bits of SLI bus words 523G, 523D, and 523A, while the remaining bits represent the highest possible digital value, i.e., 1111 in binary or "F" in hexadecimal. The data in SLI bus words 523G, 523D, and 523A thus comprises 16-bit binary words in the format [11111111 1111wxyz].

In a similar manner, data for CSFB2 is encoded in the next four more significant bits of SLI bus words 523H, 523E, and 523B, with the remaining bits representing the highest possible digital value, i.e., binary 1111. The data in SLI bus words 523H, 523E, and 523B thus comprises a 16-bit binary word in the format [11111111wxyz 1111]. Data for CSFB3 is encoded in the next four more significant bits of SLI bus words 523I, 523F, and 523C, with the remaining bits representing the highest possible digital value, i.e., binary 1111. The data in SLI bus words 523I, 523F, and 523C thus comprises a 16-bit binary word in the format [1111wxyz 1111 1111]. As shown, the words in the SLI bus data stream 523 do not contain CSFB4 data, so it remains at the highest voltage DCSFB value 1111.

SLI bus data 523 is serially shifted into SLI bus shift register 524. Once decoded by quad decoder 525, it instructs multiplexer 526 to write the appropriate 4-byte group from SLI bus data 521 into "compare" registers 527, 528, and 529, respectively. CSFB1 is loaded into Compare 1 register 527, CSFB2 data is loaded into Compare 2 register 528, and CSFB3 data is loaded into Compare 1 register 529 for subsequent conversion into analog feedback signals 539-541. As shown, CSFB4 data is not loaded into any compare register and therefore does not affect any SMPS output. This three-output decoding can be applied to RGB backlighting applications.

One possible RGB backlight is shown in FIG. 20 , where LED driver ICs 562A, 562D, and 562G control and provide one of the CSFB feedback signals 564 for SMPS1 554 to power red LED strings 560A, 560B, 560G, 560H, 560M, and 560N at a voltage of +V _LED1 on power rail 557; where LED driver ICs 562B, 562E, and 562H control and provide one of the CSFB feedback signals 564 for SMPS2 555 to power green LED strings 560C, 560D, 560I, 560J, 560P, and 560Q at a voltage of +V _LED2 on power rail 558; and where LED driver ICs 562C, 562F, and 562I control and provide one of the CSFB feedback signals 564 for SMPS3 556 to power green LED strings 560C, 560D, 560I, 560J, 560P, and 560Q at a voltage of +V LED2 on power rail 559. _LED3 powers blue LED strings 560E, 560F, 560K, 560L, 560R, and 560S.

All three CSFB signals are digitally embedded into a single SLI bus daisy chain comprising SLI buses 563A-563J and converted by interface IC 551 into individual analog feedback signals 564, facilitating dynamic control of the red, green, and blue LED supply voltages + _VLED1 , + _VLED2 , and + _VLED3 in response to instructions from μC 552 and scaler IC 553.

In system 550, each LED driver IC drives two strings of the same color LEDs and outputs a single CSFB value. In an alternative embodiment shown in FIG21, each LED driver IC 612 controls three different LED strings—one red, one green, and one blue—and outputs three different CSFB signals. Specifically, LED driver IC 612A controls red, green, and blue LED strings 610A, 610B, and 610C, respectively; LED driver IC 612B controls red, green, and blue LED strings 610D, 610E, and 610F, respectively; and so on. The last LED driver IC in this daisy chain, driver 612F, controls red, green, and blue LED strings 610Q, 610R, and 610S, respectively. Each driver IC 612 outputs its own CSFB3, CSFB2, and CSFB1 feedback values for red, green, and blue feedback and power supply control digitally embedded in SLI bus 613.

Interface IC 601 interprets the embedded CSFB data carried by SLI bus daisy chain 613 and outputs three separate analog feedback signals 614 to dynamically control SMPS1 module 604, SMPS2 module 605, and SMPS3 module 606 to produce dynamically adjusted outputs 607, 608, and 609 with corresponding voltages + _VLED1 , + _VLED2 , and + _VLED3 . In this way, scaler IC 603, μC 602, interface IC 601, and six driver ICs 612 form a dynamically adjustable backlight system with independent dynamic control of eighteen LED strings using SLI bus control without the need for multiple analog feedback loops.

For more than one CSFB signal to be embedded in the driver IC, more than one CSFB signal must be generated within the LED driver IC. FIG22 illustrates an eight-channel LED driver IC 651 that integrates eight current sink DMOSFETs 653A-653H, four independent CSFB detection circuits 654A-654D, and four independent A/D converters, resulting in a 16-bit SPI bus word 670 that embeds four independent CSFB signals CSFB1-CSFB4, wherein the four independent CSFB signals CSFB1-CSFB4 provide independent feedback control of four different SMPS output voltages + _VLED1- + _VLED4 .

In operation, the currents in LED strings 652A and 652B generate induced voltages across current sink DMOSFETs 653A and 653B. CSFB circuit 654A then determines which of these two voltages is lower and outputs the lower voltage to A/D converter 655A, which converts the analog feedback data into a 4-bit digital word, CSFB4. Similarly, the currents in LED strings 652C and 652D generate induced voltages across current sink DMOSFETs 653C and 653D. CSFB circuit 654B then determines which of these two voltages is lower and outputs the lower voltage to A/D converter 655B, which converts the analog feedback data into a 4-bit digital word, CSFB3. Similarly, voltage feedback from LED strings 652E and 652F determines the digital value of CSFB2 output by A/D converter 655C, and voltage feedback from LED strings 652G and 652H determines the digital value of CSFB1 output by A/D converter 655D.

CSFB4 data is stored in the four most significant bits of sampling latch 666, CSFB3 occupies the next four less significant bits, CSFB2 occupies the next four less significant bits, and CSFB1 fills the four least significant bits of sampling latch 666. When instructed to do so by prefix decoder 667A and prefix code 669P, all 16 bits of data from preload latch 666 are copied through multiplexer 667B into data field 669D of SLI bus shift register 5658. This data field thus contains not one but four separate 4-bit CSFB words, CSFB4 through CSFB1, as shown in data set 670.

After being shifted into the interface IC, these CSFB signals ultimately set the corresponding voltage outputs of the + _VLED4 to + _VLED1 power supplies in the manner described in FIG18 . Four CSFB signals are useful in RGBG backlights where two sets of green LED strings are powered by separate SMPS voltages. Alternatively, not all 16 bits need to be used. For example, in an RGB application, A/D converter 655A can be eliminated, and the 12 least significant bits of sampling latch 666 can be used to control three separate power supplies, such as + _VLED3 for the red LED string, + _VLED2 for the green LED string, and + _VLED1 for the blue LED string. By removing the unused CSFB 654A with current sink MOSFETs 652A and 652B, and also removing the unneeded MOSFET current sinks 652D, 652F, and 652H to implement a three-CSFB, three-channel LED driver IC, such an approach is consistent with the system example shown in FIG21 .

Claims (16)

1. An integrated circuit for controlling a power supply to a plurality of light-emitting diode strings, the integrated circuit comprising: An interface circuit coupled to a plurality of daisy-chained serial shift registers, the interface circuit being configured to receive a plurality of digital values from the plurality of serial shift registers and identify the lowest digital value from the plurality of digital values, each of the plurality of digital values corresponding to a voltage level at one end of one of the plurality of LED strings; and A converter coupled to the interface circuit, the converter being configured to convert the lowest digital value into a control signal and provide the control signal to the power supply to adjust the output voltage of the power supply, the converter comprising a digital-to-analog converter and an operational transconductance amplifier, the analog converter being configured to convert the lowest digital value into an analog voltage signal, the operational transconductance amplifier being coupled to the analog converter and configured to convert the analog voltage signal into an analog current signal and provide the analog current signal to the power supply. 2. The integrated circuit of claim 1, wherein the interface circuit includes an output terminal coupled to the input of a first serial shift register of the plurality of serial shift registers in a daisy-chain configuration. 3. The integrated circuit of claim 2, wherein the interface circuit further includes an input terminal coupled to the output of the last serial shift register of the plurality of serial shift registers in a daisy-chain configuration. 4. The integrated circuit of claim 1, wherein the interface circuit is further configured to generate a clock signal to control the operation of the plurality of serial shift registers. 5. The integrated circuit of claim 1, further comprising a serial peripheral interface for communicating with a host microcontroller. 6. An integrated circuit for controlling a power supply to a plurality of light-emitting diode strings, the integrated circuit comprising: An interface circuit coupled to a plurality of daisy-chained serial shift registers, the interface circuit being configured to receive a plurality of digital values from the plurality of serial shift registers and identify the lowest digital value from the plurality of digital values, each of the plurality of digital values corresponding to a voltage level at one end of one of the plurality of LED strings, the interface circuit including a register for storing the digital values and a comparator, the comparator being coupled to the register for storing the digital values and configured to compare the incoming digital values from the plurality of serial shift registers with the digital values stored in the register for storing the digital values to identify the lower digital value; and A converter coupled to the interface circuit is configured to convert the lowest digital value into a control signal and provide the control signal to the power supply to adjust the output voltage of the power supply. 7. The integrated circuit of claim 6, wherein the interface circuit is further configured to replace the digital value stored in the register of the stored digital value with the incoming digital value in response to the incoming digital value being lower than the digital value stored in the register of the stored digital value. 8. The integrated circuit of claim 6, wherein the converter includes a digital-to-analog converter configured to convert the lowest digital value into an analog voltage signal. 9. The integrated circuit of claim 8, further comprising an operational transconductance amplifier coupled to the analog converter and configured to convert the analog voltage signal into an analog current signal and provide the analog current signal to the power supply. 10. The integrated circuit of claim 6, wherein the interface circuit further includes an output terminal coupled to the input of a first serial shift register of the plurality of serial shift registers in a daisy-chain configuration. 11. The integrated circuit of claim 10, wherein the interface circuit further includes an input terminal coupled to the output of the last serial shift register of the plurality of serial shift registers in a daisy-chain configuration. 12. The integrated circuit of claim 6, further comprising a serial peripheral interface for communicating with a host microcontroller. 13. An integrated circuit for controlling a first power supply and a second power supply respectively supplying power to a first plurality of light-emitting diode strings and a second plurality of light-emitting diode strings, the integrated circuit comprising: An interface circuit coupled to a plurality of daisy-chained serial shift registers, the interface circuit being configured to receive a first plurality of digital values from the plurality of serial shift registers, receive a second plurality of digital values from the plurality of serial shift registers, identify a first lowest digital value from the first plurality of digital values, and identify a second lowest digital value from the second plurality of digital values, each of the first plurality of digital values corresponding to a voltage level at one end of one of the first plurality of LED strings, each of the second plurality of digital values corresponding to a voltage level at one end of one of the second plurality of LED strings, the interface circuit including a first register configured to store the first digital value and a second register configured to store the second digital value, the interface circuit being configured to compare a first incoming digital value of the first plurality of digital values with the first digital value stored in the first register to identify a first lower digital value, and to compare a second incoming digital value of the second plurality of digital values with the second digital value stored in the second register to identify a second lower digital value; and A converter coupled to the interface circuit is configured to convert the first lowest digital value into a first control signal, convert the second lowest digital value into a second control signal, provide the first control signal to the first power supply to adjust the output voltage of the first power supply, and provide the second control signal to the second power supply to adjust the output voltage of the second power supply. 14. The integrated circuit of claim 13, wherein the interface circuit is further configured to replace the first digital value stored in the first register with the first digital value in response to the first incoming digital value being lower than the first digital value stored in the first register. 15. The integrated circuit of claim 13, wherein the interface circuit is further configured to replace the second digital value stored in the second register with the second digital value in response to the second incoming digital value being lower than the second digital value stored in the second register. 16. The integrated circuit of claim 13, wherein the first plurality of light-emitting diode strings have a first color and the second plurality of light-emitting diode strings have a second color different from the first color.