HK1233774B - Parasitic compensation for radio-frequency switch applications - Google Patents

Description

Parasitic compensation for RF switching applications

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 62/011,148, filed on June 12, 2014, entitled “ARCHITECTURES AND METHODS RELATED TO INSERTION LOSS REDUCTION AND IMPROVED ISOLATION IN SWITCH DESIGNS,” and U.S. Provisional Application No. 62/011,150, filed on June 12, 2014, entitled “CIRCUITS AND METHODS RELATED TO ADJUSTABLE COMPENSATION FOR PARASITIC EFFECTS IN RADIO-FREQUENCY SWITCH NETWORKS,” the disclosure of each of which is expressly incorporated herein by reference in its entirety.

Technical Field

The present application relates to radio frequency (RF) switches.

Background Art

In many radio frequency (RF) applications, switches are used to facilitate the routing of RF signals. Such switches may be affected by one or more performance-related parameters such as insertion loss, isolation, and parasitic effects.

Summary of the Invention

In some embodiments, the present application relates to a switch structure comprising a switch network having one or more switchable radio frequency (RF) signal paths, wherein each path contributes to parasitic effects associated with the switch network. The switch structure further comprises a parasitic compensation circuit coupled to a node of the switch network. The parasitic compensation circuit is configured to compensate for the parasitic effects of the switch network.

In some embodiments, the switch network may include multiple switchable RF signal paths. A node of the switch network may be a common node for the multiple switchable RF signal paths, such that each switchable RF signal path is implemented between the common node and a corresponding path node. The common node may be an antenna port.

In some embodiments, each of the plurality of switchable RF signal paths may include a series arm switch configured to connect the common node and its corresponding path node in an on state, and to disconnect the common node from its corresponding path node in an off state. Each of the plurality of switchable RF signal paths may also include a shunt arm switch configured to connect its corresponding path node to ground when the corresponding series switch arm is in an off state, and to disconnect the path node from the ground when the series switch arm is in an on state. Each series arm switch may include a stack of transistor devices, wherein each transistor device has an off capacitance Coff that increases with its size, and each shunt arm switch may include a stack of transistor devices, wherein each transistor device has an off capacitance Coff that increases with its size. Each transistor device of the series arm switch may include N field effect transistors (FETs) arranged in a parallel configuration, and each transistor device of the shunt arm switch may include M FETs arranged in a parallel configuration, each of N and M being a positive integer.

In some embodiments, the parasitic compensation circuit may include an inductive circuit coupling the common node and the ground, wherein the inductive circuit has an inductance L that compensates for parasitic effects caused by the off-capacitance of the series arm switch and the shunt arm switch. The inductance L of the parasitic compensation circuit may be selected to have a value of L=1/[4π ² f ² (Coff_total)], where f is the operating frequency and Coff_total is the total off-capacitance of the switching network. The presence of the inductance L of the parasitic compensation circuit may allow either or both of the series arm and shunt arm switch transistors to be larger to improve switching performance while reducing the parasitic effects of the off-capacitance of the series arm switch and the shunt arm switch.

The switching performance may include insertion loss performance. The size of either or both of the series arm and shunt arm switching transistors may be larger than the size of corresponding transistors of a switch structure without the inductor L of the parasitic compensation circuit. The switch network of the switch structure with the inductor L of the parasitic compensation circuit may have lower insertion loss than the switch network of the switch structure without the inductor L.

The switching performance may include isolation performance. The size of the shunt arm switch transistor may be larger than the size of a corresponding transistor of a switch structure without the inductor L of the parasitic compensation circuit. The switch network of the switch structure with the inductor L of the parasitic compensation circuit may have higher isolation than the switch network of the switch structure without the inductor L.

In some embodiments, the inductance circuit can be configured to provide a substantially fixed value for the inductance L of the parasitic compensation circuit. In some embodiments, the inductance circuit can be configured to provide a plurality of different values for the inductance L of the parasitic compensation circuit. In such an adjustable inductance configuration, the inductance circuit can include, for example, a plurality of switchable inductors connected in series. Each switchable inductor can include an inductor and a switch arranged in parallel. The inductance values of the switchable inductors can be substantially the same or different. In some embodiments, the different inductance values can be selected to provide a cascaded binary-weighted stage.

In some teachings, the present application relates to a method for routing radio frequency (RF) signals. The method includes performing switching operations in a switching network to allow one or more RF signals to pass through one or more corresponding switchable radio frequency (RF) signal paths, wherein each path contributes to parasitic effects associated with the switching network. The method also includes compensating for the parasitic effects at nodes of the switching network.

According to some embodiments, the present application relates to a method for manufacturing a switching device. The method includes forming or providing a switching network, the switching network including one or more switchable radio frequency (RF) signal paths, wherein each path contributes to parasitic effects associated with the switching network. The method also includes forming a parasitic compensation circuit and coupling the parasitic compensation circuit to a node of the switching network, wherein the parasitic compensation circuit is configured to compensate for the parasitic effects of the switching network.

In some embodiments, the present application relates to a radio frequency (RF) module, comprising: a packaging substrate configured to house a plurality of components; and a switching network implemented on the packaging substrate. The switching network includes one or more switchable radio frequency (RF) signal paths, each of which contributes to parasitic effects associated with the switching network. The RF module also includes a parasitic compensation circuit implemented on the packaging substrate. The parasitic compensation circuit is coupled to a node of the switching network and is configured to compensate for the parasitic effects of the switching network.

In some embodiments, the switch network is implemented on a first wafer, such as a silicon-on-insulator (SOI) wafer. In some embodiments, at least a portion of the parasitic compensation circuitry may be implemented on the first wafer, and at least a portion of the parasitic compensation circuitry may be implemented on a second wafer. In some embodiments, the RF module may be an antenna switch module.

According to some teachings, the present application relates to a radio frequency (RF) device comprising a transceiver configured to process RF signals; and an antenna switch module (ASM) in communication with the transceiver. The ASM is configured to route amplified RF signals for transmission and to route received RF signals for amplification. The ASM includes a switching network having one or more switchable RF signal paths, wherein each path contributes to parasitic effects associated with the switching network. The ASM also includes a parasitic compensation circuit coupled to a node of the switching network. The parasitic compensation circuit is configured to compensate for the parasitic effects of the switching network. The RF device also includes an antenna in communication with the ASM. The antenna is configured to facilitate either or both transmission and reception of corresponding RF signals. In some embodiments, the RF device can be a wireless device such as a cellular telephone.

According to some embodiments, the present application relates to an adjustable compensation circuit for a radio frequency (RF) circuit. The adjustable compensation circuit includes an inductor circuit that couples a selected node of the RF circuit to a reference node and is configured to provide a plurality of inductance values.

In some embodiments, the inductive circuit may include a plurality of switchable inductors connected in series. Each switchable inductor may include an inductor and a switch arranged in parallel. In some embodiments, each inductor of the inductive circuit may have a substantially constant inductance value of L0, such that the inductive circuit can provide inductance values ranging from L0 to a total inductance in steps of L0, wherein the total inductance is approximately equal to L0 multiplied by the number of switchable inductors connected in series. In some embodiments, the inductive circuit may include a plurality of cascaded binary-weighted stages that are independently switchable.

In some embodiments, the RF circuit may include a switch network having a plurality of switchable RF signal paths, and the reference node may be a ground node. The selected node of the RF circuit may be a common node for the plurality of switchable RF signal paths, such as an antenna port.

In some embodiments, each of the plurality of switchable RF signal paths may include a series arm switch configured to connect the common node and its corresponding path node in an on state, and to disconnect the common node from its corresponding path node in an off state. Each of the plurality of switchable RF signal paths may also include a shunt arm switch configured to connect its corresponding path node to ground when the corresponding series switch arm is in an off state, and to disconnect the path node from the ground when the series switch arm is in an on state. Each series arm switch may include a stack of transistor devices, wherein each transistor device has an off capacitance Coff that increases with its size, and each shunt arm switch may include a stack of transistor devices, wherein each transistor device has an off capacitance Coff that increases with its size. Each transistor device of the series arm switch may include N field effect transistors (FETs) arranged in a parallel configuration, and each transistor device of the shunt arm switch may include M FETs arranged in a parallel configuration, each of N and M being a positive integer.

In some embodiments, at least one of the multiple inductance values provided by the adjustable compensation circuit may include an inductance value L that compensates for parasitic effects caused by the off-capacitance of the series arm switch and the shunt arm switch. The inductance L may be selected to have a value of L=1/[4π ² f ² (Coff_total)], where f is the operating frequency and Coff_total is the total off-capacitance of the switching network. The presence of the inductance L may allow either or both of the series arm and shunt arm switch transistors to be larger to improve switching performance while reducing the parasitic effects of the off-capacitance of the series arm switch and the shunt arm switch.

The switching performance may include insertion loss performance. The size of either or both of the series arm and shunt arm switching transistors may be larger than the size of corresponding transistors in a switch structure without the inductor L. The switch network with the switch structure having the inductor L may have lower insertion loss than the switch network without the inductor L.

The switching performance may include isolation performance. The size of the shunt arm switch transistor may be larger than the size of a corresponding transistor of a switch structure without the inductor L. The switch network of the switch structure with the inductor L may have higher isolation than the switch network of the switch structure without the inductor L.

According to some teachings, the present application relates to a method for compensating for parasitic effects associated with a radio frequency (RF) switching network. The method includes performing a switching operation in the RF switching network to allow one or more RF signals to pass through one or more corresponding switchable RF signal paths, wherein each path contributes to the parasitic effects associated with the RF switching network. The method also includes providing an inductance using an adjustable compensation circuit coupled to a selected node of the RF switching network. The inductance is selected to compensate for the parasitic effects associated with the RF switching network.

In some embodiments, the present application relates to a method for manufacturing a switching apparatus. The method includes forming or providing a switching network, the switching network including one or more switchable radio frequency (RF) signal paths, wherein each path contributes to parasitic effects associated with the switching network. The method also includes forming an adjustable compensation circuit, the adjustable compensation circuit including an inductor circuit configured to provide a plurality of inductance values. The method also includes coupling the adjustable compensation circuit between a selected node of the switching network and a reference node, wherein the adjustable compensation circuit is configured to compensate for the parasitic effects of the switching network.

According to some embodiments, the present application relates to a radio frequency (RF) module, comprising a package substrate configured to house a plurality of components; and a switch network implemented on the package substrate. The switch network comprises one or more switchable radio frequency (RF) signal paths, wherein each path contributes to parasitic effects associated with the switch network. The RF module further comprises an adjustable compensation circuit implemented on the package substrate and comprising an inductor circuit coupling a selected node of the switch network to a reference node. The inductor circuit is configured to provide a plurality of inductance values, wherein at least some of the inductance values are selected to compensate for the parasitic effects of the switch network.

In some embodiments, the switch network can be implemented on a first wafer, such as a silicon-on-insulator (SOI) wafer. In some embodiments, at least a portion of the adjustable compensation circuit can be implemented on the first wafer, and at least a portion of the adjustable compensation circuit can be implemented on a second wafer. In some embodiments, the RF module can be, for example, an antenna switch module.

In some embodiments, the present application relates to a radio frequency (RF) device comprising a transceiver configured to process RF signals; and an antenna switch module (ASM) in communication with the transceiver. The ASM is configured to route amplified RF signals for transmission and amplified received RF signals, and includes a switching network. The switching network includes one or more switchable RF signal paths, each of which contributes to parasitic effects associated with the switching network. The ASM also includes an adjustable compensation circuit having an inductor circuit coupling a selected node of the switching network to a reference node. The inductor circuit is configured to provide a plurality of inductance values, at least some of which are selected to compensate for the parasitic effects of the switching network. The RF device also includes an antenna in communication with the ASM. The antenna is configured to facilitate either or both transmission and reception of corresponding RF signals. In some embodiments, the RF device may be a wireless device such as a cellular telephone.

For purposes of summarizing this application, certain aspects, advantages, and novel features of the present invention have been described herein. It will be appreciated that not all of these advantages are necessarily achieved in accordance with any specific embodiment of the present invention. Thus, the present invention may be practiced or implemented in a manner that achieves or optimizes one advantage or group of advantages as taught herein, without necessarily achieving other advantages as may be taught or suggested herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a switching architecture having a switch network coupled to a port.

FIG. 2 illustrates an example of a switch network configured to merge multiple radio frequency (RF) signal paths to a common port.

FIG. 3 shows an example of a shunt path being turned on when a corresponding RF signal path is turned off.

FIG. 4 shows an example where a switch network includes switches implemented in a stack configuration.

5 depicts the switch network in terms of on-resistance (Ron) and off-capacitance (Coff) for the example configuration of FIG. 4 and in the example switching states of FIG. 3 .

FIG. 6A shows that in some embodiments, each switching device may include multiple FETs arranged in a parallel configuration.

FIG. 6B shows an example circuit representation and an example layout of the switching device of FIG. 6A .

FIG. 7 shows an example of insertion loss and isolation characteristics of the switches of FIGs. 4-6 .

FIG8 shows an example of a switch structure in which a parasitic compensation circuit may include an inductor L configured to reduce the effect of an off capacitance (Coff) of each switch of the switch network.

FIG9 shows the switch structure of FIG8 expressed in terms of Ron and Coff.

FIG. 10 shows that in some embodiments, the inductance L of the parasitic compensation circuit can be adjusted based on the off capacitance (Coff) of each switch of the switching network.

11 shows an example of how insertion loss performance can be improved by increasing the size of a series arm switch while reducing or maintaining its parasitic effects through the inductance (L) of a parasitic compensation circuit having one or more features as described herein.

12 shows an example of how insertion loss performance can be improved based on a much larger range of shunt arm switch sizes while reducing or maintaining its parasitic effects through the inductance (L) of a parasitic compensation circuit having one or more features as described herein.

FIG13 shows an example of how a larger sized shunt arm switch can be utilized to improve isolation performance.

FIG. 14 shows insertion loss profiles corresponding to configurations with and without parasitic compensation circuitry as a function of frequency.

FIG15 shows isolation curves corresponding to configurations with and without parasitic compensation circuitry as a function of frequency.

FIG16 shows a switch structure in which the parasitic compensation circuit includes an adjustable inductance circuit.

FIG17 shows the switch structure of FIG16 expressed in terms of Ron and Coff.

FIG. 18 shows that in some embodiments, the inductance L of the parasitic compensation circuit can be adjusted based on the off capacitance (Coff) of each switch of the switching network.

19A-19D illustrate examples of parasitic compensation circuits configured to provide different values of inductance L. FIG.

20A-20D illustrate another example of a parasitic compensation circuit configured to provide different values of inductance L. FIG.

FIG. 21 illustrates a process that may be implemented to achieve a desired inductance in a parasitic compensation circuit having one or more features as described herein.

22A-22D illustrate non-limiting examples of how a parasitic compensation circuit having one or more features as described herein may be implemented in an RF module.

FIG23 depicts an example wireless device having one or more advantageous features described herein.

DETAILED DESCRIPTION

The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

Described herein are structures and methods related to improved performance in switch designs that can be implemented, for example, in radio frequency (RF) applications. Although described in the context of RF applications, it will be appreciated that one or more features of the present application can also be used in other types of switch applications.

In RF systems, switches can be used to turn certain frequency bands on or off to facilitate receive and/or transmit functions. The use of switches has increased significantly recently, as more frequency bands are added to the existing ones. However, due to process limitations in switch design, existing switches can exhibit undesirable insertion loss and limited isolation performance.

For example, many RF switches are implemented in a stacked configuration using process technologies such as silicon-on-insulator (SOI). In such a stacked configuration, multiple switching transistors can be connected in series to provide, for example, power handling capability. A switch with a stack of switching transistors can be implemented along a signal path, and such a switch is often referred to as a series arm, a series arm switch, or the like. A switch with a stack of switching transistors can also be implemented along a shunt from a signal path, and such a switch is often referred to as a shunt arm, a shunt arm switch, or the like. The series arm switch and the shunt arm switch can be configured the same or differently.

The switch implemented in the aforementioned manner can be used in RF applications such as routing of RF signals. For example, a common port such as an antenna port can be coupled to multiple signal paths through a switching network to allow one or more paths to be operated in various operating modes. For example, such modes may include carrier aggregation (CA) mode and non-CA mode. In another example, a common port such as an input port for a broadband low noise amplifier (LNA) can be coupled to multiple signal paths through a switching network to allow one or more paths to be operated in various operating modes. Similarly, these modes may include, for example, carrier aggregation (CA) mode and non-CA mode. In both of the above examples, the switching network should preferably have performance characteristics such as low insertion loss and high isolation.

In the aforementioned RF applications, as well as other switching applications, the size of the switching transistor (e.g., expressed as W/L as described herein) can be increased to improve insertion loss and isolation performance. However, this increase in device size can lead to an undesirable increase in parasitic effects such as parasitic capacitance.

FIG1 shows a block diagram of a switch structure 100 having a switch network 102 coupled to a port (node 104). Although not shown in FIG1 , the other side of the switch network 102 can be coupled to one or more ports. In this document, various examples are described in the context of having multiple ports corresponding to multiple RF signal paths on the other side of the switch network 102. However, it will be understood that one or more features of the present application can also be implemented for a switch network having one path. In addition, it will be understood that the switch network 102 can have a more complex path design than multiple parallel paths. For example, a given path coupled to a port node 104 can be divided into multiple paths.

FIG1 shows that the switch structure 100 may also include a parasitic compensation circuit 106. As described herein, such a circuit may be configured to, for example, compensate for an increase in parasitic capacitance associated with an increase in device size (W/L). Various non-limiting examples of such a circuit are described in more detail herein.

1 , parasitic compensation circuit 106 is depicted on one side of port node 104. However, it is understood that one or more parasitic compensation circuits may also be implemented on the other side of switch network 102, with the illustrated circuit 106, without the circuit 106, or any combination thereof.

FIG2 shows an example of a switch network 102 configured to merge multiple RF signal paths to a common port. A first path from Port1 is shown coupled to a node 104 of the common port through a first series arm switch S1_series. Similarly, a second path from Port2 is shown coupled to the common node 104 through a second series arm switch S2_series. Each of the first and second paths is shown as including a shunt path, for example, to ground. The first shunt path is shown coupling a node 110 of Port1 to ground through a first shunt arm switch S1_shunt. Similarly, the second shunt path is shown coupling a node 112 of Port2 to ground through a second shunt arm switch S2_shunt. A given shunt path can be turned on whenever the corresponding RF signal path is turned off, for example, to provide higher isolation between the corresponding port and the common port.

FIG3 shows an example of the above-mentioned shunt path being connected whenever the corresponding RF signal path is closed. In FIG3, there are three RF signal paths corresponding to Port1, Port2, and Port3 coupled to the common port node 104; and the series arm switches and shunt arm switches corresponding to such paths are depicted as single-pole single-throw (SPST) switches. The first signal path is shown as being connected by the first series arm switch S1_series being in a closed state to connect Port1 to the common node 104. Each of the second and third signal paths is shown as being closed by its corresponding series arm switch (S2_series or S3_series) being in an open state to disconnect its corresponding port (Port2 or Port3) from the common node 104.

In the first signal path that is turned on, the corresponding shunt arm switch S1_shunt is shown in an open state to disconnect node 110 from ground. In each of the second and third signal paths that are turned off, the corresponding shunt arm switch (S2_shunt or S3_shunt) is shown in a closed state to connect its corresponding node (112 or 114) to ground. Therefore, in the example of Figure 3, the first signal path is active between Port1 and the common port, while each of the second and third signal paths is inactive. In each inactive path (second and third signal paths), the closed corresponding shunt arm switch (S2_shunt or S3_shunt) allows the signal and/or noise present at the corresponding port (Port2 or Port3) to be shunted to ground instead of potentially leaking through the open series arm switch (S2_series or S3_series).

In some embodiments, each of the series-arm and shunt-arm switches of FIG. 3 can be implemented in a stacked configuration comprising a plurality of switching transistors arranged in series. FIG. 4 illustrates an example in which the switch network 102 includes switches having such a stacked configuration. In FIG. 4 , there are three RF signal paths similar to the example of FIG. 3 ; however, it will be appreciated that other numbers of paths may be implemented. In FIG. 4 , the arrangement of the series-arm and shunt-arm switches for the three signal paths is substantially the same as in the example of FIG. 3 . In FIG. 4 , the common port of FIG. 3 is depicted as an antenna port; however, it will be appreciated that other ports may be the common port of FIG. 3 .

In FIG4 , the first series arm switch S1_series is depicted as including a plurality of FETs 120 connected in series between Port1 and the common node 104 of the antenna port. Similarly, the second series arm switch S2_series is depicted as including a plurality of FETs 122 connected in series between Port2 and the common node 104 of the antenna port. Similarly, the third series arm switch S3_series is depicted as including a plurality of FETs 124 connected in series between Port3 and the common node 104 of the antenna port. For purposes of description, it will be understood that each of the three series arm switches includes the same number of FETs, wherein each FET has a W/L dimension. However, it will be understood that such series arms having the same configuration are not required.

Similarly, in FIG4 , the first shunt arm switch S1_shunt is depicted as including a plurality of FETs 130 connected in series between Port1 and ground. The second shunt arm switch S2_shunt is depicted as including a plurality of FETs 132 connected in series between Port2 and ground. The third shunt arm switch S3_shunt is depicted as including a plurality of FETs 134 connected in series between Port3 and ground. For purposes of this description, it will be understood that each of the three shunt arm switches includes the same number of FETs, each having a W/L dimension. However, it will be understood that such shunt arms having the same configuration are not required. It will be understood that the number of FETs associated with the series arm switch and the shunt arm switch can be the same or different. Similarly, the W/L dimensions associated with the series arm switch and the shunt arm switch can be the same or different.

A switch network configured in the aforementioned example manner can produce on-resistance (Ron) and off-capacitance (Coff) characteristics for each switch. Generally, when the switches of a given stack are turned on, their on-resistance (Ron) is preferably low to reduce or minimize the power loss of the RF signal passing through the switch. When the switches of a given stack are turned off, their off-capacitance (Coff) is preferably low to reduce or minimize parasitic effects.

FIG5 depicts a switch network 102 represented by Ron and Coff for the example configuration of FIG4 and in the example switch state of FIG3. Thus, the first series arm switch S1_series that is turned on is shown as having an on-resistance of Ron_series. Similarly, each of the second and third shunt arm switches (S2_shunt, S3_shunt) that are turned on is shown as having an on-resistance of Ron_shunt. As described herein, the on-resistance (Ron) among the series arm switches can be the same or different. Similarly, the on-resistance (Ron) among the shunt arm switches can be the same or different.

The first shunt arm switch S1_shunt, which is turned off, is shown as having an off capacitance of Coff_shunt. Similarly, each of the second and third series arm switches (S2_series, S3_series) that are turned off is shown as having an off capacitance of Coff_series. As described herein, the off capacitance (Coff) among the series arm switches can be the same or different. Similarly, the off capacitance (Coff) among the shunt arm switches can be the same or different.

In the examples of Figures 4 and 5, each arm, whether a series arm or a shunt arm, includes multiple devices connected in series. Therefore, assuming that each device has the same on-resistance as the other devices in a given arm, the total on-resistance of the arm can be approximated by the on-resistance of each device multiplied by the number of devices. Similarly, assuming that each device has the same off-capacitance as the other devices in a given arm, the total off-capacitance of the arm can be approximated by the off-capacitance of each device divided by the number of devices.

It should also be noted that for the purposes of this description, the Ron of a device is generally inversely proportional to the device dimension ratio W/L. Thus, when a given arm (whether it is a series arm or a shunt arm) is turned on, an increase in the W/L of the device results in a decrease in the on-resistance of that arm. Furthermore, the Coff of a device is generally proportional to the device dimension ratio W/L. Thus, when a given arm (whether it is a series arm or a shunt arm) is turned off, an increase in the W/L of the device results in an increase in the off-capacitance of that arm. Examples of device dimensions W and L are described in more detail with reference to FIG6 .

FIG6A shows a configuration similar to the example of FIG4 . FIG6A further shows that in some embodiments, each device in FIG4 (e.g., 120, 122, 124, 130, 132, or 134) may include multiple FETs arranged in a parallel configuration. For example, device 140 in the series arm is shown as having two FETs connected in a parallel configuration. Similarly, device 142 in the shunt arm is shown as having two FETs connected in a parallel configuration. It will be understood that such devices in the series arm (e.g., 140) and/or the shunt arm (e.g., 142) may include a greater or lesser number of FETs.

FIG6B shows a circuit representation of a device (140 or 142) having two example FETs, and an example layout thereof. In the example of FIG6B , the drain D1 of the first FET and the drain D2 of the second FET are connected at a common node. Similarly, the source S1 of the first FET and the source S2 of the second FET are connected at a common node. Thus, the first FET and the second FET are electrically connected in parallel between the common drain node and the common source node. The gate G1 of the first FET and the gate G2 of the second FET can be controlled together or not.

In the example layout of FIG6B , two gate fingers, designated G1 and G2, disposed on the active area can create a dual FET configuration. The area to the left of the first gate G1 can function as D1, while the area to the right of the second gate can function as D2, such that the two drains D1 and D2 are connected at a common node D1D2. The area between the first gate G1 and the second gate G2 can function as a common source S1S2, and such a common source is shown connected to the common node S1S2. It will be appreciated that the designations of source and drain can be reversed.

In the example layout of FIG6B , dimension W represents the width of the active area, while dimension L represents the length of each gate. Therefore, it is understood that multiple references to the ratio W/L herein may refer to such an arrangement. It is also understood that one or more features of the present application may apply even if the dimensional parameters are expressed in other ways.

Referring to FIG6B , it is noteworthy that similar layouts can be implemented for devices with a greater or lesser number of FETs. For example, if the device has one FET, the layout can include a gate (G1) between the drain (D1) and the source (S1), with the source and drain connected to their respective nodes. In another example, if the device has three FETs, the example layout of FIG6B can be expanded to include a third gate (G3) to the right of D2, followed by a source region (S2S3) to the right of G3. For such an example, the two drain regions (D1, D2) can be connected to a common node, and the two source regions (S1S2 and S2S3) can be connected to a common node.

FIG7 shows an example of the insertion loss and isolation characteristics of the switch described with reference to FIG4-6. The upper left panel shows a graph 160 of the insertion loss of the switch network (102 in FIG4 and 5) as a function of the W/L of the series arm. The upper right panel shows a graph 168 of the insertion loss of the switch network 102 as a function of the W/L of the shunt arm. The lower left panel shows a graph 164 of the isolation of the switch network 102 as a function of the W/L of the series arm. The lower right panel shows a graph 172 of the isolation of the switch network 102 as a function of the W/L of the shunt arm.

As shown in the upper left panel, for a given W/L shunting value, as the W/L of the series arm increases, the insertion loss of the switch network 102 generally decreases to a minimum insertion loss value. However, as the W/L of the series arm continues to increase, the insertion loss of the switch network 102 increases due to, for example, an increased frequency response from Coff_series, which loads the signal path and thereby causes increased leakage into other paths. Therefore, for a given W/L shunting value, the region designated 162 includes the optimal or desired value of the W/L of the series arm corresponding to the minimum insertion loss.

As shown in the upper right panel, for a given W/L series value, as the W/L of the shunt arm increases, the insertion loss of the switch network 102 generally increases. This increase may be due to, for example, an increased frequency response from Coff_shunt, which loads the corresponding signal path and thereby causes increased leakage. Therefore, for a given W/L series value, the area represented as 170 includes the optimal or desired value for the W/L of the shunt arm.

As shown in the lower left panel, for a given W/L shunt value, as the W/L of the series leg increases, the isolation level of the switch network 102 generally decreases. Therefore, for a given W/L shunt value, the region represented as 166 includes the optimal or desired value of the W/L of the series leg for producing a high isolation level.

As shown in the lower right panel, for a given W/L series value, as the W/L of the shunt arm increases, the isolation level of the switch network 102 generally increases. Therefore, for a given W/L series value, the region designated 174 includes the optimal or desired value of the W/L of the shunt arm for producing a high isolation level.

It is worth noting that the sizes of the W/L series and W/L shunt that produce the optimum value of insertion loss and the optimum isolation are usually different. Therefore, such performance parameters can be considered individually or in some combination to produce the desired overall performance of the switching network.

As described herein, increasing the size of a switch can be beneficial; however, this increase in size typically results in an increase in off-capacitance. As described with reference to FIG7 , the off-capacitance (Coff) of both the series and shunt arm switches can contribute to degradation in insertion loss performance. Based on the foregoing, reducing the impact of this off-capacitance of a switch can be beneficial because such a reduction allows a given switch size to be increased to a larger value for a given level of parasitic effects.

FIG8 illustrates an example of a switch structure 100 in which a parasitic compensation circuit 106 may include an inductor L configured to reduce the effects of the off-capacitance (Coff) of each switch in the switch network 102. In FIG8 , the arrangement of the series arm switches (S1_series, S2_series, S3_series) and shunt arm switches (S1_shunt, S2_shunt, S3_shunt) in the switch network 102 is substantially the same as in the example of FIG4 . However, the W/L dimensions of such switches may be the same as or different from those in the example of FIG4 . For example, due to the presence of the parasitic compensation circuit 106, the W/L dimensions of either or both the series and shunt arm switches may be larger than in the example of FIG4 .

More specifically, each series arm switch may include a stack of devices, wherein each device has a size characterized by W/L. It will be understood that each device in the series arm switch may include one FET or N FETs arranged in a parallel configuration as described with reference to Figures 6A and 6B. Similarly, each shunt arm switch may include a stack of devices, wherein each device has a size characterized by W/L. It will also be understood that each device in the shunt arm switch may include one FET or M FETs arranged in a parallel configuration as described with reference to Figures 6A and 6B. Although W/L is used to describe both series and shunt arm switches, it will be understood that their respective sizes may be the same or different.

8, inductance L of parasitic compensation circuit 106 is shown coupling antenna node 104 to ground. As described herein, the value of L can be selected to reduce the effect of the off capacitance associated with switching network 102 for a selected frequency value or frequency range.

Figure 9 shows the switch structure of Figure 8, in which the switch network 102 is depicted in the form of Ron and Coff in the example switch state of Figure 3. Therefore, the first series arm switch S1_series that is turned on is shown as having a total on-resistance of Ron_series/N, where N is a positive integer. When N=1, each device in the series arm switch has one FET; and when N>1, each device has N FETs arranged in a parallel configuration. Similarly, each of the second and third shunt arm switches (S2_shunt, S3_shunt) that are turned on is shown as having a total on-resistance of Ron_shunt/M, where M is a positive integer. When M=1, each device in the shunt arm switch has one FET; and when M>1, each device has M FETs arranged in a parallel configuration.

The first shunt arm switch S1_shunt that is turned off is shown as having a total off capacitance of Coff_shunt×M, where M is a positive integer as described above. Similarly, each of the second and third series arm switches (S2_series, S3_series) that are turned off is shown as having a total off capacitance of Coff_series×N, where N is a positive integer as described above.

FIG10 shows that in some embodiments, the inductance L of the parasitic compensation circuit 106 can be adjusted based on the off capacitance (Coff) of each switch of the switch network. For example, the total off capacitance (Coff_total) of the switch network can be obtained or estimated, and the value of L can be estimated based on the LC resonant frequency, so that

Where f is the frequency of interest.

In the example of Figure 10, the value of Coff_total is based on the first signal path (between Port1 and the antenna port) being turned on and the other two signal paths being turned off. The value of Coff_total can be based on other signal routing configurations; therefore, corresponding values of L can be estimated for such configurations. In an embodiment where all series arm switches are approximately identical and all shunt arm switches are approximately identical, it can be seen that, for a given frequency of interest, a value of L can be estimated to compensate for Coff_total when any one path is turned on while the other paths are turned off. Similarly, for a given frequency of interest, if any two paths are turned on while the other paths are turned off (e.g., for carrier aggregation), Coff_total can be compensated using a value of L.

As described herein (e.g., with reference to FIG7 ), the beneficial effects of increasing the W/L dimensions of the switching transistor may be limited by the corresponding increase in parasitic capacitance. However, as described with reference to FIG10 , this parasitic capacitance can be estimated and compensated for by providing an appropriately valued inductor at a common node, such as an antenna port. FIG11-13 illustrate examples of how such an inductor can be used to improve insertion loss and isolation performance.

FIG11 illustrates an example of how insertion loss performance can be improved by increasing the size of the series arm switch while reducing or maintaining its parasitic effects through the inductance (L) of a parasitic compensation circuit having one or more features as described herein. An insertion loss curve 160 (as a function of the W/L of the series arm) is similar to the example in the upper left panel of FIG7 and corresponds to a configuration without a parasitic compensation circuit. This curve includes a minimum insertion loss value (for a given W/L of the shunt arm) as the W/L of the series arm increases (in region 162 in FIG7), after which the insertion loss increases due to the effects of the parasitic capacitance.

In FIG11 , an insertion loss curve 180 (as a function of the W/L of the series arm) is shown for a configuration with a parasitic compensation circuit. It can be seen that, due to the inductance L that reduces the effects of parasitic capacitance as described herein, multiple beneficial effects can be achieved in the context of insertion loss. For example, it can be seen that the insertion loss curve 180 is generally lower than the insertion loss curve 160 overall. In another example, the W/L of the series arm (for a given W/L of the shunt arm) can be increased to a larger value before reaching a minimum value. Beyond such a minimum value, if the W/L of the series arm continues to increase, the effects of parasitic capacitance (if any) may begin to dominate and result in an increase in insertion loss. In FIG11 , for a given shunt switch configuration (e.g., as in FIG8-10 ), this new minimum or desired reduced insertion loss value is shown in the region designated 182. Thus, arrow 184 represents an example improvement in insertion loss performance that can be achieved.

FIG12 shows an example of how insertion loss performance can be improved for a much wider range of shunt arm switch sizes while reducing or maintaining its parasitic effects through the inductance (L) of a parasitic compensation circuit having one or more features as described herein. An insertion loss curve 168 (as a function of the W/L of the shunt arm) is similar to the example in the upper right panel of FIG7 and corresponds to a configuration without a parasitic compensation circuit. This curve includes a general increase in insertion loss (for a given series arm W/L) as the W/L of the shunt arm increases.

In FIG12 , an insertion loss curve 190 (as a function of the W/L of the shunt arm) is shown for a configuration with parasitic compensation circuitry. It can be seen that the insertion loss curve 190 is generally lower than the insertion loss curve 168 overall. This general reduction in the insertion loss curve (depicted by arrow 192) is due to the inductance L, which reduces the effects of parasitic capacitance as described herein. In the example shown, the W/L of the shunt arm can be increased (for a given W/L of the series arm) while maintaining a desired insertion loss level. At the higher end of the W/L range, the improvement in insertion loss performance (of curve 190) compared to curve 168 is more pronounced, and this exemplary improvement is represented by arrow 194.

FIG13 shows an example of how a larger shunt arm switch can be used to improve isolation performance. A curve 172 of isolation (as a function of the W/L of the shunt arm) is similar to the example in the lower right panel of FIG7 and corresponds to a configuration without parasitic compensation circuitry. This curve includes a general increase in isolation (for a given series arm W/L) as the shunt arm W/L increases.

In Figure 13, the isolation curve 200 (as a function of the W/L of the shunt arm) is for a configuration having a parasitic compensation circuit having one or more features as described herein. It can be seen that the isolation curve 200 can allow the increasing trend of isolation to continue as the W/L increases. This continued increase in isolation (due to the increase in the W/L of the shunt arm) can be balanced with an increase in insertion loss. As described with reference to Figure 12, larger values of W/L can be achieved while maintaining or reducing such insertion loss. Therefore, the upper limit of the increase in the W/L of the shunt arm can be expanded to achieve increased isolation while maintaining or reducing insertion loss. In Figure 13, this increased upper limit of the isolation performance (of curve 200) is represented in region 202, and the exemplary improvement obtained is represented by arrow 204.

It is also worth noting that the sizes of the W/L series and W/L shunt that produce the optimum or desired value of insertion loss and the optimum isolation are usually different. Therefore, such performance parameters can be considered individually or in some combination to produce the desired overall performance of the switching network.

Figures 14 and 15 show examples of simulation results that demonstrate the improvements in insertion loss performance and isolation performance that can be achieved by implementing the parasitic compensation circuit as described herein. Figure 14 shows insertion loss curves corresponding to configurations with and without the parasitic compensation circuit as a function of frequency. Figure 15 shows isolation curves corresponding to the same configurations with and without the parasitic compensation circuit as a function of frequency. In both examples of Figures 14 and 15, the switch network includes three signal paths similar to the examples of Figures 4 and 8. Each series arm switch has a stack of devices, each of which has two FETs arranged in parallel (N=2). Each shunt arm switch has a stack of devices, each of which has 20 FETs arranged in parallel (M=20). The values of W/L of such transistors in the series arm switch and the shunt arm switch correspond to various optimized values in the presence of the parasitic compensation circuit. For the configuration with the parasitic compensation circuit, the value of L varies from 1nH to 8nH in steps of 1nH, and has a Q value of 30 at 2GHz.

In FIG14 , insertion loss curve 210 corresponds to the aforementioned configuration without parasitic compensation circuitry. As shown, the magnitude of the insertion loss increases with increasing frequency. Insertion loss curves 212a-212h correspond to the aforementioned configuration with parasitic compensation circuitry, with eight curves corresponding to eight example values of L. The leftmost curve 212a corresponds to L = 8 nH, the next curve 212b corresponds to L = 7 nH, the next curve 212c corresponds to L = 6 nH, the next curve 212d corresponds to L = 5 nH, the next curve 212e corresponds to L = 4 nH, the next curve 212f corresponds to L = 3 nH, the next curve 212g corresponds to L = 2 nH, and the rightmost curve 212h corresponds to L = 1 nH. It can be seen that with appropriate values of L, the insertion loss magnitude can be reduced to approximately 0.2 dB over a wide frequency range. This insertion loss magnitude is indicated as 214. It can also be seen that the improvement compared to the configuration without parasitic compensation circuitry (curve 210) becomes greater with increasing frequency. This improvement compared to the configuration without the parasitic compensation circuit (curve 210 ) is indicated by arrow 216 .

In Figure 15 , isolation curve 220 (S(4, 1)) corresponds to the aforementioned configuration without the parasitic compensation circuit. As shown, the magnitude of the isolation decreases with increasing frequency. Isolation curve 222 (S(3, 1)) corresponds to the aforementioned configuration with the parasitic compensation circuit, with eight curves corresponding to eight example values of L. It can be seen that using any of the eight values of L significantly increases the magnitude of the isolation over a wide frequency range. This improvement compared to the configuration without the parasitic compensation circuit (curve 220) is indicated by arrow 224.

As shown in the example of Figure 14, implementing different L values in the parasitic compensation circuit can significantly improve insertion loss performance over a relatively wide frequency range. In some applications, it is desirable to be able to provide this improved performance at different frequency values or frequency ranges using the same parasitic compensation circuit. In some embodiments, this functionality can be provided by a variable inductance circuit, such as a circuit having multiple switchable inductances.

FIG16 shows a switch structure 100 similar to the example of FIG8. FIG17 shows the switch structure of FIG16, wherein the switch network 102 is depicted in the form of Ron and Coff in the example switching state of FIG3. Similar to the examples of FIG8 and FIG9, the devices in the series arm include N FETs connected in parallel, where N is a positive integer; and the devices in the shunt arm include M FETs connected in parallel, where M is a positive integer.

In Figures 16 and 17, the parasitic compensation circuit 106 is shown as including an inductor circuit that can provide different inductance values through switch operation. For example, K inductors (L1, L2, ..., LK) are shown as being arranged in series between the antenna node 104 and the ground. Each inductor and the corresponding switch (SL1, SL2, ..., or SLK) are shown as being arranged in parallel. Therefore, the opening and/or closing of the switch (SL1, SL2, ..., SLK) can produce a total inductance L having a value from 0 (or close to 0) to L1+L2+ ...+LK. A more specific example of such an adjustable inductor circuit is described in more detail herein. It will be understood that the various inductance values (L1, L2, ..., LK) can be the same or different. It will also be understood that, although described in the context of the inductors being arranged in series, the inductors can also be arranged in other configurations. In some embodiments, the value K can be an integer greater than or equal to 2.

Similar to FIG10 , FIG18 illustrates that in some embodiments, the inductance L of the parasitic compensation circuit 106 can be adjusted based on the off capacitance (Coff) of each switch in the switch network. In FIG18 , such adjustment of the inductance L can be implemented using the example inductor circuit described with reference to FIG16 and FIG17 .

Figures 19 and 20 show more specific examples of the parasitic compensation circuit 106 of Figures 16-18. In the example of Figure 19, the parasitic compensation circuit 106 is shown as including eight inductors, each of which has an inductance of L0. Each inductor is shown with a switch connected in parallel. Therefore, a given inductor can provide its inductance L0 when its switch is open. When the switch is closed, the inductor is bypassed.

The chain of switched inductors described above can be implemented between a common node, such as the antenna node of Figures 16-18, and ground to provide a variable inductance from 0 (or nearly 0) to 8L0 (or nearly 8L0) in steps of L0. Therefore, if L0 has a value of 1 nH, the chain of switched inductors in the example parasitic compensation circuit 106 can provide improved insertion loss performance as described in Figure 14.

In Figure 19, four example states of a switch inductor string are shown. Figure 19A shows a state in which all eight switches (SL1 to SL8) are closed. Therefore, each of the eight inductors is bypassed, resulting in a total inductance L of approximately 0. Figure 19B shows a state in which one of the eight switches (e.g., SL1) is disconnected and the remaining switches are closed. Therefore, one inductor is active, and each of the remaining seven inductors is bypassed, resulting in a total inductance L of approximately L0. Figure 19C shows a state in which four of the eight switches (e.g., SL1 to SL4) are disconnected and the remaining switches are closed. Therefore, four inductors are active, and each of the remaining four inductors is bypassed, resulting in a total inductance L of approximately 4L0. Figure 19D shows a state in which all eight switches are disconnected. Therefore, all eight inductors are active, resulting in a total inductance L of approximately 8L0.

FIG20 shows an example of a parasitic compensation circuit 106 including inductors of different values. Each inductor is shown with a switch connected in parallel. Thus, a given inductor can provide its inductance when its switch is open. When the switch is closed, the inductor is bypassed.

FIG20 shows that in some embodiments, inductors with different values can be arranged in independently switchable cascaded binary-weighted stages. In this configuration, N stages can provide ^2N inductance states. For example, 3 stages can be implemented using inductance values of L0, 2L0, and 4L0. Using such stages, ²³ or 8 inductance states can be achieved.

For example, FIG20A shows a state in which all three switches (SL1 to SL3) are closed. Thus, each of the three inductors is bypassed, resulting in a total inductance L of approximately 0. FIG20B shows a state in which SL1 is open and the remaining switches are closed. Thus, the L0 inductor is active, and each of the remaining two inductors is bypassed, resulting in a total inductance L of approximately L0. FIG20C shows a state in which SL3 is open and the remaining switches are closed. Thus, the 4L0 inductor is active, and each of the remaining two inductors is bypassed, resulting in a total inductance L of approximately 4L0. FIG20D shows a state in which all three switches are open. Thus, each of the L0 inductor, the 2L0 inductor, and the 4L0 inductor is active, resulting in a total inductance L of approximately 7L0. Table 1 lists various combinations of three inductors for L and their corresponding total inductance values. In Table 1, an open switch corresponds to an active state of the corresponding inductor, and a closed switch corresponds to an inactive state of the inductor.

Table 1

FIG21 illustrates a process 250 that can be implemented to achieve a desired inductance in a parasitic compensation circuit having one or more features as described herein. In block 252, a range or value of an operating frequency can be determined. In block 254, a desired compensation inductance value can be determined for the operating frequency. In some embodiments, the compensation inductance value can be selected to compensate for the total off-capacitance associated with a switching network configured to facilitate the operating frequency. In block 256, one or more switching operations can be performed in an inductive circuit that couples a common node of the switching network to ground to produce the desired compensation inductance.

In some embodiments, one or more features of the present application can be implemented in multiple products. Figures 22A-22D illustrate non-limiting examples of such products in the context of an RF module. It will be appreciated that one or more parts of such an RF module can also be a product having one or more features of the present application.

For example, FIG22A shows that a semiconductor die 300 may include a switch network 102 and a parasitic compensation circuit 106 having one or more features as described herein. Such a die may include a die substrate 302. In some embodiments, the die 300 may be, for example, a silicon-on-insulator (SOI) die. FIG22A further shows that in some embodiments, the die 300 may be mounted on an RF module 310. Such a module may include a package substrate 312 configured to accommodate multiple components including the die 300. Although not shown in FIG22A, other dies and/or surface mount devices (SMDs) may also be mounted on the package substrate 312. The package substrate may include, for example, a laminate substrate or a ceramic substrate.

22B shows a configuration in which a die 300 having some of one or more features as described herein is mounted on a package substrate 312 of an RF module 310. The die 300 is shown as including a die substrate 302. In the example shown, the switch network 102 having one or more features as described herein is shown as being implemented on the die 300, and a portion of the parasitic compensation circuit 106 is shown as also being implemented on the die 300. Another portion of the parasitic compensation circuit 106 is shown as being implemented external to the die 300. Such another portion can be implemented on and/or within the package substrate (e.g., as part of the substrate, as a discrete component, or some combination thereof), or implemented on a separate die, or any combination thereof.

22C and 22D illustrate examples of an RF module 310 in which a die 300 includes a switch network 102 and a parasitic compensation circuit 106 is implemented substantially external to the die 300. In the example of FIG22C , the parasitic compensation circuit 106 is shown as being implemented on and/or within a package substrate 312, substantially external to the die 300. In the example of FIG22D , the parasitic compensation circuit 106 is shown as being implemented on a second die 304 having a die substrate 306. The two example dies 300, 304 may or may not be based on the same process technology.

Parasitic compensation circuits having one or more features of the present application are sometimes described as being implemented on a substrate such as a package substrate. It is understood that such parasitic compensation circuits may have portions implemented on the surface of the substrate, within the substrate, or any combination thereof.

In some implementations, structures, devices, and/or circuits having one or more features described herein may be included in an RF device, such as a wireless device. Such structures, devices, and/or circuits may be implemented directly in the wireless device, in one or more modular forms as described herein, or in some combination thereof. In some embodiments, such a wireless device may include, for example, a cellular phone, a smartphone, a handheld wireless device with or without telephone functionality, a wireless tablet, a wireless router, a wireless access point, a wireless base station, and the like. Although described in the context of a wireless device, it will be appreciated that one or more features of the present disclosure may also be implemented in other RF systems, such as a base station.

23 depicts an example wireless device 400 having one or more advantageous features described herein. In some embodiments, such advantageous features may be implemented in a front end (FE) module 310. In some embodiments, such a FEM may include more or fewer components than indicated by the dashed box.

The PAs in the PA module 412 can receive their respective RF signals from the transceiver 410, which can be configured and operated to generate RF signals to be amplified and transmitted, and to process the received signals. The transceiver 410 is shown interacting with the baseband subsystem 408, which is configured to provide conversion between data and/or voice signals for a user and RF signals for the transceiver 410. The transceiver 410 is also shown connected to the power management component 406, which is configured to manage power for the operation of the wireless device 400. Such power management can also control the operation of the baseband subsystem 408 and other components of the wireless device 400.

The baseband subsystem 408 is shown connected to the user interface 402 to facilitate various inputs and outputs of voice and/or data to and from the user. The baseband subsystem 408 may also be connected to the memory 404, which is configured to store data and/or instructions to facilitate operation of the wireless device and/or provide storage of user information.

In the example wireless device 400, the front-end module 310 may include a switch structure 100 configured to provide one or more functions as described herein. Such a switch structure may be implemented, for example, in an antenna switch module (ASM) 414. In some embodiments, at least some of the signals received via the antenna 420 may be routed from the ASM 414 to one or more low noise amplifiers (LNAs) 418. The amplified signals from the LNAs 418 are shown routed to the transceiver 410.

Some other wireless device configurations can utilize one or more of the features described herein. For example, a wireless device need not be a multi-band device. In another example, a wireless device can include additional antennas such as a diversity antenna, and additional connectivity features such as Wi-Fi, Bluetooth, and GPS.

In various examples disclosed herein, parasitic compensation circuits are described in the context of inductive circuits. It will be appreciated that in some embodiments, such parasitic compensation circuits may also include other non-inductive elements.

In various examples described herein, circuit elements such as capacitors, inductors, and/or resistors may be referred to. It is understood that such circuit elements may be implemented as devices such as capacitors, inductors, and/or resistors. Such devices may be implemented as discrete devices and/or distributed devices.

Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise," "comprising," and the like are to be interpreted in an inclusive sense, as opposed to an exclusive or exhaustive sense, that is, in the sense of "including but not limited to." The word "coupled," as generally used herein, means that two or more elements may be connected directly or via one or more intermediate elements. Additionally, when used in this application, the words "herein," "above," "below," and words of similar meaning shall refer to this application as a whole and not to any particular parts of this application. Where the context permits, words in the above detailed description that use the singular or plural may also include the plural or singular, respectively. The word "or" when referring to a list of two or more items encompasses all of the following interpretations of the word: any item in the list, all items in the list, and any combination of the items in the list.

The above detailed description of the embodiment of the present invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. Although specific embodiments of the present invention and examples for the present invention have been described above for illustrative purposes, various equivalent modifications within the scope of the present invention are possible as will be appreciated by those skilled in the art. For example, although processes or blocks are presented in a given order, alternative embodiments may perform processes with steps in a different order, or employ systems with blocks in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Similarly, although processes or blocks are sometimes shown as being performed serially, on the contrary, these processes or blocks may also be performed in parallel, or may be performed at different times.

The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above.The elements and acts of the various embodiments described above can be combined to provide further embodiments.

Although certain embodiments of the present invention have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the present application. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present application. The accompanying drawings and their equivalents are intended to encompass such forms or modifications as would fall within the scope and spirit of the present application.

Claims (58)

1. A switching structure, comprising: A switching network includes one or more switchable signal paths coupled to a common node. Each switchable signal path includes a series arm switch configured to connect the common node and a corresponding path node in an ON state and to disconnect the common node from the corresponding path node in an OFF state. Each switchable signal path also includes a shunt arm switch configured to connect the corresponding path node to ground when the corresponding series arm switch is OFF and to disconnect the corresponding path node from ground when the corresponding series arm switch is ON. Each switchable signal path contributes to parasitic effects associated with the switching network. A parasitic compensation circuit, coupled to the common node and configured to compensate for the parasitic effects of the switching network, includes an inductor circuit having a plurality of switchable inductors connected in series. 2. The switching structure as described in claim 1, wherein the switching network includes a plurality of switchable signal paths. 3. The switch structure as described in claim 1, wherein the common node is an antenna port or is coupled to the antenna port. 4. The switching structure of claim 1, wherein each series arm switch comprises a stack of transistor devices, each transistor device having a cutoff capacitance Coff that increases with its size, and each shunt arm switch comprises a stack of transistor devices, each transistor device having a cutoff capacitance Coff that increases with its size. 5. The switching structure of claim 4, wherein each transistor device of the series arm switch comprises N field-effect transistors arranged in parallel, and each transistor device of the shunt arm switch comprises M field-effect transistors arranged in parallel, wherein each of N and M is a positive integer. 6. The switching structure of claim 4, wherein the inductor circuit is coupled to the common node and the ground, the inductor circuit has an inductance L, the inductance L compensating for the parasitic effects of one or more of the cutoff capacitors, including the series arm switch and the shunt arm switch. 7. The switching structure as claimed in claim 6, wherein the inductance L of the parasitic compensation circuit is selected to have a value L = 1/[ ^4π²f² ( ^Coff_total )], where f is the operating frequency and Coff_total is the total cutoff capacitance of the switching network. 8. The switching structure of claim 6, wherein the presence of the inductance L of the parasitic compensation circuit allows for a larger size of either or both of the series arm and shunt arm switching transistors to improve switching performance, while reducing the parasitic effect of the cutoff capacitance of the series arm switch and the shunt arm switch. 9. The switching structure as described in claim 8, wherein the switching performance includes insertion loss performance. 10. The switching structure of claim 9, wherein the size of either or both of the series arm and shunt arm switching transistors is larger than the size of the corresponding transistor in the switching structure of the inductor L without the parasitic compensation circuit. 11. The switching structure of claim 10, wherein the switching network of the switching structure with the inductor L having the parasitic compensation circuit has a lower insertion loss than the switching network of the switching structure with the inductor L without the parasitic compensation circuit. 12. The switching structure as claimed in claim 8, wherein the switching performance includes isolation performance. 13. The switching structure of claim 12, wherein the size of the shunt arm switching transistor is larger than the size of the corresponding transistor in the switching structure of the inductor L without the parasitic compensation circuit. 14. The switching structure of claim 13, wherein the switching network of the switching structure having the inductor L of the parasitic compensation circuit has a higher isolation than the switching network of the switching structure without the inductor L. 15. The switching structure of claim 6, wherein the inductor circuit is configured to provide a substantially fixed value for the inductance L of the parasitic compensation circuit. 16. The switching structure of claim 6, wherein the inductor circuit is configured to provide a plurality of different values of the inductance L for the parasitic compensation circuit. 17. The switching structure of claim 16, wherein each switchable inductor comprises an inductor and a switch connected in parallel. 18. The switching structure of claim 16, wherein the inductance values of the switchable inductors are substantially the same. 19. The switching structure of claim 16, wherein the switchable inductor has different inductance values. 20. The switching structure of claim 19, wherein the different inductance values are selected to provide a cascaded binary weighted stage. 21. A method for routing signals, the method comprising: In a switching network, switching operations are performed to allow one or more signals to pass through one or more corresponding switchable signal paths coupled to a common node. Each switchable signal path includes a series arm switch configured to connect the common node and the corresponding path node in an ON state and disconnect the common node from the corresponding path node in an OFF state. Each switchable signal path also includes a shunt arm switch configured to connect the corresponding path node to ground when the corresponding series arm switch is OFF and disconnect the corresponding path node from ground when the corresponding series arm switch is ON. Each switchable signal path contributes to parasitic effects associated with the switching network. The parasitic effect at the common node is compensated by a parasitic compensation circuit, which includes an inductor circuit with multiple switchable inductors connected in series. 22. A method for manufacturing a switchgear, the method comprising: Forming or providing a switching network, the switching network comprising one or more switchable radio frequency signal paths, each path contributing to parasitic effects associated with the switching network; Forming a parasitic compensation circuit; and The parasitic compensation circuit is coupled to a node of the switching network. The parasitic compensation circuit is configured to compensate for the parasitic effects of the switching network. The parasitic compensation circuit includes an inductor circuit with a plurality of switchable inductors connected in series. 23. A radio frequency module, comprising: A packaging substrate configured to house multiple components; A switching network implemented on the packaging substrate, the switching network including one or more switchable radio frequency signal paths, each path contributing to parasitic effects associated with the switching network; and A parasitic compensation circuit implemented on the packaging substrate, the parasitic compensation circuit being coupled to a node of the switching network, the parasitic compensation circuit being configured to compensate for the parasitic effects of the switching network, the parasitic compensation circuit including an inductor circuit having a plurality of switchable inductors connected in series. 24. The radio frequency module of claim 23, wherein the switching network is implemented on the first chip. 25. The radio frequency module of claim 24, wherein the first wafer comprises silicon on insulator (SOI). 26. The radio frequency module of claim 24, wherein at least a portion of the parasitic compensation circuit is implemented on the first chip. 27. The radio frequency module of claim 24, wherein at least a portion of the parasitic compensation circuit is implemented on the second chip. 28. The radio frequency module as claimed in claim 23, wherein the radio frequency module is an antenna switch module. 29. A radio frequency device, comprising: The transceiver is configured to process signals; An antenna switching module, communicating with the transceiver and configured to route an amplified signal for transmission and a received signal for amplification, includes a switching network having one or more switchable signal paths coupled to a common node. Each switchable signal path includes a series arm switch configured to connect the common node and a corresponding path node in an ON state and disconnect the common node from the corresponding path node in an OFF state. Each switchable signal path also includes a shunt arm switch configured to connect the corresponding path node to ground when the corresponding series arm switch is OFF and disconnect the corresponding path node from ground when the corresponding series arm switch is ON. Each switchable signal path contributes to parasitic effects associated with the switching network. The antenna switching module also includes a parasitic compensation circuit coupled to the common node and configured to compensate for the parasitic effects of the switching network. The parasitic compensation circuit includes an inductor circuit having a plurality of switchable inductors connected in series. An antenna that communicates with the antenna switch module and is configured to cause either or both of the transmission and reception of a corresponding signal. 30. The radio frequency device of claim 29, wherein the radio frequency device is a wireless device. 31. The radio frequency device of claim 30, wherein the wireless device is a cellular phone. 32. An adjustable compensation circuit for a radio frequency switching circuit, the adjustable compensation circuit comprising an inductor circuit coupling a selected node of the radio frequency switching circuit to a reference node, the inductor circuit comprising a plurality of switchable inductors connected in series, each switchable inductor comprising a parallel arrangement of an inductor and a switch, each inductor having a substantially constant inductance value of L0, such that the inductor circuit can provide an inductance value from L0 to a total inductance in steps of L0, the total inductance being approximately equal to L0 multiplied by the number of the switchable inductors. 33. The adjustable compensation circuit as described in claim 32, wherein the radio frequency switching circuit includes multiple switchable signal paths. 34. The adjustable compensation circuit of claim 33, wherein the reference node is a ground node. 35. The adjustable compensation circuit of claim 34, wherein the selected node of the radio frequency switching circuit is a common node for the plurality of switchable signal paths. 36. The adjustable compensation circuit of claim 35, wherein the common node is the antenna port. 37. The adjustable compensation circuit of claim 35, wherein each of the plurality of switchable signal paths includes a series arm switch configured to connect the common node and its corresponding path node in an ON state, and to disconnect the common node from its corresponding path node in an OFF state. 38. The adjustable compensation circuit of claim 37, wherein each of the plurality of switchable signal paths further comprises a shunt arm switch configured to connect its corresponding path node to ground when the corresponding series switch arm is in the off state, and to disconnect the path node from the ground when the series switch arm is in the on state. 39. A switching circuit, comprising: Public nodes; Multiple series arm switches, each implemented between the common node and the corresponding path node, and configured to connect the common node and the corresponding path node in an ON state and disconnect the common node from the corresponding path node in an OFF state, each series arm switch comprising a stack of transistor devices, each transistor device having a cutoff capacitance Coff that increases with its size; Shunt arm switches are implemented between each path node of a corresponding series arm switch and ground, and are configured to connect the path node to ground when the corresponding series arm switch is in an off state and disconnect the path node from ground when the corresponding series arm switch is in an on state. Each shunt arm switch includes a stack of transistor devices, each transistor device having a cutoff capacitance Coff that increases with its size; and an adjustable compensation circuit having an inductor circuit that couples the common node to ground, the inductor circuit being configured to provide multiple inductance values, the inductor circuit including multiple switchable inductors connected in series. 40. The switching circuit of claim 39, wherein each transistor device of the series arm switch comprises N field-effect transistors arranged in parallel, and each transistor device of the shunt arm switch comprises M field-effect transistors arranged in parallel, wherein each of N and M is a positive integer. 41. The switching circuit of claim 39, wherein at least one of the plurality of inductance values provided by the adjustable compensation circuit includes an inductance value L, the inductance value L compensating for the parasitic effects caused by the cutoff capacitance of the series arm switch and the shunt arm switch. 42. The switching circuit of claim 41, wherein the inductance value L is selected to have the value L = 1/[ ^4π²f² ( ^Coff_total )], where f is the operating frequency and Coff_total is the total cutoff capacitance of the series arm switch and the shunt arm switch. 43. The switching circuit of claim 41, wherein the presence of the inductance value L allows for a larger size of either or both of the series arm and shunt arm switching transistors to improve switching performance, while reducing the parasitic effect of the cutoff capacitance of the series arm switch and the shunt arm switch. 44. The switching circuit of claim 43, wherein the switching performance includes insertion loss performance such that the size of either or both of the series arm and shunt arm switching transistors is larger than the size of the corresponding transistor of the switching circuit that does not have the inductance value L. 45. The switching circuit of claim 44, wherein the series arm switch and the shunt arm switch of the switching circuit having the inductance value L have lower insertion losses than the series arm switch and the shunt arm switch of the switching circuit not having the inductance value L. 46. The switching circuit of claim 43, wherein the switching performance includes isolation performance. This results in the shunt arm switching transistor having a larger size than the corresponding transistor in a switching circuit that does not have the inductance value L. 47. The switching circuit of claim 46, wherein the series arm switch and the shunt arm switch of the switching circuit having the inductance value L have a higher degree of isolation than the series arm switch and the shunt arm switch of the switching circuit not having the inductance value L. 48. A method for compensating parasitic effects associated with a switching circuit, the method comprising: A switching operation is performed in the switching circuit to allow one or more signals to pass through one or more corresponding switchable paths, each path contributing to the parasitic effect associated with the switching circuit; and An adjustable compensation circuit coupled to a selected node of the switching circuit is used to provide inductance, which is selected to compensate for the parasitic effects associated with the switching circuit. The inductance is obtained from a plurality of switchable inductors connected in series, each switchable inductor comprising a parallel arrangement of an inductor and a switch, each inductor having a substantially constant inductance value of L0, such that the adjustable compensation circuit can provide an inductance value from L0 to a total inductance in steps of L0, the total inductance being approximately equal to L0 multiplied by the number of switchable inductors. 49. A method for manufacturing a switchgear, the method comprising: Forming or providing a switching network, the switching network comprising one or more switchable radio frequency signal paths, each path contributing to parasitic effects associated with the switching network; An adjustable compensation circuit is formed, the adjustable compensation circuit including an inductor circuit configured to provide multiple inductance values, the inductor circuit including a plurality of switchable inductors connected in series; and The adjustable compensation circuit is coupled between a selected node and a reference node of the switching network, and the adjustable compensation circuit is configured to compensate for the parasitic effects of the switching network. 50. A radio frequency module, comprising: A packaging substrate configured to house multiple components; A switching network implemented on the packaging substrate, the switching network including one or more switchable radio frequency signal paths, each path contributing to parasitic effects associated with the switching network; and An adjustable compensation circuit implemented on the packaging substrate includes an inductor circuit that couples selected nodes of the switching network to a reference node. The inductor circuit is configured to provide a plurality of inductance values, at least some of which are selected to compensate for the parasitic effects of the switching network. The inductor circuit includes a plurality of switchable inductors connected in series. 51. The radio frequency module of claim 50, wherein the switching network is implemented on the first chip. 52. The radio frequency module of claim 51, wherein the first wafer comprises silicon on insulator (SOI). 53. The radio frequency module of claim 51, wherein at least a portion of the adjustable compensation circuit is implemented on the first chip. 54. The radio frequency module of claim 51, wherein at least a portion of the adjustable compensation circuit is implemented on the second chip. 55. The radio frequency module of claim 50, wherein the radio frequency module is an antenna switch module. 56. A radio frequency device, comprising: A transceiver, configured to process radio frequency signals; An antenna switching module communicating with the transceiver, the antenna switching module being configured to route an amplified radio frequency signal for transmission and amplified radio frequency signal for reception, the antenna switching module including a switching network comprising one or more switchable radio frequency signal paths, each path contributing to parasitic effects associated with the switching network, the antenna switching module further including an adjustable compensation circuit having an inductor circuit coupling a selected node of the switching network to a reference node, the inductor circuit being configured to provide a plurality of inductance values, at least some of the inductance values being selected to compensate for the parasitic effects of the switching network, the inductor circuit including a plurality of switchable inductors connected in series; and An antenna that communicates with the antenna switch module, the antenna being configured to cause either or both of the transmission and reception of a corresponding radio frequency signal. 57. The radio frequency device of claim 56, wherein the radio frequency device is a wireless device. 58. The radio frequency device of claim 57, wherein the wireless device is a cellular phone.