HK1230400A - Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies - Google Patents

Description

System and method for manufacturing printed circuit boards using blind vias and internal micro vias to couple subassemblies

The present application is a divisional application of chinese patent 201180038067.9 entitled "system and method for manufacturing printed circuit boards using blind vias and internal micro vias to couple subassemblies".

Technical Field

The present invention relates generally to printed circuit boards and methods of manufacturing the same, and more particularly, to a printed circuit board having circuit layers stacked by blind vias and internal micro vias and a method of manufacturing the same.

Background

Most electronic systems include printed circuit boards with high density electronic interconnections. A Printed Circuit Board (PCB) may include one or more circuit cores, substrates, or carriers. In one fabrication scheme for a printed circuit board having one or more circuit carriers, electronic circuitry (e.g., pads, electronic interconnects, etc.) is fabricated on opposite sides of a single circuit carrier to form a pair of circuit layers. These circuit layer pairs of the circuit board may then be physically and electronically joined to form a printed circuit board by: fabricating an adhesive (or prepreg or thermally conductive double-sided tape), stacking the circuit layer pairs and the adhesive in a press, curing the resulting circuit board structure, drilling through-holes, and then plating the through-holes with copper material to interconnect the circuit layer pairs.

The curing process is used to cure the adhesive in preparation for a permanent physical bond of the circuit board structure. However, the adhesive typically shrinks significantly during the curing process. Shrinkage in combination with later via drilling and plating processes can cause considerable stress into the overall structure, resulting in damage or unreliable interconnections or bonds between circuit layers. Accordingly, there is a need for materials and related processes that compensate for this shrinkage and provide for more stress relief and more reliable electrical interconnections between pairs of circuit layers.

In addition, electroplating through-holes (or vias) with copper material requires an additional, expensive and time-consuming process sequence that is difficult to achieve by rapid changeover. Fig. 1 is a flow chart of a sequential lamination process for manufacturing printed circuit boards with stacked vias, which includes costly and time consuming sequential lamination and plating steps. Accordingly, there is a need for a printed circuit board and method of manufacturing the same that can quickly and easily fabricate and/or ensure alignment of interconnects (or through-holes or micro-vias) on the printed circuit board that reduces manufacturing time and cost by reducing the repetition of critical processes.

Disclosure of Invention

Aspects of embodiments of the present invention relate to and are directed to systems and methods of manufacturing printed circuit boards using blind vias and internal micro vias to couple subassemblies. An embodiment of the invention provides a method of manufacturing a printed circuit, comprising: attaching a plurality of metal layer carriers to form a first subassembly comprising at least one copper foil pad on a first surface; applying an encapsulation material on a first surface of the first subassembly; curing the encapsulation material and the first subassembly; applying a laminating adhesive to a surface of the cured encapsulant; forming at least one via in the laminating adhesive and the cured encapsulant to expose at least one copper foil pad; attaching a plurality of metal layer carriers to form a second subassembly; and attaching the first subassembly and the second subassembly.

Another embodiment of the present invention provides a method of manufacturing a multilayer printed circuit board, the method including forming a first subassembly including: (a) attaching at least one metal layer carrier to form a first subassembly comprising at least one copper foil pad on a first surface; (b) applying an encapsulation material on a first surface of the first subassembly; (c) curing the encapsulation material and the first subassembly; (d) forming at least one first via in the cured encapsulant to expose at least one copper foil pad; (e) forming a conductive pattern on a surface of the cured encapsulant, the conductive pattern including a conductive pad coupled to at least one first via; (f) applying a laminating adhesive to a surface of the cured encapsulant; (g) forming at least one hole in the laminating adhesive proximate the at least one first via; (h) filling the at least one hole with a conductive material to form at least one second via; repeating (a) through (e) to form a second subassembly; the first subassembly and the second subassembly are attached such that the at least one second via of the first subassembly is more or less aligned with the conductive pad of the second subassembly.

Yet another embodiment of the present invention provides an attachment structure for coupling subassemblies of a multilayer printed circuit board, the structure comprising: a first component comprising a first metal layer carrier, the first metal layer carrier comprising: a first blind via comprising a first locator pad located in the top surface of the first metal layer carrier, a first laminate adhesive layer located along the top surface and the first locator pad, and a first via nearly filled with a conductive material located in the first laminate adhesive, the first via being in contact with the first locator pad; and a second component comprising a second metal layer carrier comprising a second blind via comprising a second capture pad located in a top surface of the second metal layer carrier, wherein the first component is attached to the second component with a first laminated adhesive layer such that the first via in the first adhesive is more or less aligned with the second capture pad of the second blind via.

Drawings

Fig. 1 is a flow chart of a sequential lamination process for manufacturing printed circuit boards with stacked vias, the process including sequential lamination and electroplating steps.

Figures 2a-2f illustrate a process of attaching a subassembly to form a multi-layer printed circuit board using internal micro-vias located in the package and adhesive layers, according to one embodiment of the invention.

Fig. 2g is a cross-sectional view of the completed multilayer printed circuit board of fig. 2a-2f, according to one embodiment of the invention.

Fig. 3 is a cross-sectional view of a multilayer printed circuit board having three subassemblies attached using the process of fig. 2a-2f, according to one embodiment of the invention.

Fig. 4a-4j illustrate an alternative process of attaching a subassembly to form a multi-layer printed circuit board using internal micro-vias located in an adhesive layer, according to one embodiment of the invention.

Fig. 5 is an enlarged cross-sectional view of an inter-subassembly attachment including two blind vias coupled by adhesive and conductive glue to form a thin via according to the process of fig. 4a-4 j.

Fig. 6 is an enlarged cross-sectional view of another inter-subassembly attachment including stacked vias on each subassembly coupled by adhesive and conductive glue to form vias, according to one embodiment of the invention.

Fig. 7 is an enlarged cross-sectional view of another inter-subassembly attachment using conductive paste micro-vias located between two mechanically drilled vias with enlarged surface areas, according to one embodiment of the present invention.

Detailed Description

In the following detailed description, certain exemplary embodiments of the present invention are shown and described, by way of illustration. As those skilled in the art will recognize, the described exemplary embodiments may be varied in various ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. There are shown in the drawings, or not shown in the drawings, which are not discussed in the specification since they are not essential to a complete understanding of the present invention. Like reference numerals identify like elements.

Fig. 1 is a flow chart of a sequential lamination process for manufacturing printed circuit boards with stacked vias, the process including sequential lamination and electroplating steps.

Fig. 2a-2f illustrate a process for manufacturing a printed circuit board including an attached laminated subassembly using internal micro-vias located in the package and adhesive layers, according to one embodiment of the invention.

In fig. 2a, the process begins when a laminated subassembly 100 is provided having four layers and copper pads (e.g., foils) 102 on both sides. The laminated subassembly 100 also includes two plated or filled through-hole vias 104. The layers of the subassembly may be made of metal, ceramic or insulating materials (e.g., FR4 such as teflon, thermally conductive carbon (Stablecor), halogen free, LCP, deluster (Thermount), BT, GPY, etc., where GPY is a laminate not suitable for the FR4 family, such as polyimide, aziridine cured epoxy, bismaleimide and other electrical grade laminates). However, the invention is not so limited. In other embodiments, other suitable substrate and conductive layer materials can be used. In the embodiment shown in fig. 2a, the subassembly layers have a thickness ranging between about 3 to 4 mils. However, in other embodiments, the subassembly layers and other components can have other suitable dimensions.

In various embodiments, the laminated subassembly 100 may be manufactured using the process described in fig. 1. In other embodiments, the subassembly may be a single laminate subassembly having a plurality of single metal layer carriers and stacked micro-vias. Aspects of a single lamination process for manufacturing circuit boards are further described in U.S. patent No.7,523,545, U.S. provisional patent application No.61/189171, and U.S. patent application No.12/772,086, all of which are incorporated herein by reference.

In the embodiment illustrated in fig. 2a, the laminated subassembly 100 includes four metal layers. In other embodiments, the laminated subassembly may include more or less than three metal layer carriers. In the embodiment illustrated in fig. 2a, the laminated subassembly includes two through-hole vias. In other embodiments, the stacked subassembly may have more or less than two vias. In other embodiments, the through-hole vias may be replaced with stacked micro vias, buried vias, and/or blind vias.

In fig. 2b, the process applies an encapsulation material 106 to the top surface of the laminated subassembly 100 and cures the encapsulation material 106. In many embodiments, the encapsulation material is a dielectric material. In various embodiments, curing is achieved by heating the subassembly and the encapsulating material on the subassembly at a preselected temperature for a preselected duration.

The encapsulant material may be any suitable uncured insulating material including, but not limited to, FR4 such as teflon, thermally conductive carbon (Stablecor), halogen free, etc., LCP, deluster (Thermount), BT, GPY, etc., where GPY is a laminate not suitable for the FR4 family, such as polyimide, aziridine cured epoxy, bismaleimide, and other electrical grade laminates.

In fig. 2c, the process applies a lamination adhesive 108 to the top surface of the cured encapsulation material 106.

In fig. 2d, the process forms a hole 110 for a micro-via by drilling through the lamination adhesive 108 and encapsulation material 106 to the top surface of the copper pad 102. Each of the micro vias may be formed by laser drilling (and/or mechanically drilling) a hole having a diameter ranging between about 4 to 10 mils. In other embodiments, other suitable techniques for forming the via holes may be used. In addition, other via sizes may be used.

In fig. 2e, the holes 110 are filled with conductive glue, thereby forming micro-vias 112. In some embodiments, the micro-vias are filled with copper instead of conductive paste. In one embodiment, conductive glue is used when laser drilling the via holes and copper is used when mechanical drilling the holes.

In fig. 2f, a second laminated subassembly 200 having copper pads 202 on both sides is provided and the second laminated subassembly 200 is brought into proximity with the first laminated subassembly 100.

Fig. 2g is a cross-sectional view of the completed multilayer printed circuit board of fig. 2a-2f, according to one embodiment of the present invention. In fig. 2g, the first and second subassemblies (100, 200) are brought together and attached. In some applications, it may be difficult to connect and fabricate boards with high aspect ratio vias. By attaching the laminated subassemblies using the process described above, the method of attachment and manufacture is made much easier. In the embodiment illustrated in fig. 2g, the process of fig. 2b-2e is performed on the top surface of the first stacked subassembly 100. In other embodiments, the process of fig. 2b-2e is performed on both the top and bottom surfaces of the laminated subassembly 100 to allow for the attachment of more than one second subassembly 200 to the first subassembly 100.

Fig. 3 is a cross-sectional view of a multilayer printed circuit board 300 including three subassemblies attached using the process of fig. 2a-2f, according to one embodiment of the invention. In other embodiments, more than three subassemblies may be attached using the process of fig. 2a-2 f. PCB300 includes three subassemblies with a plurality of copper pads 302 and through-hole vias 304. The subassembly is attached by internal micro vias 312 embedded in the encapsulation layers (306-1, 306-2) and adhesive layers (308-1, 308-2). In the embodiment illustrated in fig. 3, inter-subassembly attachment is achieved using micro-vias filled with conductive glue. In other embodiments, inter-subassembly attachment may be achieved using solid copper plated micro vias or solid copper through hole vias.

Fig. 4a-4j illustrate an alternative process of attaching subassemblies using internal micro-vias to form a multi-layer printed circuit board according to one embodiment of the invention.

In fig. 4a, the process begins when a laminated subassembly 400 is provided having four layers and copper pads (e.g., foils) 402 on both sides. The stacked subassembly 400 also includes two plated or filled blind vias 404 coupled to two other plated or filled blind vias 405. The layers of the subassembly may be made of metal, ceramic, or insulating materials (e.g., FR4 such as teflon, thermally conductive carbon (Stablecor), halogen free, etc., LCP, deluster (Thermount), BT, GPY, etc., where GPY is a laminate not suitable for the FR4 family, such as polyimide, aziridine cured epoxy, bismaleimide, and other electrical grade laminates). However, the invention is not so limited. In other embodiments, other suitable substrate and conductive layer materials can be used. In the embodiment shown in fig. 4a, the subassembly layers have a thickness ranging between about 3 to 4 mils. However, in other embodiments, the subassembly layers and other components can have other suitable dimensions.

In various embodiments, the laminated subassembly 400 may be manufactured using the process described in fig. 1. In other embodiments, the subassembly may be a single laminate subassembly having a plurality of single metal layer carriers and stacked micro-vias. Aspects of the single lamination process for manufacturing circuit boards are further described in the above-referenced patents and patent applications.

In the embodiment illustrated in fig. 4a, the laminated subassembly 400 includes four metal layers. In other embodiments, the laminated subassembly may include more or less than three metal layer carriers. In the embodiment illustrated in fig. 4a, the laminated subassembly includes four blind vias. In other embodiments, the stacked subassembly may have more or less than four vias. In other embodiments, the blind vias may be replaced with vias, buried vias, and/or stacked vias.

In fig. 4b, the process applies an encapsulation material 406 to the top surface of the laminated subassembly 400 and cures the encapsulation material 406. In many embodiments, the encapsulation material is a dielectric material. In various embodiments, curing is achieved by heating the subassembly and the encapsulating material on the subassembly at a preselected temperature for a preselected duration.

The encapsulant material may be any suitable uncured insulating material including, but not limited to, FR4 such as teflon, thermally conductive carbon (Stablecor), halogen free, etc., LCP, deluster (Thermount), BT, GPY, etc., where GPY is a laminate not suitable for the FR4 family, such as polyimide, aziridine cured epoxy, bismaleimide, and other electrical grade laminates.

In fig. 4c, the process forms a hole 410 for a micro-via (or via) by drilling through the encapsulation material 406 to the top surface of the copper pad 402. Each of the micro vias may be formed by laser drilling (and/or mechanically drilling) a hole having a diameter ranging between about 4 to 10 mils. In other embodiments, other suitable techniques for forming the via holes may be used. In addition, other via sizes may be used.

In fig. 4d, the hole 410 is filled with copper, forming a fixed copper micro-via 412. In some embodiments, the micro-vias 412 are filled with conductive paste instead of copper. In one embodiment, conductive glue is used when laser drilling the via holes and copper is used when mechanical drilling the holes.

In fig. 4e, the process images, develops, plates copper, adds resist, and strips the resist to form conductive patterns on the encapsulation layer 406 and on the vias 412. The conductive pattern includes capture pads 414 located on top of the vias 412.

In fig. 4f, the process applies a lamination adhesive 416 to the top surfaces of the cured encapsulation material 406 and capture pads 414.

In fig. 4g, the process forms a hole 418 for a fine micro-via by drilling through the lamination adhesive 416 to the top surface of the capture pad 414. Each of the fine micro vias may be formed by laser drilling (and/or mechanical drilling) a hole having a diameter ranging between about 1 to 3 mils. In other embodiments, other suitable techniques for forming the via holes may be used. In addition, other via sizes may be used.

In fig. 4h, the holes 418 are filled with conductive glue, thereby forming micro vias 420.

In fig. 4i, a second laminate subassembly 400-2 having features on one surface thereof substantially similar to the first subassembly 400 of fig. 4e is formed and aligned, including two blind, solid copper micro vias having electrically conductive pads located thereon, such that when the first and second laminate assemblies 400-2 are brought together for attachment, the thin, electrically conductive glue-filled micro vias of the first laminate assembly 400 are physically and electrically coupled with corresponding electrically conductive pads of the second laminate assembly 400-2 and secured by a laminate adhesive 416.

Fig. 4j is a cross-sectional view of the completed multilayer printed circuit board of fig. 4a-4i, according to one embodiment of the present invention. In fig. 4j, the first and second subassemblies (400, 400-2) are brought together and attached. In some applications, it may be difficult to connect and fabricate boards with high aspect ratio vias. In some applications, complex via structures may be too difficult to fabricate using conventional fabrication methods. By attaching the laminated subassemblies using the process described above, the method of attachment and manufacture is made much easier. In addition, the conductive paste or conductive ink micro vias between the stacked subassemblies are very fine (e.g., 3 to 5 mils). While not being bound by any particular theory, fine micro vias or joints can provide good high frequency conductivity. In many embodiments, the joint is not as conductive as a highly conductive metal such as copper. However, since the joint is thin, it can provide good conductivity to a signal having a high frequency characteristic (e.g., a radio frequency type signal, etc.). In addition, the thin copper cement joints have minimal damage to the convective currents.

In the embodiment illustrated in fig. 4a-4j, the process is performed on the top surface of the first stacked subassembly 400. In other embodiments, the process of fig. 4a-4j is performed on both the top and bottom surfaces of the laminated subassembly 400 to allow for the attachment of more than one second subassembly 400-2 to the first subassembly 400.

In various embodiments, the conductive paste or ink may include a mixture of copper and tin. In other embodiments, other suitable conductive materials may be used for the conductive paste.

Fig. 5 is an enlarged cross-sectional view of an inter-subassembly attachment 500 including two blind vias (512-1, 512-2) coupled by an adhesive (not shown) and conductive glue 520 to form a thin via, according to the process of fig. 4a-4 j. Each of the blind vias (512-1, 512-2) includes a conductive pad (502-1, 502-2) on an outer surface thereof and a conductive pad (514-1, 514-2) on an inner surface thereof. The conductive paste structure 520 forms a fine micro-via within the adhesive (see fig. 4j), which may have the desirable characteristics discussed above.

Fig. 6 is an enlarged cross-sectional view of another inter-subassembly attachment 600 including stacked vias (602, 604) on each subassembly coupled by adhesive (not shown) and conductive paste vias 606, according to one embodiment of the invention. The conductive paste vias 606 are significantly higher (e.g., z-axis length) as compared to the subassembly attachment of fig. 5. This higher pattern of conductive adhesive vias may be easier to manufacture and provide good impedance control between the board layers.

Fig. 7 is an enlarged cross-sectional view of another inter-subassembly attachment 700 utilizing a conductive adhesive micro-via 702 located between two mechanically drilled vias (704, 706) having enlarged surface areas (708, 710) according to one embodiment of the present invention.

While the above description contains many specific embodiments of the invention, these should not be construed as limitations on the scope of the invention, but rather as exemplifications of particular embodiments thereof. The scope of the invention should, therefore, be determined not with reference to the illustrated embodiments, but instead should be determined with reference to the appended claims along with their full scope of equivalents. For example, although certain components are indicated as being formed of copper, other suitable conductive materials may be used in place of copper.

Claims (17)

1. An attachment structure for coupling subassemblies of a multilayer printed circuit board, the structure comprising:

a first component, comprising:

a first metal layer carrier comprising a first blind via comprising a first copper pad located in a top surface of the first metal layer carrier;

a first encapsulation layer over the first copper pad;

a first laminate adhesive layer positioned over the first encapsulation layer; and

a first via substantially filled with a conductive material and located within the first laminate adhesive layer and first encapsulation layer, the first via being in contact with the first copper pad; and

a second component comprising a second metal layer carrier including a second blind via comprising a second copper pad positioned in a bottom surface of the second metal layer carrier,

wherein the first encapsulation layer of the first component is attached to the second copper pad and the bottom surface of the second metal layer carrier of the second component with the first lamination adhesive layer such that the first via in the first lamination adhesive layer is more or less aligned with the second copper pad of the second blind via.

2. The structure of claim 1, wherein the first and second blind vias comprise copper.

3. The structure of claim 2, wherein the first blind via is nearly filled with copper as the second blind via.

4. The structure of claim 1, wherein the electrically conductive material comprises one or more metals.

5. The structure of claim 4, wherein the conductive material comprises a material selected from the group consisting of copper and tin.

6. The structure of claim 1, wherein the conductive material comprises a conductive ink.

7. The structure of claim 1, wherein the first via in the first adhesive is approximately 3 to 5 mils thick.

8. The structure of claim 1, wherein each of the first metal layer carrier and the second metal layer carrier comprises an insulating material.

9. An attachment structure for coupling subassemblies of a multilayer printed circuit board, the structure comprising:

a first component, comprising:

a first metal layer carrier;

a first capture pad positioned on a top surface of the first metal layer carrier;

a first encapsulation layer including a first blind via positioned over the first capture pad;

a second capture pad disposed over the first encapsulation layer;

a first lamination adhesive layer positioned over the first encapsulation layer and the second capture pad;

a first via substantially filled with a conductive material and located within the first laminate adhesive layer, the first via in contact with the first capture pad; and

a second assembly, comprising:

a second metal layer carrier;

a third capture pad positioned on a bottom surface of the second metal layer carrier; and

a second encapsulation layer comprising a second blind via positioned over a bottom surface of the third capture pad;

a fourth capture pad disposed over a bottom surface of the second encapsulation layer;

wherein the second capture pad of the first component is bonded to the fourth capture pad of the second component with the first via, wherein the first via is located within the first laminate adhesive layer such that the first via in the first laminate adhesive layer is more or less aligned with the fourth capture pad of the second blind via,

wherein the second component and the first component are symmetrical with respect to the first laminate adhesive backing.

10. The structure of claim 9, wherein the first and second blind vias comprise copper.

11. The structure of claim 10, wherein the first blind via is nearly filled with copper as the second blind via.

12. The structure of claim 9, wherein the conductive material comprises one or more metals.

13. The structure of claim 12, wherein the conductive material comprises a material selected from the group consisting of copper and tin.

14. The structure of claim 9, wherein the conductive material comprises a conductive glue.

15. The structure of claim 9, wherein the first via in the first adhesion layer has a thickness of approximately 3 to 5 mils.

16. The structure of claim 9, wherein the first via in the first adhesive is approximately 3 to 5 mils thick.

17. The structure of claim 9, wherein each of the first metal layer carrier and the second metal layer carrier comprises an insulating material.