HK1230320B - Receiver unit for an rf tag - Google Patents

Description

Receiver unit for radio frequency tag

Technical Field

The invention relates to a receiver unit comprising a first and a second input to which an antenna is connected, a communication stage adapted to demodulate and/or modulate an incoming signal at the communication stage, and a power stage comprising a voltage converter for supplying power to the remaining circuitry.

Background Art

Known radio frequency tags, also known as electronic tags or communication beacons, are provided with a communication circuit. This type of communication circuit comprises an antenna connected to a modulation/demodulation stage for processing incoming and outgoing signals. Such radio frequency tags are also provided with a power supply system, i.e., a stage that uses the energy received when receiving a signal to supply power to the entire radio frequency tag.

This type of stage generally comprises an AC/DC converter which converts the received alternating current signal into a continuous power signal. This type of AC/DC converter takes the form of a diode bridge, for example of the Graetz type.

However, depending on the type of input signal, it is necessary to have an AC/DC converter capable of operating not only at low power but also at high power.

A further issue with AC/DC converters is that they can have parasitic capacitance. Indeed, each antenna operates optimally with a tuning capacitor. Therefore, it is sought to control the value of the tuning capacitor associated with the antenna, and therefore reduce the value of the parasitic capacitance, so that it does not significantly disrupt the desired antenna characteristics. Therefore, since the AC/DC converter is the largest contributor to parasitic capacitance, it is important to select components that minimize this contribution.

Furthermore, RFID tags face the risk of being destroyed by the AC/DC converter due to excessive voltage in the AC/DC converter, which can damage components. A known solution is to clip the signal when it exceeds a predetermined voltage. However, the disadvantage of clipping the input signal is that it distorts the signal, resulting in information loss.

Summary of the Invention

It is therefore an object of the present invention to overcome the disadvantages of the prior art by providing a radio frequency tag receiver unit that improves efficiency and tolerates large voltage variations in the input signal while avoiding voltage surges and signal distortion.

To this end, the present invention proposes a receiver unit comprising a first and a second input terminal connected to an antenna, a communication stage and a power supply stage, wherein the communication stage is suitable for demodulating and/or modulating an incoming signal at the communication stage, the power supply stage comprising a voltage converter for providing power to the unit, characterized in that the power supply stage further comprises a regulating circuit suitable for limiting the output voltage of the voltage converter, the regulating circuit comprising a regulator circuit suitable for determining a second current value, the second current value being a current value provided in addition to the first current value, the regulator circuit providing a control signal if the second current value exceeds a predetermined threshold, the control signal being sent to a limiter circuit, the limiter circuit being configured to limit the input voltage of the AC/DC converter circuit.

In a first advantageous embodiment, said voltage converter is of the AC/continuous type.

In a second advantageous embodiment, the voltage converter comprises at the input a ground generator consisting of a first and a second N-type MOS transistor, the first and second N-type MOS transistors being connected to each other so that their sources are connected to each other to form the ground of the voltage converter, the drain of the first transistor being connected to the first input terminal and the gate of the second transistor, and the drain of the second transistor being connected to the second input terminal and the gate of the first transistor, the voltage converter further comprising a plurality of identical structures forming a voltage modifier component, and is characterized in that the converter output comprises two N-type MOS transistors, wherein the sources of the transistors are connected to each other to form an output line, the drain of one of the transistors being connected to the last structure of the voltage modifier component extending from the first end, the drain of the other transistor being connected to the last structure of the voltage modifier component extending from the second end, the gate of each transistor being connected to its source.

In a third advantageous embodiment, the voltage modifier component is configured so that from each of the first and second input terminals a series of identical structures connected to one another extends, the first structure of each series being connected to one of the first and second input terminals and the subsequent structure, the connection point between two structures being connected to one of the first or second input terminals, so that each structure is connected to both the first terminal and the second terminal.

In a fourth advantageous embodiment, the limiter circuit comprises at least one transistor connected via its drain to the first input and via its source to the second input, the control signal being sent to its gate in order to render the at least one transistor more or less conductive.

In a fifth advantageous embodiment, the limiter circuit comprises a plurality of transistors mounted in parallel.

In a sixth advantageous embodiment, the regulating unit further comprises a bandgap voltage generator for providing the polarization current and the reference voltage to the regulator circuit.

In another advantageous embodiment, the communication stage is adapted to provide a signal representative of a communication action, which is directly connected to the limiter circuit in order to prevent regulation during such a communication action.

The present invention also relates to a radio frequency tag comprising a control unit comprising a computing unit and a memory for performing at least one function, and at least one receiver unit configured to receive or transmit signals and supply power to the control unit, characterized in that the receiver unit is a receiver unit according to the present invention.

In a first advantageous embodiment, the receiver unit is configured to operate according to a first protocol using a first frequency.

In a second advantageous embodiment, said first protocol is a long distance protocol.

In a third advantageous embodiment, the radio frequency tag further comprises a second receiver unit configured to operate according to a second protocol using a second frequency, the second receiver unit comprising a communication stage and a power supply stage for supplying an electric current to a unit, the control unit receiving the electric current, the value of the electric current being the sum of the currents from the first receiver unit and from the second receiver unit.

In another preferred embodiment, the first receiver unit further comprises a current mirror circuit for providing a signal representing a current which is an image of the sum of the currents of the first and second receiver units, the second receiver unit further comprises a current mirror circuit for providing a signal representing a current which is an image of the current provided by the second receiver unit, and is characterized in that the first receiver unit further comprises a subtractor circuit for subtracting the image of the sum of the currents of the first and second receiver units from the image of the current provided by the second receiver unit, and for providing a signal representing only the current from the first receiver unit to the limiter circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, advantages and features of the device according to the invention will become more apparent from the following detailed description of at least one embodiment of the invention, given purely by way of non-limiting example and as illustrated in the accompanying drawings, in which:

1a and 1b are schematic diagrams of a radio frequency tag and a receiver unit according to a first embodiment of the present invention.

FIG2 is a schematic diagram of an AC/DC converter of a receiver unit according to the present invention.

FIG3 is a schematic diagram of a shunt voltage regulator of a receiver unit according to the present invention.

FIG. 4 is a schematic diagram of a limiter circuit of a receiver unit according to the present invention.

FIG5 shows a schematic diagram of a variant of a receiver unit according to the invention.

6 and 7 are schematic diagrams showing a radio frequency tag according to a second embodiment of the present invention.

FIG8 is a schematic diagram of the time behavior of the radio frequency tag adjustment system according to the present invention.

DETAILED DESCRIPTION

Figure 1a shows a receiver unit 1 of a radio frequency tag, also known as a communication beacon or electronic tag, and more specifically, a receiver unit 100 according to a first embodiment. As shown in Figure 1b, this type of receiver unit 100 of this type of radio frequency tag is connected to an antenna 101 at the input via two input terminals (PAD+, PAD-), namely, a positive input and a negative input. Antenna 101 can be a dipole, a coil, or any other element capable of performing an antenna function. The radio frequency tag 1 also includes a control unit 200, which, for example, includes a computing unit and a memory for performing at least one function. Here, receiver unit 100 is configured to operate using a long-range UHF protocol. Across the two input terminals PAD+, PAD-, multiple stages are connected to each other, with each stage connected to a positive terminal via one of its terminals and to a negative terminal via its other terminal. First, there is an adjustment stage 102, which includes a large number of capacitors mounted in parallel and capable of being activated to add or remove capacitance to adjust the antenna, resonant frequency, and quality factor.

The second stage 103 includes a protection stage. This ESD protection stage protects against electrostatic discharge. This protection stage 103 is typically provided with diodes and/or thyristors. The third stage includes a communication stage 104. This communication stage includes a modulator section 104a for transmitting signals via an antenna and/or a demodulator section 104b for processing signals received via the antenna.

The fourth stage comprises the power supply stage 105, ie the stage which is able to supply electrical energy to the rest of the radio frequency tag by using power from the incoming signal.

The fourth stage comprises a voltage converter 106 for converting an input voltage into a different output voltage. In this example, it is an AC/DC conversion. The circuit provides a rectified voltage Uuhf and a current Iuhf from the AC voltage.

In a preferred embodiment, voltage converter 106 is an AC/DC converter using a modified and symmetrical Cockcroft-Walton structure, as shown in FIG2 . AC/DC converter 106 includes two input terminals E1 and E2, which are connected to two input terminals PAD+ and PAD- of the RFID tag. A ground generator 1060 is disposed at the input terminal, between the two input terminals E1 and E2, and includes two N-type MOS transistors 1060a and 1060b. The sources of transistors 1060a and 1060b are connected to each other to form a ground voltage VSS, while the gates of each transistor 1060a and 1060b are connected to the drain of the other transistor, each drain being connected to one of terminals E1 and E2.

The structure then includes a step-up portion 1061. Identical structures 1062 are connected in series from each input terminal E1, E2. These structures 1062 extending from each terminal E1, E2 are configured so that the first structure 1062 extending from terminal E1 and the first structure extending from terminal E2 form a voltage modifier stage, and so on. The AC/DC voltage converter 106 thus includes N voltage modifier stages.

Each structure 1062 includes an N-type MOS transistor 1063, the gate of which is connected to the drain of the transistor. The source of the transistor 1063 is also connected to the drain of the transistor 1063 of the next structure 1062 and to a parallel-connected capacitor 1064, which is used to supply additional power during the boosting period and is also connected to one of the input terminals E1 and E2.

The connections of the capacitors 1064 to the input terminals E1 , E2 are alternated, so that if the capacitor 1064 of one structure 1062 is connected to the terminal E1 , then the capacitor 1064 of the next structure 1062 is connected to the terminal E2 , and so on.

The configuration is also set up so that the capacitor 1064 of the first structure 1062 will be connected to the terminal E2, wherein the drain of the transistor 1063 is connected to the terminal E1, and the capacitor 1064 of the first structure 1062 will be connected to the terminal E1, wherein the drain of the transistor 1063 is connected to the terminal E2.

In the final structure 1062 of each line, the source of transistor 1063 is connected to a collector portion 1065. This collector comprises two N-type MOS transistors 1066, the sources of which are interconnected to form a VPOS output 1067. The drain of one of transistors 1066 is connected to the source of transistor 1066 in the final structure of line E1, and the drain of the other is connected to the source of the transistor in the final structure of line E2. Furthermore, the gate of each transistor 1066 is connected to its source.

This configuration makes it possible to obtain an AC/DC converter 106 having low parasitic capacitance, a characteristic sought by the present invention.

At the output of the AC/DC converter 106, the fourth stage 105 advantageously comprises a regulating circuit 107. The regulating circuit 107 is a transistor used to prevent damage to the AC/DC converter 106 when the voltage is stepped up.

In fact, the AC/DC converter circuit 106 is also a voltage boost circuit. However, when the voltage becomes too high, these components are easily damaged.

The regulation circuit 107 firstly comprises a regulator circuit as a shunt voltage regulator 108 , which is connected via one of its inputs to the output of the AC/DC converter and via its output to ground.

As shown in FIG3 , this type of shunt voltage regulator 108 includes a first input connected to the drains of three P-type MOS transistors PVLT1, PVLT2, and PVLT3. The gate of transistor PVLT1 is connected to the source of the latter and to the gate of transistor PVLT2. The source of transistor PLVT2 is connected to the gate of transistor PLVT3. Four resistors R are also connected in series to the first input. These resistors R are connected in series and are thus connected between the first input and ground.

Shunt voltage regulator 108 further includes a first N-type MOS transistor NVLT1, the gate of which serves as a second input for connecting to a reference voltage VBG. The drain of transistor NVLT1 is connected to the source of transistor PLVT1, while the source of transistor NLVT1 is connected to a pair of N-type MOS transistors NLVT2 and NLVT3. More specifically, the source of transistor NLVT1 is connected to the source of transistor NLVT2, the drain of which is connected to the source of transistor PLVT2, and the gate of which is connected to the connection point between the first and second resistors R of the resistor series. Furthermore, capacitors C1, C2, C3, and C4 are configured to be connected in parallel between the gates of transistors PLVT3 and NLVT2, and between the gate of transistor NLVT2 and ground.

The source of transistor NLVT1 is also connected to the drain of transistor NLVT3, the source of which is also connected to ground, and its gate is also connected to the gate of a fourth transistor NLVT4. This transistor NLVT4 is connected via its drain and gate to the current polarization source I1 and via its source to ground.

Finally, the shunt voltage regulator comprises a fifth transistor NLVT5, the gate and drain of which are connected to the source of the transistor PLVT3, and the source of the fifth transistor NLVT5 is connected to ground. The shunt voltage regulator 108 may be associated with a bandgap reference voltage generator 109, which provides a reference voltage VBG and is connected to the gate of the transistor NLVT1 of the shunt voltage regulator 108.

This shunt voltage regulator 108 is used to measure the current I _shunt supplied in addition to the current consumed by the control unit 200. In fact, the regulation principle relies on the fact that the current supplied by the AC/DC converter 106 is partially absorbed by the radio frequency tag circuit, i.e. the control unit 200, the remaining part, i.e. the current I _shunt, is directed to the shunt voltage regulator 108.

The regulated current from the shunt regulator mainly flows into PLVT3. MOS transistor PLVT4 uses the symbol of this shunt current I _shunt to adjust the characteristics of the AC/DC converter protection circuit.

Therefore, there is a correlation between the output current and input voltage of the AC/DC converter 106, so that the AC/DC converter 106 has a maximum input voltage at which the voltage boost will not cause damage or destruction. Therefore, this maximum current value is used as a regulation tool. In one example, this maximum current value is set at 100 μA, and the current consumed by the control unit 200 is on the order of 10 μA. The shunt voltage regulator 108 is used to supply a regulation signal S_reg, which is a function of the output voltage of the AC/DC converter 108.

This regulation signal S_reg having a current value is sent to a clipping or limiter circuit 110 as shown in Figure 4. The limiter stage 110 is connected in parallel between PAD+, PAD-, just before the AC/DC converter 108. The limiter stage 110 comprises at least one limiter transistor TL connected between terminals E1 and E2, which are connected to the input terminals PAD+, PAD-.

From each input terminal PAD+, PAD-, there extends a resistor R1 connected in series with a switch structure 1101, which includes four N-type MOS transistors 1102. The four N-type MOS transistors 1102 are connected so that the first transistor is connected to the resistor R1 via its drain and to the second transistor 1102 via its source, and so on.

Furthermore, each switch structure 1101 includes a plurality of switches 1103 equal to the number of transistors. Switches 1103 are connected to one another via one of their terminals and each is connected to the drain and gate of transistor 1102 via the other terminal. If, for example, a voltage surge occurs across inputs PAD+ and PAD-, these switch structures 1101 are used to create a fast path to control the gate of transistor TL. This fast path provides a secondary ESD protection.

The last transistors 1102 of each structure 1101 are connected to one another. At this connection point, connections are established to the gate of the limiter transistor TL and to the input module 1104, in addition to two current sources 1106a, the latter including a capacitor 1105 connected in parallel. The first current source 1106 is configured to supply the current of the shunt voltage regulator output signal S_reg, i.e., the symbol for the _{shunt current I shunt} , l _ishunt . The drain of an N-type MOS transistor 1107 is connected to the output of this current source, and its gate is connected to its drain. Transistor 1107 is also connected via its source to a second current source 1106b, the value of which is the reference value I ref provided by the bandgap reference voltage generator 109.

The limiter stage 110 is used to limit the incoming voltage in the fourth-stage AC/DC converter 106 by acting on the gate of the limiter transistor TL.

As long as the current I _ishunt sent by the signal S_reg sent from the shunt voltage regulator 108 is lower than or equal to the reference current I ref , nothing happens and the transistor TL is not activated.

Conversely, if the delivered current I _ishunt becomes greater than the reference current I ref , the two current sources 1106 are no longer balanced, and additional current is delivered to the gate of the limiter transistor 106. This current flow to the gate of the limiter transistor TL causes it to turn off, thereby causing the limiter transistor TL to become less conductive, resulting in a drop in the voltage across the AC/DC converter 106. Consequently, the current supplied by the AC/DC converter 106 decreases, causing the current I _ishunt of the control signal S_reg delivered by the shunt voltage regulator 108 to decrease and act on the limiter transistor TL to a greater or lesser extent.

One advantage of the limiter stage 110 is that it is linear, ie it does not clip or distort the input signal, it simply scales the signal.

Another advantage of the limiter stage 110 is that it regulates the voltage at the input terminals PAD+, PAD- by keeping the voltage at these input terminals PAD+, PAD- within a voltage range compatible with proper operation of the RFID tag, whereas the second stage 103 or protection stage provided with protection diodes does not. For example, using only protection diodes, the voltage at the input terminals of a five-stage AC/DC converter could reach 2 volts, which, through a multiplication factor of approximately 4, would produce a voltage of 8 volts at the converter transistor terminals, thus risking damage to the transistors, which normally operate at 2 volts.

For an input voltage of the control unit 200 ranging from tens of millivolts to tens of volts, the limiter stage 110 allows a power range from -20 dBm to +25 dBm.

The proposed regulation operates using a transfer function. The transfer function is the following function:

where _τc is the time constant due to the components of limiter 110 and capacitor 1105,

where τ _r is the time constant due to the components of the regulation circuit and the buffer capacitor Cbuff,

Wherein, e _g is the induced voltage amplitude in the antenna, which is related to the received energy and is available through the received signal field, and V _ant is the effective voltage amplitude at the input terminals PAD+, PAD- controlled by the limiter circuit 110 to maintain a reasonable voltage in the AC/DC converter 106.

Since τ _r << τ _c , where τ _c ≈ 1.7 μs and τ _r = 5 ns, the transfer function becomes:

This transfer function makes it possible to obtain a stable first-order function, as shown in FIG8 , where the large amplitude of the oscillations (A) at the beginning stabilizes in time to obtain a stable state (B).

In a variant, the limiter transistor TL comprises a plurality of transistors connected in parallel.

In another variation, shown in FIG5 , the third or communication stage 104 is used for regulation. This variation considers voltage variations associated with demodulation when a signal is received. In practice, it is possible that, while the signal is being processed, a voltage variation causing a drop in value is detected by the shunt voltage regulator and interpreted as a voltage loss. Shunt voltage regulator 108 can then turn on limiter transistor TL, allowing more voltage to flow to the AC/DC converter. However, this voltage drop is only temporary and could cause a voltage surge in the AC/DC converter, damaging it.

Therefore, the signal Sc from the third stage 104 representing a communication activity is connected to the limiter circuit 110 to prevent regulation during such a communication activity.

This variant advantageously takes voltage variations into account, so that when a signal is received via the antenna, the regulation is shunted to prevent it from being triggered, in particular in the event of a voltage drop in the modulated signal.

In a second embodiment shown in FIG7 , it is conceivable that the RFID tag is a dual-frequency RFID tag. This RFID tag thus comprises two receiver units 100, 100′, a first unit 100 operating at a first frequency (F1) according to a first protocol (P1), and a second unit 100′ connected to an antenna 101′ and operating at a second frequency (F2) according to a second protocol (P2), as shown in FIG6 . For example, the first receiver unit 100 operates at UHF, i.e., a long-range protocol, while the second receiver unit 100′ operates at HF, i.e., a short-range protocol.

In this case, the UHF receiver unit supplies the current Iuhf to the RFID control unit. The HF receiver unit also supplies the current Ihf, so that the control unit 200 is connected to both the UHF receiver unit and the HF receiver unit, and the current received by the control unit 200 is the sum of the currents Iuhf and Ifh, that is, the current Ihf+Iuhf.

Therefore, it is necessary to regulate the current from the second receiver unit 100' in order to allow for regulation to prevent distortion.

The control loop 107 further comprises a current mirror circuit 112 for providing a signal S _I1 representing the current I1 , the signal S _I1 being a symbol of the current, the value of which is the sum of the currents Iuhf and Ihf.

The second receiver unit 100 ′ further comprises a current mirror circuit 113 for providing a signal S _I2 representing the current _I2 , which is indicative of the current Ihf.

The signal S _I1 representing the current I1, which is a symbol of the current Iuhf+Ihf, and the signal S _I2 representing the current I2 are then sent to a subtractor 114 connected to the limiter circuit 110. The currents I1 and I2 are connected to the subtractor 114 so that the latter calculates the difference between I1 and I2, i.e. the following operation: Iuhf+Ihf−Ihf.

The result is a signal S_reg representing the current Iuhf used for regulation in the limiter circuit 110 .

It is clear that various modifications and/or improvements and/or combinations obvious to a person skilled in the art may be made to the various embodiments of the invention described above without departing from the scope of the invention as defined by the accompanying claims.

Of course, the first receiver unit 100 and the second receiver unit 100 ′ may have the same or different structures. Likewise, the second receiver unit 100 ′ can be configured to include a regulation loop similar to that described for the first receiver unit 100 .

Claims (17)

1. A receiver unit for an RFID tag, comprising a first input terminal (PAD+) and a second input terminal (PAD-) connected to an antenna, a communication stage, and a power stage (105), the communication stage being adapted to demodulate and/or modulate an incoming signal thereon, the power stage (105) comprising a voltage converter (106) for supplying power to a control unit (200) of the RFID tag at a first current value. The power supply stage is characterized by further including a regulating circuit (107) adapted to limit the output voltage of the voltage converter. The regulating circuit (107) includes a regulator circuit (108) adapted to determine a second current value, which is a current value provided in addition to the first current value ( _{I_shunt} ). If the second current value exceeds a predetermined threshold (I_ref), the regulator circuit (108) provides a control signal (S_reg), which is sent to a limiter circuit (110) configured to limit the input voltage of the voltage converter. 2. The receiver unit according to claim 1, wherein the voltage converter is of AC/continuous type. 3. The receiver unit according to claim 2, characterized in that the voltage converter (106) includes a grounded generator (1060) at its input terminal, the grounded generator (1060) including a first N-type MOS transistor (1060a) and a second N-type MOS transistor (1060b), the first N-type MOS transistor (1060a) and the second N-type MOS transistor (1060b) being interconnected such that the sources of the first N-type MOS transistor and the second N-type MOS transistor are interconnected to form the ground of the voltage converter, the drain of the first N-type MOS transistor is connected to the first input terminal (PAD+) of the connection antenna and the gate of the second N-type MOS transistor, and the drain of the second N-type MOS transistor is connected to the... The voltage converter further includes a plurality of identical structures (1062) forming a voltage modifier component (1061), wherein the second input terminal (PAD-) of the antenna is connected to the gate of the first N-type MOS transistor, and the voltage converter is characterized in that the output of the voltage converter includes two output N-type MOS transistors (1066), wherein the sources of the two output N-type MOS transistors are interconnected to form an output line, the drain of one of the two output N-type MOS transistors is connected to the last structure of the voltage modifier component extending from the first output terminal of the voltage modifier component, the drain of the other output N-type MOS transistor is connected to the last structure of the voltage modifier component extending from the second output terminal of the voltage modifier component, and the gate of each output N-type MOS transistor is connected to its source. 4. The receiver unit according to claim 3, characterized in that the voltage modifier component (1061) is configured to extend from each of the first input terminal (E1) and the second input terminal (E2) of the voltage modifier component a series of identical structures (1062) connected to each other, the first structure of each series being connected to one of the first input terminal (E1) and the second input terminal (E2) of the voltage modifier component and subsequent structures, the connection point between the two structures being connected to one of the first input terminal (E1) or the second input terminal (E2) of the voltage modifier component, such that each structure is connected to the first output terminal and the second output terminal of the voltage modifier component. 5. The receiver unit according to claim 1, wherein the limiter circuit (110) includes at least one transistor (TL), the at least one transistor (TL) being connected via its drain to a first input terminal (E1) of the voltage modifier component and via its source to a second input terminal (E2) of the voltage modifier component, and the control signal (S_reg) being sent to its gate to enable the at least one transistor to be more or less turned on. 6. The receiver unit according to claim 5, wherein the limiter circuit (110) comprises a plurality of transistors connected in parallel. 7. The receiver unit according to claim 1, wherein the adjustment unit (107) further comprises a bandgap voltage generator (109) for providing a reference voltage (VBG) and polarization current to the shunt voltage regulator. 8. The receiver unit according to claim 1, wherein the communication stage (104) is adapted to provide a signal (Sc) indicating a communication action, the communication action being directly connected to the limiter circuit (110) to prevent adjustment during such communication action. 9. An RFID tag (1) including a control unit (200), the control unit (200) including a computing unit and a memory for performing at least one function, and at least one receiver unit configured to receive or transmit signals and supply power to the control unit, characterized in that the receiver unit is the receiver unit (100) according to claim 1, and the at least one receiver unit includes a first receiver unit. 10. The radio frequency tag according to claim 9, wherein the first receiver unit (100) is configured to operate according to a first protocol (P1) using a first frequency (F1). 11. The radio frequency tag according to claim 10, wherein the first protocol (P1) is a long-distance protocol. 12. The RFID tag according to claim 9, wherein at least one receiver unit of the RFID tag further comprises a second receiver unit (100'), the second receiver unit (100') being configured to operate according to a second protocol (P2) using a second frequency (F2), the second receiver unit being configured to supply a second current (Ihf) to the unit (200), the control unit receiving a third current (Ihf+uhf), the value of the third current (Ihf+uhf) being the sum of a first current (Iuhf) from the first receiver unit (100) and a second current (Ihf) from the second receiver unit (100'). 13. The RFID tag according to claim 10, wherein at least one receiver unit of the RFID tag further comprises a second receiver unit (100'), the second receiver unit (100') being configured to operate according to a second protocol (P2) using a second frequency (F2), the second receiver unit being configured to supply a second current (Ihf) to the unit (200), the control unit receiving a third current (Ihf+uhf), the value of the third current (Ihf+uhf) being the sum of a first current (Iuhf) from the first receiver unit (100) and a second current (Ihf) from the second receiver unit (100'). 14. The RFID tag according to claim 11, wherein at least one receiver unit of the RFID tag further comprises a second receiver unit (100'), the second receiver unit (100') being configured to operate according to a second protocol (P2) using a second frequency (F2), the second receiver unit being configured to supply a second current (Ihf) to the unit (200), the control unit receiving a third current (Ihf+uhf), the value of the third current (Ihf+uhf) being the sum of a first current (Iuhf) from the first receiver unit (100) and a second current (Ihf) from the second receiver unit (100'). 15. The RFID tag according to claim 12, characterized in that the first receiver unit further includes a current mirror circuit (112) for providing a signal (S _I1 ) representing a fourth current (I1), the fourth current (I1) being a symbol of the sum of the currents of the first receiver unit and the second receiver unit, the second receiver unit (100') further includes a current mirror circuit (113) for providing a signal (S _I2 ) representing a fifth current (I2), the fifth current (I2) being a symbol of the second current (Ihf) provided by the second receiver unit (100'), and characterized in that the first receiver unit further includes a subtractor circuit (114) for subtracting the fifth current (I2) as a symbol of the sum of the currents of the first receiver unit and the second receiver unit from the fourth current (I1) symbolized by the current provided by the second receiver unit, and for providing a signal to the limiter circuit (110) representing only the first current (Iuhf) from the first receiver unit. 16. The RFID tag according to claim 13, characterized in that the first receiver unit further includes a current mirror circuit (112) for providing a signal (S _I1 ) representing a fourth current (I1), the fourth current (I1) being a symbol of the sum of the currents of the first receiver unit and the second receiver unit, the second receiver unit (100') further includes a current mirror circuit (113) for providing a signal (S _I2 ) representing a fifth current (I2), the fifth current (I2) being a symbol of the second current (Ihf) provided by the second receiver unit (100'), and characterized in that the first receiver unit further includes a subtractor circuit (114) for subtracting the fifth current (I2) representing the sum of the currents of the first receiver unit and the second receiver unit from the fourth current (I1) representing the current provided by the second receiver unit, and for providing a signal to the limiter circuit (110) representing only the first current (Iuhf) from the first receiver unit. 17. The RFID tag of claim 14, wherein the first receiver unit further comprises a current mirror circuit (112) for providing a signal (S _I1 ) representing a fourth current (I1), the fourth current (I1) being a symbol of the sum of currents of the first receiver unit and the second receiver unit, the second receiver unit (100') further comprises a current mirror circuit (113) for providing a signal (S _I2 ) representing a fifth current (I2), the fifth current (I2) being a symbol of a second current (Ihf) provided by the second receiver unit (100'), and wherein the first receiver unit further comprises a subtractor circuit (114) for subtracting the fifth current (I2) as a symbol of the sum of currents of the first receiver unit and the second receiver unit from the fourth current (I1) as a symbol of currents provided by the second receiver unit, and for providing a signal to the limiter circuit (110) representing only the first current (Iuhf) from the first receiver unit.