HK1228112B - Microlenses for multibeam arrays of optoelectronic devices for high frequency operation - Google Patents

Description

Microlenses for multi-beam arrays of optoelectronic devices operating at high frequencies

CROSS-REFERENCE TO RELATED APPLICATIONS

This international application claims the benefit of U.S. patent application No. 13/902,555, filed on May 24, 2013; and is related to U.S. patent application No. 13/077,769, filed on March 31, 2011, entitled “Multibeam Arrays of Optoelectronic Devices for High Frequency Operation”; U.S. patent application No. 12/707,657, filed on February 17, 2010, entitled “Multibeam Arrays of Optoelectronic Devices for High Frequency Operation”, now U.S. Patent No. 7,949,024; and U.S. patent application No. 61/153,190, filed on February 17, 2009, entitled “Multibeam Arrays of Optoelectronic Devices for High Frequency Operation”.

This international application also claims the benefit of U.S. patent application No. 13/868,034, filed on April 22, 2013, entitled “Addressable Illuminator with Eye-Safety Circuitry,” which claims the benefit of provisional U.S. patent application No. 61/636,570, filed on April 20, 2012, entitled “Addressable Illuminator with Eye-Safety Circuitry,” all of which are incorporated herein by reference in their entirety.

Technical Field

The present application relates to semiconductor devices, and more particularly to a microlens structure of a multi-beam array of a photonic device for high-power and high-frequency applications, and methods of manufacturing and using the microlens structure.

Background Art

Semiconductor lasers have made an impact on high-power laser applications due to their higher efficiency, advantages over other forms of high-power lasers in size, weight, and power (SWAP), and their lower cost. Many laser applications require high power and high frequency response, such as industrial cutting and welding, laser detection and ranging (LADAR), medical engineering, aerospace defense, optically pumped rare earth element fiber lasers, optically pumped solid crystals in diode pumped solid-state lasers (DPSS), fiber optic communications, and fusion research. Due to their high power array output, edge-emitting semiconductor lasers are widely used in such applications. However, degradation of these edge-emitting lasers is common, mainly due to the occurrence of catastrophic optical damage (COD) due to the high optical power density at the exposed emission end facet.

In contrast, vertical-cavity surface-emitting lasers (VCSELs) are not subject to catastrophic optical damage because the gain region is embedded in the epitaxial structure and is therefore not exposed to the external environment. In addition, the optical waveguide associated with the edge emitter junction has a relatively small area, resulting in significantly higher power density than VCSELs. As a practical result, VCSELs can have lower failure rates than typical edge-emitting lasers.

To date, VCSELs have been more commonly used in data and telecommunications applications that require higher frequency modulation but do not require more power. VCSELs offer advantages over edge-emitting lasers in this type of application, including ease of manufacture, higher reliability, and better high-frequency modulation characteristics. VCSEL arrays can also be manufactured efficiently at a much higher cost than edge-emitting laser arrays. However, with existing VCSEL designs, as the area of the array increases, the frequency response is affected by the thermal complexity caused by the multi-element design, parasitic impedances, and the frequency response of the wire bonds or leads required for high currents. As a result, the modulation frequency of the array is reduced.

VCSELs and methods for manufacturing VCSELs are known. See, for example, U.S. Patent Nos. 5,359,618 and 5,164,949, which are incorporated herein by reference. Forming VCSELs into two-dimensional arrays for data display is also known. See, for example, U.S. Patent Nos. 5,325,386 and 5,073,041, which are incorporated herein by reference. Flip-chip multi-beam VCSEL arrays for higher output power are described, in particular, in U.S. Patent No. 5,812,571, which is incorporated herein by reference.

However, VCSEL arrays that provide both high-frequency modulation and high power have not yet been fully developed. In addition, arranging such devices together increases heat generation, which negatively impacts high-frequency operation.

In addition, free-space optical links for short-range mobile device communications are generally designed with optical elements for efficiently transmitting low-divergence light beams (using collimating optical elements) and optical elements for efficiently receiving incident light (using focusing lenses). Because high-speed detectors are very small, with a diameter of about 60 μm at speeds of 5-10 Gb/s, the collection optical elements focus the light downward into a small spot to obtain a good signal-to-noise ratio. Therefore, such systems are very sensitive to alignment because if something moves or disturbs the alignment, the small spot may easily miss the small detector. This makes free-space optical communication difficult between mobile devices. The exception is the IrDA (Infrared Data Association) standard, which uses LED-based transmission into a very wide transmission beam and hemispherical collection optical devices. Although free-space optical links are popular at relatively low speeds, as the concept of mobile devices has developed, there is a need to develop high-bandwidth communications between two devices that can actually touch each other or are separated by only a few millimeters. While there are radio frequency methods that will work within these near field ranges, these have disadvantages including omnidirectional transmission, which is a safety issue, and regulatory issues due to RF interference problems.

Summary of the Invention

Embodiments relate to: a multi-beam optoelectronic device with high power and high frequency response, known as a VCSEL array device, various microlens structures that can be formed on the multi-beam optoelectronic device, and various methods of using the various microlens structures. The VCSEL array device is a monolithic array of VCSELs consisting of two or more VCSELs and an array of shorting mesa devices. The VCSELs of the VCSEL array can be spaced symmetrically or asymmetrically, spaced according to a mathematical function for improving power or speed characteristics, or arranged in an electrically parallel circuit with a phase relationship adjacent to each other. The VCSELs of the VCSEL array are electrically connected to a first metal contact pad formed on a heat sink substrate or carrier. The shorting mesa array devices are formed adjacent to the VCSEL array, and the devices are bonded to a second metal contact pad on the heat sink substrate or carrier. These mesa devices form a short circuit from the substrate ground to the second metal contact pad. Each VCSEL in the VCSEL array includes: a metal heat sink structure that increases the height of each VCSEL mesa; a heat sink structure; and solder. The relationship between the heat sink structure, the VCSEL array, and the mesa array reduces the parasitic impedance characteristics of the VCSEL array device, thereby increasing its output power and improving its high-frequency response. The VCSEL array and the short-circuited mesa array can also be configured to form a coplanar waveguide lead in a ground-signal-ground configuration in the bonded optoelectronic device. This configuration provides excellent signal modulation characteristics. A variety of techniques can be used to form microlenses on each VCSEL device in the array. The microlenses can be constructed and/or patterned to achieve multiple effects using the output laser rather than using external lenses.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are provided to illustrate exemplary embodiments described herein and are not intended to limit the scope of the present disclosure.

1 is a simplified cross-sectional view showing the mesa structure of both a VCSEL device and a shorted mesa device, including dielectric deposition, metal deposition, and oxidation structures and other features according to an embodiment;

2 is another simplified cross-sectional view illustrating a VCSEL device and a shorted mesa device, also showing a heat sink, bonding layer, and other features according to an embodiment;

3A is a top view of a patterned heat sink substrate showing a coplanar waveguide formed by surrounding a ground plane, signal leads separated by gaps to the ground plane, and the signal leads according to an embodiment;

3B is an embodiment of the coplanar waveguide of FIG. 3A , wherein the ground plane extends to the edge of the heat sink and forms a loop around the contact pads of the VCSEL device;

FIG4 is a cross-sectional view of the VCSEL array device of FIG2 and the heat dissipation substrate of FIG3A before bonding;

FIG5 is a schematic diagram of an embodiment of a VCSEL array device after plating;

FIG6 is a graph showing L-I-V characteristics of an embodiment of a VCSEL array device;

FIG7 is a graph illustrating modulation frequency of an embodiment of a VCSEL array device;

8 is a graph showing laser modulation frequency at different array positions at a bias current of 450 mA for an embodiment of a VCSEL array device.

FIG9 is a graph illustrating pulse widths from an embodiment of a VCSEL array device;

10 is a partially-broken cross-sectional view of a plurality of lenses provided on a VCSEL array device according to an embodiment;

FIG11 is a schematic diagram of a manner in which each of a plurality of lenses is positioned in an offset position above each VCSEL device of a VCSEL array device;

FIG12 is a schematic diagram of an embodiment of a microlens with a focus spot located behind a VCSEL array device;

FIG13 is a schematic diagram of an embodiment of a VCSEL array device bonded to a substrate (submount) using a flip chip;

FIG14 is a schematic diagram of an embodiment of a VCSEL array device using a sub-array flip chip to be bonded to a substrate;

FIG15 is a schematic diagram of the electrical contacts and transmission lines of the substrate of FIG14;

FIG16 is a schematic diagram of an embodiment in which two sub-arrays of a VCSEL array device form a circle on a detector;

FIG17 is a schematic diagram of an embodiment of grouping sub-arrays forming a larger circle for a detector;

FIG18 is a schematic diagram of an embodiment of a transceiver on a substrate;

FIG19 is a schematic diagram of an embodiment of a linear array of sub-arrays and an external macro lens;

FIG20 is a schematic diagram of an embodiment of a linear array of switches of FIG17;

FIG21 is a schematic diagram of an embodiment of operating a nonlinear laser array and a macro lens as a digital switching device;

FIG22 is a schematic diagram of an embodiment of a computing or communication device connected to a digitally switched laser array;

FIG23 is a schematic diagram of an embodiment of a linear transceiver;

FIG24 is a schematic diagram of an embodiment of a 4×4 optical switch;

FIG25 is a schematic diagram of an embodiment of a 12×12 optical switch; and

26 is a schematic diagram of an embodiment of an array of laser devices focused at different points in space.

DETAILED DESCRIPTION

VCSEL array devices, such as that described in U.S. Patent No. 5,812,571, are flip-chip VCSEL array devices that utilize a metal contact layer that also serves as a reflector for the top reflector and is formed above each mesa. This single metal layer is typically deposited using techniques such as electron beam (e-beam) evaporation or sputtering to create a highly uniform or reflective surface. While these deposition techniques are suitable for the described applications, they are inappropriate when seeking to achieve a thick metal layer surrounding the mesa, which is critical for improved heat reduction in such devices. In order to deposit a sufficiently thick layer using existing techniques, large amounts of metal, such as gold (Au), must be used, which significantly increases the cost of such devices. This type of design, as well as the designs of other existing VCSEL array devices, also increases the overall impedance of the system and complicates thermal management, thereby limiting the power and speed achievable by such arrays.

In the embodiments described herein, heat dissipation from an array of optical semiconductor devices, as well as a reduction in both parasitic capacitance and inductance (collectively referred to herein as "reduction in parasitic impedance"), is achieved by reducing the common p-contact area to a minimum size and increasing the distance between the common contact pad and the substrate ground, while surrounding the common contact pad with a ground plane at a distance derived from the properties of a coplanar waveguide, and forming a raised heat sink proximate to each active mesa element and ground mesa in the array. The minimized common p-contact area of the embodiments is a significant departure from existing designs that require an extended common p-contact area to make contact with wire bonds. The embodiments eliminate the need for wire bonds. The elimination of wire bonds reduces inductance, while the resulting raised height of the mesa and heat sink structure under electrical bias from the substrate ground to the contact pad on the heat sink substrate increases the distance between negative and positive potentials, thereby reducing the overall parasitic capacitance of the system. This is achieved by using a seed layer to form a thick plated metal heat sink that enables significant heat removal through the edge of each VCSEL, as well as improving frequency response.

Furthermore, the ground (or negative) electrical connection is made by shorting the mesa device, allowing current to flow through the coplanar leads and to a heat sink or heat-reducing substrate, without the use of wire bonds. Wire bonds are used in existing designs to connect the top of the substrate to the ground of the package, but wire bonds are undesirable because they introduce parasitic inductance that negatively impacts the frequency response of the VCSEL array device. Furthermore, the large number of leads required by existing designs introduces significant manufacturing complexity, a greater potential for defects, and increased cost.

FIG1 shows a simplified schematic cross-section of a VCSEL array device 100 according to an embodiment. It should be understood that the schematic diagram of the VCSEL array device in this embodiment illustrates an array of semiconductor devices and a method of manufacturing and bonding an array of semiconductor devices. However, it should be understood that the methods disclosed therein can be used to manufacture arrays of other semiconductor devices, such as light-emitting diodes, photodetectors, edge-emitting lasers, modulators, high electron mobility transistors, resonant tunneling diodes, heterojunction bipolar transistors, quantum dot lasers, etc. Furthermore, it should be understood that the schematic diagram of the VCSEL array device 100 in the embodiment is for illustrative purposes only and is not intended to limit the scope of the present invention in any way.

In the present embodiment, the VCSEL array device 100 includes a substrate 102 comprising gallium arsenide (GaAs), but other materials such as indium phosphide (InP), indium arsenide (InAs), silicon (Si), epitaxially grown materials, etc. may also be used to form the substrate 102. It should also be understood that the substrate 102 generally includes a lattice constant that is selected to minimize defects in the material layers subsequently grown on the substrate 102. It should also be understood that the selection of at least one of the composition and thickness of the subsequently grown material layers will provide a desired operating wavelength. The subsequent layers are deposited on the substrate 102 by epitaxial growth using molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), etc.

In this embodiment, a lattice-matched lower distributed Bragg reflector (DBR) 104 is epitaxially deposited on substrate 102 to form the first raised layer of the VCSEL mesa 103 and the shorting/shorting/grounding mesa 105. Lower DBR 104 is formed from multiple layers of alternating materials, with periodic variations in the effective refractive index in the waveguide caused by varying (high and low) refractive indices or by periodic variations in some characteristic of the dielectric waveguide, such as height. Each layer boundary causes a partial reflection of the light wave, with the resulting combination of layers acting as a high-quality mirror at the desired operating wavelength. Therefore, although lower DBR 104 (and upper DBR 108, as described further below) can include more than one material layer, for simplicity and ease of discussion herein, lower DBR 104 is illustrated in FIG1 as comprising a single layer. A portion of lower DBR 104 can also be made conductive to allow electrical contact with the VCSEL array device (not shown).

In an embodiment, an active region 106 is epitaxially deposited on the lower DBR 104. Although shown as a single layer (again for simplicity and ease of discussion), the active region 106 includes a cladding (and/or waveguide) layer, a barrier layer, and an active material capable of emitting a significant amount of light at a desired operating wavelength. In an embodiment, the wavelength of operation is a wavelength within a generally given range of from about 620 nm to about 1600 nm (for a GaAs substrate). However, it should be understood that other wavelength ranges may be desirable, and this will depend on the specific application.

As will be appreciated by those skilled in the art, the wavelength of emission is substantially determined by the choice of materials used to create the lower DBR 104 and upper DBR 108, as well as the composition of the active region 106. Furthermore, it should be understood that the active region 106 may include various light-emitting structures, such as quantum dots, quantum wells, and the like. In an embodiment, the upper DBR 108 is disposed on the active region 106, and the similar lower DBR 104 is conductive to enable an ohmic electrical connection (not shown). In some embodiments, the lower DBR 104 is n-doped and the upper DBR 108 is p-doped, but this can be reversed, with the lower DBR 104 being p-doped and the upper DBR 108 being n-doped. In other embodiments, an electrically insulating DBR (not shown) may be employed, utilizing intracavity contacts and layers relatively close to the active region.

In some embodiments, an upper reflector contact layer 109 is disposed on the upper DBR 108. The contact layer 109 is typically heavily doped to facilitate ohmic electrical connection with metal deposited on the contact layer 109 and, therefore, with the circuit (not shown). In some embodiments, the contact layer 109 can be formed as part of the upper DBR 108.

Each of the mesas 103 and 105 described above and their structures can be defined using photolithography and etching. This can be achieved by patterning the epitaxially grown layers using common photolithography steps (e.g., applying, exposing, and developing a positive-thickness resist). The thickness of the resist can vary as known in the art depending on the etch selectivity between the resist and the epitaxial layer and the desired mesa geometry.

For GaAs-based materials, chlorine (Cl)-based dry etching plasma (such as Cl ₂ :BCl ₃ ) is usually used to complete etching, but any number of gases or mixtures can be used. Etching can also be completed by many wet etchants. Other forms of etching such as ion milling or reactive ion beam etching can also be used. The depth of etching is selected to be deep enough to isolate the active area of the mesa in the array. Etching stops on the N mirrors (lower DBR 104), on the etch stop/contact layer formed in the N mirrors (lower DBR 104), or through the N mirrors (lower DBR 104) into the substrate 102. After etching to form the mesa, the remaining photoresist is removed. This can be achieved using wet solvent cleaning or dry oxygen (O ₂ ) etching or a combination of the two.

A confined region 110 may also be formed within each mesa. Within the VCSEL mesa 103, the confined region 110 defines the aperture 112 of the device. The confined region 110 may be formed as an index guide region, a current guide region, or the like, and provides optical confinement and/or carrier confinement to the aperture 112. The confined region 110 may be formed by oxidation, ion implantation, and etching.

For example, oxidation of a layer (or layers) high in aluminum (Al) content can be achieved by timing the placement of the wafer or sample in an environment of heated nitrogen ( _N2 ) bubbled with water ( _H2O ) and injected into a furnace typically at temperatures exceeding 400° C. Photolithographic steps for current confinement to define the ion implantation area can also be used, as well as combinations of these techniques with others known in the art.

It will be appreciated that the confined region 110, defining the aperture 112, may comprise more than one layer of material, but for simplicity and ease of discussion, is shown in this embodiment as comprising one layer. It will also be appreciated that more than one confined region may be used.

In the embodiments shown in the accompanying drawings, the mesa sizes and the apertures for generating the light of the VCSELs are identical and have uniform spacing. However, in some embodiments, the VCSEL mesas of the devices in the array can be of different sizes. In addition, the spacing of the VCSEL mesas in the array can be different. In some embodiments, the spacing of the light generating VCSEL mesas in array 100 is between approximately 20 μm and 200 μm. However, larger and smaller spacings are also possible.

A dielectric deposition process may be used or processed to define openings to the contact surface. First, the deposition of dielectric material 114 over the entire surface of device 100 is typically achieved by plasma enhanced chemical vapor deposition (PECVD), although other techniques such as atomic layer deposition (ALD) may also be used. In an embodiment, dielectric cap 114 is a conformal coating over the upper surface (including the sidewalls of the mesa) and is sufficiently thick to prevent leakage current from the metal layer behind it through pinholes.

Other properties to consider when selecting the thickness of this film are the capacitance created between the plated metal heat sink 124 (described further below with reference to FIG. 2 ) and the substrate 102, where thicker dielectric layer 114 is advantageous, and the need for dielectric layer 114 on the sidewalls of the VCSEL 103 to transfer heat from the active area to the heat sink 124, where a thinner layer would be beneficial. In some embodiments, multiple depositions using different deposition techniques can be used to achieve a layer with both properties. An example of such a technique is deposition of PECVD silicon nitride (Si ₃ N ₄ ) followed by electron beam deposition of Si ₃ N ₄ , or another dielectric can be deposited at a higher directional deposition rate, thereby placing a thicker dielectric material on the incident surface. Once the dielectric layer 114 has been formed, a photolithographic process is then used to define openings in the dielectric above each VCSEL mesa where contact with the top mirror contact layer 109 is to be made. The dielectric layer 114 is also removed over the substrate 102 between each VCSEL mesa 103 , over the substrate 102 around the ground mesa 105 , and over the top and sides of each ground mesa 105 .

Turning now to FIG2 , the next processing step is the photolithography process for defining the contacts above the top reflector 108, wherein the dielectric is opened in the above step to enable the formation of the p-metal layer therein in a subsequent step. In an embodiment, the opening area of the photoresist is typically about a few microns wide, slightly larger than the dielectric opening. In other embodiments, the diameter of the photoresist opening can be smaller than the diameter of the dielectric opening or as large as the diameter of the heat sink material above the shorting mesa plated in a later step. Unless the dielectric coating is conformal and covers the N reflector portions at the base of the mesa, the opening cannot be larger than the mesa diameter in the active light generating mesa or the subsequent metal will short the p- and n-potentials.

Once the opening area in the photoresist is defined, metallization can be performed above the opening area, typically using a P-type metal. The p-metal contact layer 120 is typically a multilayer deposition deposited by electron beam, resistive evaporation, sputtering, or any other metal deposition technique. First, a thin titanium (Ti) layer is deposited to provide adhesion for the next layer. The thickness of this adhesion layer can vary significantly, but is generally selected to be between about 1000 Å and about 2000 Å, since the Ti film is stressed and has a resistivity greater than that of the subsequent layers. In an embodiment, the adhesion layer is about 1000 Å thick. This layer can be replaced by other adhesive metal layers (such as chromium (Cr), palladium (Pd), nickel (Ni), etc.). In addition, this layer can be used as a reflector layer to increase the reflectivity of the contact mirror.

The next layer is deposited directly on top of the bonding layer without breaking the vacuum during deposition. In many cases, this layer serves as a protection to prevent gold (Au) or other top metals from diffusing too far into the contacts due to overheating during the bonding phase (diffusion barrier). The metal selected is typically palladium, platinum (Pt), nickel, tungsten (W) or other metals or a combination of these metals selected for this purpose. The selected thickness should depend on the specific bonding temperature required in the flip chip process. The thickness of this layer is generally between about 1000A and about 2000A. In embodiments using a low temperature bonding process, such as in an indium bonding process, the diffusion barrier layer may be optional and not deposited as part of the metal contact stack.

The next layer is typically Au, but can also be palladium or platinum, or a mixture such as gold beryllium (AuBe) or gold zinc (AuZn). In the embodiment described below, this layer is about 1000 Å thick. However, this layer can generally have a wide range of thicknesses, depending on the photoresist properties and the heating characteristics of the deposition. In some embodiments, another metal can also be deposited at this time to increase the metal thickness and form a metal heat sink at this stage, thereby reducing the number of processing steps, but this technique is not necessary and is not utilized in the exemplary device described below.

Common lift-off techniques are typically selected for this photolithography process so that the metal deposited on the surface can be easily separated from the surface area covered with photoresist, so that any metal on the photoresist is removed without adhering to the semiconductor or affecting the bonding of the metal to the semiconductor. As described above, photolithography is then used to define the openings above the various portions of the substrate 102 and the short-circuited n-contact mesa 105, where the dielectric is formed in the previous step. In an embodiment, the opening area in the photoresist corresponding to the n-metal deposition should be slightly larger than the opening in the dielectric opening for the n-metal. The n-metal layer 122 is then deposited and can form a circuit with the substrate 102 through the lower DBR 104 (if an n-mirror), within the lower DBR 104, or to the substrate 102 itself, which is usually heavily doped with an etch stop and contact layer. The process for forming the n-metal layer 122 is similar to that of the p-metal layer 120. The metal layer can be selected to include Ni/Ge/Au, Ge/Au/Ni/Au, or many such combinations. In some embodiments, the first layer or layers are selected to reduce contact resistance by diffusing into the n-doped epitaxial material of substrate 102. In other embodiments, due to the various diffusion properties of the materials, the first layer of the multilayer metal stack can also be selected as a diffusion limiting layer, such as Ni, so that the metal does not "clump" and is independent during the annealing process. Uniform distribution diffusion of these metals is desirable and can be used to reduce contact resistance, which also reduces heat. The thickness of such a multilayer metal stack can vary significantly. In the present embodiment to be described, a Ni/Ge/Au metal stack with a thickness of Å is used.

A rapid thermal annealing (RTA) step is then performed on the wafer to reduce contact resistance. For the described embodiment, the process temperature is rapidly increased to ~400°C, held for approximately 30 seconds, and then dropped to room temperature. The temperature and time conditions of the RTA step depend on the metallization and can be determined using a design of experiments (DOE) as known to those skilled in the art.

In other embodiments, this step can be performed at an earlier or later stage in the process flow, but is generally completed before the solder is deposited to reduce oxidation of the solder or adhesive metal. A photolithographic process (using a thin layer of photoresist, typically about 1 μm to 3 μm) is used and developed to define the contact openings above the substrate 102 and the contact openings above the short-circuited N-contact mesa 105 and the contact openings above the active mesa 103, where the heat sink structure will be plated or established. The next step is the deposition of a metal seed layer, and is typically a multilayer deposition and deposited by electron beam, resistive evaporation, sputtering or any other metal deposition technique. Metal layers such as Ti/Au, or many such combinations can be selected, wherein the first layer or layers are deposited for adhesion and are easily etched away and the second layer is deposited for conductivity and is easily etched away. If this technology is used to establish a heat sink, the seed layer is continuous on the surface allowing the electrical connections to be plated.

In an embodiment, thick metal is then deposited by plating to form the heat sink 124. However, other deposition methods that do not require a metal seed layer can also be used. For plating, a photolithographic process is used to define an opening above the opening defined by the previous seed layer resist. The photoresist is removed in the area where deposition will occur. The thickness of the photoresist must be selected so that it easily falls off after defining the thick metal, and is typically in the range of about 4 μm to about 12 μm in thickness. Plasma cleaning is performed using O ₂ or water in combination with ammonium hydroxide (NH ₄ OH) to remove any resist left on the gold seed layer. Next, the heat sink 124 metal is plated using a standard plating procedure. In the described embodiment, copper (Cu) is selected as the metal for plating due to its thermal conductivity properties, but non-oxidizing metals such as Au, Pd, Pt, etc. that can provide good thermal conductivity and provide an interface that does not reduce device reliability may be more suitable. The plating thickness can vary. In the described embodiment, a thickness of about 3 μm is used.

Next, the wafer or sample is placed in a solder plating agent (such as indium (In) plating) to form a bonding layer 126. At this step, other metals can be selected for their bonding characteristics. The thickness can vary significantly. In the described embodiment, about 2 μm of plated In is deposited on the heat sink. However, other solders, such as gold-tin (AuSn) alloys, can also be used, and alternative deposition techniques, such as sputtering, can also be used. After the metal deposition is completed, the photoresist is then removed as described above using solvents, plasma cleaning, or a combination of the two, and the seed layer is etched using dry etching or wet etching for etching Au, and then the seed layer is etched using dry etching or wet etching for etching Ti and/or removing _TiO2 . The seed layer photoresist is then removed using standard resist cleaning methods. At this point, the VCSEL array substrate is complete and ready for bonding.

The complete packaging of the mesa with the thick heat sink material is an important aspect of the embodiment. Since the active areas of the mesa are closest to the edges where the thick heat sink material is formed, they have good thermal conductivity, allowing the design of the embodiment to efficiently and effectively remove the heat generated by these active areas. As mentioned above, this is significantly different from existing VCSEL array device heat removal techniques that place the heat sink material on top of the mesa. These existing or previous designs require heat to move through a series of higher thermal conductivity materials (mirrors) or dielectrics, resulting in less efficient and less effective heat removal.

While some existing designs include mesas with a thin layer of heat sink material for heat reduction purposes, these designs do not take into account the resulting heat sink height. By using a thick heat sink layer and increasing the distance between the n-substrate ground potential and the p-contact surface on the heat sink substrate, the present embodiment reduces the system's parasitic capacitance as the height of the heat sink layer increases. Furthermore, in addition to heat reduction, the build-up of additional material increases the frequency response. In another embodiment, the dielectric layer 114 covers the entire substrate surrounding the n-mirror or mesa and does not form openings, allowing the heat sink material to completely cover all mesas and form a large heat sink structure, rather than individual mesas of the heat sink. In this case, only the n-contact needs to be extended from the shorted mesa to the substrate. The heat sink of the embodiment also improves the operation of the VCSEL array by reducing the heat generated by adjacent mesas. In most electrical devices, reduced heat tolerance will increase the frequency response of each device. By improving the heat dissipation performance of the VCSEL array device of the present device, a significant increase in the high-speed performance of the VCSEL array device is possible. Furthermore, it is also apparent in this embodiment that the additional height of the mesas reduces capacitance by increasing the distance between the substrate ground plane and the positive contact plates connecting all the active mesas in parallel, due to the increased heat sink buildup compared to existing array circuits. The resulting effect is a reduction in the parasitic impedance of the circuit, which also increases the frequency response of the entire array.

In addition, the shorted mesa design that forms the sub-array around the active area enables current to flow directly from the fabricated VCSEL substrate to the ground plane on the heat sink without the need to form multiple wire bonds. This aspect of the embodiment reduces manufacturing complexity and also reduces parasitic inductance from the multiple leads shown in existing arrays. The shorted mesa design forms a coplanar waveguide when flip-chip bonded to the heat sink substrate, which benefits the frequency response of the array. This design feature also allows for a simpler package design without the need for raised wire bonds, which can affect reliability and positioning.

Referring now to FIG3A , a process for preparing a heat sink or heat reducing substrate 200 for attaching to the array 100 in a non-conductive manner is described. First, a photoresist is deposited and defined above the surface of the substrate. A conventional lift-off technique is then selected for the next photolithographic process so that the metal is deposited on the surface and can be easily removed from the surface area covered with the photoresist. The metal layer is then deposited using any method. The photoresist is removed using any standard resist cleaning technique. Once this has been completed, the heat sink or heat reducing substrate is ready for flip-chip bonding. Two contact pads are then created: a first contact pad 202 for connecting to the VCSEL device 103; and a second contact pad 204 for connecting to the shorted mesa device 105.

In another embodiment, metal can be deposited over the entire surface of the dielectric material and then defined using a photolithographic process, while the exposed areas are etched away, leaving two unconnected metal pads 202 and 204. In an embodiment, the first contact pad (or signal pad) 202 is generally circular and the second contact pad (or ground pad) 204 forms a loop around the first contact pad 202, thereby forming a coplanar waveguide lead in a ground-signal-ground configuration. This configuration is well known for its excellent signal characteristics and allows for flexible device testing and packaging. In other embodiments, the contact pad 202 can be square or another shape, with the ground pad 204 forming a loop around the contact pad 202 as shown in FIG3B . The ground plane or loop must have a consistent gap 206 width from the contact pad 202 to maintain optimal operating characteristics, however, the remainder of the ground metal can extend beyond the loop shown in FIG3A , even to the edge of the substrate as shown in FIG3B , to facilitate ground connection.

The coplanar waveguide can be designed to match the impedance of the driver circuit by simply adjusting the gap width 206 and/or the signal lead width based on a given metal and non-conductive substrate thickness and material properties. The formulas for calculating the impedance of a coplanar waveguide with a dielectric substrate of finite thickness are well known and too long to be repeated here. However, by way of example, for a diamond substrate with a dielectric constant of 5.5, a metal layer thickness of 20 μm, a signal lead width of 1 mm, and a desired driver impedance of 50 ohms, the calculated gap width (between the signal pad and ground) should be 200 μm or 0.2 mm. More precise calculations can be performed, which require many higher-order considerations such as current limiting, hysteresis, temperature, surface characteristics, and background considerations.

As shown in Figures 3A and 3B, the VCSEL array and the short-circuited mesa array are shown as dashed lines to indicate where the VCSEL array and the short-circuited mesa array will be bonded to the heat sink substrate, and thus to indicate the positions of the two arrays after bonding. Optionally, an In plating or the like for bonding deposition can also be formed at these locations on the heat sink substrate 200. The laser emission is then directed through the reflector 104 and through the substrate 102 to form a multi-beam array. In an embodiment, the substrate thickness is reduced to reduce the optical power loss caused by the substrate transmission characteristics.

Flip-chip bonding is performed on two substrates with a heat sink substrate on the bottom. Figure 4 shows the alignment of the VCSEL array 100 and substrate 200 before bonding. The bonding process is performed by a machine that aligns the two substrates together; then places the two substrates in contact with each other; and heats one or both substrates before or after contacting the substrates. In the depicted embodiment, the bottom substrate is heated to approximately 285°C and held at that temperature for approximately 10 minutes. A 20-gram weight is used in the downward substrate position. The bonded wafers are allowed to cool to room temperature, concluding the process.

In another embodiment, after flip-chip bonding, the substrate 102 can be removed from the mirror 104 by adding a selectively etched layer with a high aluminum (Al) content, such as an aluminum gallium arsenide (AlGaAs) (~98%, Al) layer, or a layer composed of indium gallium phosphide (InGaP) or other such selective material that will etch at a significantly different rate than the gallium arsenide (GaAs) substrate. This layer is grown in epitaxial growth between the substrate 102 and the first epitaxial deposition of the mirror 104. Before the etching is added, an underfill material such as resist or epoxy is used to protect the device manufacturing features.

Since the etchant will not attack it or the etch rate will be drastically slowed, an etchant containing primarily hydrogen peroxide ( _H2O2 ) with a small amount of ammonium hydroxide ( _NH4OH ) _can be used to rapidly etch away the substrate, leaving behind an etch-selective layer. After the substrate material is removed, the etch layer can be selectively removed by etching the layer in a hydrochloric acid (HCl) solvent without damaging the underlying material surface. If the substrate is removed, a low-resistance contact layer is typically also grown as the first layer to form an n-contact layer as part of the reflector 104. After the substrate and selective etch layer are removed, contacts can be formed on the surface 104 and circuits can also be formed using the common photolithography steps described above.

If the mesas are etched into the substrate, the process can separate each of the VCSEL elements and the shorting mesas from each other, which can benefit the VCSEL array by removing the coefficient of thermal expansion (CTE) associated with the substrate. CTE is a physical property of a material that is expressed as the amount of expansion per degree Celsius of the material. Many times, when multiple materials are used to build a device and the CTEs of these materials are not closely matched, stresses can be generated within the device with any temperature changes. For mesa devices etched into the substrate, these devices will expand at the same rate as the heat sink substrate, except over a much smaller area where contact is made with the heat sink substrate. In another embodiment, the etching process used to remove the substrate can use a plasma-based chemistry instead of the chemical wet etching techniques described above.

The above process flow is given by way of example only. It will be appreciated that the order of some of the steps described may be interchanged, such as the order of metal deposition or the order of depositing one or both of the n-metal or p-metal prior to the oxidation step. Additionally, the top mirror structure 108 may be replaced by a dielectric DBR stack, or the mirror stack may be replaced in whole or in part by etching a grating on the top surface of the mesa. The grating is typically defined by electron beam lithography instead of photolithography, and then dry-etched to a specific depth. This results in a higher efficiency light return and may be less expensive than the epitaxially grown mirror or portion of the mirror it replaces.

The above array has been fabricated and tested. A high-speed array of 980nm high-power bottom-emitting VCSELs has been fabricated. Devices with an active area diameter of 18μm have been created within a 24μm diameter mesa to form a circular VCSEL array with a 70μm device pitch. Figure 5 shows an example of an array formed in a similar manner and shape. Each of the individual VCSEL devices in the VCSEL array (represented by a solid circle in Figure 5) is electrically connected in parallel to form a single, high-power, high-speed light source. This parallel configuration for both the signal and ground paths reduces the series resistance and inductance of the flip-chip array. In another array fabricated and tested, the array used 28 evenly spaced active light-generating mesas. These were formed in a circular pattern, and the total area of the active area (contact pads) was less than ^0.2mm² . Eighteen shorting mesas (similar to the shorting mesas represented by the dashed circles in Figure 5 for the larger array device) were present in the ground ring surrounding the circular pattern of VCSEL devices.

The laser (and array) of the tested device is made of layers grown using molecular beam epitaxy (MBE) deposited on an n-type GaAs substrate. The light-generating portion of the active region 106 in the device of Figure 1 contains three indium gallium arsenide (In0.18Ga0.82As) quantum wells. This VCSEL design employs gain-mode shifting, which occurs when the wavelength design of the active region differs from the wavelength design of the reflectors at room temperature. As the device heats up, the emission wavelength from the active region shifts by a specific amount per degree Celsius. Gain-mode shifting accounts for this shift, so that when the reflectors are designed, they match the emission wavelength at elevated temperatures. The gain-mode shift design is well suited for high-temperature operation of the array at high bias currents. However, a smaller shift would enhance the modulation response at low temperatures, and the lower reflectivity bottom reflector 104 would increase the output power. Fabrication of the device using the aforementioned processing reduced the thermal resistance to 425°C/W for a single mesa, identical to the mesa used as a component in the array.

A Keithley 2400 source meter, silicon photodiodes, and optical attenuators were used to extract the DC characteristics of the exemplary array. Figure 6 shows the photocurrent (I)-voltage (L-I-V) characteristics of the exemplary array. The threshold current and voltage are 40 mA and 1.7 V, respectively. The dashed circles above the two lines (representing voltage vs. current and power vs. current) represent the edges of the graph, and each line represents such a cell can be correctly read. At a bias current of 500 mA and room temperature, the continuous wave (CW) output power of the array is greater than 120 mW.

To measure the modulation response of the tested array, the array was biased at a fixed current up to the maximum 500mA current rating of the Cascade Microtech high-frequency probe used for the measurement. The output light was coupled into a multimode bare core fiber with a diameter of 62.5μm. The output signal of a Discovery Semiconductor DS30S p-i-n photodiode was then amplified by a Miteq RF low-noise amplifier at different bias currents. Figure 7 shows the modulation response of the selected bias currents at 20°C. The array exhibited a 3dB frequency of 7.5GHz at a bias current of 500mA. The cutoff frequency of the high-current picosecond pulse laboratory bias tee used here shows accurate measurements below 1GHz. The bandwidth can be extended to higher frequencies by increasing the bias current. Frequency response measurements of a single 18μm active diameter laser, nominally the same as the laser constituting the test array, show that 3dB modulation frequencies of up to and above 10GHz can be achieved.

A bare multimode fiber was used to scan the entire array area and measure the frequency response of the array elements at different positions. Figure 8 shows that the frequency response of the elements of the array at different radii measured from the center of the array is almost independent of position. Each point in the array represents the frequency response of a single device. This result shows that both the laser performance and the current distribution are relatively uniform over the entire array. Therefore, the VCSEL array according to this embodiment can be expanded to hundreds or thousands of elements to achieve watt-level CW power with a modulation frequency approaching 10 GHz. This type of VCSEL array is expected to be used for medium-range, high-resolution laser radar (LIDAR) and free-space communications, as well as many other applications.

Figure 9 shows the pulse response of an exemplary array with a 50 ps pulse at FWHM (full width at half maximum), where FWHM indicates the width of a pulse at half its maximum power. The lines of the graph represent 40 ps intervals.

Effective heat dissipation through metallization and flip-chip bonding of the devices allowed CW operation of the tested array at room temperature. Consequently, the monolithic multi-beam VCSEL array of this type fabricated and tested can exhibit superior frequency response compared to other multi-beam semiconductor arrays, enabling the benefits of VCSEL beam quality, reliability, modulation flexibility, and cost efficiency to compete with edge-emitting semiconductor laser arrays for applications requiring high power.

As further illustrated in Figures 10 and 11 , rather than relying on a separate lens structure to collimate or focus the light emitted by the VCSEL array and the physical limitations of such a lens, microlenses can be fabricated using a number of different processes on the backside of the surface of substrate 102. One technique for forming such microlenses involves a photolithographic process in which a lens is defined using a photoresist, such as a cylinder or other shape, and then the photoresist is melted onto the substrate before transferring these lens shapes to the substrate via etching. The etch can be a chlorine (Cl)-based dry etch that is tuned for or near uniform etch selectivity between the substrate material and the photoresist, so that both materials are etched at similar or identical rates. The photolithographic steps used to create the lenses are performed using a backside wafer alignment system commonly used in the industry. This step is performed at the end of VCSEL wafer fabrication or earlier, but generally prior to the flip-chip process described above.

Other processes that can be used to form the lenses include grayscale lithography, in which a partially transmissive photomask can be used to create a relief profile in the photoresist. For example, the resulting lens can make it possible to gradually change the amount of light passing through different parts of the lens, such as passing more light around the edges and less light through the center, or passing less light around the edges and more light through the center. Various direct write lithographic processes can also be used to define the surface profile for polymer resist coating. A small amount of polymer material can also be deposited on the surface of the substrate above each laser device, which forms the lens when the polymer cures, such as the commonly deposited epoxy resin from inkjet. Instead of manufacturing the microlenses directly on the laser array substrate, the microlenses can be manufactured on a separate transparent substrate that is attached and aligned to the laser array. The substrate material used can be any material that transmits the laser wavelength. It can be formed by injection molding, casting, hot pressing or direct machining processes. The same strategy of offsetting the microlenses with the optical axis of each emitter can be used with a separate microlens array.

The profile of the microlenses fabricated as described herein can be simple, such as the hemispherical lenses shown in Figures 10 and 11, or can be more complex, such as an aspheric profile that can be used for extended depth of field applications. In the case of the hemispherical lens, the aspheric profile can also be controlled. Other complex optical devices that can be formed include: holographic optical devices, which direct a beam of light in various directions; or diffractive optical devices, which split the beam generated by a laser device into sub-beams, each of which may point in a slightly different direction. In addition to the shape of the optical device, the optical device can have various patterns formed on the surface, which can be used to form a highly astigmatic beam profile. Similarly, the optical device can be formed or patterned to change or control polarization.

As shown in FIG10 , which is drawn for demonstration purposes and not to scale, the aperture (diameter) and curvature of each resulting lens will focus the light emitted by each VCSEL device in a desired manner. To focus the light from each VCSEL device in the VCSEL array, each lens can be offset by a desired amount to focus the propagation of the parallel beam emitted by the VCSEL array into a selected pattern (e.g., onto a tightly focused spot) (as previously noted, the distance from the lens to the electron beam convergence point in FIG10 is not drawn to scale). FIG10 and FIG11 also illustrate how the lens 1100 (shown by a solid circle) for the centered VCSEL device 1102 (shown by a dashed circle) is centered on that VCSEL device 1102, but the lenses 1104 for VCSEL devices 1106 other than the centered VCSEL device 1102 are positioned at a specific offset distance from the centered VCSEL device 1102 so that light passing through these lenses 1104 is directed to a central point. FIG11 also illustrates how a set of lenses may be offset on a VCSEL array device.

The integrated microlenses described above enable VCSEL devices to be used in short-range free-space optical links without the need for external collimation or collection optics. This in turn enables extremely compact system designs that can use thin mobile electronic systems instead of near-field RF technologies. Utilizing the integrated microlenses described herein, a VCSEL array can produce a beam-converging array as described above. For short distances, up to a few millimeters, the converging beam can effectively fill a high-speed detector without the need for external collection optics. This solution is well suited for free-space optical communication between two devices that are in contact or nearly in contact (up to a few millimeters) and in which an infrared-transmitting housing or window is provided. Mechanical alignment can be facilitated by the kinematic characteristics of the devices. As further described below, further alignment can be performed by actively selecting subarrays (within the VCSEL array) with associated microlenses that direct light into adjacent areas. For example, when an optical link is established, the most efficiently coupled subarray of the transmitter can be used, while another subarray can be in a dormant state. The initial link can initially use all subarrays until feedback from the link is established, at which point some subarrays can be turned off, which can save power and extend the battery life of the mobile device.

In the design shown in Figure 10, the detector does not require collecting optics to focus the beam downward into a small spot, as this is provided by the microlenses. The spot size and distance of the beam converging from the lens surface can be determined by many factors, including the lens curvature, the degree of offset of the lens from the laser emitter axis, the refractive index of the lens material, and the modal properties of the laser. If the microlenses are axially aligned with the laser emitter (as shown in Figure 11), the beam can be focused, collimated, or more divergent, depending on the lens' radius of curvature and the distance from the source (defined by the substrate thickness). If the lenses are offset laterally from the axis, the beam will be directed at a certain angle to the axis. This is optically equivalent to an object at a given field height being imaged at an off-axis position on the image plane. Combined with the focusing effect of the lens, this gives the designer a variety of options in transforming the beam properties of each element of the array. Again, a simple example is to create a convergence of beams that overlap at a specific distance from the surface of the lens. If each lens in the array is offset from the axis by an amount that depends on the distance of the laser array elements from the axis, the beam can be focused to a single point (as shown in FIG10 ) or to a series of axial points arranged in a row. This method of creating a focused beam spot without a large focusing lens may have other applications beyond short-range free-space optical communications. It can be used to focus beams for material modification, inject light into optical fibers and waveguides, optical pumping of solid-state and fiber lasers, and medical treatment of specific volumes of tissue or locations on the skin or other body surfaces or membranes.

By moving the lens away from the center of the laser, as shown in FIG11 , the beam of each laser can be offset by a certain angle and focused or defocused as shown in FIG10 , depending on the microlens design and the spacing from the emitter. This allows the designer to use patterns of microlenses with different offsets to converge the beam. Control of the beam direction and focus enables the laser to be directed into a single spot ( FIG10 ) where a detector is provided to receive the signal, but other focusing arrangements are also possible, as shown in FIG12 , where the focused spot is a virtual focus (which can also serve as a virtual source for other optical systems) 1200 located behind an array 1202 of VCSEL devices 1203. In FIG12 , an additional external lens 1204 is also shown to indicate that the microlens array can be combined with other optical systems to achieve other effects, such as a collimated beam 1206 from the array 1202.

In order to uniformly drive the VCSEL array, the embodiments described herein may use a substrate (via flip-chip bonding) to make electrical contact with the laser array, and the elements of the array may be contacted to the substrate using solder balls or other conductive bonds, which provide mechanical support, electrical contact, and thermal conduction. This is shown in FIG13 , which depicts a laser array 1300 flip-chip bonded to a substrate 1302. As shown, lasers (not shown) are located on the bottom surface of the array 1300 and project their beams through the base layer of the laser array 1300 and through solder pads 1304. The lasers of the laser array 1300 are electrically bonded to electrical contacts (not shown) at the ends of an impedance-matched transmission line 1306 located below the laser array 1300. The transmission line 1306 provides transmission of high data rate optical signals to the laser array 1300. Microlenses 1308 are illustrated by individual circles on the solder pads 1304 of the substrate of the laser array 1300. The substrate 1302 may be formed from a number of possible materials including silicon, ceramic, printed circuit boards, and flat flexible cables.

The microlens structure described herein is referred to as a "lensless" free-space optical link when used in free-space optical applications because the combined laser array and microlens structure does not require additional typical large collimation and collection lenses. Lensless links also provide unique alignment techniques that may not be achieved using more traditional technologies. When laser devices such as the laser devices described herein are used in free-space optical links, the alignment of the transmitted laser beam with the receiving detector is a key parameter for whether the link between the two will be successful. This is a particularly big problem for mobile device applications. A fixed link without active scanning and calibration adjustments will be difficult to line up even over very short distances. Although alignment tolerances can be reduced by making the beam spot larger, this technique is limited by the increased power consumption caused. In addition, active mechanical scanning or tracking of the transceiver becomes too cumbersome and expensive to implement.

As shown in FIG14 , embodiments described herein may utilize a multi-element laser array 1400 and laser emitters (not shown, but shown located at the bottom of the array 1400) subdivided into multiple sub-arrays 1402 as shown within pads 1404 of the substrate. The use of sub-arrays 1402 adds an active alignment element to any mechanical alignment solution. In combination with microlenses 1406, each sub-array 1402 can be configured to illuminate a specific area of a volume defined by the combined mechanical tolerances. By applying current to each electrical contact or contact pad 1413 of transmission lines 1409, 1410, 1411, and/or 1412, the corresponding sub-array 1402 can be activated, and the resulting laser beam directed by the microlenses 1406 aligned with these array elements will define the output of the array. 14 and 15 , substrate 1408 may include separate transmission lines 1409, 1410, 1411, and 1412 connected to separate contact pads 1413 of each sub-array 1402. Alternatively, each laser may be connected to separate electrical contacts and transmission lines that would enable each individual laser to be driven separately.

When each different subarray has its own electrical contacts, each subarray can be similarly switched on through control circuitry associated with the array's driver electronics. The subarrays and individual VCSEL devices can also be controlled by a controller in addition to the driver, such that the driver is under the control of the controller. Using either method of control, any combination of subarrays can be switched on individually or in combination within the capabilities of the addressing and driver electronics. Array 1400 can be configured for linear scanning or 2D scanning capabilities, and as discussed further below, the array 1400 can direct its output to different detectors if desired. This allows for non-mechanical beam scanning capabilities. Scanning can be discrete point-to-point addressing by a beam, or it can look more like continuous scanning by a larger quantum array, where the microlenses are arranged so that small incremental changes in beam position occur by switching from one subarray to another. Although the subarray approach increases the number of array elements, the higher packing density and increased die size are moderately expensive for the increased system functionality. The size of the array and the number of subarrays can be primarily determined by the tolerances to be accommodated. Tolerances include not only the alignment of the two system housings relative to each other, but also internal variations in the position of the circuit boards within the assembled module. If the transmitter and receiver are located within different module assemblies, there may be tolerances around these components and any kinematic constraints within which the assembly of these components is made.

FIG16 is a cross-sectional view illustrating an embodiment of a VCSEL array 1600 having two sub-arrays or sub-groups 1602 and 1604. Sub-groups 1602 and 1604 include a number of corresponding microlenses 1606 that are offset in a specific manner to direct and converge their beams 1608 to form a circle or circle of confusion 1610 around a detector 1612. Circles 1610 are referred to as "circles of confusion" because they are formed behind the focal point 1614 of the offset sub-groups 1602 and 1604. Circle of confusion 1610 is the area where beam 1608 extends and is associated with where the power density of beam 1608 is sufficient to meet a particular bandwidth. As beam 1608 extends, the power density in circle of confusion 1610 decreases and reaches a point where it cannot support higher bandwidths. In embodiments, an optical element 1616, such as a holographic optical element, may be positioned somewhere in the path of the beam 1608 to homogenize the beam 1608, which serves to reduce speckle and more evenly spread the power in the beam 1608. In embodiments, each subgroup 1602 and 1604 may be formed so that the beam 1608 is specifically directed to a detector or group of detectors to form the basis of an optical router.

FIG17 illustrates an embodiment of a grouping of multiple subgroups 1700 of an array 1702, wherein subgroups 1700 are arranged around a central region, wherein outer subgroups 1700 have individual convergence points for their beams 1704, and wherein all outer points surround the central subgroup convergence point 1706. This embodiment illustrates a configuration in which an overlap with beam 1704 can be formed so that the beam covers a larger area 1706, which can be achieved using a single subgroup of VCSEL beams or VCSEL devices. The configuration shown in FIG17 can be utilized by sequentially turning on each subgroup until the returns from the receiver are concentrated, which then identifies which subgroup is best aligned with the detector. Once the best aligned subgroup is determined, all other subgroups can be powered down to save energy and reduce heat buildup. Many other schemes can similarly be employed to identify the subarray 1700 with the best alignment, such as turning on all subarrays 1700 and then turning off subarrays 1700 at a certain point. This embodiment can be used for low-power applications and to increase angular alignment tolerance.

Referring back to Figures 14 and 15 , the active alignment process for a free-space optical link at link startup may include initially powering up the electronics arrays 1402 sequentially and determining which sub-array 1402 is best able to maintain the link. Control of this process may be provided by a host system. If the latency of sequentially executing the link is too long, the arrays may be initially powered up together and then powered down sequentially while the link is operating to optimize link efficiency.

If there may be displacement in alignment while the link is connected, the control system can periodically re-optimize the link. Given that the sub-arrays 1402 must operate at multiples of the threshold current, it may not be optimal to divide the power between the sub-arrays, so sub-volumes of the tolerance box may need to be carefully divided between the sub-arrays 1402.

The same strategy can be used to optimize the power of the transmitter components of a link independently of the alignment strategy. A subarray used to address a given area within the tolerance zone can have individually contacted elements within the tolerance box, where the elements can be powered on or off to adjust the transmit power. This can be advantageous for the control electronics because the selection of the subarray is a digital switching function rather than analog control of the drive current to the laser. This has some advantages in simplifying the driver electronics. It also enables the array to be driven at an optimal current level to maintain high data rates and modulation efficiency. If the current is too close to the threshold, the VCSEL will be difficult to modulate at high speed.

When used in free space optical communications, a driver for a laser array, such as driver 1804 of FIG. 18 , can include eye safety circuitry such as that described in co-pending application Ser. No. 13/868,034 , the contents of which are incorporated herein by reference in their entirety and which this application is a continuation-in-part of. As described therein, in embodiments, an addressable laser array having multiple light sources (e.g., individual laser devices or subarrays of such devices) can be used in conjunction with circuitry such that different combinations of light sources can be energized without exceeding eye safety limits and without requiring a monitoring or feedback loop to control the distance of an observer. The operation of multiple light sources can be in close proximity, which is eye safe, regardless of how many or which light sources are energized and regardless of the position of the observer. As described therein, a laser array having multiple light sources can also remain eye safe in the presence of a single point electrical fault (e.g., a short circuit) in the driver circuitry.

In addition to short-range free-space optical communication applications, the scanning capability of the laser array described herein can be used to track a receiver that is moving or vibrating relative to a transmitter, where feedback from the receiver can be sent through an optical link or through a separate channel, which may or may not be optical. This can be used to address individual elements of a detector array or fiber array that function as a receiver for a detector or other function coupled to the other end of the fiber.

Transceiver implementations can be assembled as hybrid circuits, where the transmitter and receiver elements are bonded to a substrate using standard hybrid packaging techniques. Figure 18 shows an embodiment of a transceiver 1800 built on circuit 1802. The components shown can be bonded to a surface using chip-on-board technology or traditional hybrid assembly methods. Figure 18 shows a laser array 1808 on a separate substrate 1806. The laser array can also be flip-chip bonded directly to the surface of a printed circuit. The small laser array can be configured to direct the slow convergence of the light beams by offsetting the microlenses so that the beams overlap at a spot a few millimeters away from the transceiver 1800. This is a sufficient distance to link two mobile devices that are touched at an edge or surface. Certain electronic functions (such as the laser driver 1804) can also be integrated into the silicon substrate 1806. Figure 18 shows a single transceiver with a transmitter 1808 and a receiver 1810. Two transceivers 1800, facing each other with their ends facing each other so that the laser array transmitter 1808 faces the detector 1810, facilitate a complete bidirectional link. The transceivers can bridge the short distance between them through infrared-transmissive plastic windows that are in contact or close proximity. Various methods can be used to ensure that the surfaces are associated with some misalignment tolerance limited by kinematic features or other constraints.

As previously mentioned, one or more laser arrays can be used in digital switch embodiments that are configured to direct light beams from the array/subarray to a detector with or without subarrays and with or without microlenses. As shown in FIG19 , a linear array of subarrays of laser devices 1902 produces light beams 1904 from the subarrays that are directed by external microlenses 1906 (which are shown as cylindrical lenses, but can also be any number of other optical elements, such as spherical lenses). For purposes of illustrating the embodiment, the angles of the light beams are shown as angles that may not be realistic, given the physical arrangement of the laser devices 1902 and the optical elements 1906. The same array 1900 and macro lens 1906 (which again can be a different optical element) are depicted in Figure 20 to illustrate how the linear array 1900 can be used in a switching application, where selective operation of the laser device 1902 and the arrangement of the optical device/macro lens 1906 are used to direct the light beam 1904 to the detector 1908 for a fiber optic cable 1910 arranged in a mounting structure 1912.

21 shows another embodiment in which a larger nonlinear laser array 2100 (which can have various configurations or laser devices or sub-arrays) and an optical device or micro-lens 2102 (driven by a driver device and/or controller not shown) are depicted as operating as a digital switching device to direct fiber optic cables 2106 of a structure 2108 for use with a set of detectors 2104. Although macro-lenses are shown in FIG19-21 to direct the beams to a position, other optical elements (e.g., offset micro-lenses) can be used to achieve the same effect, and micro-lenses can also be used in combination with optical elements.

Figure 22 shows another embodiment in which three or more racks 2200 of computing or communication equipment are connected to a digital switch laser array 2202 (a transceiver type configuration) that transmits data to and receives data from the equipment. Within each rack are multiple microlenses on various components equipped with laser arrays that direct data-carrying beams to various detectors that collect the data and also transmit the data out of the rack 2200, which similarly receive the data sent to the rack 2200.

Another embodiment of a transceiver is shown in Figures 23 to 25. Figure 23 shows a configuration in which each switch element 2302 of a transceiver switch 2300 is composed of four detectors 2304 and four transmitters 2306. As shown in Figure 24, a transceiver switch 2402 composed of four switch elements 2302 can be configured to communicate with an opposing transceiver switch 2404, which is also composed of four transceiver switch elements 2302. Each subset of transmitters' light beams 2406 are directed toward specific detectors of the other subset of transceivers. Figure 25 shows one of the multiple configurations of this optical switch, in this case a 12×12 optical switch 2500.

A simple switch can also be formed consisting of 12 transmitters directed towards 12 groups of transceivers, each with its own individual detector and transmitter directed back towards one of the 12 detectors on a single router side of the switch, allowing all 12 transceivers to transmit back to the routing side of the switch.

There are many other possible configurations for directing beams to detectors, and vice versa, thereby enabling communication between boards, circuits, processors, switches, and the like. There are also other possible configurations of arrayed VCSEL devices and subgroups or subarrays that can be used for purposes other than free-space communication. Furthermore, by utilizing microlens structures, not all individual VCSEL devices or subarrays of a VCSEL array need to be focused onto the same focal spot. For example, as shown in FIG26 , a linear array 2600 of VCSEL devices can be focused onto more than one focal spot by utilizing microlenses 2602. As shown in FIG26 , groups of devices can be focused onto different common focal spots, such as two outer devices 2604 focused onto spot 2606, followed by two devices 2608 focused onto spot 2610, and three inner devices 2612 focused onto spot 2614. The focused spots 2606, 2610, and 2614 will effectively form a line in space, which can be used to use the laser device as a cutting tool, such as a surgical scalpel. The VCSEL device/subarray and microlens structure can also be shaped and focused to create shapes other than lines, such as circular focused spots and other geometric patterns for other purposes. For example, the array 2600 of FIG. 26 can be used for medical devices as indicated, but can also be used to mark materials using known techniques (e.g., XY plotter-type controllers) to mark metal, glass, wood, etc.

Although the present invention has been illustrated and described herein in terms of several alternatives, it should be understood that the technology described herein may have many other uses and applications. Therefore, the present invention should not be limited to the specific description, embodiments, and various figures contained in this specification, which merely illustrate preferred embodiments, alternatives, and applications of the principles of the present invention.

Claims (63)

1. An optical device, comprising: A monolithic laser array comprising multiple vertical cavity surface emitting laser (VCSEL) devices and multiple raised inactive regions on electrical contacts, wherein the multiple VCSEL devices are arranged in a pattern on a substrate of the laser array, and each of the multiple VCSEL devices generates an axial beam. A plurality of refractive microlenses are formed within the substrate, each of which is positioned above a corresponding VCSEL device. Each refractive microlens directs a beam emitted by the corresponding VCSEL device toward a target or for scanning, without requiring external optical elements of the laser array to collimate or focus the light illuminating the target. The refractive microlenses are offset from the axis of the corresponding VCSEL device by a distance necessary for the beam to converge or diverge toward the target or for scanning, and the distance is based on a desired angular deviation of the beam. A driver circuit for powering the laser array, wherein the driver circuit is operable to modulate the VCSEL for data communication, wherein the pattern comprises two or more subarrays of VCSEL devices, wherein each of the two or more subarrays is independently powered and modulated by the driver circuit for operation, and wherein the refractive microlenses of the respective VCSEL devices of each subarray are configured as a group for directing the subarray beam from each subarray to the target or for scanning. 2. The optical device according to claim 1, wherein the optical device is a transmitter for a free-space optical data link. 3. The optical device according to claim 1, wherein the two or more subarrays are formed on the substrate. 4. The optical device of claim 3 further includes a substrate comprising two or more electrical contacts, each electrical contact being coupled to a subarray and connecting the subarray to the driver circuit via an impedance-matched transmission line embedded in the substrate for providing high data rate optical signal transmission from the driver circuit to the subarray. 5. The optical device of claim 1, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, wherein each subarray beam is directed to a different region of the receiver, and wherein operation of the two or more subarrays by the driver circuitry causes each subarray beam to actively scan the receiver to identify the subarray or combination of subarrays that provides optimal link performance at the receiver. 6. The optical device of claim 5, wherein each subarray or combination of subarrays is operated sequentially by the driver circuit. 7. The optical device of claim 1, wherein each subarray beam is directed to a different portion of a linear region in space, and wherein the operation of the two or more subarrays by the driver circuit causes each subarray beam to scan the linear region of space at discrete intervals. 8. The optical device of claim 1, wherein each subarray beam is directed to a different portion of a two-dimensional pattern in space, and wherein the operation of the two or more subarrays by the driver circuit causes each subarray beam to scan the two-dimensional pattern in space at discrete intervals. 9. The optical device of claim 1, wherein one or more of the plurality of refractive microlenses have a different radius of curvature than the other refractive microlenses in the plurality of refractive microlenses, wherein each subarray beam is directed to a different portion of a three-dimensional volume in space, and wherein the operation of the two or more subarrays by the driver circuit causes each subarray beam to scan the three-dimensional volume in space at discrete intervals. 10. The optical device of claim 1, wherein each subarray beam is directed to a common point, and wherein the operation performed by the driver circuit on the two or more subarrays produces a combination of subarray beams with varying intensity at the common point. 11. The optical device of claim 1, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, and wherein the intensity of the combined subarray beams is varied as needed to maintain a high-quality link with the receiver. 12. The optical device of claim 1, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, wherein each subarray beam is oriented in a common direction, but each subarray beam is focused at a different distance to maintain a high-quality link with the receiver. 13. The optical device of claim 1, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, and wherein operation of the two or more subarrays in different combinations by the driver circuit enables a high-quality link to be maintained during movement of the transmitter or receiver. 14. The optical device of claim 1, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, wherein the transmitter faces a second receiver, wherein the second transmitter faces the receiver, and wherein the transmitter and the receiver are positioned spaced apart at a fixed distance and operate as transceivers. 15. The optical device of claim 14, further comprising a low-bandwidth link between the transmitter and the receiver, the low-bandwidth link providing feedback on the performance of the optical link between the transmitter and the second receiver and the optical link between the second transmitter and the receiver. 16. The optical device of claim 15, wherein the driver circuitry for the transmitter operates one or more subarrays individually or in combination based on the performance and to improve the performance. 17. The optical device of claim 16, wherein the driver circuitry for the transmitter operates one or more subarrays individually or in combination based on the fixed distance and the geometry between the transmitter and the second receiver and the geometry between the second transmitter and the receiver. 18. The optical device of claim 17, wherein the transceiver is coupled to another transceiver to form an optical switch or optical router. 19. The optical device of claim 1, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, wherein one or more of the plurality of refractive microlenses include the following kinematic features: transmitting a beam of infrared wavelength and aligning the transmitter with the receiver. 20. The optical device of claim 1, wherein one or more of the plurality of refractive microlenses are formed or patterned to create a profile. 21. The optical device of claim 20, wherein the profile is hemispherical. 22. The optical device of claim 20, wherein the profile is aspherical. 23. The optical device of claim 20, wherein the contour is holographic. 24. The optical device of claim 20, wherein the profile is diffractive. 25. The optical device of claim 20, wherein the profile is astigmatic. 26. The optical device of claim 20, wherein the profile is polarization-controlled optics. 27. The optical device of claim 1, wherein the focal point of the beam emitted by the respective VCSEL device is a virtual focal point located behind the laser array. 28. The optical device of claim 27, wherein the virtual focal point serves as a source for another optical system. 29. The optical device according to claim 1, further comprising: A current source, configured to supply a total current to the plurality of VCSEL devices; and An electronic circuit comprising one or more switches for distributing a total current to zero or more of the plurality of VCSEL devices, the electronic circuit being configured to: generate eye-safe output power from a single VCSEL device when the total current is distributed only to a single VCSEL device in the light source; and generate eye-safe combined optical power from two or more VCSEL devices when the total current is distributed to two or more VCSEL devices. 30. The optical device of claim 1, wherein the target comprises two or more targets, wherein a light beam emitted by a first group of one or more VCSEL devices is focused on a first target, and a light beam emitted by a second group of at least one or more VCSEL devices is focused on a second target. 31. The optical device according to claim 30, wherein the first target and the second target form a line. 32. The optical device of claim 30, wherein the two or more targets form a geometric pattern. 33. An optical device, comprising: A monolithic laser array comprising multiple vertical cavity surface-emitting laser (VCSEL) devices and multiple raised inactive regions on electrical contacts, wherein the multiple VCSEL devices are arranged in a pattern on a first substrate of the laser array, and each of the multiple VCSEL devices generates an axial beam. A plurality of refractive microlenses are formed within a second substrate bonded to the first substrate. Each of the plurality of refractive microlenses is positioned above a corresponding VCSEL device. Each refractive microlens directs a beam emitted by the corresponding VCSEL device toward a target or for scanning, without requiring external optical elements of the laser array to collimate or focus the light illuminating the target. Each refractive microlens is offset from the axis of the corresponding VCSEL device by the distance necessary for the beam to converge or diverge toward the target or for scanning, and the distance is based on a desired angular deviation of the beam. A driver circuit for powering the laser array, wherein the driver circuit is operable to modulate the VCSEL for data communication, wherein the pattern comprises two or more subarrays of VCSEL devices, wherein each of the two or more subarrays is independently powered and modulated by the driver circuit for operation, and wherein the refractive microlenses of the respective VCSEL devices of each subarray are configured as a group for directing the subarray beam from each subarray to the target or for scanning. 34. The optical device of claim 33, wherein the optical device is a transmitter for a free-space optical data link. 35. The optical device of claim 33, further comprising a substrate including two or more electrical contacts, each electrical contact being coupled to a subarray and connecting the subarray to the driver circuit via an impedance-matched transmission line embedded in the substrate for providing transmission of a high data rate optical signal from the driver circuit to the subarray. 36. The optical device of claim 33, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, wherein each subarray beam is directed to a different region of the receiver, and wherein operation of the two or more subarrays by the driver circuitry causes each subarray beam to actively scan the receiver to identify the subarray or combination of subarrays that provides optimal link performance at the receiver. 37. The optical device of claim 36, wherein each subarray or combination of subarrays is operated sequentially by the driver circuit. 38. The optical device of claim 33, wherein each subarray beam is directed to a different portion of a linear region in space, and wherein the operation of the two or more subarrays by the driver circuit causes each subarray beam to scan the linear region of space at discrete intervals. 39. The optical device of claim 33, wherein each subarray beam is directed to a different portion of a two-dimensional pattern in space, and wherein the operation of the two or more subarrays by the driver circuit causes each subarray beam to scan the two-dimensional pattern in space at discrete intervals. 40. The optical device of claim 33, wherein one or more of the plurality of refractive microlenses have a different radius of curvature than the other refractive microlenses in the plurality of refractive microlenses, wherein each subarray beam is directed to a different portion of a three-dimensional volume in space, and wherein the operation of the two or more subarrays by the driver circuit causes each subarray beam to scan the three-dimensional volume in space at discrete intervals. 41. The optical device of claim 33, wherein each subarray beam is directed to a common point, and wherein the operation performed by the driver circuit on the two or more subarrays produces a combination of subarray beams with varying intensity at the common point. 42. The optical device of claim 33, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, and wherein the intensity of the combined subarray beam is varied as needed to maintain a high-quality link with the receiver. 43. The optical device of claim 33, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, wherein each subarray beam is oriented in a common direction, but each subarray beam is focused at a different distance to maintain a high-quality link with the receiver. 44. The optical device of claim 33, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, and wherein operation of the two or more subarrays in different combinations by the driver circuit enables a high-quality link to be maintained during movement of the transmitter or receiver. 45. The optical device of claim 33, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, wherein the transmitter faces a second receiver, wherein the second transmitter faces the receiver, and wherein the transmitter and the receiver are positioned spaced apart at a fixed distance and operate as transceivers. 46. The optical device of claim 45, further comprising a low-bandwidth link between the transmitter and the receiver, the low-bandwidth link providing feedback on the performance of the optical link between the transmitter and the second receiver and the optical link between the second transmitter and the receiver. 47. The optical device of claim 46, wherein the driver circuitry for the transmitter operates one or more subarrays individually or in combination based on the performance and to improve the performance. 48. The optical device of claim 47, wherein the driver circuitry for the transmitter operates one or more subarrays individually or in combination based on the fixed distance and the geometry between the transmitter and the second receiver and the geometry between the second transmitter and the receiver. 49. The optical device of claim 45, wherein the transceiver is coupled to another transceiver to form an optical switch or optical router. 50. The optical device of claim 33, wherein the optical device is a transmitter for a free-space optical data link, the free-space optical data link including a receiver, wherein one or more of the plurality of refractive microlenses include the following kinematic features: transmitting a beam of infrared wavelength and aligning the transmitter with the receiver. 51. The optical device of claim 33, wherein one or more of the plurality of refractive microlenses are formed or patterned to create a profile. 52. The optical device according to claim 51, wherein the profile is hemispherical. 53. The optical device according to claim 51, wherein the profile is aspherical. 54. The optical device of claim 51, wherein the contour is holographic. 55. The optical device of claim 51, wherein the profile is diffractive. 56. The optical device of claim 51, wherein the profile is astigmatic. 57. The optical device of claim 51, wherein the profile is polarization-controlled optics. 58. The optical device of claim 33, wherein the focal point of the beam emitted by the respective VCSEL device is a virtual focal point located behind the laser array. 59. The optical device of claim 58, wherein the virtual focal point serves as a source for another optical system. 60. The optical device according to claim 33, further comprising: A current source, configured to supply a total current to the plurality of VCSEL devices; and An electronic circuit comprising one or more switches for distributing a total current to zero or more of the plurality of VCSEL devices, the electronic circuit being configured to: generate eye-safe output power from a single VCSEL device when the total current is distributed only to a single VCSEL device in the light source; and generate eye-safe combined optical power from two or more VCSEL devices when the total current is distributed to two or more VCSEL devices. 61. The optical device of claim 33, wherein the target comprises two or more targets, wherein a light beam emitted by a first group of one or more VCSEL devices is focused on a first target, and a light beam emitted by a second group of at least one or more VCSEL devices is focused on a second target. 62. The optical device according to claim 61, wherein the first target and the second target form a line. 63. The optical device of claim 62, wherein the two or more targets form a geometric pattern.