HK1227171B - A carrier, a method for manufacturing the same and a method for manufacturing a coreless package substrate via the carrier - Google Patents

Description

Carrier, method for manufacturing the same, and method for manufacturing coreless package substrate using the carrier

Technical Field

The present invention relates to the field of packaging technology, and more particularly to a carrier, a method for manufacturing the same, and a method for manufacturing a coreless packaging substrate using the carrier. The coreless packaging substrate can be used in various electronic products to meet the development requirements of multifunctionality, miniaturization, and portability.

Background Art

In addition to supporting the IC chip and routing internal circuits to conduct signals between the chip and the PCB, the package substrate, or IC carrier, also features additional functions such as protection circuitry, dedicated wiring, heat dissipation design, and component modularization standards. As wireless communications, automotive electronics, and other consumer electronics products evolve toward multifunctionality, lightweight design, high frequency, high speed, low power consumption, and high reliability, the lines on the rigid package substrates that support and conduct the chips are becoming increasingly thinner, evolving from the conventional L/S ratio of 50/50μm to 25/25μm, 15/15μm, and even smaller, 8/8μm.

To meet the demand for fine circuitry, three main types of substrates (or core boards) are currently used in rigid packaging substrates. The first type primarily utilizes copper foil (12μm thick to prevent wrinkling during lamination) with a surface roughness Rz ≥ 3μm, which is then pressed together. Manufacturers then apply a "copper thinning + subtractive etching process" to the substrate to create the circuitry. This substrate offers low manufacturing costs and high circuit peel strength, but requires thinning the copper foil by 12μm, making copper thickness uniformity difficult to control and resulting in a low yield rate for the resulting circuits. This substrate can only accommodate designs with L/S ratios greater than 35/35μm. Furthermore, additional etching is required for copper buds greater than 3μm, resulting in a large etching volume and the need for extensive CAM circuit compensation, ultimately impacting circuit fabrication capabilities. The second type primarily utilizes thin copper foil (2μm thick) with an Rz value of approximately 2μm, which is then pressed together. Manufacturers utilize a modified semi-additive process (MSAP) to create the circuitry. While L/S ratios can be increased to ≥ 25/25μm, the high cost of 2μm thin copper foil limits its widespread market adoption. The third method mainly addresses circuit designs with L/S < 25/25μm. It mainly uses low-roughness thin copper foil (Rz value ≤ 1μm) or chemical copper deposition as the base copper, and then presses it into a base material through a primer coating or ABF resin to increase the circuit peel strength. The circuit is then processed using the PSAP or SAP semi-additive method. This process requires more expensive low-roughness thin copper foil and primer and ABF materials, which has extremely high manufacturing costs. In addition, due to the low Rz value of the base copper, circuit peeling and other process problems (such as residual glue on the edge of the outer shape) are prone to occur. In short, in order to cope with circuit designs with different L/S ranges of rigid packaging substrates, the industry currently uses different copper foils for lamination to manufacture the base material. As a result, downstream packaging substrate manufacturers must select different processing processes for different substrates and evaluate their stability, etc., making it difficult to find the optimal base material between cost and product qualification rate. In particular, for products at the L/S critical point, the stability of their qualification rate has always been a headache.

Compared to traditional build-up core substrates, a new packaging substrate manufacturing process has recently emerged: coreless board technology combined with embedded circuitry (ETS) and MIS processes. By embedding circuitry within prepreg (PP) or molding compound, this process eliminates undercutting and delamination by etching only the thin copper layer above the circuitry. No additional materials such as primers or ABF are required. This process offers advantages such as low cost, thinner and lighter weight, high electrical performance, and improved routing flexibility. It can easily produce substrates with L/S ratios of 20/20μm or even 10/10μm, demonstrating promising market application prospects. However, due to the excessive thinness of coreless boards, the manufacturing process exceeds the throughput capacity of many process steps, leading to board jams and resulting in board damage and scrap. To improve the yield and productivity of this process, substrate manufacturers typically employ a separation process. This involves using a carrier to support and increase the board thickness, then laminating the coreless circuitry above and below it. The coreless circuitry is then separated from the carrier to produce the packaging substrate. In other words, the coreless board technology combined with embedded circuitry (ETS) and MIS processes requires a key material—a carrier—for both support and separation. Currently, there are two main types of carriers in use. One utilizes a detachable thin copper foil pressed together to form a carrier, which is used in the manufacture of coreless packaging substrates. The coreless board is separated from the carrier before the chip is packaged, resulting in high production efficiency. However, the use of thin copper foil and a pressing process makes this carrier complex and costly to manufacture. Furthermore, it cannot be reused after the coreless board is manufactured, resulting in significant waste. The other type uses a thin iron alloy plated on a roll-to-roll basis as a carrier for use in the MIS process. During the coreless board manufacturing process, grinding and windowing of the thin iron alloy are required. While this carrier has lower material and production costs, due to process characteristics and proprietary grinding equipment, it suffers from long production processes and low efficiency, hindering widespread adoption. Furthermore, the thin iron alloy after windowing cannot be reused, resulting in significant waste. Therefore, a reusable, low-cost carrier and its manufacturing method are needed to meet the growing demand for high-end flip-chip products such as coreless ETS in the packaging substrate field.

Furthermore, in the prior art, when manufacturing coreless package substrates, copper foil is typically first bonded to a substrate using a high-temperature lamination method. Then, holes are drilled in the substrate and the copper foil on the substrate surface is partially removed through methods such as pattern plating or full-board plating to obtain the final circuit. During laser drilling, the copper foil at the location where the hole is to be drilled must be etched and thinned before drilling the hole into the substrate. When metallizing the hole, a conductive seed layer is first formed on the hole wall using processes such as electroless copper deposition (PTH) or black hole or black shadow, and then a metal conductor layer is formed on the hole wall through electroplating to improve conductivity. This process requires the use of pre-cut copper foil and multiple etching steps, making it difficult to meet the requirements of fine circuits and generating large amounts of wastewater containing metal ions, which is harmful to the environment. Furthermore, the conductive seed layer and electroplated copper layer on the hole wall have weak bonding with the substrate and easily separate from the hole wall, resulting in poor conductivity of the metallized hole. Therefore, a method for manufacturing coreless package substrates is needed that is simple, easy to control, and can ensure the conductive performance of the vias.

Summary of the Invention

The present invention is made in view of the above situation, and its purpose is to provide a reusable, low-cost carrier and its manufacturing method, as well as a method for using the carrier to manufacture a coreless packaging substrate with a simple process, easy to control and capable of ensuring the conductive performance of the via.

The first technical solution of the present invention is a method for manufacturing a carrier for a coreless packaging substrate, which includes the following steps: forming a curing resin (S1); and forming an easily peelable conductor layer on the surface of the curing resin, wherein the bonding force between the conductor layer and the curing resin is 0.01-0.05N/mm (S2).

In the carrier thus prepared, the bonding force between the conductive layer and the cured resin is as low as 0.01-0.05 N/mm. Therefore, when using this carrier to manufacture a coreless package substrate, the package substrate and the conductive layer can be easily peeled from the cured resin. The peeled cured resin can be further processed in step S2 and easily reused in the carrier preparation process.

A second technical solution of the present invention is that, in the first solution, step S1 includes laminating the low-roughness surface of the metal sheet with the uncured resin, and removing the metal sheet after lamination and thermal curing to obtain the cured resin.

The third technical solution of the present invention is that, in the second solution, the resin includes one or more of bismaleimide triazine resin, epoxy resin, cyanate resin, polyphenylene ether resin and modified resins thereof.

The fourth technical solution of the present invention is that in the first solution, step S2 includes first forming a conductive seed crystal layer on the surface of the cured resin, and then forming a conductor thickening layer on the conductive seed crystal layer, and the conductive seed crystal layer and the conductor thickening layer constitute a conductor layer.

The fifth technical solution of the present invention is that, in the fourth solution, the conductive seed layer is formed by the following methods: the conductive material is injected into the surface of the cured resin by ion implantation to form an ion implantation layer as the conductive seed layer; or, the conductive material is deposited on the surface of the cured resin by plasma deposition to form a plasma deposition layer as the conductive seed layer; or, the conductive material is first injected into the surface of the cured resin by ion implantation to form an ion implantation layer, and then a plasma deposition layer is formed above the ion implantation layer by plasma deposition, and the ion implantation layer and the plasma deposition layer together constitute a conductive seed layer.

The sixth technical solution of the present invention is that, in the fifth solution, the ion implantation layer is a doping structure formed by a conductive material and a cured resin, the outer surface of which is flush with the surface of the cured resin, and the inner surface is located at a depth of 1-100 nm below the surface of the cured resin.

The seventh technical solution of the present invention is that in the fifth solution, the plasma deposition layer includes a metal or metal oxide deposition layer with a thickness of 0-500nm, and a Cu deposition layer located above the metal or metal oxide deposition layer and with a thickness of 0-500nm, wherein the metal deposition layer contains Ni or Ni-Cu alloy, and the metal oxide deposition layer contains NiO.

An eighth technical solution of the present invention is that, in the fourth solution, step S2 includes forming a conductor thickening layer above the conductive seed crystal layer by one or more of electroplating, chemical plating, vacuum evaporation plating, and sputtering.

The ninth technical solution of the present invention is a carrier for a coreless packaging substrate, which includes: a curing resin; and a conductor layer that is easily peeled off on the surface of the curing resin, and the bonding force between the conductor layer and the curing resin is 0.01-0.05N/mm.

In this carrier, the bonding force between the conductor layer and the cured resin is as low as 0.01-0.05 N/mm. Therefore, when using this carrier to manufacture coreless package substrates, the package substrate and the conductor layer can be easily peeled from the cured resin. The peeled cured resin can be further formed into a conductor layer and easily reused in the carrier.

The tenth technical solution of the present invention is that, in the ninth solution, the curing resin includes one or more of bismaleimide triazine resin, epoxy resin, cyanate resin, polyphenylene ether resin and modified resins thereof, and the surface roughness of the curing resin is less than 2.5 μm.

An eleventh technical solution of the present invention is that, in the ninth solution, the conductor layer includes a conductive seed crystal layer and a conductor thickening layer located above the conductive seed crystal layer.

The twelfth technical solution of the present invention is that in the eleventh solution, the conductive seed crystal layer includes: an ion implantation layer whose outer surface is flush with the surface of the cured resin and whose inner surface is located inside the cured resin; or, a plasma deposition layer located above the surface of the cured resin; or, an ion implantation layer whose outer surface is flush with the surface of the cured resin and whose inner surface is located inside the cured resin, and a plasma deposition layer located above the ion implantation layer.

The thirteenth technical solution of the present invention is that, in the twelfth solution, the ion implantation layer is a doping structure formed by a conductive material and a cured resin, and its inner surface is located at a depth of 1-100 nm below the surface of the cured resin.

The fourteenth technical solution of the present invention is that in the twelfth solution, the plasma deposition layer includes a metal or metal oxide deposition layer with a thickness of 0-500 nm, and a Cu deposition layer located above the metal or metal oxide deposition layer and with a thickness of 0-500 nm, wherein the metal deposition layer contains Ni or Ni-Cu alloy, and the metal oxide deposition layer contains NiO.

A fifteenth technical solution of the present invention is that, in the eleventh solution, the conductor thickening layer includes a Cu layer with a thickness of 0-5 μm.

The sixteenth technical solution of the present invention is a method for manufacturing a coreless packaging substrate, which includes the following steps: forming a first circuit structure on the surface of a carrier (S11); laminating a first bonding layer above the first circuit structure (S12); drilling a hole in the first bonding layer (S13); forming a conductive seed layer on the surface of the first bonding layer and the wall of the hole by the following method, that is, injecting a conductive material into the surface of the first bonding layer and below the wall of the hole by ion implantation to form an ion implantation layer as a conductive seed layer, or depositing a conductive material onto the surface of the first bonding layer and below the wall of the hole by plasma deposition to form a plasma deposition layer as a conductive seed layer, or first injecting a conductive material into the surface of the first bonding layer and below the wall of the hole by ion implantation to form an ion implantation layer, and then forming a plasma deposition layer above the ion implantation layer by plasma deposition, the ion implantation layer and the plasma deposition layer together constitute a conductive seed layer (S14); forming a second circuit structure on the surface of the first bonding layer (S15); and, peeling off the carrier to obtain a packaging substrate (S16).

By forming a conductive seed layer on the surface of the bonding layer and the wall surface of the hole, the metallization of the bonding layer surface and the metallization of the hole wall can be carried out simultaneously. Therefore, the metallized via and the bonding layer surface with the conductive seed layer can be directly produced through a one-step molding process, without the need to first coat the substrate with a thick metal foil and then etch and thin the metal foil before drilling the hole in the substrate, as in the prior art. Furthermore, there is no need to form a conductive layer on the hole wall through chemical copper deposition or black hole, black shadow, or other processes to obtain the metallized via. Compared with the prior art, the process flow of the above method can be significantly shortened, and the use of etching solution can be reduced, which is beneficial to environmental protection. In addition, by adjusting various process parameters, such as the voltage, current, and plating solution concentration during electroplating, the above method can easily produce an extremely thin circuit structure layer, which can easily meet the requirements of fine circuits with narrow line widths and line spacings. In addition, when the ion implantation layer is formed, a high bonding force can be generated between the hole wall and the conductive seed layer, so that the metal layer of the hole wall will not easily fall off or be scratched during various subsequent processing or application processes. Therefore, it is beneficial to improve the conductivity of the via hole and facilitate the preparation of a packaging substrate with good conductivity.

The seventeenth technical solution of the present invention is that, in the sixteenth solution, steps S12 to S15 are repeated to form a multi-layer packaging substrate with first, second, third, ... Nth circuit structures.

The eighteenth technical solution of the present invention is that in the seventeenth solution, when forming the intermediate circuit structure of the multi-layer packaging substrate, that is, one or more of the second, third,... N-1th circuit structures, the copper foil is first laminated onto the bonding layer, holes are drilled in the copper foil and the bonding layer, and then the copper foil is etched to obtain the intermediate circuit structure.

The nineteenth technical solution of the present invention is that in the sixteenth solution, the carrier is a carrier manufactured by any method of the first to eighth solutions, or any carrier described in the ninth to fifteenth solutions.

The twentieth technical solution of the present invention is that, in the sixteenth solution, step S11 includes forming a first circuit structure on both sides of the carrier, and step S16 includes peeling the carrier from both sides to obtain two separate packaging substrates.

The twenty-first technical solution of the present invention is that in the sixteenth solution, in steps S11 and S15, the first and second circuit structures are formed by full-board electroplating or graphic electroplating methods.

The twenty-second technical solution of the present invention is that in the sixteenth solution, the ion implantation layer is a doping structure formed by a conductive material and a first bonding layer, and its outer surface is flush with the surface of the first bonding layer or the wall of the hole, and the inner surface is located at a depth of 1-500nm below the surface of the first bonding layer or the wall of the hole.

The twenty-third technical solution of the present invention is that in the sixteenth solution, step S14 also includes forming a conductor thickening layer above the conductive seed crystal layer by one or more of electroplating, chemical plating, vacuum evaporation plating, and sputtering, and the conductor thickening layer contains Cu.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the present invention will be more readily understood by those skilled in the art after reading the following detailed description with reference to the accompanying drawings. For the sake of clarity, the drawings are not necessarily drawn to scale, and some parts may be exaggerated to show specific details. In all drawings, the same reference numerals represent the same or similar parts, wherein:

1 is a flow chart showing a method for manufacturing a carrier for a coreless package substrate according to the present invention;

Figures 2(a)-(d) are schematic cross-sectional views of various carriers prepared by the method shown in Figure 1;

3 is a flow chart showing a method for manufacturing a coreless package substrate according to the present invention;

4( a )-( f ) are schematic cross-sectional views showing the structures corresponding to the steps of the method shown in FIG. 3 when producing a double-layer packaging substrate; and

5( a )-( j ) are schematic cross-sectional views showing the structures corresponding to the steps of the method shown in FIG. 3 when producing a three-layer packaging substrate.

Reference Number:

10 carriers

12 Curing resin

14 Surface of cured resin

16 conductor layer

17 Conductive seed layer

18 Ion implantation layer

20 Plasma Deposition Layer

201 Metal or metal oxide deposits

202 Cu deposition layer

22 Conductor thickening layer

100 Package substrate

102 First Line Structure

104 first bonding layer

106 Surface of the first bonding layer

108 holes

110 hole wall

116 conductor layer

117 conductive seed layer

118 ion implantation layer

120 Plasma Deposition Layer

122 Conductor thickening layer

124 Second Line Structure

126 Second bonding layer

128 Third Line Structure

130 release film

132 copper foil

134 Prepreg.

DETAILED DESCRIPTION

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail. Those skilled in the art will appreciate that these descriptions merely list exemplary embodiments of the present invention and are by no means intended to limit the scope of protection of the present invention. In addition, in order to facilitate description of the positional relationship between the various material layers, spatially relative terms such as "above" and "below", as well as "inside" and "outside" are used herein, and these terms are all relative to the surface of the carrier or bonding layer. If the A layer of material is located in a direction toward the outside of the carrier or bonding layer relative to the B layer of material, the A layer of material is considered to be located above the B layer of material, and vice versa. In addition, when describing the packaging substrate, the terms "double-layer", "triple-layer" and "multi-layer" used actually refer to the number of layers of the circuit structure in the packaging substrate.

FIG1 is a flow chart showing a method for manufacturing a carrier for a coreless package substrate according to the present invention. The method comprises the following steps: forming a curing resin (step S1); and forming an easily peelable conductor layer on the surface of the curing resin, wherein the bonding force between the conductor layer and the curing resin is 0.01-0.05 N/mm (step S2). In the carrier thus prepared, the bonding force between the conductor layer and the curing resin is as low as 0.01-0.05 N/mm. Therefore, when using the carrier to manufacture a coreless package substrate, it is easy to peel the package substrate together with the conductor layer from the curing resin. The peeled curing resin can be further processed in step S2 and can be easily reused in the carrier preparation process.

When forming the cured resin, the low roughness surface of the metal sheet can be bonded to the uncured resin, and the metal sheet can be removed after lamination and thermal curing to obtain the cured resin. The resin raw materials used may include one or more of bismaleimide triazine resin, epoxy resin, cyanate resin, polyphenylene ether resin and their modified resins. The metal sheet used can be various common metal sheets such as stainless steel sheet, aluminum sheet, copper sheet, etc., or it can be a thicker metal plate, etc. The low roughness surface of the metal sheet preferably has a surface roughness Rz value of less than 2.5 μm (i.e., ≤2.5 μm, for example, 2.0 μm, 1.0 μm, 0.5 μm, etc.), so that the cured resin finally obtained also has a corresponding lower surface roughness, which is convenient for forming a smooth conductor layer. In addition, the thermal curing process can be carried out in a vacuum press, and the removal of the metal sheet can be achieved by etching or the like. In fact, in addition to the cured resin, other insulating rigid plates with stable performance can also be used for the manufacture of the carrier in the present invention. For example, organic polymer rigid plates, ceramic plates (such as silica plates), and glass plates may also be used. Organic polymer rigid plates may include LCP, PTFE, CTFE, FEP, PPE, synthetic rubber plates, and glass fiber cloth/ceramic filler reinforced plates. Furthermore, a prepreg may be used instead of a curing resin. This prepreg may be cured in a subsequent process of manufacturing a package substrate using the carrier, rather than during the carrier manufacturing process.

Step S2 of forming the conductor layer may include first forming a conductive seed layer on the surface of the cured resin, and then forming a conductor thickening layer on the conductive seed layer. When forming the conductive seed layer, a conductive material can be injected into the surface of the cured resin by ion implantation to form an ion implantation layer as the conductive seed layer. Alternatively, a conductive material can be deposited on the surface of the cured resin by plasma deposition to form a plasma deposition layer as the conductive seed layer. Alternatively, a conductive material can be injected into the surface of the cured resin by ion implantation to form an ion implantation layer, and then a plasma deposition layer can be formed above the ion implantation layer by plasma deposition, and the ion implantation layer and the plasma deposition layer together constitute the conductive seed layer. In addition, the methods are not limited to ion implantation and plasma deposition, and a conductive layer that is easy to peel off can also be formed on the surface of the cured resin by methods such as sputtering deposition and chemical vapor deposition. By adjusting the operating parameters of various methods, the bonding force between the conductor layer and the cured resin can be stably controlled to be between 0.01-0.05N/mm.

Ion implantation can be performed by the following method: using a conductive material as a target material, under a vacuum environment, the conductive material in the target material is ionized by an arc action to produce ions, and then the ions are accelerated under an electric field to obtain a certain amount of energy. The high-energy conductive material ions then directly impact the surface of the cured resin at a certain speed and are implanted to a certain depth below the surface. A relatively stable chemical bond (such as an ionic bond or a covalent bond) is formed between the implanted conductive material ions and the resin molecules, and the two together constitute a doped structure. The outer surface of the doped structure (i.e., the ion implantation layer) is flush with the surface of the cured resin, while its inner surface penetrates into the inside of the cured resin, i.e., is located below the surface of the cured resin. Before ion implantation, the surface of the cured resin can be subjected to decontamination, surface cleaning, sealing agent treatment, vacuum environment Hall source treatment, surface deposition treatment, etc., so that the ion implantation process can proceed smoothly.

Various metals, alloys, conductive oxides, conductive carbides, conductive organic compounds, etc. can be used as conductive materials for ion implantation, such as one or more of Ti, Cr, Ni, Cu, Ag, Au, V, Zr, Mo, Nb, and alloys thereof, such as NiCr, TiCr, VCr, CuCr, MoV, NiCrV, TiNiCrNb, etc. Moreover, the ion implantation layer can include one or more layers, such as a Ni layer and a Cu layer arranged sequentially from the inside to the outside. During the ion implantation process, the depth of ion implantation and the bonding strength between the cured resin and the conductive seed layer can be easily adjusted by controlling various parameters (such as voltage, current, vacuum, ion implantation dose, etc.). For example, the depth of ion implantation (i.e., the distance between the inner surface of the ion implantation layer and the surface of the cured resin) can be adjusted to be between 0 and 100 nm, while the bonding strength between the cured resin and the conductive seed layer can be adjusted to 0.01 to 0.05 N/mm, such as 0.02, 0.03, or 0.04 N/mm, etc. The conductive material ions used in the ion implantation process are typically nanometer-sized, resulting in a relatively uniform distribution during implantation and minimal variation in the angle of incidence upon the cured resin surface. This ensures that the resulting ion-implanted layer possesses excellent uniformity and density, making it less susceptible to pinholes.

Plasma deposition can be performed in a manner similar to the ion implantation described above, except that a lower voltage is applied during deposition. Specifically, a conductive material is used as a target. Under a vacuum, the conductive material in the target is ionized by an arc to generate ions. These ions are then accelerated under an electric field, gaining a certain amount of energy and depositing onto the surface of the cured resin, thereby forming a plasma-deposited layer. In this case, the target can be the same or different conductive material as used for ion implantation. Preferably, the conductive material used for the plasma-deposited layer is selected based on the selected resin material or the composition and thickness of the ion implantation layer (if present). Furthermore, the plasma-deposited layer can also include one or more layers, such as a metal or metal oxide deposited layer and a Cu layer arranged sequentially from the inside out. In a preferred embodiment, the metal deposited layer is a Ni layer with a thickness of 0-500 nm, the metal oxide deposited layer is a Ni-Cu alloy layer with a thickness of 0-500 nm, and the Cu layer can also have a thickness of 0-500 nm. The conductive material ions used for plasma deposition are also nanometer-sized, distributed relatively evenly during deposition, and have minimal variation in the angle of incidence on the cured resin surface. Therefore, it can be ensured that the obtained plasma deposited layer has good uniformity and density, and is not prone to pinhole phenomenon.

As described above, the conductive seed layer can be formed on the surface of the cured resin by ion implantation or plasma deposition alone, or by both ion implantation and plasma deposition. For example, in the example shown in FIG2(a), the conductive seed layer 17 formed on the surface 14 of the cured resin 12 is composed solely of the ion implantation layer 18, the outer surface of the ion implantation layer 18 is flush with the surface 14 of the cured resin 12, and the inner surface is located below the surface 14 of the cured resin 12, that is, located inside the cured resin 12. In the example shown in FIG2(d), the conductive seed layer 17 is composed solely of the plasma deposition layer 20, the inner surface of the plasma deposition layer 20 is flush with the surface 14 of the cured resin 12, and the outer surface is located outside the cured resin 12. In other words, the plasma deposition layer 20 is directly above the surface 14 of the cured resin 12. 2( b) and ( c), the conductive seed layer 17 formed on the surface 14 of the cured resin 12 includes an ion-implanted layer 18 and a plasma-deposited layer 20 located above the ion-implanted layer 18. The outer surface of the ion-implanted layer 18 is flush with the surface 14 of the cured resin 12, while the inner surface is located below the surface 14 of the cured resin 12. The plasma-deposited layer 20 is attached to the ion-implanted layer 18. In a preferred embodiment, as shown in FIG2( c), the plasma-deposited layer 20 further includes a metal or metal oxide deposited layer 201 located directly above the ion-implanted layer 18 and the surface 14 of the cured resin, and a Cu deposited layer 202 located above the metal or metal oxide deposited layer 201.

The conductor thickening layer that is positioned at conductive seed crystal layer top can adopt one or more treatment modes in the methods such as electroplating, chemical plating, vacuum evaporation plating, sputtering, use for example one or more in Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and the alloy between them to form.Electroplating is preferred, because electroplating speed is fast, cost is low, and the material range that can be electroplated is very extensive, is particularly applicable to Cu, Ni, Sn, Ag and the alloy between them etc.For some conductive materials, particularly metal and alloy (for example Al, Cu, Ag and alloy thereof), the speed of sputtering can reach 100nm/min, thereby can use sputtering mode on conductive seed crystal layer, coating conductor thickening layer rapidly.Owing to having formed uniform, close conductive seed crystal layer on the surface of cured resin by ion implantation and/or plasma deposition before, so be easy to form uniform, close conductor thickening layer on this conductive seed crystal layer by aforesaid method, and then form conductor layer together with conductive seed crystal layer.

2( a) to 2 ( d ) clearly show the conductor thickening layer 22 formed above the conductive seed crystal layer 17. To facilitate use in subsequent processes of manufacturing coreless package substrates, to thicken the starting structure thickness of the package substrate processing to improve yield, and to avoid substrate warping, the conductor layer 16 on the carrier 10, including the conductive seed crystal layer 17 and the conductor thickening layer 22, preferably has a thickness of 5 μm or less (i.e., ≤ 5 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc.).

After the carrier is formed, the carrier can then be used to form a coreless packaging substrate. Figure 3 is a flow chart showing a method for manufacturing a coreless packaging substrate according to the present invention. The method includes the following steps: forming a first circuit structure on the surface of the carrier (step S11); laminating a first bonding layer above the first circuit structure (step S12); drilling holes in the first bonding layer (step S13); forming a conductive seed layer on the surface of the first bonding layer and the wall surface of the hole (step S14); forming a second circuit structure on the surface of the first bonding layer (step S15); and peeling off the carrier to obtain a coreless packaging substrate (step S16).

Through the above steps S11 to S16, a two-layer packaging substrate with surface and bottom layer circuit structures can be obtained. It should be readily understood that if a multi-layer circuit structure is desired, steps S12 to S15 can be repeated. For example, a second laminating layer can be laminated on top of the second circuit structure, followed by drilling holes in the second laminating layer. A conductive seed layer can then be formed on the surface of the second laminating layer and on the walls of the holes formed in the second laminating layer. A third circuit structure can then be formed on the surface of the second laminating layer. Finally, the carrier can be removed to obtain a packaging substrate with a three-layer circuit structure. Similarly, a multi-layer packaging substrate with first, second, third, ..., Nth circuit structures can be formed. When forming the intermediate circuit structures of the multi-layer packaging substrate, i.e., one or more of the second, third, ..., N-1th circuit structures, copper foil can be first laminated onto the laminating layer, holes can then be drilled in the copper foil and laminating layer, and the copper foil can then be etched to obtain the desired intermediate circuit structure. Since the intermediate circuit structure is not exposed, this simple method can be used to produce circuit patterns with less stringent requirements for wireframe and line spacing. In addition, when forming a multi-layer packaging substrate, instead of drilling holes in each bonding layer individually in each cycle, one or more through holes can be drilled in multiple bonding layers laminated together in a certain cycle to connect the corresponding circuit structures at one time.

As a carrier for manufacturing coreless package substrates, in addition to the carrier 10 shown in Figures 2(a) to 2(d) produced by the above method, commonly used carriers in the art can also be used, such as a carrier board formed by high-temperature lamination of an ultra-thin copper foil to a prepreg via a release film. Furthermore, when manufacturing coreless package substrates, the circuit structure can be formed on only one side of the carrier, or on both sides. In this case, the carrier can be separated from the carrier at once to form two separate coreless package substrates.

As a method for forming the circuit structure, full-plate electroplating or pattern electroplating known in the prior art can be used. For example, a photoresist film can be first coated on the conductive layer of the carrier or on the conductive seed crystal layer on the surface of the bonding layer, exposed and developed, and then etched to remove the non-circuit portion and stripped to form the circuit structure. Alternatively, a photoresist film can be first coated on the conductive layer of the carrier or on the conductive seed crystal layer on the surface of the bonding layer, exposed and developed, and then electroplated as a whole, and then stripped and quickly etched to remove the non-circuit portion, thereby forming the circuit structure. The conductive layer can be any of the conductive layers 16 shown in Figures 2(a) to 2(d).

As the material of the bonding layer, common prepreg is typically used. Organic polymer films such as PP, PI, PTO, PC, PSU, PES, PPS, PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, PPA, or pure resin films (such as epoxy resin films) without glass fiber cloth can also be used. When drilling, mechanical drilling, punching, laser drilling, plasma etching, and reactive ion etching can be used. Laser drilling can also include infrared laser drilling, YAG laser drilling, and ultraviolet laser drilling, which can form micropores with a pore size of 2-5 microns on the substrate. The shape of the hole can be various shapes such as circular, rectangular, and terraced. When laser drilling, the cross-section of the hole is usually an inverted trapezoid. In addition, during laser drilling, the partially volatilized resin after the resin is vaporized will cool and deposit on the wall of the hole. Fragments generated during cutting may also remain in the hole. Therefore, before the hole is metallized (conductive seed layer is formed in step S14), it is necessary to carry out smear removal processing to avoid problems with interlayer interconnection and reliability and to achieve good electrical contact between electrodes. The smear removal processing can be carried out by plasma cleaning or chemical etching methods. While removing the smear, the wall surface of the hole can also be slightly corroded to roughen the wall surface, which helps the conductor layer to adhere to the wall surface of the hole. The reagent adopted for roughening can be sulfuric acid or alkaline potassium permanganate.

In step S14, when forming a conductive seed layer on the surface of the first bonding layer and the wall surface of the hole, the method described above can be used. For example, the conductive material can be injected into the surface of the first bonding layer and below the wall surface of the hole by ion implantation to form an ion implantation layer as the conductive seed layer. Alternatively, the conductive material can be deposited onto the surface of the first bonding layer and the wall surface of the hole by plasma deposition to form a plasma deposition layer as the conductive seed layer. Alternatively, the conductive material can be injected into the surface of the first bonding layer and below the wall surface of the hole by ion implantation to form an ion implantation layer, and then a plasma deposition layer is formed above the ion implantation layer by plasma deposition. The plasma deposition layer and the ion implantation layer together constitute the conductive seed layer.

Specifically, ion implantation is performed using the method described above. It should be noted that when forming a carrier, it is desired that the conductor layer on the carrier can be easily peeled off from the surface of the cured resin, so the parameters of the ion implantation process are adjusted during the implantation process, especially using a lower acceleration voltage to obtain a lower ion flight speed, so that the predetermined bonding force between the conductor layer and the cured resin is as low as 0.01-0.05N/mm. However, when metallizing the hole and forming the circuit structure, it is desired that the formed conductor layer has a larger bonding force with the bonding layer material. At this time, it is necessary to apply a higher voltage in the ion implantation equipment so that the conductive material ions obtain higher energy and directly impact the surface of the bonding layer and the wall surface of the hole at a higher speed, and are implanted to a certain depth below it, for example 1-500nm (such as 50, 100, 200, 300, 400nm, etc.). In this way, the conductive material ions are forcibly implanted into the bonding layer, forming a stable chemical bond with the material molecules that constitute the bonding layer to form a doping structure, which is equivalent to forming a large number of "foundation piles" below the bonding layer surface and the wall surface of the hole. The outer surface of the doping structure (i.e., the ion implantation layer) is flush with the surface of the bonding layer or the wall of the hole, while its inner surface is located at a depth of 1-500nm below the surface of the bonding layer or the wall of the hole. The bonding force between the "base pile" and the bonding layer is high, which can reach 0.5N/mm or more, for example, between 0.7-1.5N/mm, more specifically between 0.8-1.2N/mm, which is much greater than the bonding force that can be obtained by conventional magnetron sputtering. In addition, as mentioned above, the conductive material ions used for ion implantation usually have a nanometer-scale particle size, are distributed more evenly during ion implantation, and the angle of incidence to the bonding layer surface and the hole wall is not much different. Therefore, it can be ensured that the ion implantation layer has good uniformity and density, and pinholes are not prone to occur. Moreover, the thickness ratio of the conductor layer on the hole wall and the bonding layer surface can reach 1:1, and problems such as uneven plating, holes or cracks will not occur in subsequent electroplating processes, which can effectively improve the conductive performance of the metallized hole.

In addition to the ion implantation layer, the conductive seed layer formed on the surface of the bonding layer and the wall surface of the hole can further include a plasma deposition layer located above the ion implantation layer. In addition, the plasma deposition layer can also be formed directly on the surface of the bonding layer and the wall surface of the hole by only a plasma deposition method as a conductive seed layer. These ion implantation layers and plasma deposition layers can each include one or more layers composed of the same or different materials. For example, the conductive seed layer 17 shown in Figures 2(a) to 2(d) can all be formed on the wall surface of the hole drilled in the bonding layer. Of course, when a plasma deposition layer is formed, the drilled hole may be filled with the plasma deposition layer, that is, the entire hole is filled with conductive material and there is no longer a hole structure macroscopically.

In any case, by forming a conductive seed layer on the surface of the bonding layer and the wall surface of the hole, the metallization of the bonding layer surface and the metallization of the hole wall can be carried out simultaneously. Therefore, the metallized vias and the bonding layer surface with the conductive seed layer can be directly obtained by one-time molding. There is no need to cover the substrate with a thicker metal foil in advance and then etch and thin the metal foil before drilling holes on the substrate as in the prior art, and there is no need to form a conductive layer on the hole wall through chemical copper deposition or black hole, black shadow and other processes to obtain metallized vias. Compared with the prior art, the process flow of the method of the present invention can be significantly shortened, and the use of etching solution can be reduced, which is beneficial to environmental protection. In addition, by adjusting various process parameters, such as voltage, current and plating solution concentration during electroplating, the above method can easily produce a circuit structure layer with an extremely thin thickness (for example, less than 12μm, such as 5μm, 7μm, 9μm, etc.), which is easy to meet the fine circuit requirements of narrow line width and line spacing. Furthermore, when the ion implantation layer is formed as at least a portion of the conductive seed layer, the presence of the ion implantation layer in the hole wall generates a very high bonding force (e.g., greater than 0.5 N/mm, between 0.7-1.5 N/mm, and more specifically, between 0.8-1.2 N/mm) between the hole wall and the conductive seed layer. This prevents the metal layer in the hole wall from being easily detached or scratched during subsequent processing or application. This improves the conductive performance of the via hole and facilitates the production of a packaging substrate with good conductivity.

When forming the circuit structure in step S15, a conductor thickening layer can be formed above the conductive seed layer on the surface of the bonding layer so that the entire conductive seed layer is thickened. Then, a photoresist film is covered above the conductor thickening layer and exposed and developed to expose the non-circuit portion (i.e., the area where the conductive layer does not need to be formed). Then, etching is performed to remove the conductive seed layer and the conductor thickening layer in the non-circuit portion. Finally, the photoresist film is removed to form a circuit structure having a conductive seed layer and a conductor thickening layer only in the circuit portion (i.e., the area where the conductive layer needs to be formed). Alternatively, a photoresist film can also be covered above the surface of the bonding layer and exposed and developed to expose the circuit portion. Then, electroplating is performed to form a conductor thickening layer above the conductive seed layer. Then, the photoresist film is removed and rapid etching is performed to remove the conductive seed layer of the non-circuit portion, thereby obtaining the circuit structure. At this point, the conductor thickening layer will also be etched to a thickness at least equal to the thickness of the conductive seed layer, but this will not significantly affect the conductive performance of the circuit structure. The conductor thickening layer can be formed using the method described above. For example, a thickened copper layer having a thickness of 1-1000 μm (e.g., 2 μm, 5 μm, 10 μm, 12 μm, 50 μm, 100 μm, 500 μm, etc.) can be formed on top of the conductive seed layer by electroplating using a plating solution composed of 100-200 g/L copper sulfate, 50-100 g/L sulfuric acid, 30-90 mg/L chloride ion concentration, and a small amount of additives. Alternatively, a copper foil can be pressed onto the surface of the laminating layer and the non-circuit portion of the copper foil can be removed by etching to obtain a circuit structure.

In step S16, the entire circuit structure on the carrier is separated from the carrier to obtain the desired coreless packaging substrate. When using the carrier 10 shown in Figures 2(a) to 2(d), this separation process will peel off the circuit structure together with the conductor layer 16 formed on the carrier 10, including the conductive seed layer 17 and the conductor thickening layer 22, because the bonding force between the conductor layer 16 and the cured resin 12 is as low as 0.01-0.05N/mm. After peeling, the cured resin 12 no longer has the conductor layer 16 on the surface and can be further processed to continue to be used to manufacture the carrier. In addition, when using a common high-temperature pressing carrier plate as a carrier, since a release film is pressed on the surface of the semi-cured sheet, the circuit structure together with the copper foil on the release film can be torn off by applying external force to form a coreless packaging substrate. In both cases, it is necessary to quickly etch the side of the packaging substrate close to the carrier to remove the existing conductor layer or copper foil to avoid short circuiting of the first circuit structure. When the first circuit structure is formed by directly removing the thicker conductor layer 16 on the carrier 10 by etching, although the conductor layer of the non-circuit portion no longer exists on the lower surface of the package substrate, rapid etching may be required to obtain a relatively flat surface.

After separation and rapid etching, a solder mask layer is formed on the surface of the package substrate. After exposure and development, windows are formed in the solder mask layer, and the windowed solder mask layer is cured. The solder mask layer is a protective layer that prevents physical disconnection of the circuit structure on the package substrate. During the soldering process, it prevents short circuits caused by bridging and protects against contamination from external factors such as moisture and dust, which can degrade insulation and corrode the circuit structure. By creating windows in the solder mask layer, electrodes where patches and plug-ins are required can be exposed, allowing for connection to other circuits or electronic components.

The coreless packaging substrate prepared by the above method is composed of a first circuit structure, a first bonding layer, a second circuit structure, a second bonding layer, a third bonding layer, ..., an Nth circuit structure in sequence, wherein the first circuit structure is embedded in the first bonding layer, the coreless packaging substrate is formed with a hole and a conductive seed layer is formed on the wall of the hole, the conductive seed layer includes an ion implantation layer implanted below the wall of the hole and/or a plasma deposition layer formed above the wall of the hole. The outer surface of the first circuit structure is flush with the outer surface of the first bonding layer, while the inner surface is located inside the first bonding layer. The ion implantation layer (if present) is a doped structure formed by a conductive material and a bonding layer, the outer surface of which is flush with the wall of the hole or the surface of the bonding layer, while the inner surface is located at a depth of 1-500nm below the surface of the wall of the hole or the surface of the bonding layer. The inner surface of the plasma deposition layer (if present) is flush with the wall of the hole or the surface of the bonding layer, while the outer surface is located outside the bonding layer.

The above generally describes the method for manufacturing a coreless package substrate according to the present invention. Below, several specific embodiments for implementing the method will be illustrated to enhance understanding of the present invention.

(First embodiment)

4( a ) to 4 ( f ) are schematic cross-sectional views of structures corresponding to the steps of the method shown in FIG. 3 when producing a double-layer packaging substrate according to the first embodiment of the present invention.

First, as shown in FIG4(a), a coreless package substrate is prepared using the carrier 10 shown in FIG2(a), which is prepared using the method described above. The carrier 10 includes an ion-implanted layer 18 whose outer surface is flush with the surface 14 of the cured resin 12 and whose inner surface is located below the surface 14, and a conductor thickening layer 22 located above the ion-implanted layer 18. Conventional pattern plating or full-board plating methods are used to form a first circuit structure 102 on both the upper and lower surfaces of the carrier 10. In this embodiment, copper foil is directly laminated to the surface of the carrier 10, and the non-circuit portions of the copper foil are removed by etching to obtain the first circuit structure 102. If the conductor layer 16 on the carrier 10 is sufficiently thick, the non-circuit portions of the conductor layer 16 can also be directly etched away to obtain the first circuit structure 102. This eliminates the need for copper foil and high-temperature lamination, shortening the process and reducing costs.

Next, as shown in FIG4(b), a first bonding layer 104 is laminated on top of the first circuit structure 102. In this step, the first bonding layer composed of a prepreg can be laminated on top of the first circuit structure 102 at a temperature of 210-220°C in a high-temperature laminating machine. After thermal curing, the prepreg becomes a solidified state, which can avoid the warping of the double-layer packaging substrate. Thereafter, as shown in FIG4(c), a hole 108 is drilled in the first bonding layer 104 by laser drilling. The hole 108 directly leads to the circuit pattern in the first circuit structure 102 so as to electrically connect the circuit patterns on both sides of the first bonding layer 104. Although FIG4(c) shows a hole 108 with a rectangular longitudinal cross-section, it should be easily understood that the illustration is merely exemplary. The hole formed by laser drilling generally has a longitudinal cross-section of an inverted trapezoid, and the shape of the hole can also be a variety of shapes such as cylindrical, rectangular, and terraced.

Then, as shown in FIG4(d), a conductive material is implanted below the surface 106 of the first bonding layer 104 and below the pore walls 110 of the pores 108 by ion implantation to form an ion implantation layer 118, and a conductive material is deposited by plasma deposition to form a plasma deposition layer 120 above the ion implantation layer 118. The plasma deposition layer 120 and the ion implantation layer 118 together constitute a conductive seed layer 117. FIG4(d) shows the conductive seed layer 117 consisting of both the ion implantation layer 118 and the plasma deposition layer 120, but it should be readily understood that the conductive seed layer 117 may also include only one of the structures of the ion implantation layer 118 and the plasma deposition layer 120, as described above.

Next, a conductor thickening layer 122 is formed above the conductive seed crystal layer 117 on the bonding layer surface 106, and then a photoresist film is covered on the conductor thickening layer 122 and exposed and developed to expose the non-circuit portion. Then, etching is performed to remove the conductive seed crystal layer 117 and the conductor thickening layer 122 in the non-circuit portion. Finally, the photoresist film is removed to form a circuit structure with the conductive seed crystal layer 117 and the conductor thickening layer 122 only in the circuit portion. As shown in Figure 4(e), the resulting second circuit structure 124 includes an ion implantation layer 118 implanted below the surface 106 of the first bonding layer 104, a plasma deposition layer 120 located above the ion implantation layer 118, and a conductor thickening layer 122 located above the plasma deposition layer 120. This method is the "full-board electroplating" described above.

Finally, the entire circuit structure on the upper and lower surfaces of the carrier 10 is peeled off from the carrier 10 by applying external force, thereby obtaining two separate coreless packaging substrates 100, as shown in Figure 4(f). In the carrier 10, the bonding force between the conductor layer and the curing resin can be controlled to be as low as 0.01-0.05N/mm, so that the conductor layer is easily separated from the curing resin during the peeling process. After peeling, the conductor layer 16 will adhere to the bottom of the first circuit structure 124. At this time, it is necessary to remove the conductor layer 16 by means of rapid etching or the like, and then form a solder mask layer on the surface of the resulting packaging substrate 100 and perform windowing to protect the circuit structure on the packaging substrate and form the desired electrical connection.

Ion implantation and/or plasma deposition can be performed again on the peeled cured resin 12 to form an easily peelable conductor layer on the surface of the cured resin 12. By adjusting various parameters of the ion implantation and/or plasma deposition process (e.g., voltage, current, vacuum level, implantation dose, etc.), a desired low bonding force between the cured resin and the conductor layer, such as between 0.01 and 0.05 N/mm, can be easily achieved. Such bonding force can be repeatedly and stably achieved. In other words, the peeled cured resin can be easily reused to prepare a carrier for a coreless package substrate.

(Second embodiment)

5( a ) to 5 ( j ) are schematic cross-sectional views of structures corresponding to various steps of the method shown in FIG. 3 when producing a three-layer packaging substrate according to a second embodiment of the present invention.

First, as shown in Figure 5(a), a carrier 10 is formed by pressing a thin copper foil 132 to a prepreg 134 via a release film 130. Optionally, the prepreg, copper support plate, release film and thin copper foil can be pressed together at high temperature in sequence to obtain the desired carrier. High-temperature pressing refers to the use of high temperature and high pressure to melt the prepreg and make it flow and then convert it into a cured sheet, thereby pressing the copper plates or copper foils on both sides of the prepreg together. The carrier obtained in this way greatly increases the thickness of the starting structure of the three-layer packaging substrate, thereby improving the operability of the processing and making the subsequent process easy to control, and improving the production yield of the packaging substrate. In addition to the different carriers used, the cross-sectional structures shown in Figures 5(a) to 5(e) correspond to Figures 4(a) to 4(e) respectively. It should be noted that when forming the second circuit structure 124, the copper foil can be simply laminated to the first bonding layer first, then the copper foil and the first bonding layer are drilled, and then the copper foil is etched to obtain the desired circuit structure.

In order to form a three-layer circuit structure, after forming the second circuit structure 124, it is necessary to continue laminating the second bonding layer 126 on top of the second circuit structure 124, as shown in Figure 5(f). When laminating the second bonding layer 126, as described above, the second bonding layer 126 composed of a semi-cured sheet can be high-temperature pressed on top of the second circuit structure 124 in a high-temperature laminating machine at a temperature of 210-220°C. In the case of forming a three-layer packaging substrate, two bonding layers 104 and 126 are used. Therefore, it is preferred that the first bonding layer 104 is low-temperature pressed at a temperature of 110-130°C for 5-20 minutes, at which time the first bonding layer 104 remains in a semi-cured state. When the second bonding layer 126 is subsequently laminated, high-temperature pressing is performed at a temperature of 210-220°C. At this time, the first bonding layer 104 is pressed together with the second bonding layer 126 at high temperature and becomes a cured state. Since the first and second bonding layers are cured under the same conditions, the internal stress therebetween is uniform, thus avoiding the warping of the three-layer packaging substrate.

Then, a hole 108 is drilled on the second bonding layer 126 by laser drilling. The hole 108 directly leads to the circuit pattern in the second circuit structure 124, facilitating the electrical connection of the circuit patterns on both sides of the second bonding layer 126, as shown in Figure 5 (g). In this embodiment, it is also possible not to drill a hole in the first bonding layer 104 in advance, but after laminating the second bonding layer 126, respectively drill through the first and second bonding layers 104 and 126, and through holes that only penetrate the second bonding layer 126. In this way, the drilling process can be reduced, but the electrical connection required only between the circuit structures on both sides of the first bonding layer 104 may no longer be achieved. When drilling through the two bonding layers, laser drilling can be performed two or more times in succession so that the hole penetrates the second bonding layer 126 and the first bonding layer 104 in succession.

Next, using the method described above, a conductive material is implanted into the lower surface of the second conforming layer 126 and the lower wall 110 of the hole 108 by ion implantation to form an ion implantation layer 118, which serves as a conductive seed layer 117, as shown in FIG5(h). Of course, as described above, the conductive seed layer 117 may also include a plasma deposited layer 120 located above the ion implantation layer 118, or may only include the plasma deposited layer 120 located directly above the surface of the second conforming layer 126 and the wall 110 of the hole 108.

Then, a third circuit structure 128 is formed on the surface of the second bonding layer 126 by a graphic electroplating method. That is, a photoresist film is first covered on the ion implantation layer 118 (i.e., the conductive seed crystal layer 117) formed below the surface of the second bonding layer 126, and exposed and developed to expose the circuit portion. Next, electroplating is performed to form a conductor thickening layer 122 only above the circuit portion of the conductive seed crystal layer 117. Then, the photoresist film is stripped off and rapid etching is performed to remove the conductive seed crystal layer 117 of the non-circuit portion, thereby obtaining the third circuit structure 128. At this time, the conductor thickening layer 122 located above the conductive seed crystal layer 117 in the circuit portion will also be etched away to a thickness at least equal to the thickness of the conductive seed crystal layer 117, but this will not cause a significant negative impact on the conductive performance of the circuit structure.

Finally, the entire circuit structure on both sides of the carrier 10 is peeled off from the carrier 10 by applying external force, thereby obtaining two separate coreless packaging substrates 100 with three-layer circuit structures (i.e., first, second, and third circuit structures 102, 124, and 128), as shown in Figure 5(j). After peeling, the release film 130 may adhere to the lower surface of the first circuit structure 102 along with the copper foil 132. In this case, it is necessary to remove the release film 130 in advance, and then remove the copper foil 132 attached to the lower surface of the first circuit structure by rapid etching to obtain the desired packaging substrate. Of course, the release film 130 may remain adhered to the prepreg 134 after peeling, and its adhesion is greatly reduced. In this case, it needs to be replaced with a new release film before it can be used to prepare a new carrier. In any case, compared with the carrier obtained by ion implantation and/or plasma deposition in the present invention, the carrier containing the release film is more complicated to handle and cannot be easily reused.

The foregoing description merely mentions preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described herein. It will be readily apparent to those skilled in the art that various obvious modifications, adjustments, and substitutions may be made to these embodiments to adapt them to specific circumstances without departing from the gist of the present invention. In fact, the scope of protection of the present invention is defined by the claims and may include other examples that may be envisioned by those skilled in the art. Such other examples will fall within the scope of protection of the claims if they have structural elements that are indistinguishable from the literal language of the claims, or if they include equivalent structural elements that are insignificantly different from the literal language of the claims.

Claims (17)

1. A method for manufacturing a carrier for a coreless packaging substrate, comprising the following steps: S1: Formation of cured resin; and S2: Forming an easily peelable conductive layer on the surface of the cured resin, comprising first forming a conductive seed layer on the surface of the cured resin, and then forming a conductive thickening layer on the conductive seed layer, wherein the conductive seed layer and the conductive thickening layer constitute the conductive layer. The conductive seed layer is formed in the following manner: Conductive material is implanted beneath the surface of the cured resin via ion implantation to form an ion-implanted layer as the conductive seed layer; or Conductive material is deposited on the surface of the cured resin by plasma deposition to form a plasma deposition layer as the conductive seed layer; or First, conductive material is implanted beneath the surface of the cured resin via ion implantation to form an ion-implanted layer. Then, a plasma-deposited layer is formed on top of the ion-implanted layer via plasma deposition. The ion-implanted layer and the plasma-deposited layer together constitute the conductive seed layer. Furthermore, the bonding force between the conductor layer and the cured resin is 0.01-0.05 N/mm, the surface roughness of the cured resin is below 2.5 μm, and the conductor thickening layer includes a Cu layer with a thickness of 0-5 μm. 2. The method according to claim 1, wherein step S1 comprises bonding the low-roughness surface of the metal sheet to the uncured resin, and removing the metal sheet after lamination and heat curing to obtain the cured resin. 3. The method according to claim 2, wherein the resin comprises one or more of bismaleimide triazine resin, epoxy resin, cyanate ester resin, polyphenylene ether resin, and modified resins thereof. 4. The method according to claim 1, wherein the ion implantation layer is a doped structure formed by the conductive material and the cured resin, the outer surface of which is flush with the surface of the cured resin, and the inner surface is located at a depth of 1-100 nm below the surface of the cured resin. 5. The method according to claim 1, wherein the plasma deposition layer comprises a metal or metal oxide deposition layer with a thickness of 0-500 nm and a Cu deposition layer with a thickness of 0-500 nm located above the metal or metal oxide deposition layer, wherein the metal deposition layer comprises Ni or a Ni-Cu alloy and the metal oxide deposition layer comprises NiO. 6. The method according to claim 1, wherein step S2 comprises forming the conductor thickening layer above the conductive seed layer by one or more of electroplating, electroless plating, vacuum evaporation plating, and sputtering. 7. A carrier for a coreless packaging substrate, comprising: Cured resin; and A conductive layer that is easily peelable from the surface of the cured resin, the conductive layer comprising a conductive seed layer and a conductive thickening layer located above the conductive seed layer, the conductive seed layer comprising: The outer surface is flush with the surface of the cured resin, while the inner surface is located within the ion-implanted layer inside the cured resin; or A plasma-deposited layer located above the surface of the cured resin; or An ion-implanted layer has an outer surface flush with the surface of the cured resin, while an inner surface is located inside the cured resin, and a plasma-deposited layer is located above the ion-implanted layer. The bonding force between the conductor layer and the cured resin is 0.01-0.05 N/mm, the surface roughness of the cured resin is below 2.5 μm, and the conductor thickening layer includes a Cu layer with a thickness of 0-5 μm. 8. The carrier according to claim 7, wherein the cured resin comprises one or more of bismaleimide triazine resin, epoxy resin, cyanate ester resin, polyphenylene ether resin, and modified resins thereof. 9. The carrier according to claim 7, wherein the ion implantation layer is a doped structure formed by a conductive material and the cured resin, and its inner surface is located at a depth of 1-100 nm below the surface of the cured resin. 10. The carrier according to claim 7, wherein the plasma deposition layer comprises a metal or metal oxide deposition layer with a thickness of 0-500 nm and a Cu deposition layer with a thickness of 0-500 nm located above the metal or metal oxide deposition layer, wherein the metal deposition layer comprises Ni or a Ni-Cu alloy and the metal oxide deposition layer comprises NiO. 11. A method for manufacturing a coreless packaging substrate, comprising the following steps: S11: A first circuit structure is formed on the surface of the carrier; S12: Laminate a first bonding layer on top of the first circuit structure; S13: Drill holes in the first bonding layer; S14: A conductive seed layer is formed on the surface of the first bonding layer and the wall of the hole in the following manner: Conductive material is implanted into the surface of the first bonding layer and below the wall of the hole by ion implantation to form an ion-implanted layer as the conductive seed layer; or Conductive material is deposited onto the surface of the first bonding layer and the walls of the holes by plasma deposition to form a plasma-deposited layer as the conductive seed layer; or First, conductive material is implanted into the surface of the first bonding layer and below the wall of the hole to form an ion implantation layer. Then, a plasma deposition layer is formed on top of the ion implantation layer by plasma deposition. The ion implantation layer and the plasma deposition layer together form the conductive seed layer. S15: Form a second circuit structure on the surface of the first bonding layer; and S16: Peel off the carrier to obtain a coreless packaging substrate. The carrier is a carrier manufactured by the method according to any one of claims 1-6, or a carrier according to any one of claims 7-10. 12. The method according to claim 11, characterized in that steps S12 to S15 are repeated to form a multilayer packaging substrate with first, second, third, ... Nth circuit structures. 13. The method according to claim 12, characterized in that, when forming the intermediate circuit structure of the multilayer packaging substrate, i.e., one or more of the second, third, ... N-1th circuit structures, copper foil is first laminated onto the bonding layer, holes are drilled in the copper foil and the bonding layer, and then the copper foil is etched to obtain the intermediate circuit structure. 14. The method according to claim 11, wherein step S11 includes forming a first circuit structure on both sides of the carrier, and step S16 includes peeling the carrier from both sides to obtain two separate encapsulation substrates. 15. The method according to claim 11, wherein in steps S11 and S15, the first and second circuit structures are formed by full-board electroplating or pattern electroplating. 16. The method according to claim 11, wherein the ion implantation layer is a doped structure formed by the conductive material and the first bonding layer, the outer surface of which is flush with the surface of the first bonding layer or the wall of the hole, and the inner surface is located at a depth of 1-500 nm below the surface of the first bonding layer or the wall of the hole. 17. The method according to claim 11, wherein step S14 further comprises forming a conductor thickening layer above the conductive seed layer by one or more of electroplating, electroless plating, vacuum evaporation plating, and sputtering, wherein the conductor thickening layer comprises Cu.