HK1225173B - Method and control circuit for pfc current shaping - Google Patents

Description

Method and control circuit for PFC current shaping

Technical Field

The present invention relates to a method for generating a reference signal for a current regulator of a PFC circuit of a power supply unit. The present invention also relates to a PFC circuit including such a current regulator and a power supply unit including such a PFC circuit. Furthermore, the present invention relates to a corresponding control circuit for generating a reference signal for a current regulator of a PFC circuit of a power supply unit.

Background Art

Electrical devices are usually connected to the power grid to be fed with electric power to operate them. Typically, such devices include a power supply unit to transform the electric power delivered by the grid into a specific form of electric power that can be used by the device itself or can in turn be provided to another device connected to the device.

In order to limit undesirable feedback into the power grid, such devices generally must meet certain requirements regarding the current drawn from the grid. These requirements include, for example, limits on the harmonic content of the current drawn by the device, such as those defined in standard IEC 61000-3-2. The current drawn by a power supply, such as a switch-mode power supply, generally includes a number of harmonic components, the magnitude of which depends on the internal design of the power supply, in particular on the design of the power circuit. The standard, for example, defines maximum values for the magnitude of each harmonic component, such that these values become smaller the greater the number of harmonics.

A typical (switch-mode) power supply consists of a front-end and a back-end power stage, particularly for power supplies with input power exceeding 50W (watts). The front-end is typically a PFC (power factor correction) stage that minimizes the harmonic content of the power supply's input current and generates a more or less constant output voltage. The back-end is typically a DC/DC converter that operates from a generally constant input voltage. The PFC stage includes both a power train and control logic. The power train, for example, is a boost converter directly following the PFC stage's bridge rectifier. The control logic adapts the input current so that it closely tracks the input voltage. This means that the PFC's input impedance is essentially a resistor. Its resistance is therefore a function of the grid voltage and the power supply's output power.

The above topology works perfectly for single-phase input, where a single phase is provided between a line and neutral conductor. However, for three-phase input, such as a grid with three lines but no neutral conductor, it can create harmonics that are too high for higher power levels. Depending on the specific application and configuration, for example, depending on the capacitance downstream of the rectifier, this topology may not work for power levels up to 500 W or even 1500 W due to the reduced current conduction angle. To overcome this problem, a so-called passive PFC choke can be provided downstream of the three-phase bridge rectifier, or an active PFC circuit can be provided, including one PFC choke per phase line.

However, the passive PFC choke solution has limitations with regard to power loss and size, whereas the other solution is only suitable for higher power levels, ie up to approximately 2 kW.

Another disadvantage of prior art solutions is that they do not effectively damp the resonant circuits formed by the grid impedance in combination with the EMI capacitors typically provided between the neutral conductor and the phase line of the power supply input filter. These EMI capacitors are also known as X-capacitors. Load variations at the output of the power supply lead to input current variations that excite such resonant circuits, which can result in undesirably high input voltages, which can even lead to malfunction or destruction of the power supply.

Summary of the Invention

It is therefore an object of the present invention to provide a method and a control circuit relating to the initially mentioned technical field, which enable a power draw current from a grid to have a reduced harmonic content and to be suitable for a wide power range.

The solution of the present invention is defined by the features of claim 1. According to the present invention, the reference signal I _ref for the current regulator is generated such that the magnitude of the lower harmonic components of the input current of the power supply unit increases and the magnitude of the higher harmonic components of the input current decreases. Consequently, the magnitude of at least one lower harmonic component increases and the magnitude of at least one higher harmonic component decreases. Preferably, the magnitude of more than one lower harmonic component increases and the magnitude of more than one higher harmonic component decreases. In other words, power is shifted from higher harmonics to lower harmonics.

By increasing the harmonic content of the lower harmonics and reducing the content of the higher harmonics, the correspondingly adapted power supply not only meets the requirements regarding grid distortion but also enables higher input power to be drawn from the grid. This can be done without exceeding the limits on harmonic content, such as those defined in the IEC standards mentioned above.

In a preferred embodiment of the invention, the reference signal is generated so that the magnitude of the harmonic components below the eleventh harmonic of the input current increases and the magnitude of the harmonic components above the thirteenth harmonic of the input current decreases. In this case, the magnitudes of the eleventh and thirteenth harmonics remain more or less constant.

However, the number of divisions of the lower harmonics from the higher harmonics may be any number between 5 and 20, eg depending on the application of such a current regulator.

The generation of the reference signal is typically based on the input voltage of the power supply unit. Since most commercial power grids do provide an AC voltage with a generally sinusoidal waveform, either single or multi-phase, the reference signal I _ref is generated in a preferred embodiment of the method according to the present invention as a sinusoidal signal having the angular frequency of the AC grid to which the power supply unit is connected. In general, the value I ₀ can be positive or negative and can be determined in various ways. For example, it can be selected to have a constant value between -1 and 1, independent of the operating parameters and topology of the power supply unit. However, the value I ₀ is preferably generated in dependence on the current conduction angle _θ , which has been shown to provide the best results.

In a further preferred embodiment of the present invention, I ₀ is generated as a negative value

This means that I ₀ is a fraction of the magnitude of the input current, Î. Although a positive value of I ₀ can be used, for example, in conjunction with a boost converter, a negative value of I ₀ is advantageous in applications using a buck converter.

As can be seen, I ₀ depends only on the magnitude Î and the current conduction angle _θ .

It would also be possible to determine I ₀ in different ways, such as by scaling the magnitude Î by any factor between 0 and 1 or by subtracting a variable by a fixed amount. It would also be possible to determine I ₀ as a multiple or fraction of the current conduction angle _θ , or by adding a specific value to the current conduction angle _θ . However, these solutions would reduce the power that can be drawn from the grid, since less power can be moved from higher harmonics to lower harmonics.

Therefore, _I0 is preferably generated depending on the sine of the current conduction angle _θ . Therefore, the lower the absolute value of the current conduction angle _θ , the smaller the value of _I0 becomes, and the closer the current conduction angle _θ is to π/2, the higher _I0 becomes. Furthermore, it should be noted that the closer the current conduction angle _{θ is} to π/2, the higher the peak current becomes, and therefore the efficiency of the circuit becomes lower.

The reference signal I _ref is therefore generated according to the following formula:

Aside from the magnitude Î, the sinusoidal portion of the reference signal I _ref thus corresponds to the reference signal generated and used in comparable prior art PFC converters to regulate their input current. By adding a constant negative value I ₀ to the reference signal, the impedance of the PFC circuit, which can be considered a resistor, can be significantly reduced. In the case of a three-phase power supply, this allows for a higher input power source to be drawn from the grid—up to approximately 2 kW in a typical power grid with a voltage of approximately 230 V between the phase and neutral lines, depending on the specific control mechanism. This is achieved by using only a single PFC stage after the bridge rectifier. This also saves on component count, and consequently reduces space requirements and costs.

In the prior art, the resistance of a PFC circuit is a function of the grid voltage and the power supply's output power. In contrast, the resistance of such a prior art PFC circuit is referred to as a static resistance. In contrast, the application of the present invention results in a dynamic resistance of the PFC circuit that is further dependent on the current conduction angle _θ . For negative values of I ₀ , this dynamic resistance is lower than the static resistance of a comparable prior art PFC circuit.

A further advantage of the present invention is that the dynamic resistor more effectively damps the resonant circuit formed by the reactive elements of the grid and the EMI capacitors of the power supply.

With a negative value I ₀ , the reference current is lowered, and therefore the power drawn from the grid is reduced compared to a conventional or standard PFC circuit if the magnitude of the reference signal Î were generated using the same value as in a standard PFC circuit. To achieve the same output power of the power supply unit, the magnitude Î of the reference signal I _ref must be increased. In another example, where the reference current is increased by adding a positive value I ₀ , the magnitude Î of the reference signal I _ref must be reduced to draw approximately the same power from the grid.

In a preferred embodiment of the invention, and in order to obtain the same output power of the power supply unit using a standard reference signal with a standard magnitude Î _s (i.e. where I ₀ = 0), the magnitude Î of the reference signal is generated by modifying the standard magnitude Î _s in dependence on the change in the output power of the power supply unit due to adding the value I ₀ to the reference signal I _ref (in particular, to compensate for said change in the output power).

The magnitude Î can be set, for example, by trial and error. However, the value of the magnitude Î is preferably determined by comparing the power that can be drawn from the grid using a standard PFC circuit and a comparable PFC circuit according to the present invention. The term "comparable" in this context means that the PFC circuit of the present invention differs from the standard PFC circuit only in that the reference signal is generated by adding the value I ₀ and thus adapting the magnitude Î of the reference signal.

In a standard PFC circuit, the following applies:

where Û and Î _s are the magnitudes of the grid voltage and current, _s1 and _s2 are the power transfer angles, which are typically _s1 = 0 and _s2 = π, and where is the power drawn from the grid. By solving this integral, the power can be rewritten as:

.

Generally speaking, power transfer angles are those angles between which current flow occurs. Thus, the first angle, here _s1 , is the angle where current flow begins, and the second angle, here _s2 , is the angle where current flow ends.

For a comparable PFC circuit according to the present invention, where ₀ is the current conduction angle, which is chosen so that the current i( ₀ ) at this current conduction angle is equal to 0, and where ₁ and ₂ define the power transfer angle, the value I ₀ is determined as

And the power drawn from the grid can be calculated as

This formula gives the power for a buck PFC where for power transfer angles ₁ and ₂ , ₁ > 0 and ₂ < π applies. Again, this power can be rewritten as

.

To determine the magnitude Î of the PFC circuit according to the present invention, we can equate the two power formulas for the standard PFC circuit and the improved PFC circuit, as follows

This leads to the following formula

in

.

Therefore, in a preferred embodiment of the present invention and in order to obtain the same output power of the power supply unit using a standard PFC circuit in which the reference signal has a standard magnitude Îs and in which the value I ₀ =0, the magnitude Î of the reference signal is generated by multiplying the standard magnitude Îs by a factor f _ref determined according to the above formula.

In a further preferred embodiment of the present invention, the reference signal is based on the input voltage of the power supply unit via

a) Before the bridge rectifier of the PFC circuit

b) after the bridge rectifier of the PFC circuit, or

c) Directly at the input of the power supply unit

The voltage is generated by tapping.

Since the input voltage is usually sinusoidal, the reference signal is also assumed to be sinusoidal since it is derived from the input voltage. Therefore, the reference signal can also be tapped at any other point as long as it represents the input voltage.

When generating a reference signal according to the present invention, the current conduction angle _θ is preferably selected between 0 and π/2, thereby maintaining a good power factor and low harmonic content. In a further preferred embodiment of the present invention, the current conduction angle _θ is selected between π/5 and 2π/5. However, higher or lower current conduction angles _θ do also work, albeit not as well as with the preferred values. Furthermore, it should be noted that there is no optimal value for the current conduction angle _θ ; rather, the most suitable value must be found for each application. When selecting the current conduction angle _θ , a trade-off must be made between damping resonances caused by grid impedance and certain capacitances of the power supply unit and the adverse effects on system efficiency.

Due to the reduced current conduction angle _θ , the peak input current becomes higher, but the reference signal remains sinusoidal.

Furthermore, the dynamic input resistance is typically about six to eight times lower than the static resistance of a comparable prior art PFC. However, the exact ratio depends on the current conduction angle.

In another preferred embodiment, the reference signal is not determined according to the above-mentioned formula throughout the entire period. If it would become negative, it is set to zero. The zero crossing then defines the current conduction angle _θ . In this way, negative reference signals can be avoided, which would lead to a reduction in system efficiency.

In an even more preferred embodiment of the invention, the current conduction angle _θ is chosen so that the input current starts at zero. This helps to avoid current jumps that would result in undesirable harmonic components.

As mentioned above, switched-mode power supplies often include input filters, with EMI capacitors connected across the lines (e.g., between the phase and neutral lines) or other capacitors present downstream of the rectifier. Together with the series inductance of the grid (which may be introduced, for example, by a transformer), these EMI capacitors form a resonant circuit. Such a resonant circuit can result in undesirably high input voltages in response to load variations at the power supply's input.

In another preferred embodiment of the present invention, the resulting resistance of the PFC circuit, referred to above as its dynamic resistance, is used to effectively damp resonant circuits caused by the combination of grid impedance and EMI capacitors or capacitors arranged downstream of the PFC circuit's bridge rectifier. In this way, the grid can typically be damped approximately seven times better than using the equivalent static resistance of a prior art PFC circuit. Depending on where the power supply unit's input voltage is tapped to generate the reference signal, the PFC circuit's dynamic resistance can be used to damp different resonant circuits. If, for example, the input voltage is tapped downstream of the rectifier, the PFC circuit's dynamic resistance damps resonant circuits including capacitors downstream of the rectifier.

Although such grid damping is not required in every topology, it becomes desirable or even necessary if the grid impedance includes high series inductances such as introduced by, for example, a transformer.

The invention further has the advantage that a smooth current shape can be achieved, thereby reducing the rms current (root mean square current) in the power grid.

The solution of the invention with regard to the control circuit is specified by the features of claim 11. According to the invention, the control circuit comprises means for generating the reference signal such that the magnitude of the lower harmonic components of the input current of the power supply unit is increased and the magnitude of the higher harmonic components of the input current is reduced.

The present invention is best suited for a switched-mode power supply, such that the control circuit is preferably adapted to generate a reference signal for a current regulator of a PFC circuit of the switched-mode power supply unit.

In a preferred embodiment, the control circuit is adapted to generate the reference signal _Iref as described above, ie as a sinusoidal signal having the angular frequency of the AC grid to which the power supply unit is connected.

And in another preferred embodiment, the control circuit is adapted to generate the value I ₀ in dependence on the sine of the current conduction angle _θ , in particular as a negative value I ₀ =−Î*sin( ₀ ), also as described above.

Further advantageous embodiments and combinations of features emerge from the following detailed description and the claims as a whole.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings for explaining the embodiments show:

FIG1 shows a schematic depiction of a PFC circuit according to the invention,

FIG2 shows a more detailed schematic depiction of a PFC circuit according to the invention,

3 shows a schematic depiction of the input current of a buck PFC connected to a two-phase grid for a standard control circuit and a control circuit according to the invention with two different current conduction angles,

4 shows a schematic depiction of the input current of a buck PFC connected to a three-phase grid for a standard control circuit and a control circuit according to the invention with two different current conduction angles,

Figure 5 shows some simulation waveforms of a standard PFC circuit.

FIG6 shows a schematic depiction of a portion of the frequency spectrum of the input current of the standard PFC circuit of FIG5 ,

FIG7 shows some simulation waveforms of a PFC circuit according to the present invention with a current conduction angle of π/4,

FIG8 shows a schematic depiction of a portion of the frequency spectrum of the input current of the standard PFC circuit of FIG7 ,

FIG9 shows some simulation waveforms of a PFC circuit according to the present invention with a current conduction angle π/3,

FIG10 shows a schematic depiction of a portion of the frequency spectrum of the input current of the standard PFC circuit of FIG9 ,

Figure 11 shows a schematic depiction of a standard PFC circuit,

FIG12 shows a schematic depiction of a PFC circuit according to the present invention,

13 shows a schematic depiction of the input resistance of a buck PFC connected to a two-phase grid for a standard control circuit and a control circuit according to the invention with two different current conduction angles,

14 shows a schematic depiction of the input resistance of a buck PFC connected to a three-phase grid for a standard control circuit and a control circuit according to the invention with two different current conduction angles,

Figure 15 shows some simulation waveforms of another standard PFC circuit.

FIG. 16 shows some simulated waveforms of a PFC circuit according to the present invention corresponding to the standard PFC circuit of FIG. 15 but having a current conduction angle of π/4, and

FIG. 17 shows some simulated waveforms of a PFC circuit according to the present invention corresponding to the standard PFC circuit of FIG. 15 but having a current conduction angle of π/3.

In the drawings, the same components are given the same reference numerals.

DETAILED DESCRIPTION

FIG1 shows a schematic depiction of a PFC circuit 10 according to the present invention. The first block represents a power grid 1 to which the PFC circuit 10 is connected. The second block represents an input filter 2, the third block represents a bridge rectifier 3, the fourth block represents a converter 4, and the fifth block represents a control circuit 5 that generates a reference signal for the input current of the converter 4.

FIG2 shows a more detailed schematic depiction of the PFC circuit 10 shown in FIG1 . The power grid 1 has three phase lines, a neutral connector N, which is optional and is a protective earth conductor PE. The phase lines have line-to-neutral voltages V1, V2, V3, and impedances L1, L2, and L3 and resistors R1, R2, R3 represent the grid impedance.

The input from grid 1 is fed into input filter 2. Input filter 2 comprises three X-capacitors C1, C2, and C3 connected between each phase line and the protective earth conductor PE. Furthermore, a Y-capacitor C5 is present within the protective earth conductor PE. Inductors L4, L5, and L6 represent the leakage inductance of the common-mode choke, and resistors R9, R10, and R11 represent the series resistance of the common-mode choke.

The bridge rectifier 3 includes six diodes D1, D2, D3, D4, D5, and D6 arranged in a full-bridge configuration. A capacitor C4 is connected across the output of the bridge rectifier 3 to short-circuit the current at the switching frequency of the converter 4. The rectifier output, i.e., the rectified voltage V _rec, is provided across the capacitor C4. The converter 4 can include any type of converter, such as, for example, a linear or switch-mode converter. Examples include a buck converter, a boost converter, an inverter, a flyback converter, an LLC resonant converter, or other converters with or without a transformer. Generally speaking, the converter 4 can include any type of electronically controlled load. Therefore, at least one control signal, such as a PWM signal or a reference signal, must be provided to such an electronically controlled load. The control signal thus controls the power transfer from the input to the output of the converter 4, or vice versa.

In the example shown in FIG2 , the converter 4 comprises a switch-mode converter 4.1 which receives a rectified voltage V _rec at its input and provides an output voltage V _out at its output. The switching of the switch-mode converter 4.1 is controlled by a current controller which receives a reference current I _ref to a target value of the input current of the converter 4. This reference signal is provided by a control circuit 5 which generates the reference current I _ref according to the following formula:

As mentioned above.

To generate the reference signal I _ref according to this formula, the control circuit 5 comprises, for example, a digital controller such as a microprocessor (preferably a digital signal processor DSP). However, the generation of the reference signal can also be done by analog components, which however will lead to a significant increase in the complexity and cost of the subsequent control circuit.

Figure 3 shows a comparison of input current shapes for a buck PFC converter connected to a two-phase grid in the interval between 0° (0°) and π (180°). Line 11 shows the current shape when the buck PFC is controlled by a standard control circuit. Because the buck PFC behaves like an ohmic resistor, the current starts at zero at 0°, is sinusoidal, and ends at zero at 180°. Line 12 shows the current shape for a buck PFC controlled by the control circuit according to the present invention with a current conduction angle of π/4. Therefore, the sinusoidal current starts at 45° and ends at 135°. Line 13 shows the current shape for a buck PFC controlled by the control circuit according to the present invention with a current conduction angle of π/3. Therefore, the sinusoidal current starts at 60° and ends at 120°.

In the case of two-phase operation, where the voltage between the two phases is 400 Vrms and the input power is 1500 W, the current shown in line 11 has a peak value slightly above 12 A. The vertical scale of the diagram in FIG3 is therefore two A per division.

FIG4 shows a comparison of input current shapes for a buck PFC connected to a three-phase grid. Line 14 shows the current shape when the buck PFC is controlled by a standard control circuit. Line 15 shows the current shape for a buck PFC controlled by a control circuit according to the present invention with a current conduction angle of π/4, and line 16 shows the current shape for a buck PFC controlled by a control circuit according to the present invention with a current conduction angle of π/3.

As can be seen, in three-phase operation, all of these currents begin at 60° and end at 120°, regardless of their instantaneous height. Although between 0° and 180° are three segments, each with a width of 60°, the same current waveform will be repeated three times, i.e. every 60°. However, only the middle segment of the three segments is shown in FIG2 .

Again, the vertical scale of the chart in Figure 4 is two A's per division.

Figure 5 shows the power and current waveforms resulting from a simulation of a PFC circuit with a standard control circuit (i.e., with I ₀ being 0 A). The power grid consists of three phase lines with a phase-to-phase voltage of 400 Vrms and a frequency of 50 Hz, is symmetrical, and does not include a neutral line. The simulated input power is approximately 1500 W. In this example, the standard PFC circuit can be considered a purely resistive load with a resistance of approximately 195 Ω.

For simplicity, only the current waveform 21 and power waveform 20 of a single phase line are shown. The power and current waveforms of the other two phase lines are identical, except for offsets of π/3 and 2π/3, respectively. Since the horizontal scale of Figure 5 is 5 ms (milliseconds) per segment, the power and current waveforms of the other two phase line waveforms are offset by 3 1/3 ms. The vertical scale of the upper portion of Figure 5 with the power waveform 20 is 0.2 kW per segment, and the vertical scale of the lower portion of Figure 5 with the current waveform 21 is 1 A per segment. As can be seen, the current waveform 21 and the power waveform 20 exhibit several transitions. Furthermore, the lower portion of Figure 5 shows the cumulative current waveform 22, which is the sum of the individual current waveforms of all three phase lines. Its peak value is approximately 2.9 A.

FIG6 shows a portion of a discrete spectrum 23 of the resulting input current of a PFC circuit with a standard control circuit. The number of harmonics is shown on the horizontal scale, and the harmonic content in mA on the vertical scale. Line 24 shows the limits for each harmonic according to the aforementioned IEC standard 61000-3-2 for Class A equipment.

As can be seen, the contents of the thirteenth harmonic and below do not reach the corresponding possible maximum values, whereas the harmonics from number 17 onwards do or almost do reach their possible maximum values.

Figure 7 shows the same simulation waveforms for a comparable PFC circuit including the present invention, where the current conduction angle is chosen to be π / 4. The resulting value for the value of I ₀ is approximately -7.9 A and the resistance of the PFC circuit is approximately 51 ohms.

Again, only a single power waveform 20 is shown in the upper portion of FIG. 7 , and the current waveform 21 of a single phase line is shown in the lower portion of FIG. The power and current waveforms of the other two phase lines are identical, except for being offset by π/3 and 2π/3, respectively. The vertical scale of the upper portion of FIG. 7 with the power waveform 20 is 0.4 kW per sector, and the vertical scale of the lower portion of FIG. 7 with the current waveform 21 is 1 A per sector. Compared to the current and power waveforms of the standard PFC circuit shown in FIG. 5 , the transitions in both the current waveform 21 and the power waveform 20 are reduced.

7 shows an accumulated current waveform 22. Its peak value is approximately 3.3A.

Figure 8 again shows a portion of the discrete spectrum 23 of the input current of the PFC circuit of Figure 7. In this case, the content of the fifth harmonic increases and the content of the eleventh harmonic remains unchanged. The content of the other harmonics decreases.

Figure 9 again shows the same simulation waveforms for a comparable PFC circuit including the present invention, where the current conduction angle is chosen to be π/3. The resulting value for the value of I ₀ is approximately -26.6 A and the resistance of the PFC circuit is approximately 18 ohms.

Again, only a single power waveform 20 is shown in the upper portion of FIG. 9 , and the current waveform 21 of a single phase line is shown in the lower portion of FIG. The power and current waveforms of the other two phase lines are identical, except for being offset by π/3 and 2π/3, respectively. The vertical scale of the upper portion of FIG. 9 with the power waveform 20 is 0.4 kW per division, and the vertical scale of the lower portion of FIG. 9 with the current waveform 21 is 1 A per division. As can be seen, the transitions in both waveforms have almost disappeared, and the result is a very smooth, almost sinusoidal half-wave.

Furthermore, the accumulated current waveform 22 in the lower portion of FIG. 9 has a peak value of approximately 4.1A.

FIG10 again shows a portion of the discrete spectrum 23 of the input current of the PFC circuit of FIG9 . In this case, compared to the spectrum of the standard PFC circuit of FIG5 , the fifth harmonic is further increased, and the seventh harmonic is also increased. Also in this case, the eleventh harmonic remains unchanged. However, compared to the spectrum of the standard PFC circuit, all other harmonics are reduced.

The following was found:

Current shaping is mainly a function of the current conduction angle

The eleventh and thirteenth harmonics are essentially unaffected by this current shaping; they remain more or less constant at the same power level and input voltage; therefore, they define up to the maximum power level at which this technique can be utilized

The higher the current conduction angle is chosen (between π/2 and π/4), the higher the higher-order harmonics become.

At the current conduction angle π/4

- The seventeenth harmonic is the most critical one

- The fifth and seventh harmonics are very far from their limits

• The lower the current conduction angle (between π/4 and π/3), the higher the lower order harmonics become and the lower the higher order harmonics become.

At the current conduction angle π/3

- The fifth harmonic is the most critical one

- The 17th and 19th harmonics are very far from their limits

• The optimum current conduction angle for this example appears to be somewhere between π/4 and π/3, possibly around 7/12π; in this case both the fifth and seventeenth harmonics are very close to their limits and the maximum input power is probably between 2000W and 2500W.

Figure 11 shows a schematic, rather simplified depiction of a standard PFC circuit 31. Generally, any power line can be represented by a voltage source 32 and an impedance. In our case, the line impedance is assumed to be primarily formed by the inductance L (e.g., caused by the transformer) and the shunt capacitance C. The series resistance of the grid impedance is neglected. Any standard PFC circuit can then be replaced by a constant ohmic resistor 33. This means that the current immediately follows the voltage applied by the voltage source 32.

FIG12 shows a corresponding schematic and simplified depiction of a PFC circuit 35 according to the present invention. The power line is again represented by a voltage source 32, a line impedance inductor L, and a shunt capacitor C. The PFC circuit 35 can then be replaced by a dynamic resistor 35. In this case, the current does not immediately follow the voltage applied by the voltage source 32. The resulting current follows the formula shown above, with the only difference being the appropriate offset current, referred to above as _I0 .

Figure 13 shows a schematic depiction of the input resistance of a buck PFC connected to a two-phase grid for different configurations. The horizontal scale shows the input current in amperes with a scale of 2A per division, and the vertical scale shows the input voltage in volts with a scale of 500V per division.

Line 41 shows the input resistance for a standard control circuit, line 42 shows the input resistance for a control circuit according to the invention with a current conduction angle π/4, and line 43 shows the input resistance for a control circuit according to the invention with a current conduction angle π/3.

As shown, line 41, representing the input resistance of a standard PFC circuit, behaves like an ohmic resistor and passes through the origin. However, lines 42 and 43 do not pass through the origin but are compensated so that current flow only begins at input voltage levels of approximately 450 V and 500 V, respectively. Furthermore, it can be seen that the resistance value is significantly reduced in the PFC circuit according to the present invention.

Figure 14 shows a corresponding depiction of a buck PFC but here with its input resistance connected to a three-phase grid. The horizontal and vertical scales are the same as in Figure 13.

Line 46 shows the input resistance for a standard control circuit, line 47 shows the input resistance for a control circuit according to the invention with a current conduction angle π/4, and line 48 shows the input resistance for a control circuit according to the invention with a current conduction angle π/3.

Again, line 46 of the input resistance of the standard PFC circuit behaves like an ohmic resistor and passes through the origin, and lines 47 and 48 compensate at voltage levels of approximately 450 V and 500 V, respectively. Also in this three-phase configuration, the resistance value is significantly reduced in the PFC circuit according to the present invention.

It can be said that the lower the input resistance of the PFC circuit, the greater the attenuation of the LC circuit shown in Figures 11 and 12.

Figures 15 to 17 illustrate the effects of this attenuation in different configurations. In the basic configuration used for simulation, the grid consists of three phase lines with a phase-to-phase voltage of 400 Vrms and a frequency of 50 Hz, is symmetrical, and does not include a neutral line. The simulated input power is approximately 1500 W. The PFC circuit corresponds to the left portion of PFC circuit 10 shown in Figure 2 , with the grid inductance of each line ( L1, L2, L3 ) being 2.5 mH (millihenry), the X-capacitors ( C1, C2, C3 ) having a value of 680 nF (nanofarad), and capacitor C4 having a value of 4 μF (microfarad). The horizontal scale shows time in milliseconds, and the vertical scale shows current in amperes.

Figure 15 shows the line current 51 for a standard PFC circuit (i.e., where the value _I0 is 0 A). Again, the standard PFC circuit can be considered a purely resistive load with a resistance of approximately 195 Ω. In this configuration, two resonant circuits exist. One consists of twice the line inductance L and a series connection of two X-capacitors, resulting in a 260 μs (microsecond) period at a frequency of 3.85 kHz (kilohertz). The other consists of twice the line inductance L and capacitor C4 after the bridge rectifier, resulting in an 890 μs period at a frequency of 1.12 kHz. In the case of a standard PFC circuit, neither of these resonant circuits exhibits damping.

Furthermore, the accumulated input current, ie the sum of the individual current waveforms of all three phase lines, is shown as line 52 .

FIG. 16 shows the line current 54 for a PFC circuit according to the present invention with a current conduction angle of π/4, where the value I ₀ is approximately −7.9 A and the resistance of the PFC circuit is approximately 51 ohms.

As can be seen, the ringing of the first resonant circuit cannot be damped if the phase is not conducting current, such as during three-phase operation because the load is not present. However, the ringing caused by the second resonant circuit is damped to a certain extent. The current waveform is approximately sinusoidal with only small ringing. This is due to the fact that it only occurs when the diodes of the bridge rectifier are conducting. Line 55 again shows the accumulated input current for all three phases.

FIG. 17 shows the line current 57 for a PFC circuit according to the present invention with a current conduction angle π/3, where the value I ₀ is approximately −26.6 A and the resistance of the PFC circuit is approximately 18 ohms.

Again, the oscillations of the first resonant circuit are not damped if the phase does not conduct current. However, in this case, the oscillations caused by the second resonant circuit are effectively damped. The resulting accumulated input current, shown as line 58, is an almost perfect rectified sine wave.

It was found that the attenuation is affected by the current conduction angle. The smaller the angle, the greater the attenuation.

Furthermore, it was found that the harmonics can be attenuated even better if the effect of the capacitor (C4) connected directly at the DC-side of the bridge rectifier is compensated by a slight phase shift of the current reference signal. Furthermore, it was found that the phase shift of the current waveform is a function only of the capacitor value.

In summary, it should be noted that the present invention makes it possible to provide a method and a control circuit for generating a reference signal for a current regulator of a PFC circuit of a power supply unit, wherein the current drawn from the grid has a reduced harmonic content and is therefore suitable for a wide power range. Furthermore, the present invention makes it possible to efficiently damp the resonant circuit caused by the grid impedance in combination with the capacitance of the PFC circuit.

Claims (12)

1. A method for generating a reference signal _Iref for a current regulator in a PFC circuit of a power supply unit, wherein a standard reference signal is generated as a sinusoidal signal _Is = having an angular frequency of the AC power grid to which the power supply unit is connected and a standard value Î _s , wherein the reference signal _Iref is generated as , Where ₀ is the current conduction angle, and where, in order to achieve the same output power for power supply units using a standard reference signal Î _s , the magnitude of the reference signal Î is generated by multiplying it by a factor f _ref. , This results in an increase in the magnitude of the lower harmonic component of the input current and a decrease in the magnitude of the higher harmonic component of the input current in the power supply unit compared to a power supply using a standard reference signal. The characteristic is that the factor f _ref is determined as , Where _s1 and _s2 are the power transfer angles when using the standard reference signal _Is , and where ₁ and ₂ are the power transfer angles of the power supply unit using the reference signal _Iref . 2. The method of claim 1, wherein the reference signal is based on a) Before the bridge rectifier in the PFC circuit b) After the bridge rectifier in the PFC circuit, or c) Directly at the input of the power supply unit It is generated by the voltage that is connected. 3. The method of any one of claims 1 to 2, wherein the current conduction angle _θ is selected to be between 0 and π/2. 4. The method of claim 3, wherein the current conduction angle _θ is selected between π/5 and 2π/5. 5. The method of any one of claims 1 to 2, wherein the reference signal _Iref is set to zero when it becomes negative. 6. The method of any one of claims 1 to 2, wherein the current conduction angle _θ is selected such that the input current starts at zero. 7. The method of any one of claims 1 to 2, wherein the resulting resistance of the PFC circuit is used to attenuate the resonant circuit caused by the mains impedance combined with the capacitance of the power supply unit. 8. The method as described in any one of claims 1 to 2, wherein the resulting resistance of the PFC circuit is used to attenuate the resonant circuit caused by the mains impedance combined with the capacitance of a capacitor: a) An EMI capacitor located between two conductors or between the neutral conductor and a conductor in the input filter of a power supply, or b) A capacitor placed downstream of the bridge rectifier in the PFC circuit. 9. A control circuit for generating a reference signal for a current regulator in a PFC circuit of a power supply unit, wherein a standard reference signal is generated as a sinusoidal signal _Is = , having an angular frequency of the AC power grid to which the power supply unit is connected and a standard value Î _s , comprising generating the reference signal as , Components, Where ₀ is the current conduction angle, and where, in order to achieve the same output power for power supply units using a standard reference signal Î _s , the magnitude of the reference signal Î is generated by multiplying it by a factor f _ref. , This results in an increase in the magnitude of the lower harmonic component of the input current and a decrease in the magnitude of the higher harmonic component of the input current in the power supply unit compared to a power supply using a standard reference signal. The feature is that the component that generates the reference signal _Iref is adapted to determine the factor _fref as , Where _s1 and _s2 are the power transfer angles when using the standard reference signal _Is , and where ₁ and ₂ are the power transfer angles of the power supply unit using the reference signal _Iref . 10. The control circuit of claim 9, adapted to generate a reference signal for a current regulator of the PFC circuit of a switch-mode power supply unit. 11. A PFC circuit for a switch-mode power supply unit, the PFC circuit including a current regulator comprising control circuitry for generating a reference signal _Iref for the current regulator according to any one of claims 9 to 10. 12. A switch-mode power supply unit comprising the PFC circuit according to claim 11.