HK1225165B - Electronic component, connector, connector production method, and electronic component connecting method - Google Patents

Description

Electronic component, connector, method for manufacturing connector, and method for connecting electronic components

Technical Field

The present invention relates to an electronic component connected to a circuit substrate via an adhesive, a connector connecting the electronic component on the circuit substrate, a method for manufacturing the connector, and a method for connecting the electronic component. In particular, it relates to an electronic component having a plurality of bump electrodes asymmetrically arranged on the mounting surface of the circuit substrate, a connector connecting the electronic component, a method for manufacturing the connector, and a method for connecting the electronic component.

This application claims priority based on Japanese Patent Application No. 2013-264377 filed in Japan on December 20, 2013, and Japanese Patent Application No. 2014-162480 filed in Japan on August 8, 2014, which are hereby incorporated by reference into this application.

Background Art

Connectors for connecting electronic components such as IC chips and LSI chips to the circuit boards of various electronic devices have long been available. In recent years, to achieve finer pitches and reduce weight and thickness, IC chips or LSI chips with bumps arranged on their mounting surfaces have been used as electronic components in various electronic devices. Furthermore, these electronic components, such as IC chips, are directly mounted on the circuit boards using so-called COB (chip on board) or COG (chip on glass) methods.

In COB connection or COG connection, the IC chip is thermally pressed onto the terminal portion of the circuit board via an anisotropic conductive film. Anisotropic conductive film is a conductive film made by mixing conductive particles into a thermosetting adhesive resin. Two conductors are heated and pressed together to achieve electrical conduction between the conductors using the conductive particles, and the mechanical connection between the conductors is maintained by the adhesive resin. As the adhesive constituting the anisotropic conductive film, a highly reliable thermosetting adhesive is usually used. On the other hand, a connection method using a photocuring resin or a combination of heat curing and photocuring is also used. However, when applying pressure using a tool, it is estimated that the same problems as thermosetting adhesives may be involved.

As shown in FIG6(A), an IC chip 50 with bumps has an input bump region 52 formed on the mounting surface of a circuit board, where input bumps 51 are arranged in a single row along one side edge 50a, and an output bump region 54 is provided, where output bumps 53 are arranged in two rows along a side edge 50b opposite one side edge 50a. The bump arrangement varies depending on the type of IC chip, but conventional IC chips with bumps are generally configured such that the number of output bumps 53 is greater than the number of input bumps 51, the area of output bump region 54 is wider than the area of input bump region 52, and the shape of input bumps 51 is larger than that of output bumps 53.

In COG mounting, as shown in FIG6B , IC chip 50 is mounted on electrode terminals 57 of circuit board 56 via anisotropic conductive film 55. Then, thermocompression joint 58 heats and presses IC chip 50 from above. The heat and pressure applied by thermocompression joint 58 melts the binder resin in anisotropic conductive film 55 and flows between the I/O bumps 51 and 53 and the electrode terminals 57 of circuit board 56. The binder resin then thermally cures, sandwiching conductive particles between the I/O bumps 51 and 53 and the electrode terminals 57 of circuit board 56. This electrically and mechanically connects IC chip 50 to circuit board 56.

Prior art literature

Patent Literature

Patent Document 1: Japanese Patent Application Laid-Open No. 2004-214373.

Summary of the Invention

Problems to be solved by the invention

As described above, in an electronic component such as an IC chip 50 with bumps, the input bumps 51 and output bumps 53 formed on the mounting surface have different bump arrangements and sizes, and there is a difference in area between the input bump region 52 and the output bump region 54. Furthermore, the electronic component has the input bump region 52 and the output bump region 54 arranged asymmetrically on the mounting surface.

Therefore, in the existing COB connection or COG connection, the pressing force applied by the thermocompression joint 58 to the input bump 51 and the output bump 53 will be uneven. For example, in the output bump area 54, a pressure difference can be generated between the output bump 53 arranged on the other side edge 50b and the output bump 53 arranged on the inner side of the mounting surface.

In addition, by making the pressure generated by the hot pressing joint 58 heavier on the inner edges of the input bump area 52 and the output bump area 54, in the output bump area 54, the pressure on the output bump 53 arranged on the other side of the edge 50b becomes weaker, and the conductive particles are not pressed in enough, which may cause poor conduction.

To address this issue, so-called dummy bumps, not used for signal input and output, are formed to distribute and even out the stress applied to the entire surface of the IC chip by the thermocompression joint. However, this method also increases technical difficulty due to the increased number of stress points. Furthermore, forming dummy bumps increases the number of manufacturing hours for electronic components and the required material costs. Therefore, a structure that does not use dummy bumps is desirable.

Therefore, the object of the present invention is to provide an electronic component, a connector, a method for manufacturing a connector, and a connection method that can eliminate the pressure difference caused by a thermocompression joint and improve connection reliability in an electronic component in which the input bump area and the output bump area have an area difference and are asymmetrically arranged.

Solutions to Problems

In order to solve the above-mentioned problems, the electronic component involved in the present invention is provided with an output bump area in which output bumps are arranged near one side of a pair of opposite side edges, and an input bump area in which input bumps are arranged near the other side of the above-mentioned pair of side edges. The above-mentioned output bump area and the above-mentioned input bump area have different areas and are arranged asymmetrically. In the above-mentioned output bump area or the above-mentioned input bump area, a relatively large area is formed inward from the above-mentioned one side edge or the other side edge at a distance of more than 4% of the width between the above-mentioned pair of side edges.

In addition, the connector involved in the present invention arranges the electronic component on the circuit substrate via an adhesive, and connects the above-mentioned electronic component to the above-mentioned circuit substrate by applying pressure with a pressurizing tool. In the above-mentioned connector, an output bump area in which output bumps are arranged near one side of a pair of opposite side edges is provided on the mounting surface of the above-mentioned electronic component on the above-mentioned circuit substrate, and an input bump area in which input bumps are arranged near the other side of the above-mentioned pair of side edges is provided. The above-mentioned output bump area and the above-mentioned input bump area have different areas and are arranged asymmetrically on the above-mentioned mounting surface. In the above-mentioned output bump area or the above-mentioned input bump area, a relatively large area is formed inward from the above-mentioned one side edge or the other side edge at a distance of more than 4% of the width between the above-mentioned pair of side edges.

In addition, the manufacturing method of the connector involved in the present invention is to arrange the electronic component on the circuit substrate via an adhesive, and connect the above-mentioned electronic component to the above-mentioned circuit substrate by applying pressure with a pressing tool. In the manufacturing method of the above-mentioned connector, an output bump area is provided on the mounting surface of the above-mentioned electronic component on the above-mentioned circuit substrate, in which output bumps are arranged near one side of a pair of opposing side edges, and an input bump area is provided near the other side of the above-mentioned pair of side edges, in which input bumps are arranged. The above-mentioned output bump area and the above-mentioned input bump area have different areas and are arranged asymmetrically on the above-mentioned mounting surface. In the above-mentioned output bump area or the above-mentioned input bump area, a relatively large area is formed inward from the above-mentioned one side edge or the other side edge at a distance of more than 4% of the width between the above-mentioned pair of side edges.

In addition, the connection method involved in the present invention is to arrange the electronic component on the circuit substrate via an adhesive, and connect the above-mentioned electronic component to the above-mentioned circuit substrate by applying pressure with a pressurizing tool. In the above-mentioned electronic component connection method, the mounting surface of the above-mentioned electronic component on the above-mentioned circuit substrate is provided with an output bump area in which output bumps are arranged near one side of a pair of opposite side edges, and is provided with an input bump area in which input bumps are arranged near the other side of the above-mentioned pair of side edges. The above-mentioned output bump area and the above-mentioned input bump area have different areas and are arranged asymmetrically on the above-mentioned mounting surface. In the above-mentioned output bump area or the above-mentioned input bump area, a relatively large area is formed inward from the above-mentioned one side edge or the other side edge at a distance of more than 4% of the width between the above-mentioned pair of side edges.

In order to solve the above-mentioned problems, the electronic component involved in the present invention comprises: a rectangular first bump area, forming a bump column along a first side edge; and a rectangular second bump area, forming a bump column along a second side edge opposite to the first side edge, the distance in the width direction of the first bump area is greater than the distance in the width direction of the second bump area, and the midpoint between the outer sides of the bump areas in the width direction and the outer sides of the second bump area in the width direction is located on the second side edge side compared to the midpoint between the side edges between the first side edge and the second side edge.

In addition, the connector involved in the present invention includes an electronic component and a circuit substrate connected to the circuit component via an adhesive, the electronic component includes: a rectangular first bump area, forming a bump row along a first side edge; and a rectangular second bump area, forming a bump row along a second side edge opposite to the first side edge, the distance in the width direction of the first bump area is greater than the distance in the width direction of the second bump area, and the midpoint between the outer sides of the bump areas in the width direction and the outer sides of the second bump area in the width direction is located on the second side edge compared to the midpoint between the side edges between the first side edge and the second side edge.

In addition, the manufacturing method of the connector involved in the present invention arranges the electronic component on the circuit substrate via an adhesive, and connects the above-mentioned electronic component to the above-mentioned circuit substrate by applying pressure with a pressurizing tool, and the electronic component comprises: a rectangular first bump area, forming a bump column along the first side edge; and a rectangular second bump area, forming a bump column along the second side edge opposite to the first side edge, the distance in the width direction of the first bump area is greater than the distance in the width direction of the second bump area, and the midpoint between the outer sides of the bump areas in the width direction and the outer sides of the second bump area in the width direction is located on the second side edge side compared to the midpoint between the side edges between the first side edge and the second side edge.

In addition, the connection method involved in the present invention arranges the electronic component on the circuit substrate via an adhesive, and connects the above-mentioned electronic component to the above-mentioned circuit substrate by applying pressure with a pressurizing tool. The electronic component comprises: a rectangular first bump area, forming a bump column along the first side edge; and a rectangular second bump area, forming a bump column along the second side edge opposite to the first side edge, the distance in the width direction of the first bump area is greater than the distance in the width direction of the second bump area, and the midpoint between the outer sides of the bump areas in the width direction and the outer sides of the second bump area in the width direction is located on the second side edge side compared to the midpoint between the side edges between the first side edge and the second side edge.

Effects of the Invention

According to the present invention, a large bump area is formed inward from the side edge at a predetermined ratio relative to the width of the mounting surface. This allows the pressure gradient across the width of the bump area to be gradually uniform, preventing insufficient pressing force from the thermocompression joint at the side edge. As a result, the electronic component's bumps at the side edge reliably hold the conductive particles between them and the electrode terminals formed on the circuit board, ensuring electrical continuity.

According to the present invention, since the midpoint between the outer sides of the width direction of the first bump region and the outer sides of the width direction of the second bump region is located closer to the second side edge than the midpoint between the first side edge and the second side edge, the pressure gradient formed across the width direction of the bump region is gradually uniformed, thereby preventing the occurrence of insufficient pressing force of the thermocompression joint on the side edge. As a result, the conductive particles can be reliably held in the bumps on the side edge, thereby achieving excellent conductivity.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a plan view showing a mounting surface of an electronic component according to the present invention.

FIG. 2 is a cross-sectional view showing a connection body in which electronic components are connected.

FIG. 3 is a plan view showing a mounting surface of an electronic component according to the present invention in which dummy bumps are provided.

FIG4 is a cross-sectional view showing an anisotropic conductive film.

FIG5 is a cross-sectional view showing a mounting surface in the width direction of the electronic component according to the present invention.

FIG6(A) is a plan view showing a mounting surface of a conventional electronic component, and FIG6(B) is a cross-sectional view showing a mounted state.

DETAILED DESCRIPTION

The electronic components, connectors, methods for manufacturing connectors, and methods for connecting connectors to which the present invention pertains are described in detail below with reference to the accompanying drawings. The present invention is not limited to the following embodiments, and various modifications are apparent without departing from the gist of the present invention. The accompanying drawings are schematic, and the proportions of various dimensions may differ from those in reality. Specific dimensions, etc., should be determined with reference to the following description. Furthermore, it should be understood that the accompanying drawings may contain portions with different dimensional relationships or proportions.

[First embodiment]

First, the first embodiment of the present invention will be described. The electronic component to which the present invention applies is an electronic component, such as a packaged electronic component such as a driver IC or system LSI, that is placed on a circuit board via an adhesive and connected to the circuit board by applying pressure using a thermocompression joint. The following description uses IC chip 1 as an example of an electronic component.

As shown in FIG1 , the mounting surface 2 of an IC chip 1, which is connected to a circuit substrate, is generally rectangular in shape. An output bump region 4, where output bumps 3 are arranged, and an input bump region 6, where input bumps 5 are arranged, are formed along a pair of opposing side edges 2a and 2b, which form the longitudinal direction. In IC chip 1, output bump region 4 is formed on one side edge 2a of mounting surface 2, and input bump region 6 is formed on the other side edge 2b of mounting surface 2. Thus, IC chip 1 has output bump region 4 and input bump region 6 formed separately across the width of mounting surface 2.

In the output bump region 4, for example, a plurality of output bumps 3 formed in the same shape are arranged in three rows in a staggered pattern along the length of the mounting surface 2. Furthermore, in the input bump region 6, for example, a plurality of input bumps 5 formed in the same shape are arranged in a row along the length of the mounting surface 2. Furthermore, the input bumps 5 are formed larger than the output bumps 3. Thus, in the IC chip 1, the output bump region 4 and the input bump region 6 have an area difference and are asymmetrically arranged on the mounting surface 2. Furthermore, it is preferable that the output bumps 3 arranged in the output bump region 4 are formed to be the same size. Similarly, it is preferable that the input bumps 5 arranged in the input bump region 6 are formed to be the same size.

[Offset of large bump areas]

In the IC chip 1 according to the present invention, the output bump region 4 is formed inward from one side edge 2a at a predetermined ratio relative to the IC width W extending between one side edge 2a and the other side edge 2b. This prevents uneven pressing force within the output bump region 4 when the IC chip 1 is heated and pressed against the circuit board 14 using a thermocompression joint 17, described later. Appropriate pressing force can also be applied to the output bumps 3 arranged on the side of the one side edge 2a.

Specifically, because the output bump regions 4 and input bump regions 6 of the IC chip 1 have an area difference and are asymmetrically arranged on the mounting surface 2, when pressure is applied to the entire mounting surface 2 by the thermocompression joint 17, the output bumps 3 are arranged in multiple rows, creating a pressure gradient whereby the pressure is stronger at the inner edge of the output bump region 4, which is formed over a large area across the width, facing the input bump region 6, and weaker at one side edge 2a of the mounting surface 2. This results in insufficient pressure on the output bumps 3 arranged on the side edge 2a. This may result in insufficient penetration of the conductive particles, and may increase the on-resistance of the output bumps 3, particularly in the outer edge region of the bumps.

Therefore, IC chip 1 forms output bump region 4 inward from one side edge 2a at a predetermined ratio relative to the width of mounting surface 2. This allows the pressure gradient formed across the width of output bump region 4 to be gradually uniform, thereby preventing insufficient pressing force from thermocompression joint 17 on the side of one side edge 2a. Consequently, IC chip 1 reliably holds conductive particles between output bump 3 on the side of one side edge 2a and electrode terminals 15 formed on circuit board 14, ensuring conductivity.

The distance A from the one side edge 2a to the output bump area 4 is preferably at least 4% of the IC width W between the opposing side edges 2a and 2b of the mounting surface 2. By forming the output bump area 4 inward from the one side edge 2a at a distance of at least 4% of the IC width W, even when the thermocompression joint 17 applies pressure evenly to the mounting surface 2, where the output bump area 4 and input bump area 6 are asymmetrically arranged with a difference in area, the pressing force is sufficiently transmitted to the output bump 3 arranged on the first side edge 2a side. However, if the distance A from the one side edge 2a to the output bump 3 is less than 4% of the IC width W, the pressing force of the thermocompression joint 17 may not be sufficiently transmitted to the output bump 3 on the one side edge 2a side, potentially causing poor electrical continuity due to insufficient penetration of the conductive particles.

If the distance A is too large, the pressure uniformity across the entire surface of the IC chip 1 may be disrupted, potentially causing pressure imbalance. Therefore, the distance A is preferably within 30%, more preferably within 20%, and even more preferably within 15%.

[Distance A > Distance B]

Furthermore, in the IC chip 1, it is preferred that the distance A from one side edge 2a of the relatively large output bump region 4 be longer than the distance B from the other side edge 2b of the input bump region 6. Specifically, if the distance B from the other side edge 2b of the relatively small input bump region 6 is longer than the distance A from one side edge 2a of the large output bump region 4, the pressure gradient across the width of the output bump region 4 increases, hindering the elimination of insufficient indentation of the conductive particles in the output bumps 3 on the side of the one side edge 2a.

In addition, since the input bumps 5 are arranged in a row, in the input bump area 6 with a relatively small area, due to the area difference with the output bump area 4 and the asymmetric configuration, the possibility of insufficient pressing due to uneven pressing force of the hot pressing joint 17 will be reduced, and there will be no problem even if the distance B from the other side edge 2b of the mounting surface 2 is shorter.

[Offset the large input bump area 6]

Furthermore, the structure of the input/output bumps on the mounting surface 2 of the IC chip 1 can be appropriately designed. As described above, the IC chip 1 has a relatively large output bump region 4 formed by arranging a plurality of output bumps 3 along the width direction. However, conversely, the input bump region 6 can be relatively large by arranging a plurality of input bumps 5 along the width direction.

When the input bump region 6 is relatively large, the IC chip 1 forms the input bump region 6 inward from the other side edge 2b at a predetermined ratio relative to the IC width W, preferably at least 4% of the IC width W. In this case, it is preferable that the distance B from the other side edge 2b of the relatively large input bump region 6 is longer than the distance A from the one side edge 2a of the output bump region 4.

Furthermore, when input bump region 6 is formed inward from the other side edge 2b by at least 4% of IC width W, as shown in FIG2 , when flexible substrate 16 is adjacently connected to circuit substrate 14 via anisotropic conductive film 10, the connection points between input bumps 5 and electrode terminals 15 are separated from thermocompression joints 17 that thermally pressurize flexible substrate 16. This prevents degradation of connectivity due to heat dissipation from thermocompression joints 17 after IC chip 1 is connected.

[Dummy bump]

3 , IC chip 1 may also appropriately provide a dummy bump region 19 between output bump region 4 and input bump region 6 , where so-called dummy bumps 18 not used for input and output of signals are arranged.

[Adhesive]

Furthermore, an anisotropic conductive film 10 (ACF) can be preferably used as an adhesive for connecting IC chip 1 to circuit board 14. As shown in Figure 4 , an anisotropic conductive film 10 typically comprises an adhesive resin layer (adhesive layer) 13 containing conductive particles 12 formed on a release film 11 serving as a base material. As shown in Figure 2 , anisotropic conductive film 10 connects circuit board 14 and IC chip 1 by interposing adhesive resin layer 13 between electrode terminals 15 formed on circuit board 14 and IC chip 1, thereby achieving electrical continuity.

The adhesive composition of the adhesive resin layer 13 is composed of common adhesive components including, for example, a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, and the like.

The film-forming resin preferably has an average molecular weight of about 10,000 to 80,000, and particularly includes various resins such as epoxy resins, modified epoxy resins, urethane resins, and phenoxy resins. Among them, phenoxy resins are preferred from the viewpoints of film formation state and connection reliability.

The thermosetting resin is not particularly limited, and for example, commercially available epoxy resins, acrylic resins, and the like can be used.

The epoxy resin is not particularly limited, but examples thereof include naphthalene-type epoxy resins, biphenol-type epoxy resins, novolac-type epoxy resins, bisphenol-type epoxy resins, stilbene-type epoxy resins, trisphenol methane-type epoxy resins, novolac aralkyl-type epoxy resins, naphthol-type epoxy resins, dicyclopentadiene-type epoxy resins, triphenylmethane-type epoxy resins, etc. These may be used alone or in combination of two or more.

The acrylic resin is not particularly limited, and acrylic compounds and liquid acrylates can be appropriately selected depending on the intended purpose. Examples include methyl acrylate, ethyl acrylate, isopropyl acrylate, isobutyl acrylate, epoxy acrylate, ethylene glycol diacrylate, diethylene glycol diacrylate, trimethylolpropane triacrylate, dimethyloltricyclodecane diacrylate, 1,4-butanediol tetraacrylate, 2-hydroxy-1,3-diacryloxypropane, 2,2-bis[4-(acryloyloxymethoxy)phenyl]propane, 2,2-bis[4-(acryloyloxyethoxy)phenyl]propane, dicyclopentenyl acrylate, tricyclodecane acrylate, dendrimer (acryloyloxyethyl) isocyanurate, urethane acrylate, and epoxy acrylate. Furthermore, materials in which the acrylate is a methacrylate can also be used. These can be used alone or in combination of two or more.

Latent hardeners are not particularly limited, but heat-curing hardeners are examples. Latent hardeners are normally unreactive but are activated and begin to react under various initiation conditions selected according to the intended use, such as heat, light, and pressure. Heat-activated latent hardeners can be activated by generating active species (cations, anions, or free radicals) through a dissociation reaction using heat; by stably dispersing them in an epoxy resin near room temperature and then dissolving/melting them at high temperatures to initiate the curing reaction; by melting a molecular sieve-encapsulated hardener at high temperatures to initiate the curing reaction; and by melting and curing using microcapsules. Examples of heat-activated latent hardeners include imidazoles, hydrazides, boron trifluoride-amine complexes, sulfonium salts, aminated imides, polyamine salts, dicyandiamide, and their modified forms. These can be used alone or as mixtures of two or more. Known free radical polymerization initiators can be used, with organic peroxides being particularly preferred.

The silane coupling agent is not particularly limited, and examples thereof include epoxy-based, ammonia-based, mercapto/sulfide-based, and urea-based silane coupling agents. By adding a silane coupling agent, the adhesion at the interface between the organic material and the inorganic material is improved.

[Conductive particles]

The conductive particles 12 contained in the binder resin layer 13 can be any known conductive particles used in anisotropic conductive films. Specifically, examples of conductive particles include particles of various metals or metal alloys, such as nickel, iron, copper, aluminum, tin, lead, chromium, cobalt, silver, and gold; particles formed by plating metal on the surface of particles of metal oxides, carbon, graphite, glass, ceramics, or plastics; or particles formed by further plating these particles with an insulating film. In the case of resin particles plated with metal, examples of resin particles include particles of epoxy resins, phenolic resins, acrylic resins, acrylonitrile styrene (AS) resins, benzoguanamine resins, divinylbenzene resins, and styrene resins.

The adhesive composition constituting the binder resin layer 13 is not limited to the case containing a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, etc., and may be composed of any material commonly used as an adhesive composition for anisotropic conductive films.

The release film 11 supporting the adhesive resin layer 13 is made by coating a release agent such as silicone on a material such as PET (polyethylene terephthalate), OPP (oriented polypropylene), PMP (poly-4-methylpentene-1), or PTFE (polytetrafluoroethylene). This film prevents the anisotropic conductive film 10 from drying out and maintains its shape.

The anisotropic conductive film 10 can be produced by any method, but can be produced, for example, by the following method. An adhesive composition containing a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, conductive particles, etc. is prepared. The prepared adhesive composition is applied to the release film 11 using a bar coater, a coating device, or the like, and dried in an oven or the like, thereby obtaining the anisotropic conductive film 10 in which the adhesive resin layer 13 is supported on the release film 11.

In addition, in the above embodiment, as an adhesive, an adhesive film in which a thermosetting resin composition appropriately containing conductive particles 12 is formed in a film-like shape in a binder resin layer 13 is described as an example. However, the adhesive involved in the present invention is not limited to this. For example, it can also be an insulating adhesive film composed only of the binder resin layer 13. In addition, the adhesive involved in the present invention can have a structure in which an insulating adhesive layer composed only of the binder resin layer 13 and a conductive particle-containing layer composed of the binder resin layer 13 containing the conductive particles 12 are laminated. In addition, the adhesive is not limited to such a film-shaped adhesive film. It can also be a conductive adhesive paste in which the conductive particles 12 are dispersed in the binder resin composition, or an insulating adhesive paste composed only of the binder resin composition. The adhesive involved in the present invention includes any of the above-mentioned forms.

[Connection process]

Next, the connection process for connecting IC chip 1 to circuit substrate 14 will be described. First, anisotropic conductive film 10 is temporarily attached to the mounting portion of circuit substrate 14, where electrode terminals 15 are formed. Next, circuit substrate 14 is placed on a platform of a connection device, and IC chip 1 is positioned on the mounting portion of circuit substrate 14 via anisotropic conductive film 10.

Next, heat pressing is started on the IC chip 1 at a predetermined pressure and for a predetermined time using a thermocompression joint 17 heated to a predetermined temperature at which the adhesive resin layer 13 is cured. As a result, the adhesive resin layer 13 of the anisotropic conductive film 10 exhibits fluidity and flows out from between the mounting surface 2 of the IC chip 1 and the mounting portion of the circuit board 14. Furthermore, the conductive particles 12 in the adhesive resin layer 13 are sandwiched between the output bumps 3 and input bumps 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14, causing them to be crushed.

At this time, according to the IC chip 1 to which the present invention is applied, the output bump area 4 is formed inward from one side edge 2a at a distance of more than 4% relative to the IC width W, so that the pressure gradient formed throughout the width direction of the output bump area 4 is made uniform, not only making the pressing force of the hot pressing joint 17 roughly equal throughout the entire area of the output bump area 4, but also preventing the occurrence of insufficient pressing force on the side of the one side edge 2a.

As a result, conductive particles 12 are sandwiched between output bumps 3 and input bumps 5 and electrode terminals 15 of circuit board 14, thereby electrically connecting them. In this state, the adhesive resin heated by thermocompression joint 17 is cured. Therefore, even in output bumps 3 on the side of one side edge 2a of IC chip 1, electrical continuity with electrode terminals 15 formed on circuit board 14 is reliably ensured.

Conductive particles 12 not located between the output and input bumps 3 and 5 and the electrode terminals 15 are dispersed in the binder resin, maintaining electrical insulation. This allows electrical conduction only between the output and input bumps 3 and 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14. Furthermore, by using a fast-curing resin that uses a free radical polymerization reaction as the binder resin, the binder resin can be rapidly cured even with a relatively short heating time. Furthermore, the anisotropic conductive film 10 is not limited to a thermosetting type; as long as pressure connection is performed, a light-curing or light-heat combined adhesive can also be used.

First embodiment

Next, the first embodiment of the present invention will be described. In this first embodiment, a sample of a connected structure connected to a circuit board via an anisotropic conductive film was fabricated using an IC chip having an output bump region and an input bump region with a difference in area and arranged asymmetrically on the mounting surface. The IC chips involved in the embodiment and comparative examples had varying IC widths and distances A from one side edge 2a of the mounting surface to the output bump region. The on-resistance values of the output and input bumps in each sample of the connected structure were measured and evaluated.

The IC chips according to the examples and comparative examples have an output bump region 4 in which output bumps 3 are arranged, and an input bump region 6 in which input bumps 5 are arranged, formed along a pair of opposing side edges 2a and 2b in the longitudinal direction of a generally rectangular mounting surface 2. In IC chip 1, output bump region 4 is formed on one side edge 2a of mounting surface 2, while input bump region 6 is formed on the other side edge 2b of mounting surface 2. Thus, in IC chip 1, output bump region 4 and input bump region 6 are formed separately across the width of the mounting surface (see FIG. 1 ).

In the output bump region 4, multiple output bumps 3 of the same shape are arranged in three rows in a staggered pattern along the longitudinal direction of the mounting surface 2. The output bumps formed in the output bump region 4 are designated as output bump rows 3A, 3B, and 3C, starting from one side edge 2a. The output bumps 3 formed in each row are rectangular (area: 1437.5 ^μm² ; width: 12.5 μm; length: 115 μm), with 1276 bumps arranged in each row of output bumps 3A, 3B, and 3C. The total area of the output bumps 3 in each row of bumps 3A, 3B, and 3C is 1834250 ^μm² . The total area of the output bump region 4 is 12919500 ^μm² (width: 31900 μm; length: 405 μm).

In input bump region 6, a plurality of input bumps 5 having the same shape are arranged in a row along the longitudinal direction of mounting surface 2. This row of input bumps formed in input bump region 6 is referred to as input bump row 5A. The input bumps 5 arranged in input bump row 5A are rectangular (area: 3600 ^μm² ; width: 45.0 μm; length: 80 μm), and there are 515 of them. The total area of the input bumps 5 in input bump row 5A is 1854000 ^μm² . The total area of input bump region 6 is 2553040 ^μm² (width: 31913 μm; length: 80 μm).

[Example 1]

In the IC chip according to Example 1, the IC width W between the opposing side edges 2a and 2b of the mounting surface 2 is 1.5 mm, and the IC length in the direction in which the input/output bumps 3 and 5 are arranged is 32 mm. Furthermore, the distance A from one side edge 2a to the output bump area 4 is 150 μm, which is 10% of the IC width W (1.5 mm). Furthermore, the IC chip according to Example 1 does not have a dummy bump area between the output bump area 4 and the input bump area 6. Furthermore, the distance B from the other side edge 2b to the input bump area 6 is 50 μm.

[Example 2]

The IC chip according to Example 2 was constructed under the same conditions as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was set to 100 μm. The distance A in Example 2 was 6.6% of the IC width W (1.5 mm).

[Example 3]

The IC chip according to Example 3 was the same as Example 1 except that the distance A from one side edge 2a to the output bump area 4 was set to 75 μm. The distance A in Example 3 was 5.0% of the IC width W (1.5 mm).

[Example 4]

The IC chip according to Example 4 is similar to Example 1 except that the distance A from one side edge 2a to the output bump region 4 is set to 62.5 μm. The distance A in Example 4 is 4.2% of the IC width W (1.5 mm).

[Example 5]

In the IC chip according to Example 5, the IC width W between the opposing side edges 2a and 2b of the mounting surface 2 is 2.0 mm, and the IC length in the arrangement direction of the input/output bumps 3 and 5 is 32 mm. Furthermore, the distance A from one side edge 2a to the output bump area 4 is 83 μm, representing 4.2% of the IC width W (2.0 mm). Furthermore, the IC chip according to Example 5 does not have a dummy bump area between the output bump area 4 and the input bump area 6. Furthermore, the distance B from the other side edge 2b to the input bump area 6 is 50 μm.

[Example 6]

In the IC chip according to Example 6, the IC width W between the opposing side edges 2a and 2b of the mounting surface 2 is 3.0 mm, and the IC length in the arrangement direction of the input/output bumps 3 and 5 is 32 mm. Furthermore, the distance A from one side edge 2a to the output bump area 4 is 125 μm, which is 4.2% of the IC width W (3.0 mm). Furthermore, the IC chip according to Example 6 does not have a dummy bump area between the output bump area 4 and the input bump area 6. Furthermore, the distance B from the other side edge 2b to the input bump area 6 is 50 μm.

[Comparative Example 1]

The IC chip according to Comparative Example 1 was prepared under the same conditions as in Example 1, except that the distance A from one side edge 2a to the output bump area 4 was set to 50 μm. The distance A in Comparative Example 1 was 3.3% of the IC width W (1.5 mm).

[Comparative Example 2]

The IC chip according to Comparative Example 2 was constructed under the same conditions as Comparative Example 1, except that a dummy bump area D was provided between the output bump area 4 and the input bump area 6. In dummy bump area D, dummy bumps were arranged in a single row along the length of the IC chip. Each dummy bump was rectangular (area: 1250 ^μm² ; width: 12.5 μm; length: 100 μm), and there were 1276 of them. The total area of the dummy bumps in dummy bump row D was 1595000 ^μm² . The total area of dummy bump area D was 3190000 ^μm² (width: 31900 μm; length: 100 μm).

The IC chips involved in Examples 1 to 6 and Comparative Examples 1 and 2 were connected to a circuit board via an anisotropic conductive film (trade name CP36931-18AJ, manufactured by Dexerials Co., Ltd.) to produce connected body samples. The connection conditions were 150°C, 130 MPa, and 5 seconds. For each connected body sample, the on-resistance of the output bump arrays 3A, 3B, and 3C and the input bump array 5A was measured using a four-terminal method. On-resistances of 1.0Ω or less were rated "OK," while those exceeding 1.0Ω were rated "NG." The measurement results are shown in Table 1.

[Table 1]

As shown in Table 1, in Examples 1 to 6, the on-resistance is 1.0Ω or less in all of the output bump arrays 3A, 3B, and 3C and the input bump array 5A. Furthermore, even in the output bumps 3 of the output bump array 3A arranged on the side of one side edge 2a, sufficient pressing force can be applied. This is because in Examples 1 to 6, the distance A from one side edge 2a to the output bump region 4 is set to at least 4% of the IC width W, thereby achieving a uniform pressure gradient across the width of the output bump region 4.

On the other hand, in Comparative Example 1, the on-resistance in the output bump arrays 3A and 3B is high. This is because the distance A from one side edge 2a to the output bump area 4 is 3.3% of the IC width W, creating a pressure gradient where the pressing force of the thermocompression joint decreases toward the outer output bump array. This indicates that it is best to set the distance A from one side edge 2a to the output bump area 4 to at least 4% of the IC width W.

Furthermore, in Comparative Example 2, a dummy bump region D is provided between the output bump region 4 and the input bump region 6, resulting in increased on-resistance in the output bump arrays 3A and 3B. This indicates that when the distance A from one side edge 2a to the output bump region 4 is 3.3% of the IC width W, the formation of the dummy bumps makes it difficult to achieve a pressure gradient that improves conductivity in the outer bump arrays.

Furthermore, as can be seen from Examples 5 and 6, by setting the distance A from one side edge 2a to the output bump region 4 to be greater than 4% of the IC width W, a pressure gradient capable of improving conductivity in the outer bump array can be obtained even with a wider IC width.

[Second embodiment]

Next, a second embodiment of the present invention will be described. In the following description, the same components as those of the first embodiment are denoted by the same reference numerals and their details are omitted.

[Electronic components and connectors]

The electronic component to which the present invention is applied is an electronic component that is placed on a circuit board via an adhesive and connected to the circuit board by applying pressure using a thermocompression joint. Examples of the electronic component are packaged electronic components such as driver ICs and system LSIs. Hereinafter, an IC chip 1 will be described as an example of an electronic component.

As shown in FIG1 , a mounting surface 2 on a circuit board connected to an IC chip 1 has a generally rectangular shape. An output bump region 4, where output bumps 3 are arranged, and an input bump region 6, where input bumps 5 are arranged, are formed along a pair of opposing side edges 2a and 2b in the longitudinal direction. In IC chip 1, output bump region 4 is formed on one side edge 2a of mounting surface 2, while input bump region 6 is formed on the other side edge 2b of mounting surface 2. Thus, in IC chip 1, output bump region 4 and input bump region 6 are formed separately across the width of mounting surface 2.

In the output bump region 4, a plurality of output bumps 3, for example, having the same shape, are arranged in three staggered rows along the length of the mounting surface 2. Furthermore, in the input bump region 6, a plurality of input bumps 5, for example, having the same shape, are arranged in one row along the length of the mounting surface 2. Furthermore, the input bumps 5 are formed larger than the output bumps 3. Thus, in the IC chip 1, the output bump region 4 and the input bump region 6 have an area difference and are asymmetrically arranged on the mounting surface 2. Furthermore, the output bumps 3 arranged in the output bump region 4 are preferably formed to the same size. Similarly, the input bumps 5 arranged in the input bump region 6 are preferably formed to the same size.

FIG5 is a cross-sectional view showing the mounting surface of the electronic component shown in FIG1 in the width direction. As shown in FIG5, the IC chip as the electronic component includes: an output bump region 4 having a rectangular shape as a first bump region formed by a bump array along a first side edge 2a; and an input bump region 6 having a rectangular shape as a second bump region formed by a bump array along a second side edge 2b opposite to the first side edge 2a.

Here, the widthwise distance α of the first bump region is greater than the widthwise distance β of the second bump region (α>β). Furthermore, the ratio of the bump region width difference (α-β), which is the widthwise distance α of the first bump region and the widthwise distance β of the second bump region relative to the distance between the first side edge 2a and the second side edge 2b (IC width: W), is preferably 5% to 30%, and more preferably 10% to 25%. If the bump region width difference (α-β) is too small, there is little need to move the midpoint of the outer bump region. However, if the bump region width difference (α-β) is too large, simply moving the midpoint of the outer bump region makes it difficult to eliminate the pressure difference in the thermocompression joint and improve connection reliability.

Furthermore, the midpoint (A+L2/2 or B+L2/2) between the widthwise outer sides of the first bump region and the widthwise outer sides of the second bump region is located closer to the second side edge 2b than the midpoint (W/2) between the first side edge 2a and the second side edge 2b. That is, the relationship between the distance A from the first side edge 2a to the first bump region and the distance B from the second side edge 2b to the second bump region is A>B.

2, when the IC chip 1 is heated and pressed onto the circuit substrate 14 by the thermocompression joint 17, the pressing force is prevented from being uneven inside the output bump area 4, and an appropriate pressing force can be applied to the output bumps 3 arranged on one side edge 2a.

Furthermore, the larger the distance (Δ) from the midpoint between the side edges (W/2) to the midpoint between the outer edges of the bump region (A+L2/2 or B+L2/2), i.e., (A-B)/2, the more gradual and uniform the pressure gradient formed across the width of the output bump region 4 becomes. Specifically, the distance (Δ) is preferably 0.1% to 5.0% of the distance (W) between the first side edge 2a and the second side edge 2b, and more preferably 0.3% to 3.5%. This prevents insufficient pressing force from the thermocompression joint 17 on one side edge 2a when pressure is applied to the entire mounting surface 2 by the thermocompression joint 17, as shown in Figure 2. Consequently, even in the output bump 3 on the side edge 2a of the IC chip 1, conductive particles are reliably held between the electrode terminals 15 formed on the circuit board 14, ensuring electrical continuity.

Furthermore, the structure of the input/output bumps on the mounting surface 2 of the IC chip 1 can be appropriately designed. As described above, the IC chip 1 forms a relatively large output bump region 4 by arranging a plurality of output bumps 3 along the width direction. Conversely, the input bump region 6 can also be relatively large by arranging a plurality of input bumps 5 along the width direction.

3 , IC chip 1 may also appropriately provide a dummy bump region 19 between output bump region 4 and input bump region 6 , where so-called dummy bumps 18 not used for input and output of signals are arranged.

[Adhesive]

As an adhesive for connecting the IC chip 1 to the circuit board 14 , the above-mentioned anisotropic conductive film 10 (ACF: Anisotropic Conductive Film) can be preferably used as shown in FIG. 4 .

[Method for manufacturing and connecting a connected body]

Next, the connection method for connecting IC chip 1 to circuit substrate 14 is described. First, anisotropic conductive film 10 is temporarily attached to the mounting portion of circuit substrate 14 where electrode terminals 15 are formed. Next, circuit substrate 14 is placed on a platform of a connection device, and IC chip 1 is positioned on the mounting portion of circuit substrate 14 via anisotropic conductive film 10.

Next, heat pressurization is initiated from above the IC chip 1 at a predetermined pressure and for a predetermined time using a thermocompression joint 17 heated to a predetermined temperature at which the adhesive resin layer 13 is cured. As a result, the adhesive resin layer 13 of the anisotropic conductive film 10 exhibits fluidity and flows out from between the mounting surface 2 of the IC chip 1 and the mounting portion of the circuit board 14. Furthermore, the conductive particles 12 in the adhesive resin layer 13 are sandwiched between the output bumps 3 and input bumps 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14, causing them to be crushed.

As a result, conductive particles 12 are sandwiched between output bumps 3 and input bumps 5 and electrode terminals 15 of circuit board 14, thereby electrically connecting them. In this state, the adhesive resin heated by thermocompression joint 17 is cured. Therefore, even in output bumps 3 on the one side edge 2a of IC chip 1, electrical continuity is reliably maintained between output bumps 3 and electrode terminals 15 formed on circuit board 14.

Conductive particles 12 not located between output and input bumps 3 and 5 and electrode terminals 15 are dispersed in the binder resin, maintaining electrical insulation. Consequently, electrical conduction is achieved only between output and input bumps 3 and 5 of IC chip 1 and electrode terminals 15 of circuit board 14. Furthermore, by employing a fast-curing resin that utilizes a free radical polymerization reaction as the binder resin, the binder resin can be rapidly cured even with a relatively short heating time. Furthermore, the anisotropic conductive film 10 is not limited to a thermosetting adhesive; as long as pressurized bonding is possible, a light-curing adhesive or a combination of light and heat-curing adhesives may also be used.

Second embodiment

Next, a second embodiment of the present invention will be described. In this second embodiment, a sample of a connected structure connected to a circuit board via an anisotropic conductive film was manufactured using an IC chip having an output bump region as a first bump region and an input bump region as a second bump region. The IC chips involved in the embodiment and comparative examples varied in IC width and distance A from one side edge 2a of the mounting surface to the output bump region. The on-resistance values of the output and input bumps in each sample of the connected structure were measured and evaluated.

[IC chip]

The IC chip 1 includes an output bump region 4, in which output bumps 3 are arranged, and an input bump region 6, in which input bumps 5 are arranged, along a pair of opposing side edges 2a and 2b in the longitudinal direction of a generally rectangular mounting surface 2. In IC chip 1, output bump region 4 is formed on one side edge 2a of mounting surface 2, while input bump region 6 is formed on the other side edge 2b of mounting surface 2. Thus, IC chip 1 has output bump region 4 and input bump region 6 formed separately across the width of the mounting surface (see Figures 1 and 5).

In the output bump region 4, a plurality of output bumps 3 having the same shape are arranged in three rows in a staggered pattern along the length of the mounting surface 2. The output bumps formed in the output bump region 4 are divided into rows, and are sequentially designated as output bump rows 3A, 3B, and 3C from one side edge 2a.

In the input bump region 6, a plurality of input bumps 5 formed in the same shape are arranged in a row along the longitudinal direction of the mounting surface 2. The input bump row formed in the input bump region 6 is referred to as an input bump row 5A.

[Evaluation of on-resistance]

Connected body samples were fabricated by connecting an IC chip to a circuit board via an anisotropic conductive film (trade name CP36931-18AJ, manufactured by Dexerials Co., Ltd.). The connection conditions were 150°C, 130 MPa, and 5 seconds. For each connected body sample, the on-resistance of output bump arrays 3A, 3B, and 3C, and input bump array 5A, was measured using a four-terminal method. Results were rated "OK" if the on-resistance of all bump arrays was 1.0Ω or less, and "NG" if one or more bump arrays exceeded 1.0Ω.

[Example 7]

As shown in Table 2, an IC chip was prepared in which the IC width W was 1500 μm, the distance A from one side edge 2a of the output bump area 4 was 60 μm, the width α of the output bump area 4 was 385 μm, the distance B from the other side edge 2b of the input bump area 6 was 50 μm, the width β of the input bump area 6 was 80 μm, and the ratio of the bump area width difference to the IC width W was 20.3%.

The inner-bump-area distance (L1) between the widthwise inner sides of the output bump area 4 and the widthwise inner sides of the input bump area 6 is 925 μm. The outer-bump-area distance (L2) between the widthwise outer sides of the output bump area 4 and the widthwise outer sides of the input bump area 6 is 1390 μm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint of the outer bump area (A+L2/2) is 5.0 μm, representing a ratio of 0.33% to the IC width (W).

The on-resistances of the output bump arrays 3A, 3B, and 3C and the input bump array 5A in the IC chip-connected structure sample of Example 7 were measured to be 1.0Ω, 0.9Ω, 0.4Ω, and 0.1Ω, respectively, which were evaluated as OK.

[Example 8]

As shown in Table 2, an IC chip similar to that of Example 7 was prepared, except that the distance A from one side edge 2a of the output bump region 4 was set to 75 μm. The inside-to-inside distance (L1) between the widthwise inner side of the output bump region 4 and the widthwise inner side of the input bump region 6 was 910 μm. The outside-to-outside distance (L2) between the widthwise outer side of the output bump region 4 and the widthwise outer side of the input bump region 6 was 1375 μm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint of the outside bump region (A+L2/2) was 12.5 μm, representing a ratio of 0.83% to the IC width (W).

The on-resistances of the output bump arrays 3A, 3B, and 3C and the input bump array 5A in the IC chip-connected structure sample of Example 8 were measured to be 0.9Ω, 0.8Ω, 0.4Ω, and 0.1Ω, respectively, which were evaluated as OK.

[Example 9]

As shown in Table 2, an IC chip similar to that of Example 7 was prepared, except that the distance A from one side edge 2a of the output bump region 4 was set to 150 μm. The inside-to-inside distance (L1) between the widthwise inner side of the output bump region 4 and the widthwise inner side of the input bump region 6 was 835 μm. The outside-to-outside distance (L2) between the widthwise outer side of the output bump region 4 and the widthwise outer side of the input bump region 6 was 1300 μm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint of the outside bump region (A+L2/2) was 50.0 μm, representing a ratio of 3.33% to the IC width (W).

The on-resistances of the output bump arrays 3A, 3B, and 3C and the input bump array 5A in the IC chip-connected structure sample of Example 9 were measured to be 0.9Ω, 0.7Ω, 0.5Ω, and 0.1Ω, respectively, which were evaluated as OK.

[Example 10]

As shown in Table 2, an IC chip was prepared in which the IC width W was 2000 μm, the distance A from one side edge 2a of the output bump area 4 was 63 μm, the width α of the output bump area 4 was 385 μm, the distance B from the other side edge 2b of the input bump area 6 was 50 μm, the width β of the input bump area 6 was 80 μm, and the ratio of the bump area width difference to the IC width W was 15.3%.

The inner-bump-area distance (L1) between the widthwise inner sides of the output bump area 4 and the widthwise inner sides of the input bump area 6 is 1422 μm. The outer-bump-area distance (L2) between the widthwise outer sides of the output bump area 4 and the widthwise outer sides of the input bump area 6 is 1887 μm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint of the outer bump area (A+L2/2) is 6.5 μm, representing a ratio of 0.33% to the IC width (W).

The on-resistances of the output bump arrays 3A, 3B, and 3C and the input bump array 5A in the IC chip-connected structure sample of Example 10 were measured to be 1.0Ω, 0.9Ω, 0.4Ω, and 0.1Ω, respectively, which were evaluated as OK.

[Example 11]

As shown in Table 2, an IC chip was prepared in which the IC width W was 3000 μm, the distance A from one side edge 2a of the output bump area 4 was 70 μm, the width α of the output bump area 4 was 385 μm, the distance B from the other side edge 2b of the input bump area 6 was 50 μm, the width β of the input bump area 6 was 80 μm, and the ratio of the bump area width difference to the IC width W was 10.2%.

The inner-bump-area distance (L1) between the widthwise inner sides of the output bump area 4 and the widthwise inner sides of the input bump area 6 is 2415 μm. The outer-bump-area distance (L2) between the widthwise outer sides of the output bump area 4 and the widthwise outer sides of the input bump area 6 is 2880 μm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint of the outer bump area (A+L2/2) is 10.0 μm, representing a ratio of 0.33% to the IC width (W).

The on-resistances of the output bump arrays 3A, 3B, and 3C and the input bump array 5A in the IC chip-connected structure sample of Example 11 were measured to be 1.0Ω, 0.9Ω, 0.4Ω, and 0.1Ω, respectively, which were evaluated as OK.

[Comparative Example 3]

As shown in Table 2, an IC chip similar to Example 7 was prepared, except that the distance A from one side edge 2a of the output bump region 4 was set to 50 μm and a dummy bump region was provided. The dummy bump region was provided between the output bump region 4 and the input bump region 6, and the dummy bumps were arranged in a row along the length of the IC chip. The dummy bump row was identical to the input bump row 5.

The inner-bump-area distance (L1) between the widthwise inner sides of the output bump area 4 and the widthwise inner sides of the input bump area 6 is 935 μm. The outer-bump-area distance (L2) between the widthwise outer sides of the output bump area 4 and the widthwise outer sides of the input bump area 6 is 1400 μm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint of the outer bump area (A+L2/2) is 0 μm, and its ratio to the IC width (W) is 0%.

The on-resistances of the output bump arrays 3A, 3B, and 3C and the input bump array 5A in the IC chip-connected structure sample of Comparative Example 3 were measured to be 2.3Ω, 1.2Ω, 0.5Ω, and 0.1Ω, respectively, which were evaluated as NG.

[Comparative Example 4]

As shown in Table 2, an IC chip similar to that of Example 7 was prepared, except that the distance A from one side edge 2a of the output bump region 4 was set to 50 μm. The inside-to-inside distance (L1) between the widthwise inner side of the output bump region 4 and the widthwise inner side of the input bump region 6 was 935 μm. The outside-to-outside distance (L2) between the widthwise outer side of the output bump region 4 and the widthwise outer side of the input bump region 6 was 1400 μm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint of the outside bump region (A+L2/2) was 0 μm, representing a 0% ratio to the IC width (W).

The on-resistances of the output bump arrays 3A, 3B, and 3C and the input bump array 5A in the IC chip-connected structure sample of Comparative Example 4 were measured to be 3.0Ω, 1.7Ω, 0.4Ω, and 0.1Ω, respectively, which were evaluated as NG.

[Table 2]

When dummy bumps are provided as in Comparative Example 3, the on-resistance in the output bump arrays 3A and 3B is high, making it difficult to obtain a pressure gradient sufficient to improve the conductivity in the outer bump arrays. Furthermore, when no dummy bumps are provided as in Comparative Example 4, the on-resistance in the output bump arrays 3A and 3B is higher than in Comparative Example 3.

On the other hand, when the distance (Δ) from the midpoint of the IC width (W/2) to the midpoint of the outer portion of the bump region (A+L2/2) is set to 0.3% to 3.5% of the IC width W, as in Examples 7 to 11, the on-resistance of the output bump arrays 3A, 3B, and 3C and the input bump array 5A is reduced to 1.0Ω or less. This is because the pressure gradient is uniform across the width of the output bump region 4, allowing each output bump 3 in the output bump array 3A to be pressed in with sufficient pressure.

Description of labels

1 IC chip; 2 mounting surface; 2a one side edge; 2b the other side edge; 3 output bump; 4 output bump region; 5 input bump; 6 input bump region; 10 anisotropic conductive film; 11 release film; 12 conductive particles; 13 adhesive resin layer; 14 circuit substrate; 15 electrode terminal; 17 thermocompression joint.

Claims (18)

1. An electronic component, wherein, An output bump region is provided with output bumps arranged near one side of a pair of opposite side edges, and an input bump region is provided with input bumps arranged near the other side of the pair of side edges. The output bump region and the input bump region are of different areas and are configured asymmetrically. In the output bump region or the input bump region, a relatively large area is formed inward from the nearest side edge by a distance of 4% to 30% of the width between the pair of side edges. 2. The electronic component of claim 1, wherein the output bump region is formed inward from one of the side edges at a distance of more than 4% of the width between the pair of side edges. 3. The electronic component of claim 2, wherein the distance from the one side edge to the output bump region is longer than the distance from the other side edge to the input bump region. 4. The electronic component of claim 1, wherein the input bump region is formed inward from the other side edge at a distance of more than 4% of the width between the pair of side edges. 5. The electronic component of claim 4, wherein the distance from the other side edge to the input bump region is longer than the distance from the one side edge to the output bump region. 6. The electronic component according to any one of claims 1 to 5, wherein a dummy bump is formed on the mounting surface of the electronic component between the input bump region and the output bump region. 7. The electronic component according to any one of claims 1 to 5, wherein the electronic component is an IC chip. 8. A connector for mounting electronic components on a circuit board via an adhesive and for attaching the electronic components to the circuit board by applying pressure with a pressure tool, wherein in the connector, On the mounting surface of the electronic component to the circuit board, there is an output bump area where output bumps are arranged near one side of a pair of opposing side edges, and an input bump area where input bumps are arranged near the other side of the pair of side edges. The output bump region and the input bump region have different areas and are asymmetrically arranged on the mounting surface. In the output bump region or the input bump region, a relatively large area is formed inward from the nearest side edge by a distance of 4% to 30% of the width between the pair of side edges. 9. A method for manufacturing a connector, comprising: disposing electronic components on a circuit board via an adhesive; and connecting the electronic components to the circuit board by applying pressure with a pressure tool, wherein in the method for manufacturing the connector, On the mounting surface of the electronic component to the circuit board, there is an output bump area where output bumps are arranged near one side of a pair of opposing side edges, and an input bump area where input bumps are arranged near the other side of the pair of side edges. The output bump region and the input bump region have different areas and are asymmetrically arranged on the mounting surface. In the output bump region or the input bump region, a relatively large area is formed inward from the nearest side edge by a distance of 4% to 30% of the width between the pair of side edges. 10. A method for connecting electronic components, comprising disposing the electronic components on a circuit board via an adhesive, and connecting the electronic components to the circuit board by applying pressure with a pressure tool, wherein in the method for connecting electronic components, On the mounting surface of the electronic component to the circuit board, there is an output bump area where output bumps are arranged near one side of a pair of opposing side edges, and an input bump area where input bumps are arranged near the other side of the pair of side edges. The output bump region and the input bump region have different areas and are asymmetrically arranged on the mounting surface. In the output bump region or the input bump region, a relatively large area is formed inward from the nearest side edge by a distance of 4% to 30% of the width between the pair of side edges. 11. An electronic component comprising: A rectangular first convex region, forming a row of convex dots along the first side edge; and The rectangular second convex region forms a row of convex dots along the second side edge opposite to the first side edge. The distance in the width direction of the first convex point region is greater than the distance in the width direction of the second convex point region. The midpoint between the outer sides of the first convex region and the outer side of the second convex region in the width direction is located on the second side edge, compared to the midpoint between the first and second side edges. 12. The electronic component of claim 11, wherein the distance from the midpoint between the side edges to the midpoint between the outer edges of the protrusion region is 0.1% to 5.0% of the distance between the first side edge and the second side edge. 13. The electronic component of claim 11 or 12, wherein the ratio of the width difference of the first bump region to the width of the second bump region relative to the distance between the first side edge and the second side edge is 5% to 30%. 14. The electronic component as claimed in claim 11 or 12, wherein a dummy protrusion is formed on the mounting surface of the electronic component between the first protrusion region and the second protrusion region. 15. The electronic component as claimed in claim 11 or 12, wherein the electronic component is an IC chip. 16. A connector comprising: Electronic components; and The circuit board of the electronic components is connected by an adhesive. The electronic component includes: a rectangular first protrusion region forming a row of protrusions along a first side edge; and a rectangular second protrusion region forming a row of protrusions along a second side edge opposite to the first side edge. The distance in the width direction of the first protrusion region is greater than the distance in the width direction of the second protrusion region. The midpoint between the outer sides of the protrusion regions in the width direction of the first and second protrusion regions is located on the second side edge side, compared to the midpoint between the side edges of the first and second side edges. 17. A method for manufacturing an interconnect, comprising mounting electronic components onto a circuit board using an adhesive. The electronic components are connected to the circuit board by applying pressure using a pressure tool. The electronic component includes: a rectangular first protrusion region forming a row of protrusions along a first side edge; and a rectangular second protrusion region forming a row of protrusions along a second side edge opposite to the first side edge. The distance in the width direction of the first protrusion region is greater than the distance in the width direction of the second protrusion region. The midpoint between the outer sides of the protrusion regions in the width direction of the first and second protrusion regions is located on the second side edge side, compared to the midpoint between the side edges of the first and second side edges. 18. A method for connecting electronic components, wherein the electronic components are disposed on a circuit board via an adhesive. The electronic components are connected to the circuit board by applying pressure using a pressure tool. The electronic component includes: a rectangular first protrusion region forming a row of protrusions along a first side edge; and a rectangular second protrusion region forming a row of protrusions along a second side edge opposite to the first side edge. The distance in the width direction of the first protrusion region is greater than the distance in the width direction of the second protrusion region. The midpoint between the outer sides of the protrusion regions in the width direction of the first and second protrusion regions is located on the second side edge side, compared to the midpoint between the side edges of the first and second side edges.