HK1224820B - Pixel array and image sensing system - Google Patents

Description

Pixel array and image sensing system

Technical Field

The present invention relates to image sensors, and more particularly, to three-dimensional image sensors.

Background Art

Interest in three-dimensional (3D) cameras is increasing as 3D applications become increasingly popular, such as in applications such as imaging, movies, games, computers, user interfaces, and the like. A typical passive approach for creating color 3D images is to use multiple cameras to capture stereo or multiple images. Using stereo images, objects in the image can be triangulated to create a color 3D image. One disadvantage of this triangulation technique is that it is difficult to create a color 3D image using a small device because a minimum separation distance must exist between each camera in order to create a color 3D image. In addition, this technique is complex and therefore requires significant computer processing power in order to create a color 3D image in real time. Furthermore, using multiple cameras can increase the size and cost of the imaging system.

For applications requiring real-time color 3D image acquisition, active depth imaging systems based on optical time-of-flight measurements are sometimes utilized. A time-of-flight system typically employs a light source to direct light toward an object, a sensor to detect the light reflected from the object, and a processing unit to calculate the distance to the object based on the round-trip time it takes for the light to travel to and from the object. In typical time-of-flight sensors, photodiodes are often used due to their high transmission efficiency from the photodetection region to the sensing node.

Summary of the Invention

One embodiment of the present application relates to a pixel array, comprising: a plurality of visible light pixels arranged in the pixel array, wherein each of the plurality of visible light pixels includes a photosensitive element arranged in a first semiconductor die to detect visible light, wherein each of the plurality of visible light pixels is coupled to provide color image data to a visible light readout circuit disposed in a second semiconductor die, the second semiconductor die being stacked with the first semiconductor die in a stacked chip scheme and coupled to the first semiconductor die; and a plurality of infrared (IR) pixels arranged in the pixel array, wherein each of the plurality of IR pixels includes a single photon avalanche photodiode (SPAD) arranged in the first semiconductor die to detect IR light, wherein each of the plurality of IR light pixels is coupled to provide IR image data to an IR light readout circuit disposed in the second semiconductor die.

Another embodiment of the present application relates to an image sensing system comprising: a light source for emitting infrared (IR) light pulses toward an object; a pixel array for receiving visible light and reflected IR light pulses from the object, wherein the pixel array comprises: a plurality of visible light pixels arranged in the pixel array, wherein each of the plurality of visible light pixels comprises a photosensitive element arranged in a first semiconductor die to detect the visible light from the object, wherein each of the plurality of visible light pixels is coupled to provide color image data to a visible light readout circuit disposed in a second semiconductor die, the second semiconductor die being stacked with the first semiconductor die in a stacked chip scheme stacked and coupled to the first semiconductor die; and a plurality of IR pixels arranged in the pixel array, wherein each of the plurality of IR pixels includes a single photon avalanche photodiode (SPAD) arranged in the first semiconductor die to detect the reflected IR light pulses from the object to generate time-of-flight information, wherein each of the plurality of visible light pixels is coupled to provide IR image data to an IR light readout circuit disposed in the second semiconductor die; and a control circuit coupled to control the operation of the pixel array and to control and synchronize the light source with a synchronization signal to synchronize the emission of the light pulses with the timing of sensing of photons reflected from the object.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

1 is a schematic block diagram showing an example of an imaging system for producing a three-dimensional color image of an object or scene.

2 is a block diagram showing a portion of an example of a 3D color image sensor including a color time-of-flight pixel array with corresponding readout circuitry, control circuitry, and function logic in accordance with the teachings of the present invention.

3 is a diagrammatic illustration showing an example RGB-IR filter array disposed over an example color time-of-flight pixel array in accordance with the teachings of the present invention.

4A is a schematic diagram illustrating one example of a stacked visible light pixel in accordance with the teachings of the present invention.

4B is a schematic diagram illustrating one example of a stacked-chip SPAD pixel including a quenching element in accordance with the teachings of the present invention.

5 is a cross-sectional diagram of an integrated circuit system including a 3D color image sensor with stacked die in accordance with the teachings of the present invention.

Throughout the several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to help improve understanding of the various embodiments of the present invention, the dimensions of some of the elements in the various figures may be exaggerated relative to other elements. Likewise, common and well-known elements that are useful or necessary in commercially feasible embodiments are generally not depicted to facilitate a less obstructed view of these various embodiments of the present invention.

DETAILED DESCRIPTION

Disclosed are an apparatus and system for obtaining color 3D images using time-of-flight and depth information. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, one skilled in the relevant art will recognize that the techniques described herein can be practiced without one or more of these specific details, or with other components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Throughout this specification, several technical terms are used. These terms are to be taken on their ordinary meaning in the art to which they pertain, unless otherwise specifically defined herein or the context of their use clearly implies otherwise. For example, the term "or" is used in an inclusive sense (e.g., as in "and/or") unless the context clearly dictates otherwise.

FIG1 illustrates a schematic block diagram of an example imaging system 10 that can generate a color 3D image of an object or scene 12. For example, imaging system 10 can be used as a color camera for a 3D gesture recognition system, such as may be used in a video gaming system. As shown in FIG1 , imaging system 10 includes an optical imager or camera 18 that receives and processes visible light from a scene or object 12. In the example, camera 18 generates red (R), green (G), and blue (B) color image data of scene or object 12. As such, camera 18 may also be referred to as an "RGB camera." An RBG pixel array 22 receives the visible light, and readout circuitry 24 reads out the visible image data.

In the example, imaging system 10 also includes an infrared (IR) source 14 that illuminates scene or object 12 with IR light. In one example, IR source 14 may include an IR laser or the like for providing IR light. IR imager or camera 16 receives and processes the IR light returned from scene or object 12 to generate IR image data of scene or object 12. In this manner, IR pixel array 26 receives the IR light, and IR readout circuitry 28 reads out the IR image data.

In the example, frames of image data from the RGB camera 18 and the IR camera 16 are transmitted to the image processing circuit 20, which processes the received data to generate a 3D color image of the scene or object 12. The image processing circuit 20 uses the data from the RGB camera 18 to generate the color image and uses the data from the IR camera 16 to provide depth information for generating the color 3D image. Thus, the imaging system 10 of FIG1 includes a separate RGB camera 18 and an IR camera 16 for generating a color 3D image. However, it should be noted that by utilizing multiple cameras, such as the RGB camera 18 and the IR camera 16, there are multiple sets of control signal lines and multiple data sets, which results in the imaging system 10 having a large and complex physical size and a relatively high cost.

In one example, a 3D color image can be obtained by using an imaging system in which an RGB camera and an IR camera are combined into a single image pixel array. For example, in one example, the imaging system includes an image pixel array having a plurality of visible light pixels and a plurality of silicon photonic avalanche diode (SPAD) pixels. In the example, each of the plurality of visible light pixels includes a photosensitive element such as a photodiode, for example, for receiving a portion of light, and pixel support circuitry for generating a signal representing the intensity of the received portion of light. Each of the plurality of SPAD pixels includes an avalanche diode for detecting the distance to an object, and SPAD pixel support circuitry coupled to the avalanche photodiode. The array of photosensitive elements and SPAD pixels is disposed on a sensor die, and the pixel support circuitry for the visible light pixels and SPAD pixels is disposed on an application-specific integrated circuit (ASIC) die. The sensor die and ASIC die are stacked together.

In the example, a filter is disposed over each of the plurality of visible light pixels and each of the plurality of SPAD pixels. Each filter passes a predetermined wavelength band or color of light. Each filter is aligned with an associated photosensitive element of a visible light pixel or an avalanche diode of a SPAD pixel. At least one of the filters is adapted to pass a wavelength band in the visible color band, and at least one other of the filters is adapted to pass a wavelength band in the infrared band.

To illustrate, FIG2 is a block diagram showing a portion of an example of a stacked 3D color image sensor 200 including a time-of-flight pixel array with corresponding readout circuitry, control circuitry, and function logic in accordance with the teachings of the present invention. Specifically, as illustrated in the depicted example, stacked 3D color image sensor 200 includes a color time-of-flight (TOF) pixel array 210, readout circuitry 220, control circuitry 230, function logic 240, and an IR source 250. In the example, IR source 250 emits pulsed IR light 252 that can be used to sense the round-trip distance to an object 260 based on the time-of-flight of the pulses of IR light. Specifically, the round-trip distance can be determined in accordance with the teachings of the present invention by measuring the amount of time it takes for the emitted IR light pulses 252 to travel from IR source 250 to object 260 and back to color TOF pixel array 210. By determining the round-trip distance to object 260, 3D information can be determined. 2 can be used, for example, in a variety of applications, such as part of a camera in a 3D gesture recognition system included in, for example, a video game system or the like. In one example, IR source 250 can include an IR laser that emits IR light 252 that illuminates object 260.

In the illustrated example in FIG2 , color TOF pixel array 210 is a two-dimensional (2D) array of visible light pixels 211 and SPAD pixels 212 disposed in semiconductor material of a semiconductor sensor die. Multiple SPAD pixels 212 in color TOF pixel array 210 can be used to detect reflected IR light 254 from an object 260 to provide IR image data. The multiple visible light pixels 211 in color TOF pixel array 210 detect visible light from the object 260 to provide color image data. In one example, each of the multiple visible light pixels 211 includes a photosensitive element, such as a photodiode, for receiving a portion of the light, and pixel support circuitry for generating a signal representing the intensity of the received portion of the light. Each of the multiple SPAD pixels 212 includes an avalanche diode and SPAD pixel support circuitry.

As shown in the depicted example, each of the plurality of SPAD pixels 212 is surrounded on all lateral sides by visible light pixels 211 in the semiconductor material of the color TOF pixel array 210. Thus, in accordance with the teachings of the present invention, the plurality of SPAD pixels 212 are distributed throughout the color TOF pixel array 210 among the plurality of visible light pixels 211 in the semiconductor material of the semiconductor sensor die. In one example, the ratio of the sizes of the SPAD pixels 212 to the visible light pixels 211 is 4 to 1. In another example, the ratio of the sizes of the SPAD pixels 212 to the visible light pixels can be another value, such as 9 to 1. In another example, the size of the SPAD pixels is N times larger than the size of the visible light pixels, where N is an integer. Because the stacked 3D color image sensor 200 includes a sensor die stacked with an ASIC die in a stacked chip approach, the photosensitive elements can occupy substantially the entire area of the visible light pixels 211, and the avalanche diodes can occupy substantially the entire area of the SPAD pixels 212.

In the depicted example, control circuitry 230 is coupled to control the operation of color TOF pixel array 210, as well as to control and synchronize pulses of IR light 252 emitted by IR source 250 to object 260 with synchronization signal 235 to synchronize the emission of IR light pulses 252 with the timing of sensing of photons reflected from object 260 with SPAD pixels 212. In particular, reflected IR light 254 is reflected from object 260 back to color TOF pixel array 210. Visible light is detected with visible light pixels 211 and reflected IR light 254 is detected with the plurality of SPAD pixels 212.

Frames of color image data and IR image data are transmitted from the color TOF pixel array 210 via bit lines 225 to visible light readout circuitry and IR light readout circuitry included in the readout circuitry 220. The readout circuitry 220 may include an amplifier to amplify the signal received via the bit lines 225. The bit lines 225 may be used to couple visible light pixels 211 disposed on the same column. Each of the plurality of SPAD pixels 212 in the color TOF pixel array 210 may be coupled to its own respective readout circuitry, which is different from the readout circuitry of the visible light pixels 211. The information read out by the visible light readout circuitry and IR light readout circuitry in the readout circuitry 220 may then be transmitted to digital circuitry included in the function logic 240 to store and process the information read out from the color TOF pixel array 210. In one example, the function logic 240 may determine time of flight and distance information from each of the plurality of SPAD pixels 212 in the color TOF pixel array 210. In one example, function logic 240 may manipulate the color image data and/or the IR image data (e.g., crop, rotate, adjust for background noise, or the like). In one example, function logic 240 may combine the color image data with time-of-flight information in the IR image data to provide a color 3D image.

As mentioned, it should be noted that the 3D color image sensor 200 illustrated in FIG2 can be implemented using a stacked chip approach. For example, the photosensitive elements of visible light pixels 211 and the array of avalanche diodes of SPAD pixels 212 can be disposed on a sensor die. The pixel support circuitry for visible light pixels 211 and the pixel support circuitry for SPAD pixels 212, as well as readout circuitry 220, control circuitry 230, and function logic 240 can be disposed on separate ASIC dies. In this example, the sensor die and the ASIC die are stacked and coupled together in a stacked chip approach during fabrication to implement a 3D color image sensing system in accordance with the teachings of the present invention.

FIG3 is a diagram showing an example RGB-IR filter array disposed above an example color TOF pixel array in accordance with the teachings of the present invention. In the depicted example, RGB-IR filter array 300 is disposed above one example of color TOF pixel array 210 of FIG2 in accordance with the teachings of the present invention. Referring back to FIG3 , each filter 310, 311, 312, and 313 of filters 310 is aligned with a corresponding underlying photosensitive element of visible light pixel 211, while filter 315 is aligned with a corresponding underlying avalanche diode of SPAD pixel 212. In one example, the photosensitive element of visible light pixel 211 can be substantially the same size as each filter 310, 311, 312, 313 of filters 310, and the avalanche diode of SPAD pixel 212 can be substantially the same size as filter 315. In one example, filters 310, 311, 312, and 313 are color filters arranged in a repeating pattern, such as a Bayer pattern or the like, with the smallest repeating color filter unit 314, as shown, comprising a grouping of four color filters 310, 311, 312, and 313. In one example, the size of repeating color filter unit 314 is substantially the same as the size of filter 315. In one example, filters 310, 311, 312, and 313 can be R, G, G, and B color filters, respectively, making filter array 300 an RGB-IR filter array. In one example, filter array 300 can be a CYM-IR filter array, a CYGM-IR filter array, or the like.

FIG4A is a schematic diagram illustrating one example of a four-transistor (4T) pixel cell stacked chip visible light pixel in accordance with the teachings of the present invention. The pixel circuit illustrated in FIG4A is one possible example of a visible light pixel circuit architecture for implementing each visible light pixel 211 of the color time-of-flight pixel array 210 of FIG2 . Referring back to FIG4A , each visible light pixel 400 includes a photosensitive element 410 (e.g., a photodiode) and pixel support circuitry 411, as shown. The photosensitive element 410 can be disposed on the sensor die of the stacked die system, while the pixel support circuitry 411 can be disposed on the ASIC die. In one example, the pixel support circuitry 411 includes a transfer transistor 415 coupled to the photosensitive element 410, a reset transistor 420, a source follower (SF) transistor 425, and a row select transistor 430, as shown.

During operation, photosensitive element 410 generates charge in response to incident light during an exposure period. Transfer transistor 415 is coupled to receive a transfer signal TX that causes transfer transistor 415 to transfer the charge accumulated in photodiode 410 to a floating diffusion (FD) node 417. Reset transistor 420 is coupled between power rail VDD and floating diffusion node 417 to reset visible light pixel 400 (e.g., discharge or charge floating diffusion node 417 and photodiode 410 to a predetermined voltage) in response to a reset signal RST.

Floating diffusion node 417 is coupled to control the gate terminal of a source follower transistor 425. Source follower transistor 425 is coupled between a power rail VDD and a row select transistor 430 to respond to the charge amplified signal on floating diffusion FD node 417. Row select transistor 430 couples the output of the pixel circuit from source follower transistor 425 to a readout column or bit line 435 in response to a row select signal RS.

Photosensitive element 410 and floating diffusion node 417 are reset by temporarily asserting reset signal RST and transfer signal TX. An accumulation window (e.g., an exposure period) begins when transfer signal TX is deasserted, allowing incident light to photogenerate charge in photosensitive element 410. As the photogenerated electrons accumulate in photosensitive element 410, its voltage decreases (electrons are negative charge carriers). The voltage, or charge, on photodiode 410 represents the intensity of light incident on photosensitive element 410 during the exposure period. At the end of the exposure period, reset signal RST is deasserted, turning off reset transistor 420 and isolating floating diffusion node FD 417 from VDD. Transfer signal TX is then asserted to couple photosensitive element 410 to floating diffusion node 417. Charge is transferred from photosensitive element 410 to floating diffusion node FD 417 via transfer transistor 415, causing the voltage of floating diffusion node FD 417 to drop by an amount proportional to the photogenerated electrons accumulated on photosensitive element 410 during the exposure period.

FIG4B is a schematic diagram illustrating one example of a stacked-die SPAD pixel including a quenching element in accordance with the teachings of the present invention. The pixel circuit illustrated in FIG4B is one possible example of a SPAD pixel circuit architecture for implementing each SPAD pixel 212 of the color time-of-flight pixel array 210 of FIG2 . Referring back to FIG4B , each SPAD pixel 450 includes an avalanche diode 460, a quenching element 470, and a digital counter 480 coupled as shown. The avalanche diode 460 is coupled to the quenching element 470, and both the avalanche diode 460 and the quenching element 470 can be disposed on the sensor die of the stacked-die system, while the digital counter 480 included in the readout circuit is disposed on the ASIC die. In other examples, the quenching element 470 can be included in the sensor die or the ASIC die in accordance with the teachings of the present invention. It should also be understood that the quenching element 470 can be implemented using either a passive or active quenching element in accordance with the teachings of the present invention.

Digital counter 480 can be implemented using CMOS circuitry fabricated using a standard CMOS process of a stacked die system disposed on an ASIC die and electrically coupled to receive output pulses 465 generated by avalanche diode 460 in response to received photons. Digital counter 480 can be enabled to count the number of output pulses 465 generated by avalanche diode 460 during a time window and output a digital signal 485 representing the count. Although the example depicted in FIG4B illustrates a direct connection between the pixel circuitry including avalanche photodiode 460 and digital counter 480, it should be understood that any connection (including AC coupling) between the pixel circuitry including avalanche photodiode 460 and digital counter 480 can be utilized in accordance with the teachings of the present invention. In one example, each digital counter 480 includes an amplifier for amplifying the received output pulses 465. Alternatively, or in addition to digital counter 480, timing circuitry for timing the arrival of incident photons can be placed in each pixel/column/array to determine the photon's time of flight and the round-trip distance to an object in accordance with the teachings of the present invention.

In operation, each avalanche diode 460 is reverse biased by a bias voltage V _BIAS that is higher than the breakdown voltage of each avalanche diode 460. In response to a single photogenerated carrier (generated in response to an incident photon), an avalanche multiplication process is triggered, which produces an avalanche current at the output of each avalanche diode 460. This avalanche current self-quenches in response to the voltage drop developed across the quenching element 470, which causes the bias voltage across the avalanche diode 460 to drop. After quenching of the avalanche current, the voltage across the avalanche diode 460 recovers to above the bias voltage and the avalanche diode 460 is then ready to be triggered again. The resulting output pulse 465 of each avalanche diode 460 is received by its corresponding digital counter 480, which increments its count in response to the output pulse 465.

Conventional SPAD pixel designs that incorporate a SPAD on the same chip as a CMOS digital counter fabricated using a standard CMOS process suffer from a reduced fill factor at the imaging plane due to the area occupied by the CMOS circuitry itself. Therefore, one advantage of implementing a stacked chip structure in accordance with the teachings of the present invention provides for an improved fill factor at the imaging plane.

It should be noted that the circuit diagram of FIG4B is provided herein for purposes of explanation and some other circuit elements (e.g., passive components such as resistors and capacitors and active components such as transistors) are not shown in detail so as not to obscure the teachings of the present invention. For example, the illustrated pixel circuit of FIG4B may generate an output pulse 465 that requires amplification before being sensed by the input of the digital counter 480. In another example, the connection at the node between the quenching element 470 and the avalanche diode 460 will be at a high voltage, which may require AC coupling.

FIG5 is a cross-sectional view of one example of an integrated circuit system 500 including a 3D color pixel array having stacked device dies in accordance with the teachings of the present invention. Integrated circuit system 500 is one possible implementation of the color time-of-flight pixel array 210 of FIG2 with the RGB-IR filter array 300 of FIG3. For example, the integrated circuit system 500 of FIG5 can be a cross-sectional view taken along dashed line AA' of FIG3. The illustrated example of integrated circuit system 500 shown in FIG5 includes a first device die 506, a second device die 508, and a bonding interface 507 at which the first device die 506 is bonded to the second device die 508. The first device die 506 includes a first semiconductor layer 510 and a first interconnect layer 512, while the second device die 508 includes a second semiconductor layer 514 and a second interconnect layer 516. The illustrated example shows a plurality of visible light pixels 502A, 502B, 502C, and 502D and a plurality of SPAD pixels 503A and 503B arranged in rows and columns (for example, such as also illustrated in Figures 2 and 3).

In one example, visible light pixels 502A, 502B, 502C, and 502D can each include a photosensitive region or photodiode 504A, 504B, 504C, and 504D, respectively, disposed proximate to a front side 511 of a first semiconductor layer 510. In one example, SPAD pixels 503A and 503B can each include a multiplication region 505A and 505B, respectively, formed proximate to a front side 511 of a first semiconductor layer 510. In the depicted example, photodiodes 504A, 504B, 504C, and 504D and multiplication regions 505A and 505B are configured to be illuminated through a back side 513 of the first semiconductor layer 510 in accordance with the teachings of the present invention.

In one example, the second device die 508 is a CMOS logic die fabricated using a standard CMOS process and includes a second semiconductor layer 514 that includes visible light readout circuitry 517A, 517B, 517C, and 517D, and IR light readout circuitry 519A and 519B. In one example, the IR light readout circuitry 519A and 519B includes a digital counter similar to, for example, digital counter 480 of FIG. 4 . In one example, a hybrid bonding via 528 is included at the bonding interface 507, as shown. For example, in one example, the hybrid bonding via 528 can be included to transfer the voltage of the SPAD pixels 503A and 503B included in the first device die 506 to the IR light readout circuitry 519A and 519B included in the second device die 508. Each of visible light readout circuits 517A, 517B, 517C, and 517D can include sample-and-hold circuitry and analog-to-digital conversion (ADC) circuitry. As shown in the depicted example, visible light readout circuits 517A, 517B, 517C, and 517D, as well as IR light readout circuits 519A and 519B, are formed proximate to the front side 520 of the second semiconductor layer 514. In the illustrated example, visible light readout circuits 517A, 517B, 517C, and 517D are disposed in regions of semiconductor layer 514 within their respective visible light pixels (e.g., 502A, 502B, 502C, and 502D, respectively). Similarly, IR light readout circuits 519A and 519B are disposed in regions of semiconductor layer 514 within their respective SPAD pixels (e.g., 503A and 503B, respectively). In other examples, the visible light readout circuits of adjacent visible light pixels within a color time-of-flight pixel array can be grouped to form a common die area. This common die area can be used by digital counters in the IR light readout circuits of adjacent SPAD pixels.

The above description of the illustrated embodiments of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments and examples of the invention are described herein for illustrative purposes, those skilled in the relevant art will recognize that various modifications can be made within the scope of the invention.

These modifications can be made to the invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the appended claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (14)

1. A pixel array comprising: A plurality of visible light pixels are arranged in a pixel array, each of the plurality of visible light pixels comprising a photosensitive element disposed in a first semiconductor die for detecting visible light, wherein the plurality of visible light pixels are arranged in the pixel array having color filters arranged in a Bayer pattern, the Bayer pattern having a repeating pattern including a red filter, a first green filter, a second green filter, and a blue filter to provide color image data, wherein each of the plurality of visible light pixels is coupled to provide the color image data to a visible light readout circuit disposed in a second semiconductor die, the second semiconductor die being stacked with and coupled to the first semiconductor die in a stacked chip configuration; and A plurality of infrared (IR) pixels are arranged in the pixel array, each of the plurality of IR pixels comprising a single-photon avalanche photodiode (SPAD) disposed in the first semiconductor die for detecting IR light, wherein each of the plurality of IR pixels is coupled to provide IR image data to an IR light readout circuit disposed in the second semiconductor die. Each of the plurality of IR pixels is surrounded by the plurality of visible light pixels on all lateral sides of the first semiconductor die. The plurality of IR pixels are distributed among the plurality of visible light pixels in the first semiconductor die, passing through the pixel array. 2. The pixel array of claim 1, wherein the size ratio between each of the plurality of IR pixels and each of the plurality of visible light pixels is 4 to 1. 3. The pixel array of claim 1, wherein the plurality of visible light pixels and the plurality of IR pixels are adapted to be illuminated through the back side of the first semiconductor die. 4. The pixel array of claim 1, wherein the IR image data provided by the plurality of IR pixels provides time-of-flight information to provide three-dimensional 3D image data. 5. The pixel array of claim 1, wherein the plurality of visible light pixels and the plurality of IR pixels in the first semiconductor die are coupled to the visible light readout circuit and the IR light readout circuit in the second semiconductor die via a hybrid bonding via at the bonding interface between the first semiconductor die and the second semiconductor die. 6. The pixel array according to claim 1, wherein the second semiconductor die is an application-specific integrated circuit (ASIC) die. 7. The pixel array of claim 1, wherein the IR light readout circuit comprises a plurality of digital counters coupled to count output pulses generated by each SPAD of each of the plurality of IR pixels in response to a received photon. 8. An image sensing system, comprising: A light source, used to emit infrared (IR) light pulses onto an object; A pixel array for receiving visible light and reflected IR light pulses from the object, wherein the pixel array comprises: A plurality of visible light pixels are arranged in a pixel array, each of the plurality of visible light pixels comprising a photosensitive element disposed in a first semiconductor die for detecting visible light from the object, wherein the plurality of visible light pixels are arranged in the pixel array having color filters arranged in a Bayer pattern, the Bayer pattern having a repeating pattern including a red filter, a first green filter, a second green filter, and a blue filter to provide color image data, wherein each of the plurality of visible light pixels is coupled to provide the color image data to a visible light readout circuit disposed in a second semiconductor die, the second semiconductor die being stacked with and coupled to the first semiconductor die in a stacked chip configuration; and A plurality of IR pixels are arranged in the pixel array, each of the plurality of IR pixels comprising a single-photon avalanche photodiode (SPAD) disposed in the first semiconductor die to detect reflected IR light pulses from the object to generate time-of-flight information; each of the plurality of IR pixels is coupled to provide IR image data to an IR light readout circuit disposed in the second semiconductor die; each of the plurality of IR pixels is surrounded by the plurality of visible light pixels on all lateral sides of the first semiconductor die; the plurality of IR pixels are distributed throughout the plurality of visible light pixels in the first semiconductor die, extending through the pixel array. A control circuit, coupled to control the operation of the pixel array and controlled and synchronized the light source by means of a synchronization signal, so that the emission of the light pulses is synchronized with the timing of the sensing of photons reflected from the object. 9. The image sensing system of claim 8, further comprising functional logic coupled to the visible light readout circuit and the IR light readout circuit to store and process color image data and the IR image data read from the pixel array, wherein the functional logic is coupled to combine the color image data and the IR image data to generate the time-of-flight information and provide a color three-dimensional 3D image. 10. The image sensing system of claim 8, wherein the size ratio between each of the plurality of IR pixels and each of the plurality of visible light pixels is 4 to 1. 11. The image sensing system of claim 8, wherein the plurality of visible light pixels and the plurality of IR pixels are adapted to be illuminated through the back side of the first semiconductor die. 12. The image sensing system of claim 8, wherein the plurality of visible light pixels and the plurality of IR pixels in the first semiconductor die are coupled to the visible light readout circuit and the IR light readout circuit in the second semiconductor die via a hybrid bonding via at the bonding interface between the first semiconductor die and the second semiconductor die. 13. The image sensing system of claim 8, wherein the second semiconductor die is an application-specific integrated circuit (ASIC) die. 14. The image sensing system of claim 8, wherein the IR light readout circuit comprises a plurality of digital counters coupled to count output pulses generated by each SPAD of each of the plurality of IR pixels in response to a received photon.