HK1223201B - Cascode switch for power amplifier - Google Patents

Description

Cascode Switching for Power Amplifiers

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application No. 62/098,186, filed December 30, 2014, entitled “CASCODE SWITCH FOR POWER AMPLIFIER,” the entire disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to an electronic system, and more particularly, to a cascode circuit.

Background Art

A power amplifier may be included in a wireless communication device to amplify a radio frequency (RF) signal for transmission via an antenna. The RF signal may be in a frequency range from approximately 30 kHz to 300 GHz. Certain power amplifiers may operate in multiple operating modes. For example, different operating modes may be associated with different power modes. There are many design trade-offs associated with effectively operating in each of the multiple operating modes while also achieving a desired performance level in each of the multiple operating modes.

Some multi-mode power amplifiers include RF signal paths associated with different operating modes. One or more selected RF signal paths can be switched in or out of a particular operating mode. Certain switching elements with relatively low loss and relatively low distortion can be expensive to implement and may not be easily implemented on the same die as the power amplifier.

Summary of the Invention

The innovations described in the claims each have several aspects, no single one of which is solely responsible for its desirable attributes.Without limiting the scope of the claims, some of the notable features of the disclosure will now be described briefly.

One aspect of the present disclosure is a power amplifier system comprising a first power amplifier stage, a second power amplifier stage, and a cascode circuit. The first power amplifier stage is configured to amplify a radio frequency (RF) signal. The second power amplifier stage comprises a first power amplifier transistor and a second power amplifier transistor. The cascode circuit comprises a first cascode transistor and a second cascode transistor. The first cascode transistor is configured to selectively provide an output from the first power amplifier stage to the first power amplifier transistor. The second cascode transistor is configured to selectively provide an output from the first power amplifier stage to the second power amplifier transistor.

The first power amplifier stage, the second power amplifier stage, and the cascode circuit can be implemented on a single die. The single die can be formed using a SiGe bipolar transistor process or a GaAs heterojunction bipolar transistor process.

The cascode circuit may include bipolar cascode transistors. For example, the first cascode transistor may be a first bipolar cascode transistor, and the second cascode transistor may be a second cascode transistor. The first power amplifier stage may include a first power amplifier stage bipolar transistor having a collector electrically connected to an emitter of the first cascode bipolar transistor and an emitter of the second cascode bipolar transistor. In some embodiments, the feedback circuit may provide feedback from the collector of at least one of the first cascode bipolar transistor or the second cascode bipolar transistor to an input of the first power amplifier stage. Alternatively or additionally, a termination circuit electrically coupled to the base of the first cascode bipolar transistor may provide a termination impedance for the base of the first cascode bipolar transistor.

The output of the first power amplifier stage can be provided to different power amplifier transistors of the second power amplifier stage in different operating modes. For example, the first power amplifier transistor can receive the output of the first power amplifier stage in high power mode, and the second power amplifier transistor can receive the output of the first power amplifier stage in low power mode. Alternatively or additionally, the first power amplifier transistor can receive the output of the first power amplifier stage when the output of the first power amplifier stage is within a first frequency band, and the second power amplifier transistor can receive the output when the output of the first power amplifier stage is within a second frequency band.

The first power amplifier transistor may be implemented by a first transistor array having a larger physical area than a second transistor array implementing the second power amplifier transistor.

The second power amplifier stage may include a third power amplifier transistor, and the cascode circuit may include the third cascode transistor configured to selectively provide the output from the first power amplifier stage to the third power amplifier transistor.

Another aspect of the present disclosure is a semiconductor die comprising a first power amplifier transistor, a second power amplifier transistor, and a cascode circuit. The cascode circuit comprises a first cascode bipolar transistor and a second cascode bipolar transistor. The first cascode bipolar transistor is configured to selectively provide a radio frequency (RF) signal to the first power amplifier transistor. The second cascode bipolar transistor is configured to selectively provide the RF signal to the second power amplifier transistor.

The emitter of the first cascode bipolar transistor may be electrically connected to the emitter of the second cascode bipolar transistor.The first stage power amplifier bipolar transistor may have a collector electrically connected to the emitter of the first cascode bipolar transistor and the emitter of the second cascode bipolar transistor.

The cascode circuit may include a SiGe bipolar transistor or a GaAs heterojunction bipolar transistor.

The termination circuit may be electrically connected to the base of the first bipolar cascode transistor.

Another aspect of the present disclosure is a packaged power amplifier module that includes a power amplifier die, a packaging substrate on which the power amplifier die is disposed, and packaging on the packaging substrate and the power amplifier die. The power amplifier die includes a first power amplifier stage, a second power amplifier stage, a first cascode bipolar transistor configured to selectively provide a radio frequency (RF) signal from the first power amplifier stage to a first power amplifier transistor of the second power amplifier stage in a first mode, and a second cascode bipolar transistor configured to selectively provide the RF signal from the first power amplifier stage to a second power amplifier transistor of the second power amplifier stage in a second mode.

The first power amplifier transistor may be a GaAs heterojunction bipolar transistor. The packaged power amplifier module may include a surface mount component on the package substrate, and the surface mount component is in communication with the power amplifier die. The packaged power amplifier module may include wire bonds that provide electrical connections from the power amplifier die to pads on the package substrate.

Another aspect of the present disclosure is an amplifier circuit including an amplifier bipolar transistor, a first load, a second load, and a cascode circuit. The cascode circuit includes a first cascode bipolar transistor and a second cascode bipolar transistor. The first cascode bipolar transistor is configured to selectively provide an output from the amplifier bipolar transistor to the first load. The second cascode bipolar transistor is configured to selectively provide an output from the amplifier bipolar transistor to the second load.

The amplifier bipolar transistor may include a base configured to receive a radio frequency signal and a collector configured to provide an amplified radio frequency signal. The collector of the amplifier bipolar transistor may be electrically connected to the first cascode bipolar transistor and the second cascode bipolar transistor.

The first cascode bipolar transistor can provide the output of the amplifier bipolar transistor to a first load in a first operating mode, and the second cascode bipolar transistor can provide the output of the amplifier bipolar transistor to a second load in a second operating mode. The operating modes can be associated with power modes (e.g., low power mode and high power mode) and/or frequency bands of the outputs from the amplifier bipolar transistors.

Another aspect of the present disclosure is a wireless communication device. The wireless communication device includes a power amplifier system, an antenna, and a switching module configured to selectively electrically connect the output of the power amplifier system to the antenna. The power amplifier system includes a first power amplifier stage, a second power amplifier stage, and a cascode circuit. The first power amplifier stage is configured to amplify a radio frequency (RF) signal. The second power amplifier stage includes a first power amplifier transistor and a second power amplifier transistor. The cascode circuit includes a first cascode transistor and a second cascode transistor. The first cascode transistor is configured to selectively provide the output from the first power amplifier stage to the first power amplifier transistor. The second cascode transistor is configured to selectively provide the output from the first power amplifier stage to the second power amplifier transistor. In some embodiments, the power amplifier system can provide a wireless local area network signal to the antenna via the switching module.

For the purposes of summarizing the present disclosure, certain aspects, advantages, and novel features of the present invention have been described herein. It will be understood that it is not necessary to realize all of these advantages according to any particular embodiment of the present invention. Therefore, the present invention can be implemented or carried out in a manner that realizes or optimizes an advantage or a group of advantages as taught herein without necessarily realizing other advantages that may be taught or proposed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure will now be described, by way of non-limiting examples, with reference to the accompanying drawings.

1 is a schematic diagram of a power amplifier system including a multi-stage power amplifier with cascode circuits between power amplifier stages, according to an embodiment.

2A is a schematic diagram of a power amplifier system including a multi-stage power amplifier with cascode circuits between power amplifier stages, according to an embodiment.

2B is a graph comparing the efficiency in high power mode with the efficiency in low power mode for a conventional power amplifier, where the low power mode is achieved by reducing the area of the low power output power amplifier transistor relative to the high power output power amplifier transistor.

2C is a graph comparing efficiency in high power mode to efficiency in low power mode for a power amplifier having cascode circuits between power amplifier stages according to an embodiment.

3 is a schematic diagram of a power amplifier system including a multi-stage power amplifier with cascode circuits between power amplifier stages, according to an embodiment.

4 is a schematic diagram of an electronic system including a cascode circuit with bipolar cascode transistors between an amplifier and a separate load, according to an embodiment.

FIG5A is a schematic diagram of an example of a packaged power amplifier module according to an embodiment.

5B is a schematic diagram of a cross-section of the packaged power amplifier module of FIG. 5A taken along line 5B-5B.

6 is a schematic block diagram of an example wireless communication device including a power amplifier with a cascode circuit according to any of the embodiments of FIG. 1 , FIG. 2A , FIG. 3 , and/or FIG. 4 .

DETAILED DESCRIPTION

The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein may be embodied in a number of different ways, for example, as defined and covered by the claims. In this description, reference is made to the accompanying drawings, in which the same reference numerals may indicate identical or functionally similar elements. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it should be understood that certain embodiments may include more elements than shown in the drawings and/or include a subset of the elements shown in the drawings. Furthermore, some embodiments may incorporate any suitable combination of features from two or more of the drawings.

A power amplifier (PA) can amplify a radio frequency (RF) signal in two or more operating modes. For example, the first operating mode can be a high power mode, and the second operating mode can be a low power mode.

In the first operating mode, the PA can deliver a relatively high-power output signal. The array of amplifying transistors of the power amplifier can be large enough to deliver the required high-power output signal. If such an array of amplifying transistors is too small, the amplifying transistors of the array can be driven relatively close to the high-level injection region of the transistor characteristics, which can reduce the linearity of the amplified signal. In other words, the amplified RF signal provided by the PA can be distorted due to saturation of the transistors within the inappropriately sized array.

Providing an array of appropriately sized amplifier transistors is a design choice that also involves a range of other design considerations, including, for example, the selection of PA load lines and matching circuit components. The choice of PA load lines and array size can determine the efficiency of the PA, as well as several other performance attributes of the PA. Additionally, the selection and design of appropriate matching circuits can determine how effectively the amplified RF signal from the PA array is delivered to subsequent RF signal conditioning elements in the RF chain (e.g., antennas, RF switches, etc.). In terms of facilitating high-power operation, a number of design choices can optimize the PA for high-power mode.

In the second operating mode, the PA can deliver a relatively low power output signal. The low power output signal has a lower power level than the high power output signal. Design choices made for the first operating mode may not be optimal and/or appropriate for the second operating mode. As a result, such design choices may result in significantly inefficient operation of the PA in the second operating mode. The low power operating mode of the PA can be better served by utilizing a smaller array of amplifier transistors and a completely different load line and matching circuit relative to when the PA operates in the higher power operating mode.

In the context of a multi-mode PA, it would be advantageous to be able to switch "in" or switch "out" of two or more branches of a signal amplification path so that when operating in a particular mode, a selected branch configured for a particular mode is switched "in," and in the particular mode, one or more other branches are switched "out." For example, in a PA with a low-power mode and a high-power mode, a first path comprising a larger transistor array with appropriate load lines and matching circuit elements for the high-power mode can be switched "in" for the high-power mode, and a second path comprising a smaller transistor array with appropriate load lines and matching circuit elements for the low-power mode can be switched "in" for the low-power mode.

However, relatively low-loss, relatively low-distortion switching elements may be desirable for switching RF signals from one path so that the electronic system does not significantly lose or distort the RF signal delivered from the preceding stage of RF signal conditioning. In some semiconductor technology platforms, relatively low-loss, relatively low-distortion switches are not available in the form of metal oxide field-effect transistors (MOSFETs) or other types of devices typically used as switches (e.g., mechanical switches, diodes, etc.). In fact, in some semiconductor technology platforms suitable for power amplifiers, the only suitable device available for implementing switches on the power amplifier die is a bipolar transistor.

Therefore, there is a need for an architecture that allows selection and switching between two or more RF signal paths to enable a selected RF path corresponding to a particular operating mode of the PA by virtue of semiconductor and passive device elements forming an integrated circuit in the selected path.

In this disclosure, a cascode topology is described as switching between different RF signal paths. Each current buffer transistor in the cascode topology can be either on or off, depending on the RF path desired for the selected operating mode. The cascode transistors can be implemented using bipolar transistors.

In one embodiment, two current buffer transistors are electrically connected to the power amplifier transistors of the first stage of the PA. Depending on which current buffer transistor is turned on by a switching bias control signal provided by a bias control circuit, the RF signal is delivered from the first stage of the PA to the appropriately sized amplifier transistor array of the second stage of the PA. In a low-power mode, the first current buffer transistor can provide the RF signal from the first stage of the PA to the smaller amplifier transistor array, and the second current buffer transistor can be turned off. In a high-power mode, the second current buffer transistor can provide the RF signal from the first stage of the PA to the larger amplifier transistor array, and the first current buffer transistor can be turned off. As an example, the emitter area of the smaller amplifier transistor array can be between about 1/5 and about 1/6 of the emitter area of the larger amplifier transistor array.

Therefore, the cascode topology can use bipolar transistors, such as NPN bipolar transistors, to perform the switching function, allowing the PA to have two operating modes. This technique can also be used to configure additional modes and/or RF signal paths. Additional circuitry related to stability and feedback can also be implemented.

The cascode topology may include a transconductance amplifier followed by two or more selectively enabled current buffers. The transconductance amplifier may be a common emitter amplifier, in which a bipolar transistor amplifies a signal supplied to its base and provides an amplified signal at its collector. The current buffer may be a common base amplifier, in which a bipolar transistor amplifies a signal supplied to its emitter and provides an amplified signal at its collector. The current buffer may be referred to as a cascode transistor. The cascode topology with a transconductance amplifier and a current buffer may provide relatively high input-output isolation, relatively high input impedance, relatively high output impedance, relatively high gain, and bandwidth. Due to the bias applied to each transistor, the cascode topology may reduce the power supply headroom for the amplifier stage. In certain embodiments, the supply voltage may provide sufficient headroom for the power amplifier system. For example, in one implementation, the supply voltage may be at least about 3 volts (e.g., about 3.3 volts).

The embodiments discussed herein can advantageously enable two or more operating modes by using bipolar transistor technology to switch between different RF signal paths. Thus, such embodiments can be implemented using relatively low-cost bipolar process technology alone. Using the principles and advantages discussed herein, switching between different RF signal paths can also be implemented using other relatively low-cost processes that do not have low-loss, low-distortion RF switching devices (such as field-effect transistors).

Using bipolar transistors to switch between different RF signal paths can enable such bipolar transistors to be implemented on a single die that also includes power amplifier transistors. Thus, this can eliminate the need for a second die to implement a low-loss, low-distortion RF switching device that switches between different RF paths associated with different operating modes. In some embodiments, two stages of a power amplifier and the bipolar transistors used as switches between the two stages can be implemented on a single die in a compact and integrated manner.

In addition, the ability to switch between different RF signal paths for different operating modes can enable different RF signal paths to be configured and/or optimized for one or more specific modes. For example, different RF signal paths can be implemented for higher power modes and lower power modes. Different RF signal paths can include different transistors and different matching networks so that a specific matching network can be configured for a specific amplifying transistor array output. This can simplify the individual output matching networks, thereby significantly reducing the total die area used for output matching.

Various aspects of the present disclosure relate to a multi-stage power amplifier having cascode transistors configured to selectively provide the output of one stage of the power amplifier to a transistor of a subsequent stage of the power amplifier. Bipolar transistors can implement the cascode transistors and the power amplifier. Thus, in such an implementation, when field-effect transistors are not available, the multi-stage power amplifier and the cascode transistors can be implemented. For example, the multi-stage power amplifier and the cascode transistors can be implemented on a single bare die formed using a process technology that implements bipolar transistors but not field-effect transistors. The multi-stage power amplifier can be a wireless local area network (WLAN) power amplifier with a low power state. Such a power amplifier can be implemented in a mobile computing device such as a smartphone or a wearable computer (e.g., a smart watch).

The cascode circuit may include a first cascode transistor and a second cascode transistor. The first cascode transistor and the second cascode transistor may each serve as a current buffer. The first cascode transistor may selectively provide an RF signal from a first power amplifier stage to a first power amplifier transistor of a subsequent power amplifier stage. The second cascode transistor may selectively provide an RF signal from the first power amplifier stage to a second power amplifier transistor of a subsequent stage. The bias control circuit may turn on the first cascode transistor and turn off the second cascode transistor in a first operating mode (e.g., a high-power operating mode) so that the first power amplifier transistor of the subsequent stage receives the RF signal. The bias control circuit may turn off the first cascode transistor and turn on the second cascode transistor in a second operating mode (e.g., a low-power operating mode) so that the second power amplifier transistor of the subsequent stage receives the RF signal.

The first power amplifier transistor and the second power amplifier transistor in the subsequent stage can each have a different output matching network electrically coupled to their respective outputs. Each of these output matching networks can be configured for a different operating mode. This can simplify the output matching network and/or significantly reduce the die area of the matching network.

FIG1 is a schematic diagram of a power amplifier system 10 including a multi-stage power amplifier with a cascode circuit between power amplifier stages according to an embodiment. As shown, the power amplifier system 10 includes a first power amplifier stage 12, a cascode circuit 14, a second power amplifier stage including a first portion 16 and a second portion 18, and a bias control circuit 20. In certain implementations, the power amplifier system 10 can transmit wireless local area network (WLAN) signals. In some applications, the power amplifier system 10 can provide RF output signals in the 2.4 GHz band and/or the 5 GHz band. The power amplifier system 10 can include more elements than those shown in FIG1 , and/or some embodiments may include a subset of the elements shown. The power amplifier system 10 can be implemented on a single bare die.

The first power amplifier stage 12 is configured to amplify the RF signal RF_IN and provide an amplified RF signal. The power amplifier stage 12 may include any suitable RF power amplifier transistor. For example, the first power amplifier stage 12 may be implemented by one or more bipolar transistors, such as one or more SiGe bipolar transistors or one or more GaAs heterojunction bipolar transistors (HBTs). The first power amplifier stage 12 can be activated and disabled as needed. For example, when the amplified RF signal provided by the first power amplifier stage 12 is not in use, a power amplifier bias signal (not shown in FIG. 1 ) provided to the first power amplifier stage 12 may disable the first power amplifier stage 12.

The multi-stage power amplifier of FIG1 is arranged to operate in more than one operating mode. Cascode circuit 14 can selectively provide the output of first power amplifier stage 12 to first portion 16 and/or second portion 18 of second power amplifier stage. Cascode circuit 14, together with first stage 12, can function as a switched cascode amplifier. Cascode circuit 14 can act as a switch to provide the RF output signal from first power amplifier stage 12 to a selected portion of the second power amplifier stage. As shown, cascode circuit 14 includes a first cascode transistor 22 and a second cascode transistor 24. When activated, first cascode transistor 22 can electrically connect first power amplifier stage 12 to first portion 16 of second stage. When activated, second cascode transistor 24 can electrically connect first stage power amplifier 12 to second portion 18 of second stage.

Bias control circuit 20 can provide a first signal to first cascode transistor 22 and a second signal to second cascode transistor 24. Bias control circuit 20 can be implemented using any suitable circuitry. Bias control circuit 20 can selectively bias first cascode transistor 22 as a switch. First cascode transistor 22 can be turned on and off in response to the signal level of the first signal. Bias control circuit 20 can selectively bias second cascode transistor 24 as a switch. Second cascode transistor 24 can be turned on and off in response to the signal level of the second signal. Thus, bias control circuit 20 can control first cascode transistor 22 and second cascode transistor 24 to selectively provide RF signals to first section 16 and second section 18 of the second stage of the power amplifier, respectively. The first and second signals can be generated at least in part based on an indication of an operating mode of the power amplifier system. In one embodiment, the first and second signals can be logical complements. According to another embodiment, the first and second signals can respectively control first cascode transistor 22 and second transistor 24 so that both transistors are simultaneously activated in the operating mode. The bias control circuit 20 may be a wide bandwidth bias circuit that provides a relatively low impedance to the cascode circuit 14 .

FIG2A is a schematic diagram of a power amplifier system 30 including a multi-stage power amplifier with cascode circuitry between power amplifier stages, according to an embodiment. Power amplifier system 30 is an example of power amplifier system 10 and also illustrates additional circuitry including a corresponding output matching network. As shown, power amplifier system 30 includes first power amplifier stage 12, cascode transistors 22 and 24, first and second portions 16 and 18 of a second power amplifier stage, bias control circuit 20, termination circuits 32, 36, 38, 45, and 46, a feedback circuit including resistors 40 and 41 and capacitor 42, capacitors 43 and 44, and output matching networks 48 and 49. Power amplifier system 30 may include more components than those shown in FIG2A, and/or some embodiments may include a subset of the components shown. In some embodiments, power amplifier system 30 may be implemented on a single die.

The first power amplifier stage 12 can be implemented using a bipolar transistor, as shown in FIG2A . This bipolar transistor can be referred to as an amplifier bipolar transistor. Although the amplifier bipolar transistor shown is an NPN transistor, it should be understood that the principles and advantages discussed herein can also be applied to a PNP amplifier bipolar transistor. Although shown as a single bipolar transistor, the first power amplifier stage 12 can be implemented using an array of bipolar transistors that together function as a single bipolar transistor. As shown in FIG2A , the first power amplifier stage 12 can be configured as a common-emitter amplifier, configured to amplify an RF signal received at its base. A termination circuit 32 can provide impedance matching at the base of the amplifier bipolar transistor. Termination circuit 32 can be implemented using one or more suitable passive circuit elements arranged between the base of the amplifier bipolar transistor and a reference voltage (such as ground). As shown in FIG2A , termination circuit 32 is a series LC circuit. The emitter of the amplifier bipolar transistor can be electrically connected to ground or another suitable reference voltage. The collector of the amplifier bipolar transistor can be electrically connected to a cascode circuit, which includes cascode transistors 22 and 24. As shown in FIG. 2A , the collector of the amplifier bipolar transistor is electrically connected to the emitter of the first cascode transistor 22 and the emitter of the second cascode transistor 24 .

In FIG2A , the cascode circuit is implemented using bipolar transistors. Thus, these cascode bipolar transistors can selectively provide the RF signal from the collector of the amplifier bipolar transistor to a selected portion of the second stage of the power amplifier. This can implement a switching function in bipolar technology. The switching function performed by the bipolar cascode circuit can achieve suitable performance for switching RF signals when field effect transistors or other switching elements are not available to perform the switching function. In addition, when the first and second power amplifier stages are also implemented using bipolar transistors, the cascode circuit, the first power amplifier stage, and the second power amplifier stage can be formed on a single bare die using a bipolar process.

The first cascode transistor 22 of FIG. 2A is a cascode bipolar transistor. Although the cascode bipolar transistor shown is an NPN transistor, it should be understood that the principles and advantages discussed herein can be applied to PNP cascode bipolar transistors and/or combinations of NPN and PNP cascode bipolar transistors. Each cascode transistor can be configured as a common base amplifier. As shown, the first cascode transistor 22 has an emitter, a base, and a collector. The emitter is configured to receive an RF signal from the collector of the amplifier transistor of the first power amplifier stage 12, the base is configured to receive a first signal from the bias control circuit 20, and the collector is configured to provide the RF signal to the first portion 16 of the second power amplifier stage. A termination circuit 36 is electrically connected to the base of the first cascode transistor 22. The termination circuit 36 can include a series RC circuit electrically connected between the base of the first cascode transistor 22 and a reference voltage (such as ground). The resistor of the series RC circuit can provide a controlled impedance to ensure stability. The capacitor of the series RC circuit can be used as a decoupling capacitor to provide terminal impedance for RF signals.

The second cascode transistor 24 of FIG2A is a cascode bipolar transistor. As shown, the first cascode transistor 24 has an emitter, a base, and a collector. The emitter is configured to receive an RF signal from the collector of the amplifier transistor of the first power amplifier stage 12, the base is configured to receive a second signal from the bias control circuit 20, and the collector is configured to provide the RF signal to the second portion 18 of the second power amplifier stage. A termination circuit 38 is electrically connected to the base of the second cascode transistor 24. The termination circuit 38 may include a series RC circuit electrically connected between the base of the second cascode transistor 24 and a reference voltage (such as ground). The resistor of the series RC circuit can provide a controlled impedance to ensure stability. The capacitor of the series RC circuit can serve as a decoupling capacitor to provide a termination impedance for the RF signal.

The bias control circuit 20 may generate a first signal and a second signal. The bias control circuit 20 may generate these signals based at least in part on an indication of an operating mode of the power amplifier system 30. The first signal and the second signal may be direct current (DC) signals. These signals may be provided to the respective bases of the cascode transistors via a resistor having a relatively low impedance. In some embodiments, the first signal may be the logical complement of the second signal. Thus, in such embodiments, one of the first cascode transistor 22 or the second cascode transistor 24 may be turned on, while the other may be turned off. The signal levels of the first signal and the second signal may control whether the first cascode transistor 22 and the second cascode transistor 24 are turned on or off, respectively. In one implementation, the first bias signal and the second bias signal may provide a difference of approximately 400 mV between the bases of the first cascode transistor 22 and the second cascode transistor 24. For example, the base of one cascode transistor may be approximately +200 mV, while the base of the other cascode transistor may be approximately -200 mV.

The base of the amplifier bipolar transistor can receive feedback from at least one of the collectors of the cascode bipolar transistors. As shown in FIG2A , resistors 40 and 41 are arranged in series between the collectors of cascode transistors 22 and 24. Resistors 40 and 41 can help stabilize the circuit. Capacitor 42 can be electrically connected between the base of the amplifier bipolar transistor and an intermediate node between resistors 40 and 41. Capacitor 42 can provide RF feedback from the cascode circuit to the base of the common-emitter amplifier of the first stage 12 of the power amplifier.

The first portion 16 of the second power amplifier stage is configured to receive an RF signal from the first cascode transistor 22. The RF signal can be received via a capacitor 43, as shown in FIG2A . Capacitor 43 can serve as an alternating current (AC) coupling capacitor. In FIG2A , the first portion 16 of the second power amplifier stage is a bipolar power amplifier transistor having a base configured to receive an RF signal from the collector of the first cascode transistor 22 and to provide an amplified RF signal at its collector. In certain embodiments, the bipolar power amplifier transistor can have an emitter electrically connected to ground via a through-wafer via. A terminal circuit 45 can be electrically connected to the base of the power amplifier transistor. In certain embodiments, the terminal circuit 45 can be electrically connected to ground via a through-wafer via. As shown, an output matching network 48 is electrically connected to the collector of the power amplifier transistor. The output matching network 48 can be arranged to provide output matching for a specific operating mode of the power amplifier system. The output matching network 48 may include, for example, one or more series LC circuits electrically connected between the collector of the first power amplifier transistor and ground, and one or more parallel LC circuits electrically connected in series between the collector of the first power amplifier transistor and electronic components in the RF signal path.

The second portion 18 of the second power amplifier stage can be functionally similar to the first power amplifier stage 16 . While the second cascode transistor 24 provides the RF signal from the first power amplifier stage 16 , the second portion 18 of the second power amplifier stage can receive the RF signal. The power amplifier transistors of the first portion 16 can be referred to as first power amplifier transistors, and the power amplifier transistors of the second portion 18 can be referred to as second power amplifier transistors. The second portion 18 of the second power amplifier stage can be implemented using bipolar power amplifier transistors having a different emitter area than the first portion 16 of the second power amplifier stage. For example, each of these power amplifier transistors can be implemented using a smaller transistor array, and the array sizes of the first portion 16 and the second portion 18 can be different. As an example, the emitter area of the second portion 18 can be approximately five times the emitter area of the first portion 16 . Although shown as a single bipolar power amplifier transistor, the first portion 16 of the second power amplifier stage and the second portion 18 of the second power amplifier stage can each be implemented using an array of bipolar transistors that together function as a single bipolar transistor. More generally, any transistor discussed herein can be implemented using an array of suitable transistors. When second portion 18 has a larger emitter area than first portion 16, second portion 18 can provide better performance for higher power modes, and first portion 16 can provide better performance for lower power modes. Termination circuits 45 and 46 can provide different termination impedances for operation in different operating modes. As shown, termination circuits 45 and 46 can each include a series LC circuit.

Matching network 49, together with the second power amplifier transistor of the second stage, can be arranged to meet performance criteria for a particular operating mode, such as a high power mode. Similarly, matching network 48, together with the first power amplifier transistor, can be arranged to meet performance criteria associated with an operating mode different from that of the second power amplifier transistor and matching network 49. For example, the different operating mode can be a low power mode. As another example, the particular operating mode and the different operating mode can be associated with different frequency bands of the RF input signal RF_IN. Bias control circuit 20 and cascode transistors 22 and 24 can provide the RF signal amplified by first stage 12 to the particular power amplifier transistor depending on the operating mode. The operating mode can be associated with the power mode and/or frequency band of power amplifier system 30.

Figures 2B and 2C provide a comparison between the efficiency of a conventional wireless local area network (WLAN) power amplifier and the efficiency of a cascoded switched amplifier according to an embodiment. The curves in Figures 2B and 2C represent the efficiency of the power amplifier as a function of output power for different power operating modes.

FIG2B is a graph comparing the efficiency in high power mode and the efficiency in low power mode for a conventional power amplifier, where the low power mode is achieved by reducing the area of the low power output power amplifier transistor relative to the high power output power amplifier transistor without changing the load. The graph of FIG2B indicates that at 15 dBm in the conventional power amplifier, the efficiency can be improved from about 7% for the high power mode to about 8% for the low power mode.

FIG2C is a graph comparing efficiency in high power mode and efficiency in low power mode for a power amplifier having cascode circuitry between power amplifier stages according to an embodiment. The low power curve in FIG2C corresponds to using cascode transistors to drive an optimized low power output stage. The curve in FIG2C indicates that at 15 dBm in a power amplifier having cascode circuitry, efficiency can be improved from approximately 7% in high power mode to approximately 14% in low power mode.

FIG3 is a schematic diagram of a power amplifier system 50 including a multi-stage power amplifier with cascode circuits between power amplifier stages according to an embodiment. Power amplifier system 50 is similar to power amplifier system 10 of FIG1 , except that power amplifier system 50 includes two or more portions of a second stage that can be selectively enabled by separate cascode transistors. Power amplifier system 50 may include more elements than those shown in FIG3 , and/or some embodiments may include a subset of the elements shown. Power amplifier system 50 may be implemented on a single die.

1 , and includes cascode transistors corresponding to each section of the second power amplifier stage. For example, when the second stage includes three sections 16, 18, and 52, cascode transistors 22, 24, and 54 can selectively provide the output of the first stage 12 to the corresponding sections 16, 18, and 52 of the second stage.

Bias control circuit 20' is a modified version of bias control circuit 20 of FIG. 1 , which can provide control signals to more than two cascode transistors. Bias control circuit 20' can activate a selected one of the cascode transistors in cascode circuit 14'. According to some embodiments, bias control circuit 20' can activate only one cascode transistor in cascode circuit 14' at a time. This can help stabilize cascode circuit 14' and/or power amplifier system 50. In another embodiment, bias control circuit 20' can activate more than two cascode transistors at a time.

Each of the sections 16, 18, and 52 of the second power amplifier stage can be configured for one or more specific operating modes. For example, each of the sections 16, 18, and 52 of the second power amplifier stage can be electrically connected to a different output matching network and/or have a different terminating impedance circuit electrically coupled to its input. It should be understood that the principles and advantages discussed herein can be applied to any suitable number of power amplifier sections of a power amplifier stage. For example, the principles and advantages discussed herein can be applied to a cascode circuit used as a switch between four or more sections of a first power amplifier stage and a second power amplifier stage.

In some embodiments, a cascode circuit may be disposed between stages of a plurality of different multi-stage power amplifiers. According to some embodiments, the multi-stage power amplifier may include at least three stages, and the cascode circuit may function as a switch between a first stage and a second stage, and another cascode circuit may function as a switch between the second stage and a third stage. Furthermore, as used herein, a first stage of a power amplifier may refer to one stage of a multi-stage power amplifier, and a second stage of a power amplifier may refer to a subsequent stage of the multi-stage power amplifier that receives input from the first stage.

Although some features have been discussed with reference to various power modes, such as low power mode and high power mode, for illustrative purposes, the principles and advantages discussed herein can be applied to any different modes. Such modes may include, for example, modes associated with different frequency bands, modes associated with different frequency bands and different power modes, different signaling modes (e.g., a nominal mode and an intermittent signaling mode, such as a public safety mode, like an NS_07 mode), etc., or any combination thereof.

Although some features have been discussed with reference to power amplifiers for illustrative purposes, the principles and advantages discussed herein can be applied to any application that can benefit from using bipolar transistors and/or cascode transistors to perform switching functions. For example, FIG4 shows an electronic system 60 that includes an amplifier bipolar transistor 62, a first load 64, a second load 66, and a cascode circuit including a first cascode bipolar transistor 22 and a second cascode bipolar transistor 24. The first cascode bipolar transistor 22 can selectively provide the output from the amplifier bipolar transistor 62 to the first load 64, and the second cascode bipolar transistor 24 can selectively provide the output from the amplifier bipolar transistor 62 to the second load 66. In some applications, the amplifier transistor 62 can be arranged to amplify RF signals. In other applications, the amplifier transistor 62 can be arranged to amplify audio signals. As another example, any of the cascode circuits discussed herein can be implemented between stages of a multi-stage RF amplifier.

In some embodiments, the first power amplifier stage, the cascode circuit, and the second power amplifier stage can be integrated on a single bare die. The single bare die can be included in a packaged power amplifier module. One or more other components can be included on the single bare die. The bare die can be encapsulated in plastic. For example, the single bare die can be a SiGe bare die or a heterojunction bipolar transistor (HBT) GaAs bare die. The packaged power amplifier module can, for example, be mounted to an RF circuit board associated with the wireless communication device 511 of Figure 6.

Figure 5A is a schematic diagram of one example of a packaged power amplifier module 300. The power amplifier 300 may include more components than shown and/or a subset of the components shown. Figure 5B is a schematic diagram of a cross-section of the packaged power amplifier module 300 of Figure 5A taken along line 5B-5B.

The packaged power amplifier module 300 includes an integrated circuit (IC) or bare die 301, a surface mount component 303, wire bonds 308, a package substrate 320, and a package 340 (not shown in FIG. 5A ). The package substrate 320 includes pads 306 formed from conductors arranged therein. In addition, the bare die 301 includes pads 304, and the wire bonds 308 can electrically connect the pads 304 of the bare die 301 to the pads 306 of the package substrate 320. Although wire bonds 308 are shown, the bare die 301 can be electrically connected to other circuit elements of the packaged power amplifier module 300 through different electrical connections. For example, a flip-chip bare die can include bumps as electrical connections to the flip-chip bare die. As shown in FIG. 5A and FIG. 5B , the bare die 301 includes a first amplifier stage 12, a cascode circuit 14, and a second power amplifier stage 16 formed therein.

The package substrate 320 can be configured to house multiple components, such as a bare die 301 and surface mount elements 303, which can include, for example, surface mount capacitors and/or inductors. Alternatively or additionally, the packaged power amplifier module 300 can include an integrated passive device bare die (not shown) and/or a control bare die (not shown).

As shown in FIG5B , the packaged power amplifier module 300 is shown to include a plurality of contact pads 332 arranged on a side of the packaged power amplifier module 300 opposite the side on which the die 301 is mounted. Configuring the packaged power amplifier module 300 in this manner can facilitate connecting the packaged power amplifier module 300 to a circuit board, such as a telephone board for a wireless communication device. The example contact pads 332 can be configured to provide an RF signal, a bias signal, one or more power low voltages, and/or one or more power high voltages to the die 301 and/or the surface mount component 303. As shown in FIG5B , the electrical connection between the contact pads 332 and the die 301 can be facilitated by connections 333 passing through the package substrate 320. The connections 333 can represent electrical paths formed through the package substrate 320, such as connections associated with vias and conductors of a multi-layer laminated package substrate.

The packaged power amplifier module 300 may also include one or more packaging structures to, for example, provide protection and/or facilitate operation of the packaged power amplifier module 300. Such packaging structures may include an overmold or encapsulation 340 formed over the package substrate 320 and the components and one or more die disposed thereon.

It should be understood that while the packaged power amplifier module 300 is described in the context of wirebond-based electrical connections, one or more features of the present disclosure may also be implemented in other packaging configurations including, for example, flip-chip die configurations.

FIG6 is a schematic block diagram of an example wireless communication device 511 that may include one or more power amplifiers. The wireless communication device 511 may include a multi-stage power amplifier with a cascode circuit according to the principles and advantages discussed herein, for example, with reference to FIG1 through FIG4. The wireless communication device 511 may include one or more power amplifier modules, such as one or more power amplifier modules having any combination of the features discussed with reference to FIG5A and FIG5B. In some embodiments, the wireless communication device 511 may be a mobile phone, such as a smartphone.

The example wireless communication device 511 depicted in FIG6 may represent a multi-band and/or multi-mode device, such as a multi-band/multi-mode mobile phone. In some embodiments, the wireless communication device 511 may include a switching module 512, a transceiver 513, an antenna 514, a first power amplifier stage 12, a cascode circuit 14, a second power amplifier stage 16/18, one or more other power amplifiers 517, a control component 518, a computer-readable medium 519, a processor 520, and a battery 521.

The transceiver 513 may generate RF signals for transmission via the antenna 514. Additionally, the transceiver 513 may receive incoming RF signals from the antenna 514.

It should be understood that various functions associated with transmitting and receiving RF signals can be implemented by one or more components collectively represented in FIG6 as transceiver 513. For example, a single component can be configured to provide both transmitting and receiving functions. In another example, the transmitting and receiving functions can be provided by separate components.

Similarly, it should be understood that various antenna functions associated with transmitting and receiving RF signals can be implemented by one or more components, collectively represented as antenna 514 in FIG. 6 . For example, a single antenna can be configured to provide both transmit and receive functions. In another example, transmit and receive functions can be provided by separate antennas. In yet another example, different frequency bands associated with wireless communication device 511 can be provided using different antennas. In some cases, wireless communication device 511 can include a main antenna and a diversity antenna.

In FIG6 , one or more output signals from the transceiver 513 are depicted as being provided to the antenna 514 via one or more transmit paths 515. In the example shown, different transmit paths 515 can represent output paths associated with different frequency bands and/or different power outputs. For example, a multi-stage power amplifier including a first stage 12 and a second stage 16/18 and another power amplifier 517 can represent amplification associated with different power output configurations (e.g., low power output and high power output), and/or amplification associated with different frequency bands. In addition, each of these power amplifiers can include an output stage that is configured to amplify RF signals for a particular power operating mode (e.g., low power output and high power output) and/or amplify signals associated with different frequency bands (e.g., low power high frequency output; low power low frequency output; high power high frequency output; and high power low frequency output).

Although FIG. 6 illustrates a configuration using two transmission paths 515 , the wireless communication device 511 may include more or fewer transmission paths 515 .

The power amplifiers shown can be used to amplify a variety of RF signals. For example, one or more of the power amplifiers can receive an enable signal that can be used to pulse the output of the power amplifier to assist in transmitting a wireless local area network (WLAN) signal, such as a WLAN 802.11g signal or any other suitable pulsed signal. In some embodiments, one or more of the power amplifiers are configured to amplify Wi-Fi signals. It is not necessary for each of the power amplifiers to amplify the same type of signal. For example, one power amplifier can amplify a WLAN signal, while another power amplifier can amplify a Global System for Mobile Communications (GSM) signal, a Code Division Multiple Access (CDMA) signal, a W-CDMA signal, a Long Term Evolution (LTE) signal, an EDGE signal, or a Bluetooth signal, for example.

One or more features of the present disclosure may be implemented in the example communication standards, modes, and/or frequency bands described above, as well as other communication standards.

In FIG6 , one or more detected signals from antenna 514 are depicted as being provided to transceiver 513 via one or more receive paths 516. In the example shown, different receive paths 516 may represent receive paths associated with different frequency bands. While FIG6 illustrates a configuration using four receive paths 516, wireless communication device 511 may be adapted to include more or fewer receive paths 516.

To facilitate switching between the receive path and the transmit path, the switch module 512 can be configured to electrically connect the antenna 514 to the selected transmit path or receive path. Thus, the switch module 512 can provide multiple switching functions associated with the operation of the wireless communication device 511. In some embodiments, the switch module 512 can include multiple switches configured to provide functions associated with, for example, switching between different frequency bands, switching between different power modes, switching between a transmit mode and a receive mode, or any combination thereof. The switch module 512 can also be configured to provide additional functions, including filtering and/or duplexing of signals.

FIG6 illustrates that in certain embodiments, a control component 518 may be provided to control various control functions associated with the switching module 512, the power amplifier, and/or one or more other operating components. In certain implementations, the control component 518 may be implemented on the same bare die as the power amplifier. In certain implementations, the control component 518 may be implemented on a different bare die from the power amplifier. The control component 518 may include control and bias circuits for biasing the cascode circuit 14.

In certain embodiments, processor 520 can be configured to facilitate the realization of the various processes described herein. For the purpose of description, the embodiments of the present disclosure can also be described with reference to the flow chart and/or block diagram of method, device (system) and computer program product. It should be understood that each box in the flow chart and/or block diagram and the combination of the boxes in the flow chart and/or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create parts for realizing the action specified in the flow chart and/or block diagram.

In some embodiments, these computer program instructions may also be stored in a computer-readable memory 519, which may instruct a computing device or other programmable data processing apparatus to operate in a specific manner so that the instructions stored in the computer-readable memory produce an article of manufacture, including instruction components that implement the actions specified in one or more blocks of the flowchart and/or block diagram. The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus so that a series of operations are performed on the computer or other programmable apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable apparatus provide instructions for implementing the actions specified in one or more blocks of the flowchart and/or block diagram.

Battery 521 may be any suitable battery for use in wireless communication device 511 , including, for example, a lithium-ion battery.

Some of the embodiments described above provide examples in conjunction with power amplifiers and/or mobile devices. However, the principles and advantages of the embodiments can be applied to any other system or device that can benefit from any circuit described herein, such as any uplink cellular device. The teachings herein are applicable to various power amplifier systems, including systems with multiple power amplifiers, including, for example, multi-band and/or multi-mode power amplifier systems. The principles and advantages of the embodiments can be applied to any other system or device that can benefit from cascode circuitry between power amplifier stages.

Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, cellular communication infrastructure such as base stations, and the like. Examples of electronic devices may include, but are not limited to, mobile phones such as smartphones, wearable computing devices such as smart watches or earbuds, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, cars, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, cameras, cameras such as digital cameras, portable memory chips, washing machines, dryers, washer/dryers, peripheral devices, clocks, and the like. In addition, electronic devices may include unfinished products.

Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise," "include," and the like should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to." As generally used herein, the word "coupled" refers to two or more elements that can be connected directly or through one or more intermediate elements. Furthermore, as generally used herein, the word "connected" refers to two or more elements that can be connected directly or through one or more intermediate elements. Furthermore, when used in this application, the words "herein," "above," "below," and words of similar meaning should refer to this application as a whole, not to any particular part of this application. When the context permits, words in the above specific embodiments that use the singular or plural may also include the plural or singular, respectively. When referring to a list of two or more items, the word "or" covers all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

Furthermore, unless specifically stated otherwise, or understood otherwise within the context of its use, conditional language used herein, such as, among others, "may," "could," "might," "would," "for example," "for example," and "such as," is generally intended to convey that some embodiments include and other embodiments do not include certain features, elements, and/or states. Thus, such conditional language is generally not intended to imply that features, elements, and/or states are in any way required for one or more embodiments, or that one or more embodiments must include logic for determining, with or without author input or prompting, whether such features, elements, and/or states are included in or to be performed in any particular embodiment.

Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein can be embodied in various other forms; in addition, various omissions, substitutions, and changes in the form of the methods and systems described herein can be made without departing from the spirit of the present disclosure. For example, although the boxes are presented in a given arrangement, alternative embodiments can perform similar functions with different components and/or circuit topologies, and some boxes can be deleted, moved, added, subdivided, combined, and/or modified. Each of these boxes can be implemented in a variety of different ways. Any appropriate combination of the elements and actions of the various embodiments described above can be combined to provide additional embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications that will fall within the scope and spirit of the present disclosure.

Claims (42)

1. A power amplifier system, comprising: The first power amplifier stage is configured to amplify radio frequency signals; A second power amplifier stage includes a first power amplifier transistor and a second power amplifier transistor, wherein the first power amplifier transistor is implemented by a first transistor array having a physical area larger than that of a second transistor array implementing the second power amplifier transistor; and A common-emitter common-base circuit includes a first common-emitter common-base transistor and a second common-emitter common-base transistor, the first common-emitter common-base transistor being configured to selectively provide the output from a first power amplifier stage to a first power amplifier transistor, and the second common-emitter common-base transistor being configured to selectively provide the output from the first power amplifier stage to a second power amplifier transistor. 2. The power amplifier system of claim 1, wherein the first power amplifier stage, the second power amplifier stage, and the common-base circuit are implemented on a single bare die. 3. The power amplifier system of claim 2, wherein the individual bare dies are formed using either a silicon-germanium bipolar transistor process or a gallium arsenide heterojunction bipolar transistor process. 4. The power amplifier system of claim 1, wherein the first common-base transistor is a first common-base bipolar transistor, and the second common-base transistor is a second common-base bipolar transistor. 5. The power amplifier system of claim 4, wherein the first power amplifier stage includes a first power amplifier stage bipolar transistor having a collector electrically connected to the emitter of the first common-base bipolar transistor and the emitter of the second common-base bipolar transistor. 6. The power amplifier system of claim 5, further comprising a termination circuit electrically coupled to the base of the first common-emitter common-base bipolar transistor and configured to provide a termination impedance, the termination circuit including a resistor in series with a capacitor. 7. The power amplifier system of claim 1, wherein the first power amplifier transistor is configured to receive the output of the first power amplifier stage in a high-power mode, and the second power amplifier transistor is configured to receive the output of the first power amplifier stage in a low-power mode. 8. The power amplifier system of claim 1, wherein a first power amplifier transistor is configured to receive the output when the output of the first power amplifier stage is in a first frequency band, and a second power amplifier transistor is configured to receive the output when the output of the first power amplifier stage is in a second frequency band. 9. The power amplifier system of claim 1, wherein the second power amplifier stage includes a third power amplifier transistor, and the common-base circuit includes a third common-base transistor configured to selectively provide the output from the first power amplifier stage to the third power amplifier transistor. 10. A power amplifier system, comprising: The first power amplifier stage includes a first power amplifier stage bipolar transistor configured to amplify radio frequency signals; The second power amplifier stage includes a first power amplifier transistor and a second power amplifier transistor; and A common-emitter, common-base circuit includes a first common-emitter, common-base bipolar transistor (CPT) and a second CPT. The first CPT is configured to selectively provide an output from a first power amplifier stage to a first power amplifier transistor. The second CPT is configured to selectively provide an output from the first power amplifier stage to a second power amplifier transistor. The first power amplifier stage bipolar transistor has a collector electrically connected to the emitter of the first CPT and the emitter of the second CPT. The feedback circuit is configured to provide feedback from the collector of at least one of the first common-base bipolar transistor or the second common-base bipolar transistor to the input of the first power amplifier stage. 11. The power amplifier system of claim 10, wherein the first power amplifier transistor is implemented by a first transistor array having a larger physical area than a second transistor array that implements the second power amplifier transistor. 12. A semiconductor bare die, comprising: First power amplifier transistor; A second power amplifier transistor, wherein the first power amplifier transistor is implemented by a first transistor array having a physical area larger than that of a second transistor array implementing the second power amplifier transistor; and A common-emission common-base circuit includes a first common-emission common-base bipolar transistor and a second common-emission common-base bipolar transistor, wherein the first common-emission common-base bipolar transistor is configured to selectively provide an RF signal to a first power amplifier transistor, and the second common-emission common-base bipolar transistor is configured to selectively provide an RF signal to a second power amplifier transistor. 13. The semiconductor die of claim 12, wherein the emitter of the first common-emitter common-base bipolar transistor is electrically connected to the emitter of the second common-emitter common-base bipolar transistor. 14. The semiconductor bare die of claim 13, further comprising a first-stage power amplifier bipolar transistor having a collector electrically connected to the emitter of the first common-base bipolar transistor and the emitter of the second common-base bipolar transistor. 15. The semiconductor die of claim 14, further comprising a feedback circuit configured to provide feedback from the collector of the first common-emission common-base bipolar transistor to the base of the first-stage power amplifier bipolar transistor. 16. The semiconductor bare die of claim 12, wherein the common-base circuit comprises a silicon-germanium bipolar transistor or a gallium arsenide heterojunction bipolar transistor. 17. The semiconductor die of claim 12, further comprising a terminating circuit electrically connected to the base of the first common-emission common-base bipolar transistor. 18. The semiconductor die of claim 17, wherein the termination circuit includes a resistor connected in series with a capacitor. 19. A packaged power amplifier module, comprising: A power amplifier bare die includes a first power amplifier stage, a second power amplifier stage including a first power amplifier transistor implemented by a first transistor array having a physical area larger than that of a second transistor array implementing a second power amplifier transistor, a first common-emission common-base bipolar transistor configured to selectively provide radio frequency signals from the first power amplifier stage to the first power amplifier transistor in a first mode, and a second common-emission common-base bipolar transistor configured to selectively provide radio frequency signals from the first power amplifier stage to the second power amplifier transistor in a second mode. The power amplifier die is disposed on the packaging substrate; and Packaging on the packaging substrate and the bare power amplifier die. 20. The packaged power amplifier module of claim 19, wherein the first power amplifier transistor is a gallium arsenide heterojunction bipolar transistor. 21. The packaged power amplifier module of claim 19, further comprising a surface mount assembly on the package substrate, the surface mount assembly communicating with the power amplifier die. 22. The packaged power amplifier module of claim 19 further includes wire bonding that provides electrical connections from the power amplifier bare die to a pad on the package substrate. 23. A method for amplifying a radio frequency signal, the method comprising: In the first mode, a first common-emitter common-base bipolar transistor with an emitter electrically connected to the collector of a bipolar power amplifier transistor is used to provide an RF signal from the collector of the bipolar power amplifier transistor to the first power amplifier transistor. In the first mode, the radio frequency signal is amplified using a first power amplifier transistor; In the second mode, a second common-emitter common-base bipolar transistor having an emitter electrically connected to the collector of the bipolar power amplifier transistor is used to provide the radio frequency signal from the collector of the bipolar power amplifier transistor to the second power amplifier transistor; and In the second mode, the radio frequency signal is amplified using a second power amplifier transistor, which is coupled to different output matching networks as the first power amplifier transistor. 24. The method of claim 23, further comprising providing feedback from the collector of the first common-base bipolar transistor to the base of the bipolar power amplifier transistor. 25. The method of claim 23, wherein the first power amplifier transistor is implemented by a first transistor array having a physical area larger than that of a second transistor array implementing the second power amplifier transistor. 26. The method of claim 23, wherein the first mode is associated with a power mode different from the second mode. 27. The method of claim 23, wherein the base of the first common-electrode common-base bipolar transistor is electrically connected to a terminating circuit comprising a resistor connected in series with a capacitor. 28. The method of claim 23, further comprising turning off the first common-base bipolar transistor in the second mode to disconnect the first common-base bipolar transistor. 29. The method of claim 23, wherein the radio frequency signal is a wireless local area network signal. 30. A wireless communication device, comprising: The first power amplifier stage includes bipolar power amplifier transistors configured to amplify radio frequency signals; The second power amplifier stage includes a first power amplifier transistor and a second power amplifier transistor; A common-emitter common-base circuit includes a first common-emitter common-base bipolar transistor and a second common-emitter common-base bipolar transistor, wherein the first common-emitter common-base bipolar transistor is configured to selectively provide the output from a first power amplifier stage to a first power amplifier transistor, and the second common-emitter common-base bipolar transistor is configured to selectively provide the output from the first power amplifier stage to a second power amplifier transistor. Antenna; and The switching module is configured to selectively connect the output of the second power amplifier stage to the antenna. 31. The wireless communication device of claim 30, wherein the bipolar power amplifier transistor has a collector electrically connected to the emitter of the first common-base bipolar transistor and the emitter of the second common-base bipolar transistor. 32. The wireless communication device of claim 30, further comprising a feedback circuit configured to provide feedback from the collector of the first common-emittance common-base bipolar transistor to the base of the bipolar power amplifier transistor. 33. The wireless communication device of claim 30 further includes a terminating circuit electrically coupled to the base of the first common-emittance common-base bipolar transistor. 34. The wireless communication device of claim 30, wherein the first common-emission common-base bipolar transistor is configured to provide the output from the first power amplifier stage to the first power amplifier transistor in a high-power mode, and the second common-emission common-base bipolar transistor is configured to provide the output from the first power amplifier stage to the second power amplifier transistor in a low-power mode. 35. The wireless communication device of claim 30, wherein the first power amplifier transistor is implemented by a first transistor array having a physical area larger than that of a second transistor array implementing the second power amplifier transistor. 36. The wireless communication device of claim 30, wherein the first power amplifier transistor and the second power amplifier transistor are electrically connected to different output matching networks. 37. The wireless communication device of claim 30, wherein the second power amplifier stage is configured to provide a wireless local area network signal to the antenna. 38. An amplifier circuit, comprising: Amplifier bipolar transistor; First load and second load; A common-emitter common-base circuit includes a first common-emitter common-base bipolar transistor and a second common-emitter common-base bipolar transistor, wherein the first common-emitter common-base bipolar transistor is configured to selectively provide the output from the amplifier bipolar transistor to a first load, and the second common-emitter common-base bipolar transistor is configured to selectively provide the output from the amplifier bipolar transistor to a second load; and The feedback circuit is configured to provide feedback from the collector of the first common-emitter common-base bipolar transistor to the base of the amplifier bipolar transistor. 39. The amplifier circuit of claim 38, wherein the feedback circuit comprises a resistor and a capacitor arranged in series between the collector of the first common-base bipolar transistor and the base of the amplifier transistor. 40. The amplifier circuit of claim 39, wherein the feedback circuit includes a second resistor arranged in series with the capacitor between the collector of the second common-base bipolar transistor and the base of the amplifier transistor. 41. The amplifier circuit of claim 38 further includes a terminating circuit electrically coupled to the base of the first common-emitter common-base bipolar transistor, the terminating circuit including a resistor connected in series with a capacitor. 42. The amplifier circuit of claim 38, wherein the base of the amplifier bipolar transistor is configured to receive a radio frequency signal, and the collector of the amplifier bipolar transistor is configured to provide an amplified radio frequency signal, and the collector of the amplifier bipolar transistor is electrically connected to the emitter of the first common-base bipolar transistor and the emitter of the second common-base bipolar transistor.