HK1220818B - Digital interpolator and method of interpolating - Google Patents

Description

Digital interpolator and interpolation method

Technical Field

The present invention relates to a digital interpolator and a corresponding method of interpolating a sequence of digital signals at a first clock frequency to a sequence of signals at a second clock frequency greater than the first clock frequency.

Background

It is advantageous for efficient data storage to reduce the amount of data in the memory and to regenerate a series or sequence of signals from only two consecutive stored signals or stored values. In this way, storage space may be saved and/or data to be stored may be compressed. For certain applications, such as wearable or mobile electronic devices with such similar mobile phones or wristwatches, there may be a need for storing data representing sounds or music at a relatively low sampling rate. Hardware-implemented interpolation of stored signals is typically required when reading data from memory and for reproducing sound or music from the stored data.

There are solutions using cascaded digital interpolators of finite response Filters (FIR), e.g. to achieve interpolation from 32kHz to 256 kHz. The cascading of FIR filters requires a relatively large number of gates or memory blocks, which in turn may cover a substantial portion of the corresponding Integrated Circuit (IC) area.

Interpolation filters are also known in view of patent application EP 0658979 a2 and patent US 5,835,390.

Patent application US 2010/0135368 a1 describes a device capable of performing interpolation of an input sample stream. To this end, the interpolation mechanism comprises an upsampler structure having a linear interpolator. The upsampler circuit includes a differentiator, a linear interpolator, and an integrator for providing an output interpolated signal having a frequency greater than the frequency of the input signal.

Disclosure of Invention

It is therefore an object of the present invention to provide an improved digital interpolator in which the hardware of the interpolator requires less integrated circuit space. In addition, the digital interpolator should present a rather simple structure in terms of the number and arrangement of its gates or memory blocks in order to save space on the integrated circuit. At the same time, the digital interpolator should provide good or excellent interpolation results and should operate stably even on a long-term scale.

In a first aspect, the invention relates to a digital interpolator comprising an input for receiving an input signal at a first clock frequency. The digital interpolator further includes an output that provides the interpolated signal at a second clock frequency, wherein the second clock frequency is greater than the first clock frequency. The interpolator comprises a differentiator connected to the input. The interpolator further comprises an interpolator stage connected to the differentiator output and further comprises an integrator connected to the output and to the interpolator output.

Thus, the digital interpolator comprises three stages or components, namely a differentiator stage, identified as differentiator, an interpolator stage and an integrator or integrator stage. The three components or stages are arranged in a sequence or cascade. The input to the digital interpolator is provided by the input of the differentiator. The output of the differentiator is connected to the input of the interpolator stage and the output of the interpolator stage is connected to the input of the integrator, while the output of the integrator forms the output of the digital interpolator. As will be explained below, the sequence or cascade of differentiators, interpolator stages and integrators provides a space-saving approach to a digital interpolator that is smaller in space compared to a cascade of several FIRs. The total number of memory blocks or memory cells on the IC may likewise be reduced. At the same time, the overall architecture of the digital interpolator can be simplified. In practice, digital interpolators, including differentiators, interpolator stages and integrators, are rather robust and serve to provide an interpolated signal of sufficient or even excellent quality.

According to an embodiment, the digital interpolator comprises a first clock running at a first clock frequency, and further comprises a second clock running at a second clock frequency. As already mentioned, the second clock frequency is greater than the first clock frequency. In a further embodiment the second clock frequency is an integer multiple of the first clock frequency. A sequence or cascade of digital interpolators, i.e. differentiators, interpolator stages and integrators is used to provide a signal for each clock signal of the second clock frequency based on a continuous signal of the first clock frequency. For example, the second clock frequency is eight times greater than the first clock frequency. In this way, the compressed signal stored in the memory based on the first clock frequency and subjected to the read operation can be transferred into the interpolation signal based on the second clock frequency.

According to another embodiment, the differentiator operates at a first clock frequency and the interpolator stage and the integrator operate at a second clock frequency. The signal to be interpolated is first differentiated by means of a differentiator. Thus, a first derivative of the sequence of data signals is derived and acquired. Interpolation performed by the interpolator stage is then performed and carried out based on the sequence of differential signals. But the end integrator transforms the interpolated signal to a data signal at a second clock frequency that is greater than the first clock frequency at which the output reading is made.

In this way the overall architecture of the digital interpolator can be simplified without any substantial adverse effect on the signal quality, compared to conventional solutions that may be based on a cascade of FIR stages.

According to a further embodiment, the differentiator comprises a memory driven or operated by the first clock frequency, and further comprises a subtractor calculating a difference between an input signal at a first clock time of the first clock and an input signal at a subsequent clock time of the first clock. Typically, the memory effectively acts as a shift register. The memory stores the input signal at a first clock time of the first clock and forwards the stored signal to the differentiator at a subsequent clock time of the first clock.

While forwarding the first input signal to the differentiator at or during the subsequent clock time, storing, by the memory, a signal provided by and coinciding with the subsequent clock time of the first clock. Further, i.e. during the next successive clock time, the signal stored at or during the second clock time is forwarded to a differentiator or the like. Thus, while the subtractor of the differentiator is connected to the memory output of the differentiator and to the overall input of the digital interpolator, i.e. to the input of the differentiator, the memory provides the input signal and forwards the input signal to the differentiator corresponding to the previous clock time. The subtractor may then be operated to calculate the difference between the input signal at the first clock time and the input signal at the second or successive clock times. Thus, the output of the subtractor is always indicative of the variations and differences between successive input signals provided at the first clock frequency.

According to another embodiment, the interpolator stage comprises a memory, an adder, a divider, and a subtractor. Wherein the output of the adder is connected to the input of the divider. The output of the divider is connected to the memory input. A memory output is connected to an input of the adder and another input of the adder is connected to an output of the differentiator. In other words, the interpolator stage comprises a loop consisting of an adder, a divider and a memory.

Here, one input of the subtractor is connected to an input of the interpolator stage. The subtractor is thus in parallel with the adder, while the second input of the subtractor is connected to the output of the divider. This particular arrangement of memory, adder, divider and subtractor allows the calculation of a series of signals between the output of the differentiator at a first clock time and the output of the differentiator at a subsequent or second clock time. The interpolator stage, which is realized by an arrangement of a memory, an adder, a divider and a subtractor, provides a specific interpolation function which is quite advantageous and efficient for calculating a series of signal values based on the second clock frequency, wherein the series of signal values successively approaches a successive signal value provided based on the first clock frequency.

Through the loop of memory, adder and divider, the signal previously stored by the memory may be added to the signal initially provided, for example, at the first clock time of the first clock frequency. The sum of the two signals is divided by a divider and the divided signal is stored in a memory which can be used as a kind of shift register compared to the memory of the differentiator. The interpolator stage operates on the second clock signal, in contrast to the differentiator. The time interval between successive operations of the interpolator stage is therefore shorter than the time interval between two successive signals provided at the first clock frequency.

Assuming that the output of the differentiator at a first clock time of the first clock is 0 and the output at successive clock times of the first clock equals 1, the interpolator stage may be operated so as to calculate a signal sequence between these successive output signals. Assuming that the interpolator stage divider continues to divide by a factor of 2, the loop of adders, dividers and memory can be run to generate a sequence of the following values: 1/2, 3/4, 7/8, 15/16, 31/32, and the like.

According to a further embodiment, the divider of the interpolator stage divides the output of the adder by a constant factor. The output of the divider is connected to the input of the memory of the interpolator stage. The memory of the interpolator stage is driven by the second clock frequency. The input of the memory provided at the first clock time of the second clock is then provided to the input of the adder at a subsequent or successive clock time of the second clock. Thus, one input of the adder of the interpolator stage is connected to the output of the memory of the interpolator stage, while the other input of the adder is connected to the output of the differentiator, in particular to the output of the subtractor of the differentiator.

According to a further embodiment, the divider of the interpolator stage divides the output of the adder by a constant factor before storing the divided output of the adder by the memory of the interpolator stage.

According to another embodiment, the subtractor of the interpolator stage has a first input connected to the differentiator output and further has a second input connected to the output of the divider. In this way, the subtracter of the interpolator stage is used to provide the sequence signal based on the second clock frequency.

Assuming that the input signal of the interpolator stage jumps from 0 to 1 and further assuming that the divider constantly divides the output of the adder by a factor of 2, the output sequence of the subtractor is changed to: 1/2, 1/4, 1/8, 1/16, 1/32, and the like. In this way, a series of signals may be generated, with the difference between successive signals decreasing. In this way, a more efficient interpolation scheme may be provided than linear interpolation.

According to a further embodiment, the output of the subtractor of the interpolator stage is connected to the integrator of the digital interpolator. Thus, a series of signals as described above may be integrated by an integrator. Furthermore, by means of the integrator, the initial derivative provided by the differentiator can be compensated and thus the signal output of the digital interpolator is in the same domain compared to its initial input.

According to another embodiment, the integrator comprises a memory and an adder. One input of the adder is connected to the memory of the integrator, while the other input of the adder is connected to the output of the interpolator stage. The integrator is also driven by the second clock signal. In this way, a sequence of interpolated signals may be generated.

In another embodiment, the memory of the interpolator and the memory of the integrator operate at the second clock frequency. In this way, the interpolator stage and the integrator are effectively clocked by the second clock frequency and the corresponding clock signal.

According to a further embodiment, at least one of the memory of the interpolator and the memory of the integrator is resettable by the first clock, i.e. by the first clock signal. In this manner, the interpolator may be reset at the beginning of the interpolation operation. In this way potential drift of the digital interpolator output can be avoided.

In a further embodiment, at least one of the memory of the interpolator stage and the memory of the integrator is connected with an output of an OR-gate (OR-gate) having an input connected to the first clock. In this way, the memory of at least one of the interpolator stage or the integrator is reset at regular time intervals, which time intervals correspond to the time intervals between successive signals of the first clock. Also in this way, drift of the output signal of the digital interpolator can be avoided and counteracted.

Typically, both the memory of the interpolator stage and the memory of the integrator are each connected to the first clock via a separate or gate.

According to another aspect, the invention also relates to an electronic device comprising at least one digital interposer as described above. The electronics may be implemented as a mobile or wearable device. The electronic device may comprise an electronic watch or a mobile phone.

In a further aspect, the invention also relates to a method of interpolating an input signal provided based on a first clock frequency to a series of signals based on a second clock frequency, wherein the second clock frequency is greater than the first clock frequency. The method comprises the steps of differentiating an input signal provided at a first clock frequency, interpolating a sequence of consecutive differentiated signals, and integrating the interpolated signal sequence.

In particular the method is carried out by a digital interpolator as described above. Thus, the invention described in connection with the digital interpolator is equally applicable to the interpolation method and vice versa. In particular, any of the features, benefits and characteristics described with respect to the digital interpolator are equally applicable to the method of interpolation; and vice versa.

Drawings

Embodiments of the invention will be described hereinafter with reference to the accompanying drawings, in which:

figure 1 schematically shows a circuit diagram of a digital interpolator,

figure 2 shows a further representation of a digital interpolator,

figure 3 shows the output and input signals of a digital interpolator,

FIG. 4 shows various signals of a digital interpolator at its input, its output and the output or input of its components, i.e. differentiators, interpolator stages and/or integrators, and

fig. 5 is a flow chart of a corresponding interpolation method.

Detailed Description

In fig. 1, a digital interpolator 10 is shown in a block diagram. The digital interpolator includes an input 12 that receives and processes an input signal 50 and further includes an output 18 that provides an interpolated output signal 52. The digital interpolator 10 further comprises a first clock input 14 and a second clock input 16. The input signal 50 is provided based on a first clock signal driven by a first clock frequency f1, while the output 18 is driven by a second clock signal, i.e. by a second clock frequency f2, the second clock frequency f2 being greater than the first clock frequency f 1.

The digital interpolator 10 comprises a differentiator 20, an interpolator stage 30 and an integrator 40. The differentiator 20, the interpolator stage 30 and the integrator 40 are connected to each other to form a cascade. The output of the differentiator 20 is connected to the input of the interpolator stage 30, while the output of the interpolator stage is connected to the input of the integrator 40. The output of integrator 40 forms or corresponds to output 18 of digital interpolator 10. The input 12 of the digital interpolator 10 is equal to the input of the differentiator 20 or is connected to the input of the differentiator 20.

The first clock input 14 is connected to a first clock 15 operating at a first clock frequency f 1. The second clock input 16 is connected to a second clock 19 driven by a second clock frequency f2, the second clock frequency f2 being greater than the first clock frequency f 1.

Typically, the second clock frequency f2 is an integer multiple of the first clock frequency f 1.

The differentiator 20 comprises a memory 22 driven by the first clock 15 and further comprises a subtractor 24. Subtractor 24 includes a first input 24a and a second input 24 b. The first input 24a is connected to the input 12 while the second input 24b is connected to the output 22c of the memory 22. A first input 22a of the memory 22 is likewise connected to the input 12. A second input 22b of the memory 22 is connected to the first clock 15 via the clock input 14. In this manner, memory 22 functions and appears like a shift register. The memory 22 is operable to store one signal value and output the stored signal value at an ongoing clock signal. In this way, one input 24a of the subtractor 24 of the differentiator 20 is connected to the input 12, while the other input 24b is connected to the output 22c of the memory 22. In this manner, subtractor 24 has a signal input at time T and an input at time T-1.

The subtractor 24 thus compares and subtracts the successive signals present on the differentiator 20 at the subsequent clock time of the first clock 15.

An output 24c of the subtractor 24 forms an output 25 of the differentiator 20 which is connected to the interpolator stage 30.

The interpolator stage 30 comprises a further memory 32, an adder 34, a divider 36 and a subtractor 38. As shown in fig. 1 and 2, the interpolator stage 30 comprises and forms an interpolator stage output 39 connected to an integrator 40, in particular to an input of the integrator 40. The memory 32 of the interpolator stage 30 comprises a first input 32a connected to an output 36b of the divider 36.

An input 36a of the divider 36 is connected to an output 34c of the adder 34. A second input 34b of the adder 34 is connected to the output 32c of the memory 32. In this manner, the memory 32, adder 34, and divider 36 form a closed loop. The memory 32 further comprises a second input 32b connected to the second clock 19. Thus, the memory 32 of the interpolator stage 30 is driven by the second clock 19 and therefore runs faster than the differentiator 20. A first input 34a of the adder 34 of the interpolator stage 30 is connected to the output 25 of the differentiator 20 and thus to the output 24c of the subtractor 24 of the differentiator 20.

Assuming that the input signal 50 transitions from 0 to 1 and runs with a first clock and drives two consecutive signals, the loops 32, 34, 36 of the interpolator 30 are used to generate a sequence of signals such as 1/2, 3/4, 7/8, 15/16, etc.

The interpolator stage 30 further comprises a subtractor 38 having a first input 38a and a second input 38b and an output 38c, wherein the output 38c forms an output 39 of the interpolator stage 30. An input 38a of subtractor 38 is directly connected to output 25 of differentiator 20. The other input 38b of the subtractor 38 is connected to the output 36b of the divider 36. In this way, the signal sequences as described and referred to above are transmitted into sequences such as 1/2, 1/4, 1/8, 1/16, 1/32, and the like.

The integrator 40 includes a further adder 44 and a memory 42. A first input 42a of the memory is connected to an output 44c of the adder 44, while the other input 42b of the memory 42 is likewise connected to the second clock 19. An input 44a of the adder 44 is connected to the output 39 of the interpolator stage 30. The other input 44b of the adder 44 is connected to the output 42c of the memory 42. As is apparent from fig. 1, the adder 44 and the memory 42 of the integrator 40 are arranged in a closed loop so that the continuous signal taken at the input 44a of the adder 44 is accumulated. So for example when the input signal 50 transitions from 0 to 1 between successive signals t and t +1 of the first clock 15, the integrator 40 quickly delivers an intermediate value that quickly approaches the target value of the input signal present at the clock time t + 1.

The digital interpolator 10 according to fig. 1 is shown in more detail in fig. 2. Wherein like or similar reference numerals refer to like or similar parts. In addition, two or gates 35, 45 are shown. Or gate 35 includes an output 35c connected to a reset input of memory 32 of interpolator stage 30. One input 35a of the or-gate 35 is connected to a reset switch, not shown in particular, while the other input 35b is connected to the first clock 15 or the first clock input 14.

In a similar manner, a first input 45a of the or-gate 45 of the integrator 40 is also connected to the reset switch, while a second input 45b of the or-gate 45 is connected to the first clock 15 or the first clock input 14. And wherein the output 45c of the or gate is connected to the reset input of the memory 42 of the integrator 40. In this way the memory 32, 42 is repeatedly reset each time the first clock 15 performs one further step. In this manner, drift and cancellation effects of the output signal when the digital interpolator 10 is activated may be compensated for or eliminated.

In addition and in comparison to fig. 1, fig. 2 further shows a further memory 26 of the differentiator 20. An output 26c of the additional memory 26 is connected to an input 22a of the memory 22. The input 26a of the additional memory 26 is connected to the input 12 of the digital interpolator 10. The other input 26b is therefore also connected to the first clock 15 or to the first clock input 14. In this way, the other input 26 serves as a memory 22 and thus as a buffer for the differentiator 20.

Further in fig. 2, there is another or second adder 46 in the integrator 40 after the first adder 44. A first input of the second adder 46 is connected to the output of the first adder 44 and a second input of the second adder 46 is connected to a second input of the subtractor 24 of the differentiator 20. The output of the second adder 46 provides the interpolated output signal 28, which is the output of the integrator 40 of the digital interpolator 10.

It is noted that the second adder 46 uses the starting data value from the differentiator 20 to add the result of the interpolation. At each reset the interpolation result is zero and the second adder gives at its output 28 only the start data.

In fig. 3, an input signal 50 provided based on a first clock frequency f1 is shown together with an output signal 52 of the digital interpolator 10 provided based on a second clock frequency f 2. As shown in fig. 3, the input signal 50 is rather coarse, while the output signal 52 represents a rather smooth interpolation of successive signal values of the input signal 50.

The amplitude of the input signal 50 and the output signal 52 with respect to time is shown in fig. 4. In addition, fig. 4 shows the output of the differentiator 20 and thus the differentiated input signal 54. Fig. 4 further indicates the output of the interpolator stage 30 and exemplarily shows the interpolator stage output signal 56. A comparison of the input signal 50 and the output signal 52 shows a smoothing of the input signal 50.

It will finally be noted that the divider 36 of the interpolator stage 30 is presently described as a divider operating with a divisor equal to 2. However, there are many other conceivable implementations that employ different dividers 36 that can easily implement different interpolation schemes.

Fig. 5 further shows a flow chart of an interpolation method introduced and run by the digital interpolator 10. In a first step 100 the input signal is differentiated. In a successive second step 102 the interpolated differential signal or derived signal 54 is interpolated to form the interpolator stage output signal 56. In a further step 104, the interpolated and differentiated signal 56 is integrated by the integrator 40 to form the output signal 52 at a second clock frequency f2, the second clock frequency f2 being greater than the clock frequency f1 at which the input signal 50 is provided.

Claims (13)

1. A digital interpolator comprising an input (12) receiving an input signal at a first clock frequency and comprising an output (18) providing an interpolated signal at a second clock frequency, the second clock frequency being greater than the first clock frequency, the interpolator comprising:

a differentiator (20) connected to the input (12),

-an interpolator stage (30) connected to the differentiator output (25), and

an integrator (40) connected to the output (18) and to an output (39) of the interpolator stage (30),

the digital interpolator is characterized in that the interpolator stage (30) comprises a memory (32), an adder (34), a divider (36) and a subtractor (38), wherein an output (34c) of the adder (34) is connected to an input (36a) of the divider, wherein an output (36b) of the divider is connected to the memory input (32a), and wherein a memory output (32c) is connected to an input (34b) of the adder (34), wherein a first input (38a) of the subtractor (38) is connected to the differentiator output (25) and a second input (38b) of the subtractor (38) is connected to the output (36b) of the divider, and wherein another input (34a) of the adder (34) is connected to the differentiator output (25).

2. The digital interpolator of claim 1, further comprising a first clock (15) running at the first clock frequency and comprising a second clock (19) running at the second clock frequency.

3. The digital interpolator of claim 1, wherein the second clock frequency is an integer multiple of the first clock frequency.

4. The digital interpolator of claim 1, wherein the differentiator operates at the first clock frequency and wherein the interpolator stage (30) and the integrator operate at the second clock frequency.

5. The digital interpolator according to claim 1, wherein the differentiator (20) comprises a memory (22) and a subtractor (24), the memory (22) being driven by the first clock frequency and the subtractor (24) being adapted to calculate a difference between an input signal at a first clock time of the first clock (15) and an input signal at a subsequent clock time of the first clock (15).

6. The digital interpolator of claim 1, wherein the divider (36) divides an output (34c) of the adder (34) by a constant factor.

7. The digital interpolator according to claim 1, wherein an output (38c) of the subtractor (38) of the interpolator stage (30) is connected to the integrator (40).

8. The digital interpolator according to claim 1, wherein the integrator (40) comprises a memory (42) and an adder (44), wherein one input (44b) of the adder (44) is connected to the memory (42) of the integrator and wherein another input (44a) of the adder (44) is connected to the output (39) of the interpolator stage (30).

9. The digital interpolator of claim 1, wherein the memory (32) of the interpolator stage (30) and the memory (42) of the integrator run at the second clock frequency.

10. The digital interpolator of claim 9, wherein at least one of the memory (32) of the interpolator stage (30) and the memory (42) of the integrator is resettable by the first clock (15).

11. The digital interpolator of claim 10, wherein at least one of the memory (32) of the interpolator stage and the memory (42) of the integrator is connected to an output (35c, 45c) of an or gate (35, 45) having an input connected to the first clock (15).

12. An electronic device comprising at least one digital interpolator according to claim 1.

13. An interpolation method for interpolating a digital input signal (50) at a first clock frequency to an output signal (52) at a second clock frequency, the method comprising the steps of:

-differentiating a digital sequence of the input signal (50),

-interpolating the differentiated sequence in an interpolator stage (30), the interpolator stage (30) comprising a memory (32), an adder (34), a divider (36) and a subtractor (38), wherein an output (34c) of the adder (34) is connected to an input (36a) of the divider, wherein an output (36b) of the divider is connected to the memory input (32a) and wherein a memory output (32c) is connected to an input (34b) of the adder (34), wherein a first input (38a) of the subtractor (38) is connected to a differentiator output (25) and a second input (38b) of the subtractor (38) is connected to an output (36b) of the divider, and wherein another input (34a) of the adder (34) is connected to the differentiator output (25), and

-integrating the interpolated signal from the interpolator stage (30).