HK1220269B - Bidirectional communication method and bidirectional communication device using same - Google Patents

Description

Two-way communication method and two-way communication device using the same

Technical Field

The present invention relates to a two-way communication method and a two-way communication device using the same.

Background Art

In conventional bidirectional communication methods, a phase-locked loop (PLL) or clock data recovery (CDR) circuit is formed on both the first and second parties. When the first party transmits a clock signal, the second party recovers the clock signal and then transmits data. Similarly, when a clock signal is transmitted in the opposite direction, the second party recovers the clock signal and then transmits and receives data.

Summary of the Invention

Technical issues

The bidirectional communication method according to conventional technology includes the process of recovering the clock, and therefore performs the process of recovering the clock whenever the sender and the receiver change. However, in order to recover the clock, the locking time of the phase-locked loop (PLL) or clock data recovery (CDR) circuit is consumed, and because the locking time is consumed whenever the sending and receiving changes, the delay increases. In order to reduce the delay, a parallel bus structure, multiple clock buses and multiple control signal buses can be used. However, there may be signal skew between the buses, and the number of pins of the chip increases uneconomically.

The present embodiment is proposed to solve these problems of the conventional technology and aims to provide a two-way communication method and a two-way communication device using the two-way communication method, in which the sender and the receiver can be changed at high speed without phase lock time to perform data transmission.

Technical Solutions

An aspect of the present invention provides a communication method between a first party and a second party operating using a clock provided by the first party, the communication method comprising the following steps: a phase calibration step; a step of sending a command packet by the first party to the second party; and a data sending and receiving step of sending and receiving data packets between the first party and the second party based on the command packet, wherein the phase calibration step is performed to calibrate the phase of the first party's transmission sampling clock and the phase of the first party's reception sampling clock.

Another aspect of the present invention provides a communication method, in which a first party sends data to a second party using a clock provided by the first party, the communication method comprising the following steps: (a) the first party changes the phase of the clock to generate an initial clock (preliminary clock) having a target phase; (b) the first party samples a mutually predetermined training pattern using the initial clock and sends the sampled pattern to the second party; (c) the second party samples the received pattern using the clock, compares the sampled pattern with the predetermined training pattern, and sends the comparison result; (d) the first party selects the initial clock as a transmission sampling clock based on the comparison result; and (e) the first party samples the data to be sent using the transmission sampling clock whose phase has been adjusted, and sends the sampled data to the second party.

Another aspect of the present invention provides a communication method, in which a second party sends data to a first party using a clock provided by a first party, and the communication method includes the following steps: (a) the second party sends a mutually predetermined training pattern to the first party; (b) the first party changes the phase of the clock to generate an initial clock with a target phase; (c) the first party samples the pattern provided by the second party using the initial clock and compares the sampled pattern with the predetermined training pattern; (d) the first party selects the initial clock as a receiving sampling clock based on the comparison result; and (e) the data sent by the second party is sampled using the receiving sampling clock.

Another aspect of the present invention provides a communication device, which includes: a first party, the first party includes a clock provider and multiple first-party data transceivers, the clock provider is configured to provide a clock, and the multiple first-party data transceivers are configured to provide data or receive data; a second party, the second party includes a clock receiver and multiple second-party data transceivers, the multiple second-party data transceivers are configured to provide the data or receive the data; a data channel unit, the data channel unit includes a data channel, the data channel is configured to connect the multiple first-party data transceivers with the multiple second-party data transceivers respectively; and a clock channel, the clock channel is configured to provide the clock from the first party to the second party, wherein the first party and the second party operate using the clock.

Beneficial effects

According to the communication method or the communication device of the present embodiment, it is not necessary to wait for the lock time of the phase-locked loop (PLL) every time the transmission side and the reception side are changed, and thus the delay period is shortened.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a block diagram outlining a communication device according to the present exemplary embodiment.

FIG2 is a flowchart summarizing the communication method according to this exemplary embodiment.

Figures 3(a) and 3(b) are exemplary timing diagrams illustrating a transmit phase calibration process, wherein Figure 3(a) is a schematic timing diagram illustrating a process in which a first party utilizes a clock to generate a plurality of initial clocks and generates a training pattern sampled using the initial clocks, and Figure 3(b) is a schematic timing diagram illustrating a process in which a second party utilizes a clock to sample a received pattern.

FIG. 4 is an exemplary timing diagram illustrating a receive phase calibration process.

FIG. 5 is a timing chart schematically illustrating a process in which a first party writes stored data to a second party.

FIG. 6 is a timing chart schematically showing a process in which the first side 10 reads data stored in the second side 20 .

FIG. 7 is a diagram illustrating a process in which the second side 20 performs updating when the second side 20 is a dynamic random access memory (DRAM) requiring updating.

DETAILED DESCRIPTION

Since the description of the present invention is only for the purpose of describing the structure or function, the scope of the present invention should not be understood as being limited by the exemplary embodiments disclosed below. In other words, the exemplary embodiments can be modified in various ways and implemented in various forms, and therefore the scope of the present invention should be understood as including equivalents that can embody the technical spirit of the present invention.

The meanings of the terms used herein should be understood as follows.

Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It should also be understood that when the terms "comprise", "include", "include", "comprising", "including", "comprising" are used herein, the terms specify the presence of the stated features, integers, steps, operations, elements, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts or combinations thereof.

Unless the context clearly indicates a particular order, the steps may be performed in an order different from that described. In other words, the steps may be performed in the same order as described, may be performed substantially simultaneously, or may be performed in a reverse order.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. It should also be understood that, unless expressly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, rather than an ideal or overly formal interpretation of their meaning.

In this specification, signal lines are not categorized by type. Thus, a data bus can be a signal line for transmitting a single-ended signal or a pair of lines for transmitting a differential signal. Each line shown in the drawings can be interpreted as a single signal or bus signal composed of one or more analog or digital signals, and its description can be added as needed.

Hereinafter, the present embodiment will be described with reference to the accompanying drawings. FIG2 is a block diagram summarizing a communication device according to the present embodiment. Referring to FIG1 , the communication device according to the present embodiment includes a first party 10 for transmitting or receiving data, and a second party 20 for receiving data transmitted by the first party 10 or transmitting data to the first party 10.

The first side 10 includes a clock provider 310 for providing a clock, and a plurality of data transceivers 100 for providing or receiving data. The second side 20 includes a clock receiver 320 and a plurality of data transceivers 200 for providing or receiving data. In an exemplary embodiment, the first side 10 may further include a command transmitter 410 for providing a command packet, and the second side 20 may further include a command receiver 420 for receiving a command packet.

The communication device according to this embodiment includes a data channel unit including data channels DATA 1, DATA 2, ..., and DATA n, which respectively connect a plurality of first-party data transceivers 100 and a plurality of second-party data transceivers 200; a clock channel CLK, which provides a clock from the first party 10 to the second party 20; and a command channel CMD, which transmits a command packet. The first party 10 and the second party 20 operate using the same clock.

FIG2 is a flowchart summarizing a communication method according to this embodiment. Referring to FIG2 , the communication method according to this embodiment is a communication method between a first party and a second party using a clock provided by the first party, and includes a phase calibration step (S100), a step of the first party sending a command packet to the second party (S200), and a step of transmitting and receiving data packets between the first party and the second party based on the command packet (S300). The phase calibration step is performed to calibrate the phase of the first party's transmit sampling clock and the phase of the first party's receive sampling clock.

1 , the first side 10 includes a plurality of data transceivers 100. Each data transceiver 100 includes a receiver 110 and a transmitter 120. Receiver 110 includes a receive buffer 112 that receives serial data from a data channel; a deserializer 114 that deserializes the serial data and provides the deserialized data to the internal circuitry of the first side 10; and a receive phase adjuster 116 that receives a common clock (clk) from a clock provider 310 to generate a receive sampling clock (r_clk), and provides the receive sampling clock (r_clk) to deserializer 114. Deserializer 114 samples the serial data received from the data channel using the receive sampling clock (r_clk), deserializes the sampled data, and provides the deserialized data to the first side internal circuitry (not shown).

The transmitter 120 includes a serializer 124 that receives parallel data from a first-party internal circuit (not shown) and serializes the parallel data; a transmit buffer 122 that provides the serialized data to a data channel; and a transmit phase adjuster 126 that receives a common clock clk from a clock provider 310 to generate a transmit sampling clock t_clk and provides the transmit sampling clock t_clk to the serializer 124. The serializer 124 converts the parallel data received from the first-party internal circuit into a serial signal, samples the serial signal using the transmit sampling clock t_clk, and transmits the sampled serial signal to the data channel.

In an exemplary embodiment, the command transmitter 410 includes: a serializer 414 that receives a command packet from a first-party internal circuit (not shown) and serializes the received command packet; a command buffer 412 that transmits the serialized command packet to the second party 20 via a command channel CMD; and a command phase adjuster 416 that receives a clock clk from a clock provider 310 to generate a command sampling clock cmd_clk, and provides the command sampling clock cmd_clk to the serializer 414.

The clock provider 310 includes a clock generator 314 and a clock buffer 312. The clock generator 314 includes a voltage-controlled oscillator (VCO), a crystal oscillator (XO), and a phase-locked loop (PLL) or a delay-locked loop (DLL). The clock generator 314 provides the signal provided by the VCO or XO to the PLL or DLL, thereby generating a clock signal having a target frequency. The clock signal clk provided by the clock generator 314 serves as a clock commonly provided to the first party 10 and the second party 20. The clock buffer 312 transmits the clock clk provided by the clock generator 314 to the second party 20 via the clock channel CLK. The clock generator 314 provides the clock clk to the receive phase adjuster 116 and the transmit phase adjuster 126 via the clock buffer 312.

The clock "clk" generated by the clock provider 310 is provided to the second party 20 via the clock channel CLK. The second party 20 uses the clock provided by the first party 10 to sample data and transmit the sampled data, or uses the clock provided by the first party 10 to sample received data. Both the clock provided to the first party 10 and the clock provided to the second party 20 are generated by the clock provider 310. However, due to differences in the electrical environment, including differences in voltages supplied to the first and second parties 10, 20, processes used to generate the signals, temperature differences, and the transmitted clock channel CLK, a phase shift occurs. The two clock signals with a phase shift have the same frequency but different phases. Therefore, when it is necessary to distinguish between the clock used by the first party 10 and the clock used by the second party 20, the clock used by the first party 10 is referred to as "clk", while the clock used by the second party 20 is referred to as "clk2".

The second side 20 includes a clock receiver 320 that receives a clock from the clock channel CLK and provides the received clock to the plurality of data transceivers 200. The clock receiver 320 includes a clock buffer 322 that provides a clock clk2 to each of the data transceivers 200. As described above, unlike the first side 10, the second side 20 does not generate a clock. Therefore, the second side 20 receives the clock provided from the first side 10 and samples the received data and the data to be transmitted using the received clock clk2.

Each data transceiver 200 included in the second side 20 includes a receiver 210 and a transmitter 220. The receiver 210 includes a receive buffer 212 that buffers data received from a data channel and provides the data to a deserializer 214; and a deserializer 214 that deserializes the serial data provided by the receive buffer 212. The deserializer 214 receives a clock clk2 to sample the received data, deserializes the sampled data, and provides the deserialized data to a second side internal circuit (not shown).

Transmitter 220 includes a serializer 224 that receives and serializes data transmitted from a second-party internal circuit (not shown), and a transmit buffer 222 that transmits the serialized data to a data channel. Serializer 224 converts a parallel signal provided from the second-party internal circuit into a serial signal, samples the serial signal using clock clk2, and transmits the sampled serial signal to the data channel.

The command receiver 420 receives a command packet from the command channel CMD and provides the command packet to the second-party internal circuit (not shown). The command receiver 420 includes a deserializer 424 that samples the command packet received by the command buffer 422 using the clock clk2, deserializes the sampled command packet, and provides the deserialized command packet to the second-party internal circuit (not shown).

In an exemplary embodiment, the first party 10 can be implemented in a timing controller of a display device that displays an image, and the second party 20 can be implemented as a memory for storing display image information. In order to achieve high information storage density, the memory focuses on forming a circuit containing a repetitive regular pattern. Therefore, there may be problems with the die size and the difficulty level of implementation when implementing a clock generation circuit, a phase adjustment circuit, etc. with a non-repetitive and irregular layout on the memory. However, according to this embodiment, the timing controller and the memory can be operated simultaneously using the clock provided by the timing controller, and thus the problems of the conventional technology can be solved. In addition, the advantage provided by this embodiment is that it can achieve high information storage density and low latency.

The phase calibration step (see S100 of FIG. 2 ) includes: a transmission phase calibration process, i.e., calibrating the phase of the transmission sampling clock t_clk used by the first side 10 to transmit data packets so that the second side 20 can effectively sample the data packets transmitted from the first side 10; and a reception phase calibration process, i.e., calibrating the phase of the reception sampling clock r_clk used by the first side 10 to sample data packets so that the first side 10 can effectively sample the data packets provided by the second side 20. In one exemplary embodiment, the phase calibration step also includes a process of calibrating the phase of the command sampling clock cmd_clk used to sample command packets.

In this specification, “effective sampling” means that bit information in a data holding period can be sampled because an edge of a sampling clock for sampling is not included in a data conversion period.

Figures 3(a) and 3(b) are exemplary timing diagrams illustrating a transmit phase calibration process. Figure 3(a) is a schematic timing diagram illustrating a process in which the first party 10 generates multiple initial clocks using a clock and generates a training pattern sampled using the initial clocks, and Figure 3(b) is a schematic timing diagram illustrating a process in which the second party 20 samples a received pattern using clock clk2. Referring to Figure 3(a), the transmit phase adjuster 126 receives the clock clk shown in Figure 3(a) and generates a first initial clock _{pre_clk1} having a phase. As one implementation example, the transmit phase adjuster 126 includes a phase interpolator and generates an initial clock having a target phase by interpolating one cycle of the received clock signal clk. As another implementation example, the transmit phase adjuster 126 includes a delay element and is capable of generating an initial clock having a target phase by delaying the received clock signal clk by a target delay time.

The transmission phase adjuster 126 provides the generated first initial clock pre_clk ₁ to the serializer 124, and the serializer 124 uses the provided first initial clock pre_clk ₁ to sample a training pattern mutually predetermined between the first party 10 and the second party 20. For example, the training pattern can be provided by an internal circuit (not shown) of the first party. In another example, the training pattern can be a pattern set in the serializer 124.

As shown in the drawing, the training pattern s_ts1 sampled using the first initial clock pre_clk ₁ has a phase corresponding to the phase of the initial clock for sampling. The training pattern s_ts1 sampled using the first initial clock pre_clk ₁ is provided to the transmission buffer 122, and the transmission buffer 122 provides the sampled pattern s_ts1 to the second party 20 via the data channel.

The receiving buffer 212 of the second party 20 receives and buffers the sampled training pattern s_ts1 and provides the sampled training pattern s_ts1 to the deserializer 214 of the second party 20. The deserializer 214 samples the received pattern using a sampling clock and deserializes the sampled pattern. The clock clk2 used for sampling on the second party 20 is provided to the second party 20 via a clock channel CLK different from the data channel. Due to differences in electrical conditions such as voltage differences between the first party 10 and the second party 20, and differences in environmental conditions such as temperature and humidity between the locations of the first party 10 and the second party 20, the clock clk2 provided to the second party deserializer 214 has a different phase from the clock clk provided to the first party 10.

When the training pattern transmitted by the first party 10 is sampled using the clock clk2, there is a question of whether the training pattern can be sampled effectively. Therefore, as will be described below, when the training pattern is sampled using the clock clk2, an initial clock having a phase for restoring the training pattern on the second party 20 is detected, and a data packet is sampled using a clock such as the sampling clock and the sampled data packet is transmitted to the second party 20.

In FIG3(b), as described above, the phase difference between the clock clk2 of the second party 20 and the sampled training pattern s_ts1 received by the second party ₂₀ is different from the phase difference between the clock clk of the first party 10 and the sampled training pattern _{s_ts1} . For example, when the deserializer 214 performs sampling using the rising edge of the clock clk2, the rising edge of the clock clk2 is located in the bit transition period of the training pattern _{s_ts1} , and therefore cannot accurately sample the bits of the training pattern _{s_ts1} . Therefore, when the pattern _{s_ts1} is sampled using the clock clk2, the sampled pattern is different from the predetermined training pattern. In this case, the second party 20 transmits an inconsistency signal to the first party 10. As an exemplary embodiment, the inconsistency signal can be transmitted via a data channel among the multiple data channels that has not been phase-calibrated.

The transmission phase adjuster 126 receives the clock clk to generate a second initial clock pre_clk ₂ having a different phase from the first initial clock pre_clk ₁ , and provides the second initial clock pre_clk ₂ to the serializer 124. The serializer 124 samples a predetermined training pattern using the provided second initial clock pre_clk ₂ , thereby generating a sampled training pattern s_ts _2. As described above, the phase of the sampled training pattern corresponds to the phase of the clock used for sampling.

Serializer 124 provides the sampled training pattern _{s_ts2} to transmit buffer 122, which in turn provides the sampled training pattern _{s_ts2} to second party 20 via a data channel. Receive buffer 212 of second party 20 buffers the sampled training pattern _{s_ts2} and provides it to deserializer 214. Deserializer 214 samples the sampled training pattern _{s_ts2} using clock clk2. As shown in FIG3(b), the phase of training pattern _{s_ts2} sampled using the second initial clock _{pre_clk2} differs from the phase of training pattern _{s_ts1} sampled using the first initial clock _{pre_clk1} . Because the rising edge of clock clk2 used for sampling does not fall within a bit transition period, _the sampled training pattern _{s_ts2} can be effectively sampled. Therefore, the result of sampling training pattern _{s_ts2} using clock clk2 is consistent with the predetermined training pattern. The second side 20 transmits a coincidence signal to the first side 10 via another data channel on which phase alignment is not performed.

The transmission phase adjuster 126 generates initial clocks whose phases change sequentially, and provides the corresponding initial clocks to the serializer 124, thereby generating a training pattern sampled using the corresponding initial clock. The sampled training pattern generated in this manner exhibits the phase offset shown in FIG3(b). Therefore, when s_ts _k-1 is sampled, the rising edge of the clock clk2 is not within the bit transition period, and the pattern can be effectively sampled. However, when s_ts _k is sampled, the rising edge of the clock clk ₂ is included in the bit transition period, and the pattern cannot be effectively sampled. Therefore, the second party 20 transmits a consistent signal until s_ts _k-1 is sampled, and when s_ts _k is sampled because the sampled training pattern is different from the predetermined training pattern, the second party 20 transmits an inconsistent signal to the first party.

The first party 10 determines the phase range of the initial clock that receives the coincidence signal. Referring to FIG3( b ), the pattern from s_ts ₂ to s_ts _k-1 can be effectively sampled using clock clk _2. Therefore, in one exemplary embodiment, the first party 10 selects the following initial clock as the transmission sampling clock t_clk: the initial clock having any phase within the range from the phase of the clock signal pre_clk ₂ used to sample s_ts ₂ to the phase of the clock signal pre_clk k _{- 1 used to sample s_ts k-1} . In another exemplary embodiment, the first party 10 selects the following initial clock as the transmission sampling clock t_clk: the initial clock having a phase in the middle of the range from the phase of the clock signal pre_clk ₂ used to sample s_ts ₂ to the phase of the clock signal pre_clk _k-1 used to sample s_ts _k-1 .

In FIG3(b), s_data is a timing diagram showing a case where the first party 10 selects an initial clock having a phase in the middle of the range as the transmission sampling clock t_clk, and the second party receives data s_data sampled using the transmission sampling clock t_clk. As shown in the figure, the sampling edge of the clock _clk2 is positioned so that bits of the sampled data s_data can be sampled.

FIG4 shows an exemplary timing diagram illustrating a receive phase calibration process. Referring to FIG4 , for example, an internal circuit (not shown) of the second side 20 provides a predetermined training pattern to the serializer 224, and the serializer 224 samples the provided training pattern using the clock clk2 and provides the sampled training pattern to the data channel via the transmit buffer 222. The receive buffer 112 of the first side 10 receives the training pattern r_ts provided by the second side 20 via the data channel, buffers the training pattern r_ts, and provides it to the deserializer 114. In another example, the predetermined training pattern may be set in the serializer 224.

The pattern r_ts is obtained by sampling and transmitting the pattern using the clock clk2 of the second side 20. As described above, the clock clk2 of the second side 20 has a different phase from the clock clk of the first side 10, and therefore the receive sampling clock used for sampling should be generated on the first side 10. The receive phase adjuster 116 receives the clock clk and generates an initial clock pre_clk _a with a phase of 0.001. The receive phase adjuster 116 provides the generated initial clock pre_clk _a to the deserializer 114, and the deserializer 114 samples the pattern r_ts using the provided initial clock pre_clk _a .

In one example, the receive phase adjuster 116 may be implemented as a phase interpolator that receives the clock clk and generates an initial clock having a target phase by interpolating the phase. In another example, the receive phase adjuster 116 may include a delay element that receives the clock clk and generates an initial clock having a target phase by delaying the clock clk by a predetermined delay time.

As shown in the figure, the rising edge of the initial clock pre_clk _a used by deserializer 114 for sampling falls during a bit transition period of pattern r_ts, and therefore cannot effectively sample pattern r_ts. Therefore, when the sampling result is compared with the predetermined training pattern, it can be determined that they are different. In one exemplary embodiment, first party 10 sends an inconsistency signal to second party 20.

The receive phase adjuster 116 generates an initial clock pre_clk _b with a phase of by adjusting the phase of the clock clk, and provides the initial clock pre_clk _b to the deserializer 114. The rising edge of the initial clock pre_clk _b used by the deserializer 114 for sampling does not fall within the bit transition period of the pattern r_ts, and thus the pattern r_ts can be effectively sampled. Therefore, when the sampling result is compared with the predetermined training pattern, it can be determined that they are the same.

The reception phase adjuster 116 generates an initial clock while sequentially changing the phase of the clock clk, and sequentially provides the generated initial clock to the deserializer 114. The deserializer 114 samples the pattern r_ts using the provided initial clock and determines whether the sampled pattern is consistent with the predetermined training pattern. As shown in FIG4 , the initial clock pre_clk _k with a phase of has a rising edge outside the bit transition period of the pattern r_ts, and thus the deserializer 114 can effectively sample the pattern r_ts. However, the initial clock pre_clk _k+1 with a phase of has a rising edge within the bit transition period of the pattern r_ts, and therefore cannot effectively sample the pattern r_ts.

In an exemplary embodiment, the first side 10 selects any one of the initial clocks pre_clk _b having the bth phase to pre_clk _k having the kth phase as the reception sampling clock r_clk to sample data provided by the second side 10 .

In another exemplary embodiment, the first side 10 may determine a range of initial clock phases capable of validly sampling a pattern, and select an initial clock with a phase in the middle of this phase range as the receive sampling clock r_clk. In one example, when the initial clock phases capable of validly sampling a pattern are three consecutive phases: the a-th phase, the b-th phase, and the c-th phase, the first side 10 may select an initial clock with a b-th phase in the middle of these phases as the receive sampling clock r_clk. In another example, when the initial clock phases capable of validly sampling a pattern are four consecutive phases: the a-th phase, the b-th phase, the c-th phase, and the d-th phase, the first side 10 may select an initial clock with either a b-th phase or a c-th phase in the middle of these phases as the receive sampling clock r_clk.

In one exemplary embodiment, the phase calibration process also includes a command clock phase calibration process for sampling a command packet provided by the first side 10. The process of providing a command packet from the first side 10 to the second side 20 and calibrating the phase of the command sampling clock is similar to the process of calibrating the phase of the transmission sampling clock described above. The command packet is provided from an internal circuit (not shown) of the first side 10 to the serializer 414, and the serializer 414 samples the command packet using the command sampling clock cmd_clk and transmits the sampled command packet to the second side 20.

The second party 20 receives the command packet via the command channel CMD, and the command buffer 422 buffers the received command packet and provides it to the deserializer 424. The deserializer 424 samples the command packet using the clock clk2, deserializes the sampled command packet, and provides the deserialized command packet to the second party internal circuit (not shown). In an exemplary embodiment, the command phase adjuster 416 receives the common clock clk, generates an initial clock with a target phase, samples a training pattern using the initial clock, and provides the sampled training pattern to the second party command receiver 420.

The deserializer 424 samples the received pattern using the second-party clock clk2, determines whether the sampled pattern matches the predetermined training pattern, and provides a consistency signal or a non-consistency signal to the first party 10. As will be described below, there are three types of channels for transmitting information between the first party 10 and the second party 20: a clock channel CLK, data channels DATA 1 to DATA n, and a command channel CMD. Of these channels, bidirectional transmission is only possible on the data channels DATA 1 to DATA n. Therefore, the second-party internal circuit (not shown) transmits a consistency signal or a non-consistency signal to the first party 10 via the data channels.

For example, in the process of calibrating the phase of the command sampling clock, the second-party internal circuit (not shown) can transmit a coincidence signal or a disagreement signal by causing all the data channels DATA 1 to DATA n to transmit logic 1 or logic 0 to the first party 10. In another example, the second-party internal circuit (not shown) can transmit a coincidence signal or a disagreement signal via any one predetermined data channel between the first party 10 and the second party 20.

The command phase adjuster 416 can determine the phase range of the initial clock that can effectively sample the training pattern for the deserializer 424 based on the consistent signal or the inconsistent signal. For example, the command phase adjuster 416 can select an initial clock with a phase in the middle of the phase range as the command sampling clock cmd_clk. In another example, the command phase adjuster 416 can select an initial clock with a phase within any phase range as the command sampling clock cmd_clk.

The result of the phase calibration may vary according to all channels including the data channel and the command channel. Therefore, the phase calibration is adjusted or grouped according to the corresponding channel.

Each of the multiple transceivers 100 included in the first party 10 performs a phase calibration process to generate a transmit sampling clock and a receive sampling clock. When the multiple transceivers 100 included in the first party 10 perform phase calibration simultaneously, there may be a lack of channels for transmitting consistent signals and/or inconsistent signals, and the phase calibration process for forming the transmit sampling clock may take an excessively long time. In one exemplary embodiment, all transceivers 100 can be classified into two groups to perform phase calibration processes separately. In another exemplary embodiment, all transceivers 100 can be classified into even-numbered data transceivers and odd-numbered data transceivers, and the phase calibration process can be performed separately.

In one exemplary embodiment, when the first and second parties 10 and 20 transmit and receive data in frames consisting of multiple lines, phase calibration is performed after a predetermined number of frames have been transmitted and received. Because the phase can change depending on changes in the voltage supplied to the first and second parties 10 and 20 and the environment, performing phase calibration after a predetermined number of frames have been transmitted and received can reduce data transmission errors caused by phase changes. Therefore, when frame data is transmitted and received periodically, the phase calibration step is performed periodically, while when frame data is transmitted and received irregularly, the phase calibration step is performed irregularly. For example, phase calibration can be performed during the vertical blanking period after a predetermined number of frames have been transmitted and received.

In another exemplary embodiment, phase calibration can be performed during a blanking period in which neither the first side 10 nor the second side 20 is operating. For example, when the first side 10 is a data transmission chip and the second side 20 is a dynamic random access memory (DRAM), the DRAM cannot receive or output data during a refresh cycle. Therefore, the first side 10 cannot perform phase calibration during the memory's refresh cycle.

In other words, when memory refresh is performed periodically, the phase calibration step is performed periodically, and when memory refresh is performed aperiodically, the phase calibration step is performed aperiodically.

In one exemplary embodiment, when the apparatus including the first side 10 and the second side 20 is supplied with power and performs initial operation, the first side 10 and the second side 20 perform a phase calibration step. When the initial operation is completed after the command sampling clock, the transmission sampling clock, and the reception sampling clock are all generated, the phase calibration step is performed.

The first side 10 sends a command packet to the second side 20 (S200, see FIG2 ). The command packet is a packet that the first side 10 instructs the second side 20 to perform a process. The command packet may be, for example, a read packet RD for the first side 10 to read information stored in the second side 20, a write packet WR for writing information provided by the first side 10 to the second side 20, or a refresh packet RF for performing a refresh when the second side 20 is a DRAM.

In addition, the command packet may include a row address strobe (RAS) packet for specifying a row address of the second party 20, and a column address strobe (CAS) packet for specifying a column address of the second party 20, and may also include a no operation (NOP) packet indicating the absence of a command. A person of ordinary skill will be able to define and use the command packet in various forms other than the command packet exemplified in the following description.

FIG5 is a timing diagram schematically illustrating a process in which a first party writes stored data to a second party. Referring to FIG5 , the process of writing data provided by the first party to the second party will be described. The first party 10 sends a write packet WR via a command channel CMD (S200, see FIG2 ). The first party 10 sends a plurality of NOP packets, thereby ensuring time for the second party 20 to receive the write packet WR, decode it, and perform internal processing. For example, the number of NOP packets sent can be changed according to the time taken for the second party to decode and perform internal processing.

After transmitting a sufficient number of NOP packets, the first party 10 transmits a RAS packet via the command channel CMD and transmits a synchronization packet SYNC via the data channels DATA 1, DATA 2, ..., and DATA n. The synchronization packet SYNC is a packet used to indicate the starting point of data when data is transmitted from the first party 10 to the second party 20 or when data is transmitted from the second party 20 to the first party 10.

While sending the CAS packet via the command channel CMD, the first party 10 sends data for writing via the data channels DATA 1, DATA2, ..., and DATA n. FIG5 shows that two packets are sent via each data channel, but the number of data packets sent via each channel can be changed. The second party 20 decodes the data provided via the data channels DATA 1, DATA2, ..., and DATA n and stores the decoded data at the address specified by the RAS packet and the CAS packet. As shown in the drawings, data can be additionally sent by sending another RAS packet and another CAS packet. Although not shown in the drawings, by sending either the RAS packet or the CAS packet, data to be stored in the corresponding row or column can be additionally sent.

As shown in FIG5 , packets transmitted from the first party 10 to the second party 20 do not have the same phase. This is because the channel-specific data receiver 210 of the second party 20 sets the transmission sampling clock t_clk so that the transmitted packets can be effectively sampled using the second-party clock clk2 regardless of clock offsets caused by voltage variations and temperature variations between the first party 10 and the second party 20. Therefore, packets transmitted via the corresponding data channels DATA 1, DATA 2, ..., and DATA n and the command channel CMD can have different phases.

FIG6 is a timing diagram schematically illustrating a process in which the first party 10 reads data stored in the second party 20. Referring to FIG6 , the process in which the first party 10 reads data stored in the second party 20 will be described. The first party 10 transmits a read packet RD via a command packet CMD (S200, see FIG2 ). As in the write process, the first party 10 transmits a plurality of NOP packets, allowing the second party 20 to receive the read packet RD and perform internal processing such as decoding.

By sending RAS and CAS packets via the command channel CMD, the first party 10 provides the address of the data to be read to the second party 20. The second party 20 obtains the data using the address specified by the RAS and CAS packets. The second party 20 performs a predetermined decoding process on the obtained data and transmits the decoded data to the first party 10 via the data channels DATA 1, DATA 2, ..., and DATA n.

As with the write process, data can be additionally read by sending another RAS packet and another CAS packet via the command channel CMD. Although not shown in the drawings, by sending either a RAS packet or a CAS packet, data to be stored in the corresponding row or column can be additionally sent.

As shown in FIG6 , data packets provided from the second party 20 via data channels DATA 1, DATA 2, ..., and DATA n are sampled using the second party instance clk2 and transmitted. Although not shown in the figure, clock offsets may occur due to voltage differences, temperature differences, etc. between the first party 10 and the second party 20. However, each first-party data receiver 110 sets a reception sampling clock r_clk to overcome phase offsets during the phase calibration process and sample data. Therefore, despite the phase offset, data packets can be effectively sampled.

FIG7 illustrates a process in which the second side 20 performs a refresh when the second side 20 is a DRAM requiring refresh. Referring to FIG7 , the first side 10 transmits a refresh packet RF via the command channel CMD. As with the read and write processes described above, the first side 10 transmits multiple NOP packets to ensure command decoding. The first side 10 specifies the row address and/or column address to be refreshed using RAS and CAS packets, respectively, and transmits the RAS and CAS packets to the second side 20, causing the refresh to be executed.

According to this embodiment, data communication can be performed between a first party and a second party using a clock signal provided by the first party, and even when the transmitting and receiving parties change, the PLL or clock data recovery (CDR) device does not perform clock lock. Therefore, delay time can be reduced.

While the present invention has been shown and described with reference to particular exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as defined by the following claims.

Industrial Applicability

The above records

Claims (26)

1. A communication method between a first party and a second party operating using a clock provided by the first party, the communication method comprising the following steps: Phase calibration steps; The steps of the first party sending command packets to the second party; and The steps of sending and receiving data packets between the first party and the second party according to the command packets. Specifically, the phase calibration step is performed to calibrate the phase of the first party's received sampling clock, and The phase calibration step includes the following steps: The second party provides the first party with a mutually predetermined training mode; The first party generates the initial clock from the clock. The first party uses the initial clock to sample the training pattern provided by the second party; Determine whether the sampling pattern using the initial clock is consistent with the predetermined training pattern; and An initial clock with a phase that makes the sampling mode using the initial clock equal to the predetermined training mode is selected as the receiving sampling clock. 2. The communication method according to claim 1, wherein the phase calibration step is performed such that the sampling edge of the received sampling clock samples the bits contained in the training mode. 3. The communication method according to claim 1, wherein the phase calibration step is performed periodically. 4. The communication method according to claim 1, wherein the phase calibration step is performed periodically. 5. The communication method according to claim 1, wherein the first party is a timing controller. The second party is a memory, and The data groups are displayed on the display panel. 6. The communication method according to claim 1, wherein the phase calibration step further includes the following step: calibrating the phase of a command sampling clock, the command sampling clock being used to sample the command packets sent from the first party to the second party. 7. A communication method in which a first party transmits data to a second party using a clock provided by the first party, the communication method comprising the following steps: (a) The first party changes the phase of the clock to generate an initial clock with a target phase; (b) The first party samples mutually predetermined training patterns using the initial clock and sends the sampled patterns to the second party; (c) The second party uses the clock to sample the received pattern, compares the sampled pattern with the predetermined training pattern, and sends the comparison result; (d) The first party selects an initial clock as the transmission sampling clock based on the comparison result; and (e) The first party samples the data to be transmitted using the transmission sampling clock whose phase has been adjusted, and transmits the sampled data to the second party. 8. The communication method according to claim 7, wherein step (a) is performed to delay or interpolate the clock such that the initial clock has the target phase. 9. The communication method according to claim 7, wherein steps (a) to (c) are performed multiple times, and The initial clock is generated according to different phases based on the number of times steps (a) to (c) are executed. 10. The communication method according to claim 9, wherein step (d) comprises the following steps: The phase range of the initial clock, which indicates that the sampled pattern matches the predetermined training pattern, is calculated; and An initial clock within the phase range is determined as the transmission sampling clock. 11. The communication method according to claim 7, wherein, after the transmission of the data to be transmitted is completed, steps (a) to (d) are performed again. 12. A communication method in which a second party transmits data to a first party using a clock provided by the first party, the communication method comprising the following steps: (a) The second party sends a mutually predetermined training mode to the first party; (b) The first party changes the phase of the clock to generate an initial clock with a target phase; (c) The first party samples the pattern provided by the second party using the initial clock, and compares the sampled pattern with the predetermined training pattern; (d) The first party selects an initial clock as the receiving sampling clock based on the comparison result; and (e) The data sent by the second party is sampled using the received sampling clock. 13. The communication method of claim 12, wherein step (b) is performed to delay or interpolate the clock such that the initial clock has the target phase. 14. The communication method according to claim 12, wherein steps (a) to (c) are performed multiple times, and The initial clock is generated according to different phases based on the number of times steps (a) to (c) are executed. 15. The communication method according to claim 14, wherein step (d) comprises the following steps: The phase range of the initial clock, which indicates that the sampled pattern matches the predetermined training pattern, is calculated; and An initial clock having a phase contained within the said phase range is determined as the received sampling clock. 16. The communication method according to claim 12, wherein, after the transmission of the data to be transmitted is completed, steps (a) to (d) are performed again. 17. A communication device, the communication device comprising: A first party, comprising: a clock provider configured to provide a clock; and a plurality of first party data transceivers configured to provide or receive data; The second party includes a clock receiver and a plurality of second-party data transceivers configured to provide or receive the data. A data channel unit, comprising a data channel configured to connect the plurality of first-party data transceivers to the plurality of second-party data transceivers respectively; and A clock channel configured to provide the clock from the first party to the second party. The first party and the second party operate using the clock. The first-party data transceiver includes: An input unit, comprising: a deserializer configured to convert serial data provided from the data channel into parallel data and output the parallel data; and an input phase adjuster configured to receive the clock, generate a receive sampling clock from the clock for sampling the parallel data, and provide the receive sampling clock to the deserializer; and An output unit, comprising: a serializer configured to convert provided parallel data into serial data and output the serial data to the data channel; and an output phase adjuster configured to receive the clock, generate a transmit sampling clock from the clock for sampling the serial data, and provide the transmit sampling clock to the serializer. Among these steps, the phase calibration step is performed, and In the phase calibration step, the input phase adjuster uses an initial receiving clock to sample a predetermined training pattern provided by the second party, determines whether the sampled data is consistent with the predetermined training pattern, and selects the initial receiving clock as the receiving sampling clock. 18. The communication device of claim 17, further comprising a command channel configured to provide command packets to the second party. The first party further includes a command unit configured to provide the command group. 19. A communication method between a first party and a second party operating using a clock provided by the first party, the communication method comprising the following steps: Phase calibration steps; The steps of the first party sending command packets to the second party; and The steps of sending and receiving data packets between the first party and the second party according to the command packets are as follows: Specifically, the phase calibration step is performed to calibrate the phase of the first party's transmitting sampling clock, and The phase calibration step includes the following steps: The first party generates the initial clock from the clock. The predetermined training pattern is sampled using the initial clock, and the sampled pattern is sent to the second party. The second party uses the clock to sample the received pattern; Determine whether the sampling pattern performed by the second party is consistent with the predetermined training pattern; and An initial clock with a phase that makes the sampling mode using the clock equal to the predetermined training mode is selected as the transmission sampling clock. 20. The communication method of claim 19, wherein the phase calibration step is performed such that the sampling edge of the transmission sampling clock samples the bits contained in the training mode. 21. The communication method of claim 19, wherein the phase calibration step is performed periodically. 22. The communication method according to claim 19, wherein the phase calibration step is performed periodically. 23. The communication method according to claim 19, wherein the first party is a timing controller. The second party is a memory, and The data groups are displayed on the display panel. 24. The communication method according to claim 19, wherein the phase calibration step further includes the step of: calibrating the phase of a command sampling clock, the command sampling clock being used to sample the command packets sent from the first party to the second party. 25. A communication device, the communication device comprising: A first party, comprising: a clock provider configured to provide a clock; and a plurality of first party data transceivers configured to provide or receive data; The second party includes a clock receiver and a plurality of second-party data transceivers configured to provide or receive the data. A data channel unit, comprising a data channel configured to connect the plurality of first-party data transceivers to the plurality of second-party data transceivers respectively; and A clock channel configured to provide the clock from the first party to the second party. The first party and the second party operate using the clock. The second-party data transceiver includes: An input unit, comprising: a deserializer configured to receive serial data from the data channel, sample the serial data using the clock, convert the sampled serial data into parallel data, and output the parallel data; and A serializer, configured to receive parallel data, convert the received parallel data into serial data, sample the serial data using the clock, and provide the sampled serial data to the data channel, and Among these steps, the phase calibration step is performed, and In the phase calibration step, the output phase adjuster samples a predetermined training pattern using an initial transmission clock and provides the sampled pattern to the second party. The input unit of the second party samples the pattern provided by the first party, determines whether the sampled data is consistent with the predetermined training pattern, and provides a phase-matching signal to the first party. The first party selects the initial transmission clock as the transmission sampling clock. 26. The communication device of claim 25, further comprising a command channel configured to provide command packets to the second party. The first party further includes a command unit configured to provide the command group.