HK1218025B - Variable load power amplifier supporting dual-mode envelope tracking and average power tracking performance - Google Patents

Description

Variable load power amplifier supporting dual-mode envelope and average power tracking performance

Cross-references of related applications

This application claims the entire disclosures of U.S. Provisional Patent Application No. 62/055,614, filed on September 25, 2015, entitled “VARIABLE LOAD POWER AMPLIFIER SUPPORTING DUAL-MODE ENVELOPE TRACKING AND AVERAGE POWER TRACKING PERFORMANCE,” and U.S. Application No. 14/824,679, filed on August 12, 2015, entitled “VARIABLE LOAD POWER AMPLIFIER SUPPORTING DUAL-MODE ENVELOPE TRACKING AND AVERAGE POWER TRACKING PERFORMANCE,” each of which is hereby incorporated by reference herein.

Technical Field

The present disclosure relates generally to wireless communication systems, and more particularly to improving the functionality and efficiency of internal power amplifiers.

Background Art

Power amplifiers (PAs) are widely used in networks to set the transmission power level of information-carrying signals. For example, PAs are used to set the pulsed energy of lasers in optical networks. PAs are also included in various wireless network devices, such as base stations and mobile devices, to set the transmission power level of radio frequency (RF) signals. PAs are also used in local area networks to enable various devices to connect, either wired or wirelessly.

Because PA operation often characterizes the signal transmission of mobile devices, managing PA operation is a concern in mobile devices. Therefore, PAs are designed to meet performance targets dictated by their intended use. However, design choices that meet certain performance targets may be detrimental to other aspects. For example, efficiency and output power are often competing performance targets. Accordingly, previously available PA designs often prioritize meeting one of output power and efficiency. Non-PAs that prioritize efficiency are often based on envelope tracking (ET), while PAs that prioritize output power are often based on average power tracking (APT). ET involves adjusting the voltage supply of the PA based on the envelope of the input RF signal amplified by the PA, while APT involves adjusting the voltage supply based on the average output power of the PA. PAs designed for use with ET typically have a higher load line in order to operate at higher efficiency. PAs designed for use with APT typically have a lower load line in order to deliver more saturated power.

ET and APT each have advantages for corresponding signaling configurations. Therefore, enabling switching between ET and APT in response to real-time signaling configuration changes may be beneficial. Using previously known techniques, such switching involves two different PA modules, which are expensive and increase the number of components and device size. Therefore, a compromise is often made between selecting only one PA based on ET or APT. If an ET-based PA is selected, the PA will exhibit suboptimal output power performance for certain signaling configurations. If an APT-based PA is selected, the PA will generally exhibit suboptimal signaling performance for other signaling configurations. In both cases, the selected PA fails to meet the corresponding performance measures for various corresponding signaling conditions.

Summary of the Invention

Various implementations described herein include apparatus, arrangements, and methods for improving the performance of power amplifiers that provide both envelope tracking (ET) and average power tracking (APT). Numerous details are described herein to facilitate a thorough understanding of the exemplary implementations shown in the accompanying drawings. The present invention may be practiced without the specific details described herein. Furthermore, well-known methods, components, and circuits have not been fully described to avoid unnecessarily obscuring an understanding of the more relevant aspects of the implementations described herein.

For example, one implementation includes a variable-load power amplifier comprising: a plurality of amplifiers, each of the plurality of amplifiers selectively connectable to one of a plurality of parallel combinations, each of the plurality of parallel combinations being characterized by a respective load line. The variable-load power amplifier further comprises a plurality of control elements arranged to selectively connect one or more of the plurality of amplifiers to one of the plurality of parallel combinations, each of the plurality of control elements having a respective input terminal provided for receiving a respective control signal, each of the plurality of control elements being responsive to the respective control signal.

In some implementations, the variable load power amplifier further includes a control bus coupled to respective input terminals of the plurality of control elements to provide respective control signals for influencing selection of the plurality of amplifiers.

In some implementations, each of the plurality of amplifiers can be connected to a common input node to receive a common input signal provided for selecting one or more of the plurality of amplifiers.

In some implementations, the variable load power amplifier further includes inter-stage impedance matching, providing inter-stage impedance matching to transmit a common input signal to a common input node of the plurality of amplifiers.

In some implementations, the variable load power amplifier further includes a driver stage, wherein an inter-stage impedance match is coupled between the driver stage and a common input node of the plurality of amplifiers.

In some implementations, each of the plurality of amplifiers can be connected to a common output node to transmit an output signal generated by selecting one or more of the plurality of amplifiers.

In some implementations, at least one of the plurality of control elements includes a differential amplifier, the differential amplifier is coupled to receive the corresponding control signal, and in response to receiving the response control signal, one of the plurality of amplifiers is connected to or disconnected from the specific parallel combination.

In some implementations, at least one of the plurality of parallel combinations has a higher load line suitable for use on an envelope tracking module coupled between inputs to the plurality of amplifiers and a voltage supply for the plurality of amplifiers.

In some implementations, at least one of the plurality of parallel combinations has a lower load line suitable for use on an average power tracking module coupled between a common output of the plurality of amplifiers and a voltage supply of the plurality of amplifiers.

In some implementations, the present disclosure relates to a variable-load power amplifier module, comprising a packaging substrate configured to house a plurality of components. The variable-load power amplifier module further comprises a variable-load power amplifier arranged on the packaging substrate, the variable-load power amplifier comprising a plurality of amplifiers, each of the plurality of amplifiers being selectively connectable to one of a plurality of parallel combinations, each of the plurality of parallel combinations presenting a corresponding load line. The variable-load power amplifier module further comprises a performance mode controller coupled to the variable-load power amplifier and configured to provide one or more control signals to the variable-load power amplifier to generate a specific load line corresponding to a performance mode.

In some implementations, the variable load power amplifier module further includes: a plurality of control elements, the plurality of control elements being provided to affect selection of one or more of the plurality of amplifiers in response to receiving one or more control signals; and a control bus coupled between the performance mode controller and the plurality of control elements.

In some implementations, the variable load power amplifier module further includes an envelope tracking module coupled between a common input of the plurality of amplifiers and a common voltage supply node of the plurality of amplifiers, and configured to provide an envelope signal to the common voltage supply node.

In some implementations, the performance mode controller is further configured to support the envelope tracking module in a corresponding operating mode and provide a combination of one or more control signals to the variable load power amplifier to affect selection of one or more of the plurality of amplifiers, the plurality of amplifier combinations having a higher load line suitable for use with the envelope tracking module.

In some implementations, the variable load power amplifier module further includes an average power tracking module coupled between a common output of the plurality of amplifiers and a common voltage supply node of the plurality of amplifiers, and configured to adjust a DC voltage level on the common voltage supply node.

In some implementations, the performance mode controller is further configured to support the average power tracking module in a corresponding operating mode and provide a combination of one or more control signals to the variable load power amplifier to perform selection of one or more of the plurality of amplifiers, the plurality of amplifier combinations having a lower load line suitable for use on the average power tracking module.

In some implementations, each of the plurality of amplifiers can be connected to a common input node to receive a common input signal provided to select one or more of the plurality of amplifiers; and/or each of the plurality of amplifiers can be connected to a common output node to transmit an output signal generated by selecting one or more of the plurality of amplifiers.

According to some teachings, the present disclosure relates to a radio frequency (RF) device comprising a transceiver configured to process an RF signal. The RF device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The RF device further comprises a variable load power amplifier module coupled to the transceiver and configured to generate an amplified RF signal, the variable load power amplifier module comprising a plurality of amplifiers, each of the plurality of amplifiers being connectable to one of a plurality of parallel combinations, each of the plurality of parallel combinations presenting a corresponding load line.

In some implementations, the RF device is a wireless device.

In some implementations, the wireless device includes at least one of a base station, a repeater, a cellular phone, a smart phone, a computer, a laptop, a tablet, and an external device.

In some implementations, the RF device further includes a performance mode controller coupled to the variable load power amplifier, the performance mode controller being configured to provide a control signal to the variable load power amplifier to generate a specific load line of the corresponding performance mode.

In some implementations, the performance mode controller is further configured to support: the envelope tracking module being in a first operating mode and providing a combination of control signals to the variable load power amplifier to perform selection of one or more of the plurality of amplifiers, the plurality of amplifier combinations having a higher load line suitable for use on the envelope tracking module; and the average power tracking module being in a second operating mode and providing a combination of control signals to the variable load power amplifier to perform selection of one or more of the plurality of amplifiers, the plurality of amplifier combinations having a lower load line suitable for use on the average power tracking module.

In some implementations, each of the plurality of amplifiers can be connected to a common input node to receive a common input signal provided to select one or more of the plurality of amplifiers; and/or each of the plurality of amplifiers can be connected to a common output node to transmit an output signal generated by selecting one or more of the plurality of amplifiers.

In some implementations, the present disclosure relates to a method for operating a variable load amplifier. The method can include receiving a mode selection signal indicating that one of envelope tracking performance and average power tracking performance is prioritized. The method can also include generating a combination of control signals in response to receiving the mode selection signal, the generated combination of control signals indicating selection of a specific parallel combination of one or more of a plurality of amplifiers having characteristic load line values suitable for one of envelope tracking performance and average power tracking performance, based on the mode selection signal. The method can also include providing the combination of control signals to a corresponding plurality of control elements to select the one or more of the plurality of amplifiers.

For the purpose of summarizing this disclosure, specific aspects, advantages, and novel aspects of the present invention are described herein. It should be understood that not all of these advantages may be achieved according to any specific embodiment of the present invention. Therefore, the present invention may be implemented or carried out in a manner that achieves or optimizes one or a group of advantages described herein without necessarily achieving the other advantages described or suggested herein.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to enable a more detailed understanding of the present disclosure, a more particular description will be given with reference to the features of various implementations, some of which are shown in the accompanying drawings. However, the accompanying drawings only illustrate features that are more closely related to the present disclosure and, therefore, are not to be understood as limiting, as the description may admit of other effective features.

1 is a block diagram of a portion of a wireless device including a power amplifier module according to some implementations.

2 is a schematic diagram of a variable load power amplifier operating configuration according to some implementations.

3A is a more detailed schematic diagram of the variable load power amplifier shown in FIG. 2 , according to some implementations.

3B is another more detailed schematic diagram of the variable load power amplifier shown in FIG. 2 , according to some implementations.

4 is a flow chart of an implementation of a method of operating the variable load power amplifier shown in FIG. 2 , according to some implementations.

5 is a block diagram of a variable load power amplifier operating configuration according to some implementations.

6 is a performance graph illustrating gain compression of a variable load power amplifier according to some implementations.

7 is a performance graph illustrating output power performance of a variable load power amplifier according to some implementations.

8 is a performance graph illustrating power added efficiency performance of a variable load power amplifier according to some implementations.

9A-9C are schematic diagrams of different integrated circuit implementations of the variable load power amplifiers of Figs. 2 and 3A-3B.

10 is a schematic diagram of an implementation of a module comprising the variable load power amplifier of FIGS. 2 and 3A-3B .

11 is a schematic diagram of an implementation of a wireless device incorporating the variable load power amplifier of FIGS. 2 and 3A-3B .

As is customary, various features shown in the accompanying drawings may not be shown to scale. Therefore, for the sake of clarity, the dimensions of various features may be arbitrarily enlarged or reduced. Furthermore, some of the accompanying drawings may not show all components of a given system, method, or apparatus. Finally, throughout the specification and accompanying drawings, the same symbols may be used to represent the same features.

DETAILED DESCRIPTION

The few, if any, section headings given herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

Power amplifiers (PAs) are used in communications networks to set the transmission level of data signals. For example, PAs are used to set the energy of transmitted pulsed lasers in optical communications networks. PAs are used in the radio frequency (RF) components of wireless devices, such as base stations and mobile devices, to set the power level transmitted by the antenna. PAs are also used in local area networks to support connectivity for servers, computers, laptops, and peripheral devices.

FIG1 is a block diagram of a portion of a wireless device 100 including a power amplifier module according to some implementations. Although relevant features are shown, those skilled in the art will appreciate from this disclosure that various other features are not shown for the sake of brevity and to not obscure the understanding of the more relevant aspects of the exemplary implementations disclosed herein. To this end, the wireless device 100 includes a baseband subsystem 110, an RF transceiver 120, a duplexer 130, a PA module 140, a low noise amplifier (LNA) 151, a tuning circuit 160, and an antenna 170.

Tuning circuit 160 is coupled between antenna 170 and duplexer 130. RF transceiver 120 is coupled in series between subsystem 110 and the parallel path provided by PA module 140 and LNA 151. RF transceiver 120 includes a transmit signal chain 122 and a receive signal chain 121. LNA 151 couples antenna tuner 160 to receive signal chain 121 via duplexer 130. Similarly, PA module 140 couples transmit signal chain 122 to antenna tuner 160 via duplexer 130. PA module 140 includes PA 141, which is used to set the power level of the data signal provided by transmit signal chain 122 and transmit the data signal via antenna 170.

In some implementations, the tuning circuit 160 is configured to adjust the impedance matching between the antenna 170 and the rest of the wireless device 100. In other words, the tuning circuit 160 can operate to set and present an antenna load impedance ( _Zantenna ) to the rest of the wireless device 100.

In some implementations, transmit signal chain 122 is configured to up-convert a modulated signal received from baseband subsystem 110 to a carrier frequency. In some implementations, receive signal chain 121 is configured to down-convert the modulated signal and provide the down-converted signal to baseband subsystem 110. Duplexer 130 is configured to provide frequency domain isolation between transmit RF signals and receive RF signals, enabling simultaneous use of transmit signal chain 122 and receive signal chain 121.

Typically, the PA 141 is designed to meet performance targets tailored to the expected usage profile of the wireless device 100. For example, efficiency and output power are often competing performance criteria for various signaling configurations, and previously available PA designs often prioritize one or the other. PA designs prioritizing efficiency are often based on envelope tracking (ET), while PA designs prioritizing output power are often based on average power tracking (APT). To operate at higher efficiency, ET-based PAs typically have a higher load line, while APT-based PAs typically have a lower load line to deliver higher saturation power. ET and APT each have advantages for their respective signaling configurations. Therefore, it would be beneficial to be able to switch between ET and APT performance in response to real-time signaling configuration changes. However, with previously available PA designs, this switching involves two different PA modules, which are expensive and increase the number of components and device size. Consequently, a compromise is often made between selecting only one PA based on ET or APT. If a PA with ET is selected, it may exhibit suboptimal output power performance for some signaling configurations. In contrast, if an APT-based PA is selected, the PA typically exhibits suboptimal efficiency performance for other signaling configurations.

By contrast, various implementations described herein include systems, methods, and apparatus configured to provide a variable load power amplifier (VLPA) operable to support dual-mode ET and APT performance without the attendant cost, complexity, and component count of two different PT modules. More specifically, some implementations include a variable load power amplifier (VLPA) comprising a plurality of amplifiers selectively connected to one of a plurality of parallel combinations. Each parallel combination is characterized by a load line suitable for a particular performance mode.

To achieve these objectives, FIG2 is a schematic diagram of a VLPA operating configuration 200 according to some implementations. While relevant features are shown, those skilled in the art will appreciate that various other features are not shown for the sake of brevity and to not obscure the broader understanding of the disclosed examples. As a non-limiting example, VLPA operating configuration 200 includes: a VLPA 210, a performance mode controller 250, an ET mode 220, an APT control module 230, and a DC-DC converter 240.

The VLPA 210 is arranged to receive an RF input signal ( _RFin ) from an input node 211 through a coupling capacitor 213 ( _C1 ) and to provide an amplified RF output signal ( _RFout ) at an output node 214. In various implementations, the capacitor 213 ( _C1 ) is implemented as a single capacitor or a multi-component capacitive circuit arrangement. The VLPA 102 also has a voltage supply node 201 provided for receiving a voltage supply level.

Performance mode controller 250 is coupled to VLPA 210 via control line 252. In some implementations, control line 252 comprises a control bus that is coupled to respective input terminals of control elements included in VLPA 210 (shown in Figures 3A and 3B). Performance mode controller 250 is configured to provide one or more control signals to VLPA 210 to generate a specific load line for a respective performance mode. Performance mode controller 250 is also coupled to ET module 220 via control line 254 and to APT control module 230 via control line 256. Control signals provided on respective control lines 254, 256 enable operation of respective ET and APT modules 220, 230. Performance mode controller 250 also includes a mode control input node 251. Input signals received on mode control input node 251 cause VLPA operating configuration 200 to switch between various performance modes. 3A and 3B , in one performance mode, the VLPA 210 operates to have a higher load line suitable for use with the ET module 220. In another performance mode, the VLPA 210 operates to have a lower load line suitable for use with the combination of the APT control mode 230 and the DC-DC converter 240.

The ET module 220 is coupled to the voltage supply node 201 via a capacitor 223 (C ₂ ). The ET module 220 also includes an input node 221 provided for receiving the voltage envelope of the RF input signal (RF _in ) (ie, the envelope signal V _env ).

APT control module 230 is configured to control the operation of DC-DC converter 240 using at least one control signal provided on control line 235. APT control module 230 is also coupled to receive an indication of the average output power of VLPA 210 via input line 233, which is coupled to output node 214 of VLPA 210. DC-DC converter 240 is coupled to voltage supply node 201 of VLPA 210 via inductor 241 ( _L1 ). DC-DC converter 240 is provided to provide an adjustable DC voltage level to voltage supply node 201 of VLPA 210 in response to a control signal from APT control module 230. In some implementations, DC-DC converter 240 supplies the adjustable DC voltage level by switching between DC voltage levels provided to input 242.

FIG3A is a schematic diagram of a VLPA 210a according to some implementations using CMOS transistors. Identical elements in FIG2 and FIG3A include the same reference numbers. Furthermore, while certain specific features are shown, it will be apparent to those skilled in the art from this disclosure that various other features are not shown for the sake of brevity and to not obscure the understanding of the more relevant aspects of the examples disclosed herein.

In some implementations, VLPA 210a includes a driver stage 310, an interstage matching network 340, and a plurality of amplifiers, each of which is selectively connected to one of a plurality of parallel combinations using a corresponding control element. The control elements are arranged to selectively connect one or more amplifiers to one of the parallel combinations. Each control element has a corresponding input terminal for receiving a corresponding control signal.

Driver stage 310 includes first and second NMOS transistors 311 and 312, whose sources and drains are coupled between voltage supply node 201 and ground. An inductor 317 (L ₂ ) is disposed between voltage supply node 201 and the drain of second NMOS transistor 312, also labeled as node 319. The gate of second NMOS transistor 312 is coupled to receive a bias voltage (V _bias2 ) provided by a series combination of capacitor 316 (C ₃ ) and resistor 315 (R ₁ ). The gate of first NMOS transistor 311 is coupled to receive an RF input signal (RF _in ) from node 211 (see FIG. 2 ) and a bias voltage (V _bias1 ) from node 311 via resistor 313 (R ₂ ).

The output of the driver stage 310 is provided from node 319 to an interstage matching network 340. The output of the interstage matching network 340 is coupled to a common input node 341 of the plurality of amplifiers. While it will be appreciated by those skilled in the art that many amplifiers include any number of amplifiers, including two or more, for simplified purposes only, the plurality of amplifiers in FIG3A includes only a first variable stage amplifier 320 and a second variable stage amplifier 330, which are selectively operable in a parallel combination. Similarly, only two respective control elements 326, 336 are provided, associated with the first and second variable stage amplifiers 320, 330.

The first variable-stage amplifier 320 includes third and fourth NMOS transistors 321 and 322, each having its source and drain connected between the voltage supply node 201 and ground. An inductor 327 (L ₃ ) is disposed between the voltage supply node 201 and the drain of the fourth NMOS transistor 322, also labeled as a common node 329. The gate of the fourth NMOS transistor 322 is coupled to a corresponding control element 326. The gate of the third NMOS transistor 321 is coupled to receive the RF input from the interstage matching network 340 at a common input node 341 and a bias voltage (V _bias3 ) from a node 324 via a resistor 323 (R ₂ ). Similarly, the second variable-stage amplifier 330 includes fifth and sixth NMOS transistors 331 and 332, whose sources and drains are coupled between the voltage supply node 201 and ground. An inductor 327 (L ₃ ) is disposed between the voltage supply node 201 and the drain of the sixth NMOS transistor 332, which is also labeled as a common node 329. The gate of the sixth NMOS transistor 322 is coupled to a corresponding control element 336. The gate of the fifth NMOS transistor 331 is coupled to receive the RF input from the interstage matching network 340 at a common input node 341 and a bias voltage (V _bias3 ) from a node 334 via a resistor 333 (R ₂ ).

As shown in FIG3A , in some implementations, control elements 326 and 336 each comprise a respective differential amplifier. To this end, control elements 326 and 336 each comprise a respective control input 326 a and 336 a provided to receive a respective control signal (V _CTRL1 , V _CTRL2 ) from performance mode controller 250. Control elements 326 and 336 also each comprise a respective reference input 326 b and 336 b provided to receive a reference voltage level (V _ref ). In some implementations, VLPA 210 a comprises a control bus coupled to respective input terminals of a plurality of control elements (e.g., 326 and 336 ) to provide respective control signals for selecting the plurality of amplifiers.

In operation, control signals (V _CTRL1 , V _CTRL2 ) are used to activate or deactivate each of the first and second variable-stage amplifiers 320 and 330. In other words, a plurality of control elements are arranged to selectively couple one or more of the plurality of amplifiers to one of a plurality of parallel combinations, each of the plurality of control elements having a corresponding input terminal provided for receiving a corresponding control signal, and each of the plurality of control elements is responsive to the corresponding control signal. Thus, each of the plurality of amplifiers can be connected to a common output node 329 to transmit an output signal generated by selecting one or more of the plurality of amplifiers.

2 and 3A , in some implementations, the performance mode controller 250 is further configured to enable the ET module 220 to operate in a corresponding operating mode. To this end, the performance mode controller 250 provides a combination of one or more control signals to the VLPA 210 a to select one or more of the plurality of amplifiers, the plurality of amplifiers having a higher load line suitable for use with the ET module 220. Similarly, in some implementations, the performance mode controller 250 is further configured to enable the APT control module 230 to operate in a corresponding operating mode. To this end, the performance mode controller 250 provides a combination of one or more control signals to the VLPA 210 a to select one or more of the plurality of amplifiers, the plurality of amplifiers having a lower load line suitable for use with the APT control module 230.

FIG3B is a schematic diagram of a VLPA 210 b employing heterojunction bipolar transistors (HBTs) according to some implementations. Identical elements in FIG3A and FIG3B include the same reference numbers, and for the sake of brevity, only the differences are described herein. To this end, compared to the VLPA 210 a of FIG3A , the VLPA 210 b of FIG3 b includes six HBTs 411, 412, 421, 422, 431, and 433, replacing the six NMOS transistors 311, 312, 321, 322, 331, and 333 used in the VLPA 210 a of FIG3A .

As described above, in operation, control signals (VCTRL1, VCTRL2) are used to activate or deactivate each of the first and second variable-stage amplifiers 320, 330. In other words, multiple control elements are arranged to selectively connect one or more of the multiple amplifiers to one of a plurality of parallel combinations. Each of the plurality of control elements has a corresponding input terminal provided for receiving a corresponding control signal, and each of the plurality of control elements is responsive to the corresponding control signal. Consequently, each of the plurality of amplifiers can be connected to a common output node 329 to transmit an output signal generated by selecting one or more of the plurality of amplifiers.

FIG4 is a flow chart illustrating an implementation of a method 400 for operating a VLPA according to some implementations. In some implementations, the method 400 is performed by a performance management system or a controller associated with the VLPA. In summary, the method 400 includes receiving a mode selection signal and selecting a characteristic load line value appropriate for a corresponding performance mode.

To this end, as represented by block 4-1, method 400 includes receiving a mode selection signal. For example, as represented by block 4-1a, in some implementations, the mode selection signal indicates selection of an ET performance mode, in which the VLPA is adjusted to have a higher load line suitable for use with an ET module. Similarly, as represented by block 4-1b, in some implementations, the mode selection signal indicates selection of an APT performance mode, in which the VLPA is adjusted to have a lower load line suitable for use with an APT module.

As represented by block 4-2, method 400 includes generating a combination of control signals in response to receiving a mode selection signal. For example, as represented by block 4-2a, in some implementations, generating a combination of control signals includes generating one or more control signals indicating selection of a particular parallel combination of one or more amplifiers having characteristic load line values suitable for an ET performance mode. Similarly, as represented by block 4-2b, in some implementations, generating a combination of control signals includes generating one or more control signals indicating selection of a particular parallel combination of one or more amplifiers having characteristic load line values suitable for an APT performance mode.

As indicated by block 4-3, method 400 includes providing control signals to the VLPA. For example, as indicated by block 4-3a, in some implementations, providing control signals includes providing a combination of one or more control signals to a corresponding plurality of control elements to select one or more of the plurality of amplifiers. Furthermore, as indicated by block 4-3b, in some implementations, providing control signals includes providing at least one control signal to an ET module. Similarly, as indicated by block 4-3b, in some implementations, providing control signals includes providing at least one control signal to an APT module.

FIG5 is a block diagram of a VLPA system 500 according to some implementations. The VLPA system 500 shown in FIG5 is similar to, and is derived from, the VLPA operating configuration 200 shown in FIG2 . Identical elements in FIG2 and FIG5 are provided with the same reference numerals, and for the sake of brevity, only the differences between FIG2 and FIG5 are described herein. Furthermore, while certain specific features are shown, it will be apparent to those skilled in the art from this disclosure that various other features are not shown for the sake of brevity and to avoid obscuring the understanding of the more relevant aspects of the exemplary implementations disclosed herein.

To this end, VLPA system 500 includes an implementation of VLPA 210, DC-DC converter 240, and ET module 220. Furthermore, VLPA system 500 includes: one or more processing units (CPUs) 502; one or more output interfaces 503; a memory 506; a programming interface 508; and one or more communication buses 504 for interconnecting these components with various other components.

In some implementations, the communication bus 504 includes circuitry that interconnects and controls communications between system components. Memory 506 includes high-speed random access memory, such as DRAM, SRAM, DDR RAM, or other random access solid-state storage devices; and may include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. Memory 506 optionally includes one or more storage devices located remotely from the CPU(s) 502. Memory 506 includes non-transitory computer-readable storage media. In some implementations, memory 506 or its non-transitory computer-readable storage media stores subsequent programs, modules, and data instructions, or includes a subset of the optional operating system 530, performance mode controller 550, APT control module 540, and ET control module 520.

The operating system 530 includes processes for handling various basic system services and for performing hardware-related tasks.

In some implementations, the performance mode controller 550 includes an APT control submodule 551 and an ET control submodule 553 .

In some implementations, the APT control submodule 551 is configured to support an APT performance mode associated with the operation of the VLPA 210. In some implementations, the APT control submodule 551 is configured to generate one or more control signals to select one or more of the plurality of amplifiers of the VLPA 210 that, in combination, have a lower load line suitable for use with the APT control module 540. In some implementations, the APT control submodule 551 is configured to generate at least one control signal to affect the operation of the APT control module 540. For these purposes, in some implementations, the APT control submodule 551 includes a set of instructions 551a and heuristics and metadata 551b.

In some implementations, the ET control submodule 553 is configured to support an ET performance mode associated with the operation of the VLPA 210. In some implementations, the ET control submodule 553 is configured to generate one or more control signals to select one or more of the plurality of amplifiers of the VLPA 210 that, in combination, have a higher load line suitable for use with the ET control module 520. In some implementations, the ET control submodule 553 is configured to generate at least one control signal to perform the operation of the ET control module 520. To achieve these objectives, in some implementations, the ET control submodule 553 includes a set of instructions 553a and heuristics and metadata 553b.

In some implementations, the APT control module 540 is configured to control the operation of the DC-DC converter 240. To this end, in some implementations, the APT control module 540 includes a set of instructions 541a and heuristics and metadata 541b.

In some implementations, the ET control module 520 is configured to control the operation of the ET module 220. To this end, in some implementations, the ET control module 520 includes a set of instructions 521a and heuristics and metadata 521b.

FIG6 is a performance graph 600 illustrating gain compression of a VLPA according to some implementations. In some implementations, as the number of amplifiers (N) in the VLPA increases, the amplitude-to-amplitude gain increases, and the output power level at which the gain begins to decrease also decreases. FIG7 is a performance graph 700 illustrating output power performance of a variable load power amplifier according to some implementations. In some implementations, as the number of amplifiers (N) in the VLPA increases, the output power as a function of power increases. FIG8 is a performance graph 800 illustrating power added efficiency performance of a variable load power amplifier according to some implementations. In some implementations, as the number of amplifiers (N) in the VLPA increases, the overall power added efficiency is linear over a large range of output power values.

Figures 9A-9C are block diagrams of various integrated circuit implementations of the VLPA 210 of Figure 2, according to some implementations. While some typical features are shown, those skilled in the art will appreciate, based on this disclosure, that various other features are not shown for the sake of brevity and to avoid obstructing understanding of the more relevant aspects of the typical implementations disclosed herein. To this end, for example, Figure 9A illustrates that, in some implementations, some or all of the VLPA 210 can be part of a semiconductor chip 900. As an example, the VLPA 210 can be formed on a substrate 902 of the chip 900. A plurality of connectors 904 can also be formed on the substrate 902 to facilitate functionality associated with some or all of the VLPA 210.

9B shows that in some implementations, a semiconductor chip 900 having a substrate 902 can include some or all of the performance mode controller 250 and some or all of the VLPA 210. A plurality of connection pads 904 can also be formed on the substrate 902 to facilitate functionality associated with some or all of the performance mode controller 250 and some or all of the VLPA 210.

9C shows that in some implementations, a semiconductor chip 900 having a substrate 902 can include some or all of the VLPA 210, some or all of the performance mode controller 250, some or all of the APT control module 230, and some or all of the ET module 220. A plurality of connectors 904 can also be formed on the substrate 902 to facilitate functionality associated with some or all of the VLPA 210, some or all of the performance mode controller 250, some or all of the APT control module 230, and some or all of the ET module 220.

In some implementations, one or more of the features described herein can be included in a module. FIG10 is a schematic diagram of an implementation of a module including the variable load power amplifier of FIG2 and 3A-3B. Although some typical features are shown, it will be apparent to those skilled in the art, based on this disclosure, that various other features are not shown for the sake of brevity and to not obscure the understanding of the more relevant aspects of the typical implementation disclosed herein. Module 1000 includes: a package substrate 1052, a connection pad 1056, a CMOS (complementary metal oxide semiconductor) chip 900, an HBT (heterojunction bipolar transistor) chip 1010, a matching network 1008, and one or more surface mount devices 1060.

CMOS chip 900 includes a substrate 902 that includes some or all of at least one of performance mode controller 250, APT control module 230, and ET module 220. Multiple connectors 904 are formed on substrate 902 to facilitate functionality associated with some or all of at least one of performance mode controller 250, APT control module 230, and ET module 220. Similarly, HBT chip 1010 includes a substrate 1002 that includes some or all of VLPA 210 and some or all of bias circuitry 1003 for setting static conditions for VLPA 210. HBT chip 1010 also includes multiple connectors 1004 formed on substrate 1002 to facilitate functionality associated with some or all of VLPA 210 and some or all of bias circuitry 1003.

Connector pads 1056 on package substrate 1052 facilitate electrical connections to and from each of CMOS chip 900 and HBT chip 1010. For example, connector pads 1056 facilitate routing various signals and supply currents and/or voltages to CMOS chip 900 and HBT chip 1010 using wire bonds 1054.

In some implementations, components mounted on or formed on or in the package substrate 1052 can also include, for example, one or more surface mount devices (SMDs) (e.g., 1060) and one or more matching networks (e.g., 1008). In some implementations, the package substrate 1052 can include a laminate substrate.

In some implementations, module 1000 can also include one or more packaging structures to, for example, provide protection and facilitate easier handling of module 1000. Such packaging structures can include an overmold formed on packaging substrate 1052 and sized to substantially seal the various circuits and components thereon.

Although module 1000 is described in the context of wire bond-based electrical connections, it should be understood that one or more features of the present disclosure can be implemented in other packaging configurations, including flip-chip configurations.

In some implementations, a device and/or circuitry having one or more features disclosed herein can be included in an RF device, such as a wireless device. Such a device and/or circuitry can be implemented directly in the wireless device, in a modular fashion as described herein, or in some combination thereof. In some implementations, such a wireless device can include, for example, a cellular phone, a smartphone, a handheld wireless device with or without phone functionality, a wireless tablet, a wireless router, a wireless access point, a wireless base station, and the like. That is, as will be apparent to those skilled in the art from this disclosure, in various implementations, the low-frequency loss correction module can be included in various devices, such as a computer, a laptop, a tablet device, a network, a kiosk, a personal digital assistant, an optical modem, a base station, a repeater, a wireless router, a mobile phone, a smartphone, a gaming device, a computer server, or any other computing device. In various implementations, such a device includes: one or more processors; one or more memory devices; a display; and/or other user interface components, such as a keyboard, a touchscreen display, a mouse, a trackpad, a digital camera, and/or any number of auxiliary devices for increased functionality.

FIG11 is a schematic diagram of an implementation of a wireless device 1100 that, according to some implementations, includes one or more features described herein, such as the VLPA 210 of FIG2 . While some typical features are shown, those skilled in the art will appreciate from this disclosure that various other features are not shown for the sake of brevity and to not obscure the more relevant aspects of the typical implementations disclosed herein.

The one or more VLPAs 210 shown here are biased by corresponding bias circuit(s) (not shown) and compensated by corresponding compensation circuit(s) (not shown). In some implementations, the VLPAs 210 are packaged in a module that includes a matching circuit 1118. The VLPAs 210 are capable of receiving corresponding RF signals from a transceiver 1114, configuring and operating the transceiver 1114 in a known manner to generate RF signals to be amplified and transmitted, and processing received signals. The transceiver 1114 shown interacts with a baseband subsystem 1110, configuring the baseband subsystem 1110 to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver 1114. The VLPAs 210 are also shown connected to a performance mode controller 250. The performance mode controller 250 is coupled to the ET module 220 and the APT module 230.

The baseband subsystem 1110 is shown connected to the user interface 1102 to facilitate receiving various inputs of voice and/or data from the user and providing various outputs of voice and/or data to the user. The baseband subsystem 1110 can also be connected to the memory 1104 to configure the memory 1104 to store data and/or instructions to facilitate the operation of the wireless device and/or provide storage for user information.

In the exemplary wireless device 1100, the output of the VLPA 210 is shown matched to the antenna and routed to the antenna 1124 via a corresponding duplexer 1120 and a band select switch 1122. The band select switch 1122 can include, for example, a single-pole, multiple-throw (e.g., SP4T) switch to allow selection of an operating band (e.g., Band 2). In some implementations, each duplexer 1120 can allow simultaneous transmit and receive operations using a common antenna.

Many other wireless device configurations can employ one or more of the features described herein. For example, a wireless device need not be a multi-band device. In another example, a wireless device can include additional antennas such as a diversity antenna and additional connectivity features such as Wi-Fi, Bluetooth, and GPS.

Although various implementation schemes falling within the scope of the appended claims have been described above, it should be understood that the various implementation features described above can be implemented in a large number of different forms, and any specific structure and/or function described above is merely illustrative. In light of this disclosure, it should be understood by those skilled in the art that the schemes described herein can be implemented independently of any other schemes, and two or more of these schemes can be combined in various ways. For example, a device can be implemented and/or a method can be implemented using any number of schemes set forth herein. In addition, in addition to one or more schemes set forth herein, or in addition to one or more schemes set forth herein, such a device and/or such method can also be implemented using other structures and/or functions.

It should also be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, as long as all occurrences of "first power amplifier" are consistently renamed and all occurrences of "second power amplifier" are consistently named, then a first power amplifier can be referred to as a second power amplifier, and similarly, a second power amplifier can be referred to as a first power amplifier, which changes the meaning of the description. The first power amplifier and the second power amplifier are both power amplifiers, but they are not the same power amplifier.

The technical terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the claims. As used in the description of the embodiments and in the appended claims, the singular forms "a", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any one and all possible combinations of one or more listed associated items. It should also be understood that the terms "include" and/or "comprise" when used in this specification indicate the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude the presence or addition of one or more features, integers, steps, operations, elements, parts and/or groups thereof.

The term "if" as used herein may be understood, depending on the context, to mean "when" the stated precondition holds true or "after" the stated precondition holds true or "in response to determining" that the stated precondition holds true or "upon determining" that the stated precondition holds true or "in response to detecting" that the stated precondition holds true. Likewise, the phrases "if it is determined that [the stated precondition holds true]" or "if [the stated precondition holds true]" or "when [the stated precondition holds true]" may be understood, depending on the context, to mean "after determining" that the stated precondition holds true or "in response to determining" that the stated precondition holds true or "upon determining" that the stated precondition holds true or "upon detecting" that the stated precondition holds true or "in response to detecting" that the stated precondition holds true.

Claims (20)

1. A variable load power amplifier, comprising: A plurality of amplifiers, each of which can be selectively connected to one of a plurality of parallel combinations, each of which is characterized by a corresponding load line, the load line comprising at least a first load line corresponding to an envelope tracking performance mode and a second load line corresponding to an average power tracking performance mode; and A plurality of control elements are arranged to selectively connect one or more of the plurality of amplifiers to one of the plurality of parallel combinations, each of the plurality of control elements having a corresponding input terminal for receiving a corresponding control signal, each of the plurality of control elements being responsive to the corresponding control signal, and each control element comprising an envelope tracking module coupled to a voltage supply to the plurality of amplifiers and an average power tracking module coupled to a DC-DC converter. 2. The variable load power amplifier of claim 1 further includes a control bus coupled to corresponding input terminals of the plurality of control elements to provide corresponding control signals for influencing the selection of the plurality of amplifiers. 3. The variable load power amplifier of claim 1, wherein each of the plurality of amplifiers is connectable to a common input node to receive a common input signal provided for selecting one or more of the plurality of amplifiers. 4. The variable load power amplifier of claim 3 further includes interstage impedance matching, the interstage impedance matching being provided to transmit the common input signal to the common input node of the plurality of amplifiers. 5. The variable load power amplifier of claim 4, further comprising a driver stage, wherein the interstage impedance matching is coupled between the driver stage and the common input node of the plurality of amplifiers. 6. The variable load power amplifier of claim 1, wherein each of the plurality of amplifiers is connectable to a common output node to transmit an output signal generated by selecting one or more of the plurality of amplifiers. 7. The variable load power amplifier of claim 1, wherein at least one of the plurality of control elements comprises a differential amplifier, coupled to the differential amplifier to receive a corresponding control signal, and in response to receiving the corresponding control signal, causing one of the plurality of amplifiers to be connected to or disconnected from a particular parallel combination. 8. The variable load power amplifier of claim 1, wherein the first parallel combination of the plurality of parallel combinations is characterized by the implementation of the first load line and the envelope tracking module coupled between the input of the plurality of amplifiers and the voltage supply of the plurality of amplifiers. 9. The variable load power amplifier of claim 1, wherein the second parallel combination of the plurality of parallel combinations is characterized by the implementation of the second load line and the average power tracking module coupled between the common output of the plurality of amplifiers and the voltage supply of the plurality of amplifiers. 10. A variable load power amplifier module, comprising: A packaging substrate configured to accommodate a plurality of components; A variable load power amplifier, the variable load power amplifiers being arranged on the package substrate, the variable load power amplifier comprising a plurality of amplifiers, each of the plurality of amplifiers being selectively connected to one of a plurality of parallel combinations, each of the plurality of parallel combinations being characterized by a corresponding load line, the load line comprising at least a first load line corresponding to an envelope tracking performance mode and a second load line corresponding to an average power tracking performance mode; and A performance mode controller coupled to the variable load power amplifier, the performance mode controller being configured to provide one or more control signals to the variable load power amplifier and an envelope tracking module coupled to the voltage supply of the plurality of amplifiers and an average power tracking module coupled to the DC-DC converter, in order to generate a specific load line for a corresponding performance mode. 11. The variable load power amplifier module according to claim 10, further comprising: A plurality of control elements are provided to influence the selection of one or more of the plurality of amplifiers in response to receiving one or more control signals; and A control bus, which is coupled between the performance mode controller and the plurality of control elements. 12. The variable load power amplifier module of claim 10, further comprising the envelope tracking module, the envelope tracking module being coupled between the common input of the plurality of amplifiers and a common voltage supply node of the plurality of amplifiers, and the envelope tracking module being configured to provide an envelope signal to the common voltage supply node. 13. The variable load power amplifier module of claim 12, wherein the performance mode controller is coupled to the envelope tracking module and is further configured to provide a combination of one or more control signals to the variable load power amplifier to influence the selection of one or more of the plurality of amplifiers, the plurality of amplifiers being characterized in combination by the first load line corresponding to the envelope tracking performance mode. 14. The variable load power amplifier module of claim 10, further comprising the average power tracking module, the average power tracking module being coupled between the common output of the plurality of amplifiers and a common voltage supply node of the plurality of amplifiers, and the average power tracking module being configured to adjust the DC voltage level on the common voltage supply node. 15. The variable load power amplifier module of claim 14, wherein the performance mode controller is coupled to the average power tracking module and is further configured to provide a combination of one or more control signals to the variable load power amplifier to influence the selection of one or more of the plurality of amplifiers, the plurality of amplifiers being characterized in combination by the second load line corresponding to the average power tracking performance mode. 16. The variable load power amplifier module according to claim 10, wherein: Each of the plurality of amplifiers can be connected to a common input node to receive a common input signal for selecting one or more of the plurality of amplifiers; and Each of the plurality of amplifiers can be connected to a common output node to transmit an output signal generated by selecting one or more of the plurality of amplifiers. 17. A radio frequency device, comprising: A transceiver configured to process radio frequency signals; An antenna that communicates with the transceiver and is configured to facilitate the transmission of amplified radio frequency signals; and A variable load power amplifier module, connected to the transceiver and configured to generate the amplified radio frequency signal, comprises a plurality of amplifiers, each selectively connectable to one of a plurality of parallel combinations, each of the parallel combinations being characterized by a corresponding load line, the load line comprising at least a first load line corresponding to an envelope tracking performance mode and a second load line corresponding to an average power tracking performance mode; and A plurality of control elements are arranged to selectively connect one or more of the plurality of amplifiers to one of the plurality of parallel combinations, each of the plurality of control elements having a corresponding input terminal for receiving a corresponding control signal, each of the plurality of control elements being responsive to the corresponding control signal, and each control element comprising an envelope tracking module coupled to a voltage supply to the plurality of amplifiers and an average power tracking module coupled to a DC-DC converter. 18. The radio frequency device of claim 17, further comprising a performance mode controller coupled to the variable load power amplifier module, the performance mode controller being configured to provide control signals to the variable load power amplifier module to generate a specific load line for a corresponding performance mode. 19. The radio frequency device of claim 18, wherein the performance mode controller is further configured to support: The envelope tracking module is in a first operating mode and provides a combination of control signals to the variable load power amplifier module to influence the selection of one or more of the plurality of amplifiers, which are characterized by a first load line corresponding to the first operating mode; and The average power tracking module is in a second operating mode and provides a combination of control signals to the variable load power amplifier module to influence the selection of one or more of the plurality of amplifiers, which are characterized by a second load line corresponding to the second operating mode. 20. The radio frequency device according to claim 17, wherein: Each of the plurality of amplifiers can be connected to a common input node to receive a common input signal for selecting one or more of the plurality of amplifiers; and/or Each of the plurality of amplifiers can be connected to a common output node to transmit an output signal generated by selecting one or more of the plurality of amplifiers.