HK1210874B - Semiconductor device - Google Patents

Description

semiconductor devices

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2014-012155 filed on January 27, 2014 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

Technical Field

The present invention relates to a technology for a semiconductor device, and relates to a technology effectively used in, for example, a semiconductor device including a semiconductor chip mounted on a wiring substrate having a plurality of stacked wiring layers.

Background Art

Signal transmission paths, which electrically couple circuits formed on a semiconductor chip with external devices, are formed on a wiring substrate on which the semiconductor chip is mounted. To mitigate any impedance discontinuities formed in these signal circuit paths, discontinuity cancellation technology is used to eliminate these discontinuities by utilizing the inverse impedance discontinuity.

For example, Japanese Unexamined Patent Application Publication No. 2004-253947 (Patent Document 1) discloses a technology in which a third planar circuit having a higher characteristic impedance than a first planar circuit and a fourth planar circuit having a higher characteristic impedance than a second planar circuit are coupled in series between the first planar circuit and the second planar circuit having a higher characteristic impedance than the first planar circuit.

Furthermore, for example, Non-Patent Document 1 discloses a technique for matching the average impedance to 50 ohms by surrounding the front and rear ends of a low-impedance portion composed of a through via and a solder ball pad with a high-impedance line.

For example, non-patent document 2 discloses a technology that matches the average impedance in a signal transmission path including a low-impedance portion consisting of a through via and a solder ball pad to 50 ohm impedance by combining a small via and a wiring pattern with the aid of a conductor layer formed in an inductor structure.

[Non-Patent Document 1]

Nanju Na, Mark Bailey and Asad Kalantarian, "Package PerformanceImprovement with Counter-Discontinuity and its Effective Bandwidth", Proceedings of 16th Topical meeting on Electrical Performance of ElectronicPackaging, p.163to p.166(2007)

[Non-Patent Document 2]

Namhoon Kim, Hongsik Ahn, Chris Wyland, Ray Anderson, Paul Wu, "Spiral ViaStructure in a BGA Package to Mitigate Discontinuities in Multi-GigabitSERDES System", Proceedings of 60th Electronic Components and Technology Conference, p.1474to p.1478(2010)

Summary of the Invention

However, when applying an inverse impedance discontinuity in the opposite direction along the transmission path to cancel the impedance discontinuity, the signal frequency increases, and in some cases, when the impedance cannot be canceled, this state may act as a double impedance discontinuity. In other words, along the signal transmission path of high-frequency signals, the signal is reflected at the interface of the impedance discontinuity, i.e., at approximately twice the impedance discontinuity. Therefore, a countermeasure is needed to bring the impedance discontinuity closer to the specified impedance (e.g., 50 ohms).

When an opening is formed on the conductor pattern of the separation layer to cover the portion where the impedance discontinuity occurs in order to offset the capacitive impedance discontinuity, since the return path (return current path) of the corresponding signal transmission path and the signal transmission path are separated from each other at a local point, inductive crosstalk noise tends to occur more easily in that portion.

Other novel features and concepts will become more apparent from the accompanying drawings and description in this specification.

According to one aspect of the present invention, a wiring substrate in a semiconductor device includes: a first wiring layer forming first wiring for transmitting signals; and a second wiring layer mounted adjacent to an upper or lower layer of the first wiring layer. Furthermore, a first conductor plate having a first opening formed at a position overlapping a portion of the first wiring layer in the thickness direction, and a first conductor pattern positioned within the first opening of the first conductor plate are formed on the second wiring layer. The first conductor pattern includes a mesh pattern portion isolated from the first conductor plate, and a plurality of coupling portions connecting the mesh pattern portion and the conductor plate.

According to this aspect of the present invention, the noise immunity of the semiconductor device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a perspective view of a semiconductor device of this embodiment;

FIG2 is a bottom view of the semiconductor device shown in FIG1 ;

3 is a perspective plan view showing the internal structure of the semiconductor device on the wiring substrate with the heat sink removed;

FIG4 is a cross-sectional view taken along line A-A of FIG1;

FIG5 is an enlarged cross-sectional view showing an example of a stripline wiring structure;

6 is an enlarged cross-sectional view showing an example of a wiring structure of a microstrip line;

7 is an enlarged plan view showing an example of a planar shape of a conductor pattern serving as an electromagnetic wave absorber;

FIG8 is an enlarged cross-sectional view taken along the wiring extending direction indicated by the dotted line in FIG7;

FIG9 is an enlarged cross-sectional view at a different position from FIG8;

FIG10 is an enlarged perspective view showing a basic structure of a conductor pattern of the enlarged view in FIG9;

FIG11 is an enlarged sectional view showing a modification example corresponding to FIG9;

FIG12 is an enlarged plan view showing a modification corresponding to FIG7;

FIG13 is an enlarged plan view showing another modification corresponding to FIG7;

FIG14 is an enlarged perspective view showing the periphery of the conductor pattern of FIG13;

15 is a diagram for explaining the assembly process flow of the semiconductor device shown in FIG. 1 to FIG. 4;

16 is a diagram for illustrating a manufacturing process for forming a conductor pattern serving as an electromagnetic wave absorber on a wiring substrate in the substrate preparation process of FIG. 15 ;

FIG17 is an enlarged plan view showing a modification corresponding to FIG7;

FIG18 is an enlarged plan view showing another modification corresponding to FIG7;

FIG19 is an enlarged plan view showing another modification corresponding to FIG7;

FIG. 20 is an enlarged plan view showing another modification example corresponding to FIG. 7 .

DETAILED DESCRIPTION

(Description of the format, basic terms and usage in these instructions)

In this specification, the description of the embodiments is divided into multiple parts as needed for convenience. However, unless otherwise specified, these are not separate units, and regardless of whether the overall description is a single example of a part, a detailed fragment of another part, or a modified example of a part or the entire part, etc., repeated descriptions of the same parts are omitted as a convention. Furthermore, unless otherwise specified, among the constituent elements of these embodiments, the constituent elements are not required except when logically limited to the described amount and except when the context clearly indicates otherwise.

Furthermore, when describing materials and components, such as "X includes A," unless otherwise specifically stated or clearly indicated from the context of the embodiment description, the description does not exclude elements other than A. For example, among components, the description may mean "X includes A as a main component," etc. Even in terms such as "silicon component," the component is not limited to silicon and may be, of course, a SiGe (silicon and germanium) alloy or other multi-element alloy using Si as a main component, or a component including other added elements. Furthermore, in gold plating, copper (Cu) layers, nickel plating, etc., unless otherwise specified or unless otherwise specifically stated, the component is not just a simple element and may also include gold, copper (Cu), nickel, or other elements as main components.

Furthermore, even in the case of specified values or quantities, the values may exceed the specified values and may also be values below the specified values except when logically limited to the specified quantities or except when the context clearly indicates otherwise.

In these descriptions, the terms planar surface and side surface are used. The semiconductor element forming surface of the semiconductor chip is used as a reference surface, and a horizontal plane parallel to the reference surface is described as a planar surface. In addition, a surface intersecting with the planar surface is described as a side surface. The direction connecting two planar surfaces positioned so as to be separated from each other when viewed from the side surface is described as a thickness direction.

The terms upper surface and lower surface are also used in this specification. However, there are various semiconductor package mounting conditions, so after the semiconductor package is mounted, the upper surface may be positioned below the lower surface in some cases. In this specification, the planar surface on the semiconductor element forming surface side of a semiconductor chip, or the planar surface on the chip mounting surface side of a wiring substrate, is described as the upper surface, and the surface opposite the upper surface is described as the lower surface.

In each drawing of the embodiments, the same or similar parts are shown by the same or similar numerals or reference numerals, and the description is generally not repeated.

In the drawings, hatching may be omitted even in cross-sections if the drawings are complex or if gaps can be clearly identified. Regarding this, the outline of the background may be omitted even for horizontally closed holes if this is clarified by the description. Furthermore, hatching or dot patterns may be added to clearly indicate the absence of gaps or to clearly indicate the boundaries of regions even when the drawings are not cross-sections.

(Example)

FIG1 is a perspective view of a semiconductor device of the present embodiment. FIG2 is a bottom view of the semiconductor device shown in FIG1 . FIG3 is a perspective plan view showing the internal structure of the semiconductor device on a wiring substrate in a state where a heat sink is removed. FIG4 is a cross-sectional view taken along line A-A of FIG1 . In FIG1 to FIG4 , the number of terminals is reduced to improve visual understanding. In FIG4 , the number of solder balls 4 is reduced more than the number of solder balls in the example shown in FIG2 for better visual understanding. Although omitted from the figure, the number of terminals (joining pad 2PD, welding area 2LD, solder ball 4) can match various modifications different from the states shown in FIG1 to FIG4 .

<Semiconductor devices>

The overall structure of a semiconductor device 1 of the present embodiment will first be described with reference to Figures 1 to 4. The semiconductor device 1 of the present embodiment includes a wiring substrate 2 and a semiconductor chip 3 mounted on the wiring substrate 2 (see Figure 4).

The wiring substrate 2 shown in Figure 4 includes: an upper surface (surface, main surface, first surface, chip mounting surface) 2a on which the semiconductor chip 3 is mounted, a lower surface (surface, main surface, second surface, mounting surface) 2b on the side opposite to the upper surface 2a, and a plurality of side surfaces 2s placed between the upper surface 2a and the lower surface 2b, and when viewed from the plan view shown in Figures 2 and 3, the external shape is formed into a square (refer to Figures 1 to 3).

The wiring substrate 2 is an interposer (relay substrate) for electrically coupling the semiconductor chip 3 mounted on the upper substrate 2a side and the mounting substrate (not shown in the figure); and includes a plurality of wiring layers (six layers in the example shown in FIG4 ) that electrically couple the lower surface 2b side serving as the mounting surface and the upper surface 2a side serving as the chip mounting surface. For example, the wiring substrate 2 is formed by stacking multiple layers on the upper surface 2Ca and lower surface 2Cb of an insulating layer (core layer, core material, core insulating layer) 2CR comprising a prepreg material in which resin is impregnated with glass fiber, using a build-up technique for each of the plurality of wiring layers. The wiring layer on the upper surface 2Ca side of the insulating layer 2CR and the wiring layer on the lower surface 2Cb side are electrically coupled via a plurality of through-hole wirings 2TW embedded in a plurality of through-holes formed so as to penetrate from one side of the upper surface 2Ca and the lower surface 2Cb to the other.

FIG4 shows a wiring substrate 2 including an insulating layer 2CR as a core layer as an example of a wiring substrate. However, compared to the modified example shown in FIG4 , a coreless substrate is not included. In other words, through-hole wiring 2TW is used. In this case, the wiring layer on the lower layer 2b side and the wiring layer on the upper layer 2a side are electrically coupled via a plurality of via wirings 2V for contacting the respective wiring layers.

A plurality of bonding pads (terminals, semiconductor chip coupling terminals) 2PD are formed on the upper surface 2a of the wiring substrate 2 for electrically coupling to the semiconductor chip 3. A plurality of lands (terminals, external terminals, external electrodes) 2LD serving as external input/output terminals of the semiconductor device 1 are formed on the lower surface 2b of the wiring substrate 2. The plurality of bonding pads 2PD and the plurality of lands 2LD are each electrically coupled through a plurality of via wirings 2V serving as interlayer conduction paths and a plurality of wirings 2d formed in the wiring substrate 2. In the example shown in FIG4 , an insulating layer 2CR serving as a core layer is included on the wiring substrate 2. Therefore, the upper surface 2Ca side and the lower surface 2Cb side of the insulating layer 2CR are coupled by through-hole wiring 2TW, which is a conductor (for example, a metal such as copper) embedded in a through-hole formed to pass from one side of the upper surface 2Ca and the lower surface 2Cb of the insulating layer 2CR to the other side. The structure of each wiring layer of the wiring substrate 2 will be described in detail later.

In the example of FIG. 4 , solder balls (solder material, terminals, external terminals, electrodes, external electrodes) 4 are coupled to corresponding plurality of lands 2LD. Solder 4 is a conductive material used to electrically couple a plurality of terminals on the mounting board (omitted in the figure) to the plurality of lands 2LD during mounting of the semiconductor device 1 on a mounting board (not shown). For example, solder balls 4 are solder materials, such as Sn-Pb solder materials containing lead (Pb) or substantially free of lead, or lead-free solder. Examples of lead-free solders include tin (Sn), tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), and lead-copper (Sn-Cu). The term "lead-free solder" herein refers to a lead (Pb) content of 0.1% by weight per unit volume, and this content is determined to meet the RoHS (Restriction of Hazardous Substances) standard.

As shown in FIG2 , a plurality of solder balls 4 are placed in a matrix shape (array shape, matrix shape). Although omitted in the drawing of FIG2 , a plurality of welding areas 2LD (refer to FIG4 ) in which the plurality of solder balls 4 are bonded are also arranged in a matrix shape. A semiconductor device in which a plurality of external terminals (solder balls 4, welding areas 2LD) are placed in a matrix shape on the mounting surface side of the wiring substrate 2 is called an area array type semiconductor device. The area array type semiconductor device can effectively utilize the mounting surface side (lower surface 2b) of the wiring substrate 2 as a space for placing external terminals, and is therefore preferred in that the mounting surface area of the semiconductor device can be prevented from increasing even if the number of external terminals increases. In other words, a semiconductor device with an increased number of external terminals according to high functionality and high integration can be installed in a space-saving manner.

In the examples shown in Figures 1, 2, and 4, a so-called BGA (Ball Grid Array) type semiconductor package using solder balls 4 as external terminals is shown as an example. However, there are also various variations in the structure and layout of the external terminals. For example, on the lower surface 2b shown in Figure 4, variations include a structure in which multiple solder lands 2LD are exposed, or a structure in which a thin solder material is bonded to the multiple solder lands 2LD exposed on the lower surface 2b. Semiconductor packages with these types of variations are called LGAs (Land Grid Arrays).

The semiconductor device 1 includes a semiconductor chip 3 mounted on a wiring substrate 2. As shown in FIG4, each semiconductor chip 3 includes a surface (main surface, upper surface) 3a, a back surface (main surface, lower surface) 3b on the opposite side of the surface 3a, and a side surface 3s located between the surface 3a and the back surface 3b. The semiconductor chip 3 shown in FIG3 has a square shape, and when viewed from a plan view, its surface area is smaller than the surface area of the wiring substrate 2. In the example shown in FIG3, each of the four side surfaces 3s of the semiconductor chip 3 is mounted in the central portion of the upper surface 2 of the wiring substrate 2 so as to extend along each of the corresponding four side surfaces 2s of the wiring substrate 2.

A plurality of pads (bonding pads) 3PD are formed on the surface 3a of the semiconductor chip 3, as shown in Figure 4. In this embodiment, the plurality of pads 3PD are arranged in a matrix shape (matrix shape, array shape) on the surface 3a of the semiconductor chip 3. It is preferable to position the plurality of pads 3PD used as electrodes of the semiconductor chip 3 in a matrix shape because the surface 3a of the semiconductor chip 3 can be effectively used as a space for positioning the electrodes, so that even if the number of electrodes of the semiconductor chip 3 increases, the surface area can be prevented from increasing. Although not shown in the figure, a modification of this embodiment can be applied to a semiconductor chip type in which a plurality of pads are formed on the periphery of the surface 3a.

4, the semiconductor chip 3 is mounted on the wiring substrate 2 in a state where the surface 3a faces the upper surface 2a of the wiring substrate 2. This type of mounting method is called a face-down method or a flip-chip method.

Although not shown in the figure, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip 3 (more specifically, formed in a semiconductor element formation region on the element formation surface of the semiconductor substrate serving as the base material of the semiconductor chip 3). The plurality of pads 3PD are electrically coupled to the plurality of semiconductor elements (more specifically, between the semiconductor element formation region and the surface 3a, not shown in the figure) via wiring (omitted in the figure) formed on an internally disposed wiring layer in the semiconductor chip 3.

For example, the semiconductor chip 3 (more specifically, the base material of the semiconductor chip 3) includes silicon (Si). In addition, an insulating film is formed on the surface 3a to cover the wiring and the base material of the semiconductor chip 3. The respective surfaces of the plurality of pads 3PD are exposed from the insulating film through openings formed in the insulating film. The plurality of pads 3PD each include metal, and in this embodiment, include aluminum (Al), for example.

As shown in FIG4 , the plurality of pads 3PD of the semiconductor chip 3, each coupled with a protruding electrode 3BP, and the plurality of pads 3PD of the semiconductor chip 3 are electrically coupled to the plurality of bonding pads 2PD of the wiring substrate 2 via the plurality of protruding electrodes 3BP. The protruding electrodes 3BP are metal components formed to protrude from the surface 3a of the semiconductor chip 3. In this embodiment, the protruding electrodes 3BP are so-called solder bumps, in which a solder material is stacked on the pads 3PD via an underlying metal film (underbump metal). For example, the underlying metal film can be a laminated film in which, for example, titanium (Ti), copper (Cu), nickel (Ni) (in some cases, a gold (Au) film, if further formed on the nickel film) is stacked in multiple layers from the side coupled to the pads 3PD. The solder material comprising the solder bumps can be, for example, a lead-containing solder material or a lead-free solder similar to the solder balls 4 described above. When the semiconductor chip 3 is mounted on the wiring substrate 2, solder bumps may be pre-formed between the plurality of pads 3PD and the plurality of bonding pads 2PD, and a heat treatment (reflow soldering) performed while the solder bumps are in contact with each other forms the protruding electrodes 3BP by integrating the solder bumps. In a modified example of this embodiment, a columnar bump including a solder film on the leading edge of a conductive pillar including copper (Cu) and nickel (Ni) may be used as the protruding electrode 3BP.

As shown in FIG4 , an underfill resin (insulating resin) 5 is deposited between the wiring substrate 2 and the semiconductor chip 3. The underfill resin 5 is deposited to block the space between the substrate 3 a of the semiconductor chip 3 and the upper surface 2 a of the wiring substrate 2. The underfill resin 5 comprises an insulating (non-conductive) material (such as a resin material) and is deposited to seal the electrical coupling portion (the junction of the plurality of protruding electrodes 3BP) between the wiring substrate 2 and the semiconductor chip 3. By depositing the underfill resin 5 in this manner so as to seal the coupling portion of the plurality of protruding electrodes 3BP, it is possible to alleviate strain occurring in the electrical coupling portion between the semiconductor chip 3 and the wiring substrate 2.

<Wiring Structure of Signal Transmission Path>

Next, the wiring structure of the signal transmission path in wiring substrate 2 shown in Figures 1 to 4 will be described. Figure 5 is an enlarged cross-sectional view showing an example of a stripline wiring structure. Figure 6 is an enlarged cross-sectional view showing an example of a microstrip wiring structure. Figure 7 is an enlarged plan view showing an example of the planar shape of a conductor pattern serving as an electromagnetic wave absorber. Figure 8 is an enlarged cross-sectional view taken along the wiring extension direction indicated by the dotted line in Figure 7.

In Figure 7, even in the plan view, hatching is applied to the conductor plane 2PL, and a dot pattern is applied to the main pattern portion MPm of the conductor pattern MP1, so that each structural portion of the electromagnetic wave absorber can be easily distinguished from the conductor plane 2PL surrounding the electromagnetic wave absorber. Furthermore, in Figure 7, to clearly illustrate the planar positional relationship between the electromagnetic wave absorber and the wiring 2d formed in a separate wiring layer from the electromagnetic wave absorber, an example of the layout of the wiring 2d configuring the signal transmission path is shown by dashed lines. Furthermore, in Figure 8, the solder balls 4 shown in Figure 4 are omitted to make the drawing easier to view and understand.

The plurality of transmission paths in the wiring substrate 2 of the present embodiment include, for example, a transmission path (high-speed transmission path) for transmitting signals at a transmission speed of, for example, about 10 Gbps (gigabits per second) to 25 Gbps. In order to achieve a high transmission speed along this type of signal transmission path, in view of the need for better anti-interference performance along the signal transmission path, it is preferable to suppress the expansion of the electric field and the expansion of the electromagnetic field around the signal transmission path. In other words, suppressing the scattering of electromagnetic waves generated in the signal transmission path can improve the anti-interference performance of the signal transmission path.

A wiring structure that suppresses the expansion of the electric field or magnetic field around the signal transmission path is a technology as shown in Figures 5 and 6, which forms a conductor plane (conductor plate) 2PL formed as a plate-shaped metal film to overlap with the wiring 2d used as the signal transmission path in the thickness direction, and provides a standard potential to the conductor plane 2PL, such as a ground potential.

In the example wiring structure shown in Figure 5, conductor planes 2PL, serving as plate-shaped metal films, are formed in both the upper and lower wiring layers of wiring 2d. In other words, when viewed from the side, wiring 2d is enclosed between conductor planes 2PL formed in the upper and lower wiring layers. Furthermore, conductor planes 2PL are formed in the same wiring layer as wiring 2d to isolate it from the wiring 2d, and the area surrounding wiring 2d is surrounded by conductor planes 2PL. The wiring structure shown in Figure 5 is referred to as a stripline.

On the other hand, in the example wiring structure shown in Figure 6, conductor plane 2PL is placed in a lower layer of the wiring layer used for wiring 2d. Furthermore, conductor plane 2PL is formed in the same wiring layer as wiring 2d to isolate it from wiring 2d, and the periphery of wiring 2d is surrounded by conductor plane 2PL. However, in the wiring structure shown in Figure 6, wiring 2d is formed in the uppermost layer of the wiring layer, so conductor plane 2PL is not formed on the upper layer of wiring 2d. The wiring structure shown in Figure 6 is called a microstrip line.

In the case of the microstrip line shown in Figure 6, conductor plane 2PL is formed below wiring 2d, overlapping with wiring 2d in the thickness direction. Therefore, electric and electromagnetic fields are less likely to expand below wiring 2d. Furthermore, conductor plane 2PL is formed to isolate wiring 2d, which is located in the same wiring layer as wiring 2d, and the periphery of wiring 2d is surrounded by conductor plane 2PL. Therefore, when viewed from a plan view, electric and electromagnetic fields are unlikely to expand circumferentially around wiring 2d. However, without conductor plane 2PL formed upward from wiring 2d, electric and electromagnetic fields are more likely to expand upward from wiring 2d than downward from wiring 2d. Consequently, compared to the microstrip line shown in Figure 5, it is more susceptible to the dispersion effects of electromagnetic waves or the effects of noise propagation from other nearby wiring.

Therefore, in a path where signals propagate at high speed, the stripline wiring structure shown in FIG5 is superior to the microstrip wiring structure shown in FIG6.

However, in the wiring substrate 2 shown in FIG4 , multiple stacked wiring layers are electrically coupled, and the upper surface 2a side and the lower surface 2b side are electrically coupled. Therefore, it is difficult to apply a stripline structure to all parts of the transmission path, and the transmission path also includes portions where the wiring structure is subject to fluctuations. An example of a portion of the wiring structure subject to fluctuations is the portion of the via wiring 2V that electrically couples between adjacent wiring layers. The portion coupling the solder pad 2LD with the wiring 2d that is part of the signal transmission path, and the portion coupling the through-hole solder pad 2TL with the wiring 2d, are particularly prone to generating large signal reflections in the coupling portion for the via wiring 2V. Therefore, scattering (or dispersion) of electromagnetic waves caused by signal reflections is likely to occur.

Another example of fluctuations in the wiring structure can be found, for example, in a portion where the structure changes from a stripline to a microstrip line or in a portion where the structure changes from a microstrip line to a stripline.

Electromagnetic waves traveling along a transmission path are prone to scattering at locations where the wiring structure changes. When some of these scattered electromagnetic waves return in the direction from which they originally came (or, in other words, when signal reflection occurs), the locations along the transmission path where the wiring structure changes are observed as impedance discontinuities. Therefore, technologies are needed to compensate for these impedance discontinuities in order to improve the reliability of semiconductor devices that incorporate signal transmission paths for transmitting electrical signals at high speeds.

As described above, there is a method of adding an anti-impedance discontinuity in the opposite direction to cancel out the portion with impedance discontinuity. However, when using this method, when the frequency of the signal becomes higher, the impedance cannot be canceled out, and in some cases, the effect of two impedance discontinuities is revealed.

To counteract capacitive impedance discontinuities, another method involves forming an opening in another layer of conductor pattern (conductor plane 2PL) that covers the portion where the impedance discontinuity occurs to suppress capacitive coupling. However, with this method, the distance between the signal transmission path and the return path (return current path) corresponding to the signal transmission path is partially isolated, making the target area susceptible to inductive crosstalk noise.

Therefore, the present inventors conducted research on high-speed transmission path technologies that effectively disable impedance discontinuities. The present inventors noted the following relationship between impedance discontinuities and signal reflections. Specifically, rather than signal reflections occurring due to impedance discontinuities, the present inventors discovered that a portion of the scattered electromagnetic waves, returning in the direction from which they originally came, is observed as an impedance discontinuity. In light of this, the present inventors noted that if the scattered electromagnetic waves could be eliminated, the impedance discontinuity could be disabled regardless of its sign (capacitance or inductance).

In this embodiment, an electromagnetic wave absorber capable of eliminating scattered electromagnetic waves by converting them into heat is installed in a portion where impedance discontinuity is observed, or in other words, at a position overlapping a portion where the wiring structure changes in the thickness direction along the signal transmission path. The electromagnetic wave absorber includes a metal conductor or the like.

In the examples shown in Figures 7 and 8, when viewed from above, a conductor pattern (metal pattern) MP1, which serves as an electromagnetic wave absorber, is formed within an opening PLh formed in a conductor plane 2PL. For example, the conductor plane 2PL is a ground plane (a conductor plate for supplying a standard potential) to which a standard potential is supplied. The opening PLh shown in Figure 8 is formed to extend through the thickness of the conductor plane 2PL. Furthermore, the conductor pattern MP1 includes a main pattern portion (mesh pattern portion) MPm isolated from the conductor plane 2PL and a plurality of coupling portions MPj that connect the main pattern portion MPm and the conductor plane 2PL. The main pattern portion MPm and the coupling portions MPj are each formed from the same metal material as the planar conductor 2PL (for example, primarily copper).

When a signal is transmitted (a signal current flows) in wiring 2d, which is part of the signal transmission path, electromagnetic waves are scattered toward the periphery of wiring 2d. When electromagnetic waves generated along the signal transmission path on the main pattern portion MPm of the conductor pattern MP1 arrive, current flows in the main pattern portion MPm. If the frequency band of the signal transmission path, or in other words, the frequency band used by the signal transmission path, is a high-frequency wave, the skin effect causes high conduction resistance in the main pattern portion MPm. As a result, electrical energy is converted into heat energy and at least a portion of the electromagnetic wave is eliminated. In other words, the conductor pattern MP1 acts as an electromagnetic wave absorber, which eliminates at least a portion of the electromagnetic wave through Joule conversion.

On the other hand, when electromagnetic waves flow through a current, even if separated from the main pattern portion MPm shown in FIG7 , a portion of the electromagnetic waves can be eliminated by, for example, using a conductor pattern formed in a planar circular shape (not shown) rather than a grid-like pattern of multiple openings MPh. However, when converting electromagnetic wave energy into heat energy, a large surface area of the main pattern portion MPm is preferred from the perspective of improving efficiency. Therefore, the main pattern portion MPm of the conductor pattern MP1 of this embodiment preferably has a grid pattern with multiple openings MPh at systematic intervals.

If only the function as an electromagnetic wave absorber is considered, as with the conductor pattern MP1, there is no need to couple the conductor plane 2PL and the main pattern portion MPm. However, as will be described later, in this regard, a portion of the electromagnetic wave absorber can be utilized as a return path for the signal transmission path. Therefore, the conductor plane 2PL and the main pattern portion MPm are electrically coupled via the coupling portion MPj. Furthermore, if the conductor plane 2PL and the main pattern portion MPm are electrically coupled, the voltage potential of the conductor pattern MP1, which functions as an electromagnetic wave absorber, is stabilized at the same potential as that of the conductor plane 2PL (e.g., ground potential).

The electromagnetic wave absorber here is formed to suppress the scattering of electromagnetic waves along the signal transmission path and is therefore located at a position overlapping with the portion of wiring 2d that forms the signal transmission path in the thickness direction, as shown in Figure 8. The conductor plane 2PL is a ground plane that supplies a standard potential (e.g., ground potential) as described above and is a portion of the return path corresponding to the signal transmission path. As shown in Figure 7, the electromagnetic wave absorber is formed within the opening PLh of the conductor plane 2PL, so that if the conductor plane 2PL is not electrically coupled to the electromagnetic wave absorber, the return path corresponding to the signal transmission path can bypass the perimeter of the opening PLh. In other words, the separation distance between the signal transmission path and the return path becomes wider in certain sections.

From the perspective of reducing crosstalk noise between multiple signal transmission paths, it is preferable to reduce and also set a fixed spacing distance between the signal transmission path and the return path. However, as described above, when the return path detours along the perimeter of the opening PLh formed in the conductor plane 2PL, the spacing distance between the signal transmission path and the return path becomes larger in certain sections. Therefore, the influence of crosstalk noise is easily caused by points with large spacing distances. Again, if the electromagnetic wave absorber and the conductor plane 2PL are not coupled to each other, crosstalk noise immunity is reduced in certain sections. Therefore, the inventors further investigated the technology of using a portion of the electromagnetic wave absorber as a return path and discovered the structure of the present embodiment.

In this embodiment, as shown in Figures 7 and 8, the conductor pattern MP1, which functions as an electromagnetic wave absorber, is electrically coupled to the conductor plane 2PL, which functions as a ground plane and serves as a return path for the signal transmission path. In this manner, a portion of the conductor pattern MP1, which functions as an electromagnetic wave absorber, can be utilized as a return path for the signal transmission path.

As shown in FIG7 , the main pattern portion MPm for the conductor pattern MP1 is formed into a grid pattern with a plurality of periodically positioned openings MPh therein. Each opening MPh is a through-hole that penetrates the metal film forming the conductor pattern MP1 in the thickness direction. In the example shown in FIG7 , the through-holes are arranged in a grid pattern. The grid pattern is formed in the planar shape of the main pattern portion MPm, thereby forming a return path along the grid pattern. Therefore, regardless of the layout of the wiring 2d formed at a position overlapping the conductor pattern MP1 in the thickness direction, a return path can be formed along the direction in which the wiring 2d extends.

Furthermore, in this embodiment, multiple coupling portions MPj are formed to connect the conductor plane 2PL and the main pattern portion MPm. Therefore, when viewed from a plan view, if any or all of the multiple coupling portions MPj are formed near the wiring 2d, the wiring 2d can be formed along the coupling portion MPj. In the example shown in FIG7 , when viewed from a plan view, one of the multiple coupling portions MPj of the conductor pattern MP1 overlaps with the wiring 2d in the thickness direction. In this plan view, the coupling portion MPj positioned closest to the wiring 2d then forms a return path corresponding to the signal transmission path. In the example shown in FIG7 , one of the multiple coupling portions MPj overlaps with the wiring 2d, causing it to form a return path.

In other words, this embodiment can suppress electromagnetic wave scattering in the portion where impedance discontinuity is observed by the electromagnetic wave absorber. By utilizing a portion of the electromagnetic wave absorber as a return path, it can also prevent the signal transmission path and the return path from being isolated from each other at certain points. Furthermore, if the electromagnetic wave absorber can be utilized as a return path, there are no restrictions on the wiring layout in which the electromagnetic wave absorber is formed, allowing many electromagnetic wave absorbers to be formed in the wiring substrate 2. Consequently, the noise immunity of the semiconductor device 1 shown in FIG4 can be improved.

The following considerations can be made from the perspective of improving the degree of freedom in wiring layout design in this embodiment. Specifically, in this embodiment, the conductor pattern MP1, which includes a main pattern portion MPm forming a planar mesh pattern, is positioned so as to overlap a portion of the wiring 2d in the thickness direction and is electrically coupled to the conductor plane 2PL. Consequently, regardless of the layout of the wiring 2d, a return path can be formed along the direction in which the wiring 2d extends, thereby increasing the degree of freedom in designing (or routing) the wiring 2d.

Terminology: A return path is formed along the direction in which the wiring 2d (ie, the signal transmission path) extends, and also includes the case where the wiring 2d and the overall return path overlap at a position overlapping with the opening PLh in the thickness direction, and also includes the following case.

In the examples shown in Figures 7 and 8, the planar shape of the wiring 2d within the opening PLh does not completely match the mesh pattern (grid pattern) of the main pattern portion MPm of the conductor pattern MP1, and there is a portion where the opening MPh and the wiring 2d overlap. In other words, when viewed from a plan view, there is a portion where the position of the wiring 2d deviates from the position of the conductor pattern MP1 forming the return path.

However, since the main pattern portion MPm is a mesh pattern, the return path is formed along the mesh pattern. Therefore, if the diameter of each opening MPh in the mesh pattern can be made smaller, the deviation between the return path and the wiring 2d can be reduced. The inventors have evaluated that the deviation (or offset) between the return path and the wiring 2d (signal transmission path) depends on the required return loss characteristics and is preferably 50μm or less.

The planar shape of the opening MPh shown in the example of FIG7 is a quadrilateral; and the length of one side of the opening MPh is, for example, a square of about 30 μm to 200 μm. There are many variations of the size and planar shape of the opening MPh. The shape of the opening MPh can be, for example, circular, square, or even polygonal. The planar shape of the opening MPh can be a shape other than a regular polygon or a regular (perfect) circle (for example, an elliptical or rectangular shape, etc.). However, as the operating frequency becomes higher, the size of the hole must be reduced.

In the example shown in FIG7 , when viewed from a plan view, one of the plurality of coupling portions MPj on the conductor pattern MP1 overlaps with the wiring 2d in the thickness direction. However, as described above, even if there is a deviation between the position of the wiring 2d and the position of the conductor pattern MP1 serving as the return path (e.g., coupling portion MDj) when viewed from a plan view, crosstalk noise can be reduced if the deviation (or offset) is small.

In this embodiment, even when using the optional layout design of the wiring 2d, the amount of deviation between the coupling portions MPj and the wiring 2d can be reduced, thereby allowing the multiple coupling portions MPj to be positioned at approximately the same spacing distance from each other. In the example shown in FIG7 , along an imaginary line VLx passing through the center of the opening PLh in the X direction, the multiple coupling portions MPj include two coupling portions MPjx positioned so as to surround the main pattern portion MPm. Furthermore, along an imaginary line VLy passing through the center of the opening PLh in the Y direction intersecting the X direction, the multiple coupling portions MPj include two coupling portions MPjy positioned so as to surround the main pattern portion MPm. Furthermore, of the two coupling portions MPjx and the two coupling portions MPjy, two coupling portions MPjs are positioned between adjacent coupling portions MPjx and MPjy. Each coupling portion MPj is positioned so as to align with each other at approximately the same spacing distance.

The number of coupling portions MPjs placed between coupling portion MPjx and coupling portion MPjy can be adapted to various variations depending on the size of opening PLh. For example, if the opening area of opening PLh is sufficiently small, and if the offset or deviation of wiring 2d is within the acceptable range regardless of where it is positioned between coupling portion MPjx and coupling portion MPjy, then no coupling portion MPjs is necessary. Furthermore, if one coupling portion MPjs is positioned between coupling portion MPjx and coupling portion MPjy, then one coupling portion MPjs can be placed as long as the offset or deviation of wiring 2d is within the acceptable range. Furthermore, if the opening area of opening PLh is large, three or more coupling portions MPjs can be placed between coupling portion MPjx and coupling portion MPjy. However, from the perspective of improving the degree of freedom in layout design of wiring 2d, even if multiple coupling portions MPjs are placed, the planar shape of conductor pattern MP1 is preferably point-symmetrical about the center of opening PLh.

As shown in FIG7 , each of the multiple coupling portions MPjs extends at a 45-degree slope in the X and Y directions. By arranging the coupling portions MPjs so that they extend at a 45-degree slope in the X and Y directions, the spacing between the multiple coupling portions MPjs is easily aligned. Furthermore, when designing a wiring layout, the wiring is often arranged to have two axes (e.g., the X and Y axes) as reference axes and a third axis with a 45-degree slope combined with the two reference axes. The wiring 2d that forms a signal transmission path, such as that shown in FIG7 , may, for example, include multiple bends, with the bend angle being a multiple of 45 degrees (the angle portion being less than 180 degrees being any of 45, 90, or 135 degrees). Therefore, when the direction in which the coupling portions MPjs extend is at a 45-degree slope relative to the X and Y directions, as shown in FIG7 , the direction in which the wiring 2d extends and the direction in which the coupling portions MPjs extend are easily aligned.

<Location of Placing the Electromagnetic Wave Absorber>

Next, the position for placing the conductor pattern MP1 serving as the electromagnetic wave absorber shown in Figures 7 and 8 will be described. Figure 9 is an enlarged cross-sectional view for a position different from that of Figure 8. Figure 10 is an enlarged cross-sectional view showing the basic structure of the conductor pattern of the enlarged cross-sectional view of Figure 9. Figure 11 is an enlarged cross-sectional view showing a modified example corresponding to Figure 9.

In Figures 9 and 11 , the hatched portion of the main pattern portion MPm of the conductor pattern MP1 and the plurality of openings formed in the conductor pattern MP1 are not shown. Furthermore, in Figures 9 and 11 , a coupling portion MPj is shown by a dashed line to schematically illustrate the electrical coupling between the main pattern portion MPm of the conductor pattern MP1 and the conductor plane 2PL. The conductor plane 2PL coupled to the conductor plane MP1 is omitted from the diagram to make the diagram easier to understand.

A conductor plane serving as an electromagnetic wave absorber is formed in a portion where the wiring structure is changed as already described. In the example of Fig. 8 , the conductor pattern MP1 is formed at a position overlapping with the land 2LD in the thickness direction.

In the example shown in FIG8 , the wiring substrate 2 includes a wiring layer WL1 in which a wiring 2d is used as a signal transmission path, a wiring layer WL2 adjacent to the upper layer side (chip mounting surface side) of the wiring layer WL1 and forming a conductor pattern MP1, and a wiring layer WL3 adjacent to the lower layer side (mounting surface side) of the wiring layer WL1 and forming a signal transmission path. The wiring 2d and the land 2LD are electrically coupled via a via wiring 2V serving as an interlayer conductive path. The land 2LD is an external terminal of the semiconductor device 1 (see FIG4 ) and is coupled to a solder ball (see FIG4 ), so the width of the land must be prepared to be sufficiently larger than the wiring 2d.

In FIG8 , when a signal is transmitted to wiring 2d (through which a signal current flows) and the frequency of this signal is sufficiently high, significant signal reflection occurs at the coupling portion of via wiring 2V, which electrically couples pad 2LD and wiring 2d, resulting in scattered electromagnetic waves. Signal reflection is more likely to occur in the portion electrically coupling wiring 2d, which is formed as a narrow wiring shape, and pad 2LD, which is a metal pattern having a width sufficiently greater than that of wiring 2d, rather than in the portion coupling the wirings 2d together. As these scattered electromagnetic waves broaden outward, transmission performance along the signal transmission path deteriorates. Therefore, in this embodiment, conductor pattern MP1 is formed in a position overlapping pad 2LD in the thickness direction, and wiring 2d, which transmits the signal (through which a signal current flows), is positioned between conductor pattern MP1 and pad 2LD. Furthermore, in the example shown in FIG6 , via wiring 2V is formed between pad 2LD and conductor pattern MP1 (in other words, in a position overlapping pad 2LD and conductor pattern MP1 in the thickness direction).

In this way, at least a portion of the scattered electromagnetic waves emitted from the portion where the wiring structure changes is captured by the conductor pattern MP1 and dissipated by converting them into heat. To facilitate the capture of scattered electromagnetic waves, the opening diameter of the opening MPh (the length of one side when the planar shape is a quadrilateral) is preferably smaller than the wavelength of the electromagnetic waves corresponding to the signal frequency band of the transmitted signal. Furthermore, the opening diameter of the opening MPh (the length of one side when the planar shape is a quadrilateral) is particularly preferably 1/20 or less of the wavelength of the electromagnetic waves.

Furthermore, in this embodiment, in the wiring layer WL2, the conductor plane MP1 and the conductor plane 2PL are electrically coupled via a plurality of coupling portions MPj (see FIG. 7 ), so that the spacing distance between the signal transmission path and the return path can be maintained at a fixed distance. Therefore, in this manner, crosstalk noise that occurs due to the distance in a local portion between the signal transmission path and the return path can be prevented.

In the examples shown in Figures 7 and 8, the conductor pattern MP1 is formed at a position overlapping with the land 2LD. However, there are other parts where the wiring structure varies. For example, when the plurality of insulating layers 2e in the wiring substrate 2e include an insulating layer (core layer, core insulating layer) 2CR made of a prepreg material as shown in Figure 9, the through-hole wiring 2TW electrically coupling the upper surface 2Ca and lower surface 2Cb of the insulating layer 2e is coupled to the through-hole land 2TL having a larger width (diameter) than the wiring 2d.

In the example shown in FIG9 , the wiring substrate 2 includes a wiring layer WL1 on the lower surface 2Cb side of the insulating layer 2CR serving as the core layer, on which wiring 2d serving as a signal transmission path is formed; a wiring layer WL2 adjacent to the lower side (mounting surface side) of the wiring layer WL1 and on which a conductor pattern MP1 is formed; and a wiring layer WL3 adjacent to the upper side (chip mounting surface side) of the wiring layer WL1 and on which a through-hole land 2TL is formed. On the upper surface 2Ca side of the insulating layer 2CR serving as the core layer, the wiring substrate 2 includes a wiring layer WL4 on which wiring 2d serving as a signal transmission path is formed; a wiring layer WL5 adjacent to the upper side (mounting surface side) of the wiring layer WL4 and on which a conductor pattern MP1 is formed; and a wiring layer WL6 adjacent to the lower side (chip mounting surface side) of the wiring layer WL4 and on which a through-hole land 2TL is formed.

For example, the through-hole land 2TL has a planar shape with a circular conductor pattern. The diameter (width) of the through-hole land 2TL is smaller than the diameter of the land 2LD shown in FIG8 , but larger than the width of the wiring 2d. Since the insulating layer 2CR serving as the core layer is relatively hard and thicker than other insulating layers (build-up layers) formed using build-up technology, the diameter of the through-hole wiring 2TW is larger than the diameter of the via wiring 2V formed in the build-up layer. Therefore, the width of the through-hole lands 2TL formed at both ends of the through-hole wiring 2TW is larger than the diameter of the wiring 2d and the via wiring 2V.

In FIG9 , when a signal is transmitted to wiring 2d (through which a signal current flows) and the frequency of the signal is sufficiently high, signal reflection occurs at the coupling portion of via wiring 2V, which electrically couples through-hole land 2TL and wiring 2d, resulting in scattered electromagnetic waves. Signal reflection occurs on both the upper surface 2Ca and lower surface 2Cb sides of insulating layer 2CR, which serves as a core layer.

Thus, in this embodiment, the conductor patterns MP1 are formed at positions overlapping with the through-hole lands 2TL in the thickness direction, and the wiring 2d for transmitting signals (through which the signal current flows) is placed between the conductor patterns MP1 and the through-hole lands 2TL. Furthermore, in the example shown in FIG. 9 , the via wiring 2V is formed between the through-hole lands 2TL and the conductor patterns MP1 (in other words, at positions overlapping with the through-hole lands 2TL and the conductor patterns MP1 in the thickness direction).

In this manner, at least a portion of the scattered electromagnetic waves emitted at the coupling portion of the via wiring 2V for electrically coupling the through-hole land 2TL and the wiring 2d is captured by the conductor pattern MP1 and dissipated by being converted into heat energy. The preferred shape of the conductor pattern MP1 is the same as that previously described using FIG. 7 and FIG. 8 , and therefore, repeated descriptions are omitted.

However, in the example shown in FIG9, the wiring layer WL3 of the conductor pattern MP1 is formed; and the wiring layer WL3 of the land 2LD is formed as shown in FIG8, so that in some cases, due to the position of the land 2LD, the wiring layer 3 cannot be formed. In this case, placement priority is given to the land 2LD (see FIG8), and the conductor pattern MP1 is formed in a portion that does not overlap with the land 2LD and the through-hole land 2T.

Due to the relationship between the layout and number of the through-hole welding area 2TL and the welding area 2LD, when the through-hole welding area 2TL and the welding area 2LD overlap in the thickness direction, the number of wiring layers can be increased, and the conductor pattern MP1 can be formed between the through-hole welding area 2TL and the welding area 2LD overlapping in the thickness direction, as in the modified examples shown in Figures 11 and 12.

Wiring substrate 2A according to the modified example shown in FIG11 differs from wiring substrate 2 shown in FIG9 in that wiring layer WL7 having lands 2 formed thereon is mounted adjacent to the lower layer side (mounting surface side) of wiring layer WL3 having conductor pattern MP1 formed thereon. From a different perspective, wiring substrate 2A according to the modified example shown in FIG11 differs from wiring substrate 2 shown in FIG9 in that multiple conductor patterns MP1 are formed on wiring layer WL3, and multiple lands 2LD are also formed on wiring layer WL7, which is different from wiring layer WL3. Wiring substrate 2A further includes wiring layer WL1 having wiring 2d for transmitting signals (where signal current flows), and wiring layer WL3 having conductor pattern MP1 formed thereon. Both of these are formed between wiring layer WL2 having through-hole lands 2TL formed thereon and wiring layer WL7 having lands 2LD formed thereon.

In the example of the wiring substrate 2A, the number of wiring layers is increased more than that of the wiring substrate 2 shown in Figures 8 and 9. However, even if the land 2LD and the through-hole land 2TL overlap in the thickness direction, the conductor pattern MP1 serving as an electromagnetic wave absorber can be placed at a position where the through-hole land 2TL and the land 2LD overlap in the thickness direction. Therefore, the spread of scattered electromagnetic waves generated in the coupling portion between the through-hole land 2TL and the wiring 2d can be prevented.

The pad 2LD shown in FIG11 is an external terminal for supplying a standard (or reference) potential. Therefore, a portion of the planar conductor 2PL is exposed from the insulating layer 2e and used as the pad 2LD. This allows the via wiring 2V, which couples the planar conductor 2PL of the wiring layer WL7 and the planar conductor 2PL of the wiring layer WL3, to be positioned so as not to overlap the conductor pattern MP1. Consequently, the conductor pattern MP1 having the same planar shape as, for example, the conductor pattern MP1 shown in FIG7 can be formed into an electromagnetic wave absorber.

The wiring substrate 2B of the modified example shown in FIG12 differs from the wiring substrate 2A shown in FIG11 in that a wiring layer WL9 is provided with wiring 2d. This wiring 2d is coupled to the pad 2LD between the wiring layer WL7, which has a pad 2LD, and the wiring layer WL3, which has a conductor pattern MP1. The wiring 2d formed in the wiring layer WL9 serves as a partial signal transmission path (through which a signal current flows) that transmits the same or different signals as the wiring 2d formed in the wiring layer WL1. The wiring 2d is coupled to the pad 2LD via a via wiring 2V. On the other hand, the wiring substrate 2B of the modified example shown in FIG12 differs from the wiring substrate 2A shown in FIG11 in that the wiring 2d constituting each signal path (through which a signal current flows) is formed in both the upper and lower layers of the conductor pattern MP1.

In the case of wiring substrate 2B, the number of wirings is increased even more than in wiring substrate 2A shown in FIG11 . However, even if lands 2LD, serving as signal transmission paths, and through-hole lands 2TL, serving as signal transmission paths, overlap in the thickness direction, conductor pattern MP1, serving as an electromagnetic wave absorber, can be placed at a position overlapping in the thickness direction with wiring 2d coupled to through-hole lands 2TL and wiring 2d coupled to lands 2LD. This prevents scattered electromagnetic waves emitted from the portion coupling wiring 2d and through-hole lands 2TL from spreading toward lands 2LD. Furthermore, scattered electromagnetic waves emitted from the portion coupling lands 2LD and wiring 2d from spreading toward through-hole lands 2TL can be prevented from spreading. In other words, in the case of wiring substrate 2B, the influence of electromagnetic waves emitted from layers below conductor pattern MP1 and electromagnetic waves generated in layers above conductor pattern MP1 can be reduced, respectively.

Furthermore, in the case of wiring substrate 2B, the signal current flowing through wiring 2d formed in wiring layer WL9 and the signal current flowing through wiring 2d formed in wiring layer WL1 can be the same signal current or different signal currents. In other words, this effect can be achieved regardless of whether wiring 2d formed in wiring layer WL9 and wiring 2d formed in wiring layer WL1 form a single signal transmission path or a separate signal transmission path.

The wiring substrate 2A shown in FIG11 includes a wiring layer WL8 formed in an upper layer of the wiring layer WL5 formed with the conductor pattern MP1 and having a planar conductor 2PL. The wiring substrate 2B shown in FIG12 includes a wiring layer WL10 in which the planar conductor 2PL is formed between the wiring layer WL8 and the wiring layer WL. When there is no large-diameter (width) pattern such as the welding area 2LD formed on the upper surface 2Ca side of the insulating layer 2CR, the wiring layer WL8 shown in FIG11 and the wiring layer WL10 shown in FIG12 can be omitted. However, from the perspective of suppressing bending deformation on the wiring substrate by approximating the expansion coefficient values on the upper surface 2Ca and the lower surface 2Cb of the insulating layer 2CR serving as the core layer, the number of layers in the wiring layer formed on the upper surface 2Ca side and the lower surface 2Cb side of the insulating layer 2CR is preferably the same.

When many conductor patterns MP1 are formed on a single wiring layer of wiring substrate 2, multiple signal transmission paths can overlap on a single conductor pattern MP1. For example, in the examples shown in Figures 13 and 14, wiring 2d1 is formed to transmit a first signal to a wiring layer below the wiring layer in which conductor pattern MP1 is formed. Similarly, wiring 2d2 is formed to transmit a second signal, different from the first signal current, to a wiring layer above the wiring layer in which conductor pattern MP1 is formed. Different types of signals are transmitted to wiring 2d1 and wiring 2d2, respectively, so that crosstalk noise is emitted when the return paths of each signal transmission path overlap.

However, as already described, the conductor pattern MP1 of this embodiment is electrically coupled to the planar conductor 2PL, which serves as a ground plane, via multiple coupling bodies MPj (see FIG13 ). Therefore, portions of the conductor pattern MP1 can be utilized as return paths, making it difficult for the return paths of each signal transmission path to overlap. Similarly, in this embodiment, the distance between the return path and the signal transmission path can be made substantially the same as described above. Consequently, the effects of crosstalk noise on the signal path can be reduced.

<Method for Manufacturing Semiconductor Device>

When referring to the flowchart shown in Figure 15, the manufacturing method (assembly method) of the semiconductor device 1 shown in Figures 1 to 4 is described next. Figure 15 is a diagram for describing the process of the assembly process of the semiconductor device shown in Figures 1 to 4. In the following description of the manufacturing method, a wiring substrate 2 of a pre-formed product size is prepared, and the method of manufacturing a single semiconductor device 1 is described. However, as a modification, a so-called multi-piece board divided into a plurality of product forming areas is prepared, and after assembling the respective product forming areas, the multi-piece manufacturing method can also be applied to each of the subdivided product forming areas and obtain a plurality of semiconductor devices. Therefore, the single-piece manufacturing process applied during the multi-piece manufacturing method is written in parentheses in Figure 15.

In the substrate preparation process shown in FIG15 , the wiring substrate 2 shown in FIG4 is first prepared. The term "preparing a wiring substrate 2" encompasses purchasing a completed wiring substrate 2 and preparing it, in addition to preparing the wiring substrate 2 itself. With reference to FIG1 through FIG14 , the wiring substrate 2 prepared in this process is a pre-formed structural material, except that the solder balls 4 shown in FIG4 are not yet coupled and the semiconductor chip 3 is not yet mounted. However, solder material (solder bumps) for bonding the protruding electrodes 3BP are pre-formed on the plurality of bonding pads 2PD of the wiring substrate 2.

The semiconductor pattern MP1 shown in Figures 7 to 14 is formed as follows, for example. Figure 16 is a diagram for schematically describing a production process for forming a conductor pattern serving as an electromagnetic wave absorber on a wiring substrate in the substrate preparation process shown in Figure 15 .

The semiconductor pattern MP1 shown in Figures 7 to 14 is formed simultaneously with other metal patterns formed in the same layer (the same wiring layer), such as the planar conductor 2PL and wiring 2d shown in Figure 4. In the example shown in Figure 16, as a mask forming process, a film-shaped mask MSK is first formed on the conductor pattern surface of the insulating layer 2e. The mask MSK is formed in a position where the conductor pattern MP1 (see Figure 7) is not formed. In the example shown in Figure 7, the mask MSK is formed in the portion corresponding to the plurality of openings MPh or openings PLh.

Next, when forming the conductor pattern, a metal film formed by metal deposition patterning is deposited in the opening of the mask MSK. The metal film includes the conductor pattern MP1 and the planar conductor 2PL.

Next, in the mask stripping process, the film mask MSK is removed. When the mask MSK is removed, the opening MPh and the opening PLh are formed on the portion where the mask MSK existed.

Next, in the insulating layer forming process, the insulating layer 2e serving as a build-up layer is formed to cover the conductor pattern MP1 and the planar conductor 2PL. In this process, the insulating layer 2e is embedded in the opening MPh and the opening PLh of the conductor pattern MP1.

The above-mentioned conductor pattern MP1 of the present embodiment is formed simultaneously with the conductor plane 2PL or the wiring 2d (see FIG. 4), so that further manufacturing processes are not added even if the conductor pattern MP1 is formed.

In the semiconductor chip preparation process shown in Figure 15, the semiconductor chip 3 shown in Figure 4 is prepared. An insulating film is formed on the surface 3a of the semiconductor chip 3 to cover the substrate and wiring of the semiconductor chip 3. The insulating film at the opening formed on the insulating film exposes the respective surfaces of a plurality of pads 3PD. Each of the plurality of pads 3PD includes metal, and in this embodiment is made of, for example, aluminum (Al). A plurality of protruding electrodes 3BP are coupled to the plurality of pads 3PD, respectively, and the plurality of pads 3PD of the semiconductor chip 3 and the plurality of bonding pads 2PD of the wiring substrate 2 are electrically coupled via a plurality of protruding electrodes 3BP, respectively. The protruding electrodes 3BP are, for example, laminated solder materials or so-called solder bumps stacked by the lower metal film (lower bump metal) on the pads 3PD.

Next, in the semiconductor chip mounting process, a semiconductor chip 3 such as that shown in FIG4 is mounted on the upper surface 2a serving as the chip mounting surface of the wiring substrate 2. In this embodiment, mounting is performed using a face-down mounting method (or flip-chip method) so that the surface 3a on which the plurality of bonding pads 3PD are formed faces the opposite side of the upper surface 2a of the wiring substrate 2. In this way, the circuit formed on the semiconductor chip 3 and the circuit (transmission circuit) formed on the wiring substrate 2 are electrically coupled by bonding the solder bumps formed on the plurality of bonding pads 2PD of the wiring substrate to the plurality of protruding electrodes 3BP.

Next, in the filling process of underfill, an underfill resin (insulating film resin) 5 is placed between the semiconductor chip 3 and the wiring substrate 2 as shown in FIG4 . The underfill resin 5 is placed to seal the space between the surface 3 a of the semiconductor chip 3 and the upper surface 2 a of the wiring substrate 2. The underfill resin 5 includes an insulating material (non-conductive material) (e.g., a resin material) and is filled to seal the electrical coupling portion (coupling portion for the plurality of bump electrodes 3BP) of the semiconductor chip 3 and the wiring substrate 2.

As another mounting method used as a modified example, a bottom filling resin 5 can be applied in which, before the semiconductor chip mounting process shown in Figure 15, a pre-coated resin material as a film or paste (not shown in the figure) can be applied to a chip mounting area serving as a predetermined area for mounting the semiconductor chip 3, and the semiconductor chip 3 is pressed from the insulating material.

Next, in the ball mounting process, a plurality of solder balls 4 are mounted on the lower surface 2b serving as the mounting surface of the wiring substrate 2. In this process, the plurality of solder balls 4 are placed on the lands 2LD exposed from the insulating layer 2e on the mounting surface shown in FIG. 4 , and the plurality of solder balls 4 can be mounted through a reflow process (a cooling process after heating and fusing a solder component).

When performing the single-piece manufacturing process, in order to obtain a plurality of semiconductor devices 1 , a single piece is manufactured in each product forming region by cutting the wiring substrate for multi-piece manufacturing along a cutting line (parting line) that separates the plurality of product forming regions.

After that, necessary tests and inspections such as external inspection and electric test are performed, and transportation or board installation, which is not shown in the drawings, is performed.

<Modification>

The detailed description given above is based on an embodiment of the invention proposed by the present inventors. However, the present invention is not limited to this embodiment, and it goes without saying that various modifications are possible without departing from the spirit and scope of the present invention. Although various modifications of this embodiment have been described, representative modifications of the above embodiment will be described below.

In the above embodiment, an example of a semiconductor device 1 as shown in FIG4 was described using a wiring substrate 2 including an insulating layer 2CR made of a prepreg material as a core layer. However, the technology described in this embodiment can also be applied to a so-called coreless substrate formed by stacking build-up layers without a core. In this way, through-hole wiring 2TW and through-hole lands 2TL that pass through the core layer are not formed. Therefore, if the conductor pattern MP1 is formed at a position substantially overlapping with the lands 2LD in the thickness direction as shown in FIG8, the noise immunity of the semiconductor device 1 can be improved.

Similarly, as a signal type in the above embodiment, an example is described using a so-called single-ended signal, in which the "H" level and the "L" level are set as the signal voltage level when the ground potential is used as a standard. However, among the signal types, there is a differential signal, in which the signal potential is respectively provided to a pair of signal transmission paths (differential pair), and the potential difference for the differential pair is set to the "H" and "L" levels. The technology described in the above embodiment can also be applied to a signal transmission path for transmitting a differential signal. Figure 17 is an enlarged plan view showing a modified example corresponding to Figure 7.

The wiring substrate 2D shown in FIG17 differs from the wiring substrate 2 shown in FIG7 in that differential signals flow through wiring 2d. More specifically, an opening PLh is formed in a planar conductor 2PL, one of the wiring layers of the wiring substrate 2D that forms the planar conductor MP1, at a position overlapping in the thickness direction with a portion of wiring 2d3, one of the differential pairs. Furthermore, another opening PLh is formed in the planar conductor 2PL at a position overlapping in the thickness direction with a portion of wiring 2d4, the other of the differential pairs. Similarly, each conductor pattern MP1 is formed in two different openings PLh.

The differential pair includes wiring 2d3 and wiring 2d4, and these constitute a signal transmission path along which a differential signal is transmitted. Wiring 2d3 and wiring 2d4 are formed in the same wiring layer as each other, and the wiring layer in which the conductor pattern MP1 is formed is adjacent to the wiring layer in which wiring 2d3 and wiring 2d4 are formed.

In the case of single-ended signals described in the above embodiments, maintaining a fixed gap distance between the signal transmission path and the return path was described as a basic noise countermeasure. In the case of differential signals, in addition to maintaining a fixed gap distance between each signal transmission path and the return path, it is also important to match the impedance along the signal transmission path pair. In the modified example shown in FIG17 , the electrical coupling of each conductor pattern MP1 with the planar conductor 2PL serving as a ground plane allows the conductor pattern MP1 to function as an electromagnetic wave absorber, thereby functioning as a portion of the return path for each signal transmission path.

The main pattern portion MPm of the conductor pattern MP1 includes a grid pattern having a plurality of openings MPh arranged at regular intervals. The planar grid pattern of the main pattern portion MPm results in a return path formed along the grid shape. Therefore, regardless of the layout of the wirings 2d3 and 2d4 formed at positions overlapping the conductor pattern MP1 in the thickness direction, a return path can be formed along the direction in which the wirings 2d3 and 2d4 extend.

Therefore, if the wiring 2d3 and the wiring 2d4 serving as the differential pair can be configured in appropriate shapes, impedance matching of the differential pair can be easily achieved in the wiring substrate 2D shown in FIG 17. Similarly, in the above-described embodiment, the plurality of coupling portions MPj that couple the conductor plane 2PL and the main pattern portion MPm allow the wiring 2d3 and 2d4 to be formed along the coupling portions MPj.

Although redundant description is omitted, the preferred shape of the conductor pattern MP1 of the above-described embodiment (for example, the preferred shape from the perspective of improving the degree of freedom of wiring layout) can be applied in the same manner to the embodiment for transmitting differential signals shown in FIG17. Thus, from the perspective of achieving impedance matching, it is preferable that the conductor pattern MP1 of the overlapping wiring 2d4 and the conductor pattern MP1 of the overlapping wiring 2d3 have the same shape.

In the above embodiment, as an example of the planar shape of the main pattern portion MPm of the conductor pattern MP1, an example of a plurality of square openings MPh arranged in a grid pattern is described. However, various modifications are applicable. For example, in the wiring substrate 2E shown in FIG18 , the opening shapes of the plurality of openings MPh formed in the main pattern portion (grid pattern portion) MPm of the conductor pattern MP1 are formed into circular shapes. As another example, in the wiring substrate 2F shown in FIG19 , the opening shapes of the plurality of openings MPh formed in the main pattern portion (grid pattern portion) MPm of the conductor pattern MP1 are formed into rectangular shapes.

As described using FIG. 16 , when mask MSK is used during the formation of the mesh-patterned conductor pattern MP1, if the opening diameter of the opening MPh is reduced, the mask MSK may peel off during the manufacturing process. As shown in FIG. 19 , if the opening shape of the opening MPh is rectangular, the planar area of the mask MSK is increased, thereby preventing the mask MSK from peeling off before the conductor pattern shown in FIG. 16 is formed.

In the wiring substrate 2G shown in FIG20 , the shape of the plurality of openings MPh formed in the main pattern portion (grid pattern portion) MPm of the conductor pattern MP1 is a mixture of square and rectangular shapes. Similarly, in the plurality of openings MPh of the wiring substrate 2F, among the long sides LS and short sides SS that form the outlines of the plurality of rectangles, the short sides SS are arranged in a zigzag shape so as not to form a single row relative to the Y direction. In this way, even when the planar area of the opening MPh becomes larger, the degree of offset or deviation between the return path and the wiring 2d can be suppressed. In FIG20 , in order to achieve a zigzag arrangement, an example of a mixture of rectangular openings MPh and square openings MPh is shown, but this arrangement can be achieved by using rectangular openings MPh.

When the opening portion MPh is a mixture of rectangular opening portions MPh and square opening portions MPh as in the wiring substrate 2G shown in FIG20 , it is difficult to form the planar shape of the conductor pattern MP1 so as to be point-symmetrical with respect to the center of the opening portion PLh as in the wiring substrate 2 shown in FIG16 . Thus, from the perspective of improving the degree of freedom in the layout design of the wiring 2d, even when some coupling portions MPjs are placed, the planar shape of the conductor pattern MP1 is preferably line-symmetrical with respect to one of the center lines passing through the center of the opening portion PLh (for example, the vertical line VLy in the example shown in FIG20 ).

The various modifications described above can also be effectively applied as combinations of each of the above-described embodiments.

Representative technical concepts extracted from the semiconductor device and the method for manufacturing the semiconductor device of the above-described embodiment and modifications allow the following aspects to be stated.

Supplementary Feature 1

A method for manufacturing a semiconductor device, comprising:

(a) A process for preparing a wiring substrate comprising: a chip mounting surface; a mounting surface disposed on an opposite side of the chip mounting surface; a plurality of first terminals disposed on the chip mounting surface; a plurality of second terminals disposed on the mounting surface; and a multilayer wiring layer electrically coupling the plurality of first terminals and the plurality of second terminals;

(b) a process of mounting a semiconductor chip on the semiconductor chip mounting surface of the wiring substrate, the semiconductor chip including a surface on which a plurality of electrode pads are formed and a rear surface positioned on the opposite side of the surface, and electrically coupling the plurality of electrode pads of the semiconductor chip to the plurality of first terminals, respectively;

The plurality of wiring layers include: a first wiring layer forming a first wiring layer transmitting a first signal, and a second wiring layer installed above and below the first wiring layer,

A first conductor plate and a first conductor pattern are formed in the second wiring layer, the first conductor plate including a first opening at a position overlapping with a portion of the first wiring in a thickness direction, and the first conductor pattern is placed in the first opening of the first conductor plate.

The first opening is formed to pass through the first conductor plate in a thickness direction, and

The first conductor pattern includes: a mesh pattern portion isolated from the first conductor plate; and a plurality of coupling portions coupling the mesh pattern portion and the first conductor plate.

Claims (28)

1. A semiconductor device, comprising: A semiconductor chip, the semiconductor chip comprising a surface having a plurality of electrode pads formed thereon, and a back surface positioned on the opposite side of the surface; and A wiring substrate comprising: a chip mounting surface for mounting the semiconductor chip; a mounting surface positioned opposite the chip mounting surface; a plurality of first terminals mounted on the chip mounting surface and electrically coupled to the plurality of electrode pads of the semiconductor chip; a plurality of second terminals mounted on the mounting surface; and a plurality of wiring layers electrically coupling the first terminals and the second terminals. The wiring layer includes: a first wiring layer having a first wiring formed thereon, and a second wiring layer mounted adjacent to the upper or lower layer of the first wiring layer, wherein a first signal is transmitted to the first wiring layer. A first conductor plate and a first conductor pattern are formed in the second wiring layer. The first conductor plate includes a first opening in the thickness direction at a location where it overlaps with a portion of the first wiring. The first conductor pattern is mounted in the first opening of the first conductor plate. The first opening is formed to pass through the first conductor plate in the thickness direction. The first conductor pattern includes a grid pattern portion coupled to the first conductor plate through multiple coupling portions. 2. The semiconductor device according to claim 1, The coupling part includes: Two first coupling portions, when viewed in a plan view, are positioned to surround the grid pattern portion along a first virtual line, the first virtual line passing through the center of the first opening in a first direction; and Two second coupling portions, when viewed in plan view, are positioned to surround the grid pattern portion along a second virtual line that passes through the center of the first opening along a second direction that intersects the first direction. 3. The semiconductor device according to claim 2, The coupling portion further includes a plurality of third coupling portions, which, when viewed from a plan view, are installed between adjacent first coupling portions and second coupling portions among the two first coupling portions and the two second coupling portions. 4. The semiconductor device according to claim 3, Each of the third coupling portions extends in a direction at a 45-degree angle relative to the first direction and the second direction. 5. The semiconductor device according to claim 3, The first coupling part, the second coupling part, and the third coupling part are installed such that the spacing between them is the same. 6. The semiconductor device according to claim 1, The planar shape of the first conductor pattern is point-symmetric with respect to the center of the first opening. 7. The semiconductor device according to claim 1, The planar shape of the first conductor pattern is linearly symmetrical with respect to the center line passing through the center of the first opening. 8. The semiconductor device according to claim 1, In a plan view, the first wiring extends along one of the coupling portions. 9. The semiconductor device according to claim 1, In the plan view, the first wiring overlaps with one of the coupling portions. 10. The semiconductor device according to claim 1, The plurality of wiring layers further includes a third wiring layer, which is adjacent to the second wiring layer and is also different from the first wiring layer; A second wiring is formed in the third wiring layer, and the second wiring transmits a second signal that is different from the first signal. A portion of the second wiring overlaps with the first conductor pattern in the thickness direction. 11. The semiconductor device according to claim 1, In this configuration, a plurality of second openings in the shape of rectangular openings are regularly arranged in the grid pattern portion of the first conductor pattern. 12. The semiconductor device according to claim 11, The short sides of the rectangles of the plurality of second openings are arranged in a zigzag pattern so that they do not form a single row relative to the direction in which the short sides extend. 13. The semiconductor device according to claim 1, Wherein, the first wiring layer is formed between the second wiring layer and the third wiring layer having the second terminal, and The first conductor pattern overlaps with one of the second terminals in the thickness direction. 14. The semiconductor device according to claim 13, In the thickness direction, the first wiring is electrically coupled to one of the second terminals via a pass wiring at a position where it overlaps with the first conductor pattern. 15. The semiconductor device according to claim 1, The wiring substrate includes: The core layer is made of prepreg material and includes a first surface positioned on the chip mounting surface of the wiring substrate and a second surface on the opposite side of the first surface. Through-hole wiring, the through-hole wiring passing from one of the first surface and the second surface of the core layer to the other surface; A first through-hole welding area, the first through-hole welding area being coupled to the through-hole wiring on the first surface; and The second through-hole welding area is coupled to the through-hole wiring on the second surface. The first conductor pattern is formed above the first through-hole welding area and below the second through-hole welding area, respectively. The first conductor pattern overlaps with the first through-hole welding area and the second through-hole welding area in the thickness direction. 16. A semiconductor device, comprising: A semiconductor chip, the semiconductor chip comprising: a surface having a plurality of electrode pads formed thereon, and a back surface positioned on the opposite side of the surface; and A wiring substrate comprising: a chip mounting surface for mounting the semiconductor chip; a mounting surface positioned opposite the chip mounting surface; a plurality of first terminals mounted on the chip mounting surface and electrically coupled to the electrode pads of the semiconductor chip; a plurality of second terminals mounted on the mounting surface; and a plurality of wiring layers electrically coupling the first terminals and the second terminals. The wiring layer includes: a first wiring layer having first wiring formed thereon, and a second wiring layer mounted adjacent to the upper or lower layer of the first wiring layer, wherein the first wiring layer and the second wiring layer are configured as a differential pair, and differential signals are transmitted to the differential pair. The second wiring layer includes: A first conductor plate, the first conductor plate comprising: a first opening formed in the thickness direction at a location overlapping a portion of the first wiring, and a second opening formed in the thickness direction at a location overlapping a portion of the second wiring; A first conductor pattern, the first conductor pattern being positioned within the first opening of the first conductor plate; and The second conductor pattern is positioned within the second opening of the first conductor plate. The first opening and the second opening are each formed to pass through the first conductor plate in the thickness direction, and The first conductor pattern and the second conductor pattern each include a grid pattern portion coupled to the first conductor plate through multiple coupling portions. 17. The semiconductor device according to claim 16, The first conductor pattern and the second conductor pattern have the same shape. 18. A semiconductor device, comprising: A semiconductor chip having a front surface, a rear surface opposite to the front surface, and electrode pads formed on the front surface; and A wiring substrate having a first main surface, a second main surface opposite to the first main surface, and terminals formed on the first main surface and electrically connected to the electrode pads of the semiconductor chip, the semiconductor chip being mounted on the wiring substrate such that the front surface and the first main surface of the wiring substrate face each other. The wiring layer includes a first wiring layer and a second wiring layer. The first wiring is formed in the first wiring layer. The second wiring layer is formed in the thickness direction between the first main surface and the first wiring layer. The first board is formed in the second wiring layer and has a first opening at a location where it overlaps with a portion of the first wiring. The first pattern is formed within the first opening in the second wiring layer and has multiple openings. The first pattern is electrically and mechanically connected to the first board via a plurality of first coupling portions in the second wiring layer. In the plan view, the interval between two adjacent ports among the plurality of ports is greater than or equal to the width of each of the plurality of first coupling portions. 19. The semiconductor device according to claim 18, In the plan view, the first pattern has a grid pattern portion. 20. The semiconductor device according to claim 18, The wiring substrate includes: The core layer has a first surface positioned on the first main surface side of the wiring substrate and a second surface opposite to the first surface; Through-hole electrode, the through-hole electrode extending from the first surface of the core layer to the second surface of the core layer in the thickness direction; and The first through-hole welding area is connected in the thickness direction to the through-hole electrode on the first surface, and is connected to the first wiring via the first through-hole wiring. The first pattern is formed on the first through-hole welding area and overlaps with the first through-hole welding area. 21. The semiconductor device according to claim 20, The wiring substrate includes: The second through-hole welding area is connected to the through-hole electrode on the second surface in the thickness direction; and The second pattern is formed in the thickness direction below the welding area of the second through hole, and The second pattern overlaps with the welding area of the second through hole. 22. The semiconductor device according to claim 21, The first pattern and the second pattern are the same shape. 23. The semiconductor device according to claim 21, Wherein, in the direction along the first main surface of the wiring substrate, the length of the second pattern is greater than the length of the first pattern. 24. The semiconductor device according to claim 21, The second pattern has multiple openings. 25. The semiconductor device according to claim 21, In the plan view, the second pattern is a grid pattern section. 26. The semiconductor device according to claim 21, The wiring substrate includes: The second wiring is formed between the second through-hole soldering area and the second pattern, and The second wiring is connected to the welding area of the second through hole via the second through hole wiring in the thickness direction. 27. The semiconductor device according to claim 21, The wiring substrate includes: A third wiring layer is formed between the second pattern and the second main surface of the wiring substrate; and A second plate, formed in the third wiring layer, has a second opening at a location overlapping a portion of the second wiring. The second pattern is arranged in the second opening of the second plate, and The second pattern is connected to the second plate via a plurality of second coupling portions. 28. The semiconductor device according to claim 18, External electrodes are formed on the second main surface and electrically coupled to the terminals via multiple wiring layers.