HK1205596B - Power amplifier modules including related systems, devices, and methods - Google Patents

Abstract

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3x1016 cm-3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

Description

Power amplifier module including related systems, devices and methods

Related information of divisional application

The application is a divisional application of a Chinese invention patent application with the international application number of PCT/US2013/045742, the application date of PCT/US2013, 6 and 13 in 2013, the priority date of PCT/US 2012, 6 and 14 in 2012, and the application number of PCT application of a power amplifier module comprising related systems, devices and methods is 201380001003.0 after the PCT application enters the national stage.

Cross reference to related applications

This application claims priority from U.S. provisional application 61/659,848 filed on 6/14/2012.

Technical Field

The present disclosure relates generally to power amplifiers, and in particular to power amplifier modules. More specifically, but not limited to the specific embodiments below described in accordance with the best mode of practice, the present invention relates to power amplifier modules for use in wireless communications and includes related systems, devices, and methods.

Background

A power amplifier may be included in the mobile device to amplify the RF signal for transmission via the antenna. For example, in mobile devices having Time Division Multiple Access (TDMA) architectures, such as those found in the global system for mobile communications (GSM), Code Division Multiple Access (CDMA), and wideband code division multiple access (W-CDMA) systems, power amplifiers may be used to amplify RF signals having relatively low power. Managing amplification of RF signals may be important because the desired transmit power level may depend on how far away the user is from the base station and/or the mobile environment. The power amplifier may also be used to help adjust the power level of the RF signal over time in order to prevent transmission signal interference during the assigned reception time slots.

Power consumption of the power amplifier and its associated Power Added Efficiency (PAE) may be important considerations. In view of the increasing demands associated with wireless communications that provide voice, data, and system control, there is a need for improved power amplifiers, power amplifier modules, and devices, systems, and methods related thereto. Furthermore, there is a need for a power amplifier with improved power efficiency.

Certain specific aspects of the present disclosure relate to the field of integrated circuit packaging, and more particularly, to systems and methods of forming wire bond pads for packaging Radio Frequency (RF) Integrated Circuits (ICs).

Silicon or other semiconductor wafers are fabricated into integrated circuits as is known to those skilled in the art of IC fabrication. The IC is bonded and electrically connected to a carrier or substrate having a number of electrical and metal trace layers and packaged for use. A surface plating material is plated onto the top layer of the copper traces to provide electrical connection points between the IC and the substrate, permitting the IC to interface with the outside world. Traditionally, nickel/gold (Ni/Au) has been the standard surface plating material for RFIC products, and in certain cases, RFIC wire bonds to Ni/Au wire bond pads plated on the surface of the substrate to form electrical connections of the RFIC to its package. However, the increase in gold prices has increased the packaging costs associated with Ni/Au surface plating.

Other particular aspects of the present disclosure relate to the field of integrated circuit layout and packaging, and more particularly to systems and methods of layout and packaging of Radio Frequency (RF) Integrated Circuits (ICs).

Still further aspects of the invention relate more particularly to bipolar transistors and products including bipolar transistors. Bipolar transistors, such as Heterojunction Bipolar Transistors (HBTs), are implemented in a wide variety of applications. Such bipolar transistors may be formed on a semiconductor substrate, such as a gallium arsenide (GaAs) substrate. One illustrative application of bipolar transistors is in power amplifier systems. As technology has evolved, the specifications of power amplifier systems have become more stringent to meet.

As indicated above, one aspect of power amplifier performance is linearity. The measure of linear performance may include a channel power ratio, such as an adjacent channel power ratio (ACPR1) and an alternative channel power ratio (ACPR2), and/or a channel leakage power ratio, such as an adjacent channel leakage power ratio (ACLR1) and an alternative channel leakage power ratio (ACLR 2). ACPR2 and ACLR2 may be referred to as a second channel linearity metric. The ACPR2 values and ACLR2 values may correspond when measured at an offset of about 1.98MHz from the frequency of interest.

By convention, most publications in the literature have focused on ACPR1 and ACLR1 linear measures, and very few publications on either ACRP2 or ACLR 2. Recent ACPR2 and ACLR2 system specifications from the industry have been particularly difficult to meet, especially when other system specifications related to RF gain are met. Accordingly, there is a need for improved linearity in systems including bipolar transistors, such as power amplifier systems.

Still further aspects of the invention relate to a dual mode digital control interface for a power amplifier.

A number of electronic devices, including wireless devices, can have one or more components controlled or set by a front-end component. For example, the power amplifier may be set or configured by a power amplifier controller. In some cases, the power amplifier controller may itself be controlled or configured by another interface component based on the state of the device.

Typically, the various components within the device will be formed by different tissues. To facilitate interoperability between components that may be designed by different organizations, several standards are typically employed for different types of devices and components. As technology advances, standards may change or new standards may be adopted. In some cases, the newer standard is not compatible with the older standard.

And still further aspects of the invention relate to Heterojunction Bipolar Transistor (HBT) power amplifier bias circuits. A power amplifier is typically an active element that can amplify an input signal to produce an output signal that is significantly larger than the input signal. There are many types of power amplifiers and there are many ways to form a power amplifier. For example, some power amplifiers may be formed using Heterojunction Bipolar Transistors (HBTs). Many HBT power amplifiers use a diode stack bias configuration. In some such configurations, the diode stack bias configuration exhibits sensitivity to device β, which can result in substantial quiescent current variations of the amplifier. Furthermore, variations in quiescent current can affect performance parameters and can degrade product yield.

Other aspects of the present invention are directed to understanding that in some semiconductor material systems, it is possible to combine different device technologies on a single semiconductor die to form a hybrid structure. For example, in certain material systems, it is possible to integrate a Heterojunction Bipolar Transistor (HBT) together with a Field Effect Transistor (FET) on a single substrate to make a structure known as a BiFET. Devices, such as RF power amplifiers, may be fabricated using BiFET technology to have increased design flexibility. Accordingly, a BiFET power amplifier including an HBT and a FET may advantageously be designed to operate at a lower reference voltage than a bipolar transistor power amplifier. Device manufacturers are particularly concerned with high power BiFET amplifiers that can be formed by integrating FETs into gallium arsenide (GaAs) HBT processes. However, previous attempts to integrate FETs into gaas hbt processes have only produced n-type FET devices.

Accordingly, it would be desirable to have a BiFET device structure that includes p-type FET devices, and that may include complementary n-type and p-type FET devices.

And still further aspects of the improved techniques disclosed herein relate to terminating harmonic components of a signal. In relatively high frequency applications, such as Radio Frequency (RF) applications, unwanted signal reflections and/or noise may occur. Such unwanted signal reflections and/or noise may occur at the fundamental frequency of the signal and/or at other frequencies, such as harmonics of the fundamental frequency of the signal. To reduce the effects of signal reflections and/or noise, impedance matching may be implemented. One illustrative application in which minimizing unwanted signal reflections and/or noise is advantageous is in power amplifier systems.

Power Added Efficiency (PAE) is a metric used to assess power amplifiers. In addition, linearity is another metric used to assess power amplifier performance. PAE and/or linearity may be a metric by which a customer, such as an Original Equipment Manufacturer (OEM), determines which power amplifiers to purchase. For example, a customer may not purchase a power amplifier having a PAE below a certain level due to the effect of the PAE on the customer's product. For example, a lower PAE may reduce the battery life of an electronic device (e.g., a mobile phone). However, enhancing PAE can adversely affect linearity at the cost. Similarly, improving linearity may result in a reduction in PAE. At the same time, customers desire power amplifiers with high linearity and high PAE.

The load line at the output of the power amplifier may affect both PAE and linearity. Some conventional power amplifier systems have included load lines to match the impedance of the power amplifier output at the fundamental frequency of the power amplifier output signal and also to perform harmonic termination. However, it has proven difficult to match the impedance of the fundamental frequency of the power amplifier output in a manner that optimizes both PAE and linearity while including harmonic termination. Therefore, there is a need to improve both the linearity and the PAE of a power amplifier.

Yet further aspects of the present invention now relate to transmission lines for high performance radio frequency applications.

The transmission line may be implemented in a variety of contexts, such as on a package substrate or Printed Circuit Board (PCB). Multilayer laminated PCBs or package substrates are widely used in Radio Frequency (RF) applications.

RF circuits, such as power amplifiers, Low Noise Amplifiers (LNAs), mixers, Voltage Controlled Oscillators (VCOs), filters, switches, and all transceivers, have been implemented using semiconductor technology. However, in RF modules (e.g., RF front end modules including power amplifiers, switches, and/or filters), single chip integration may be impractical due to the implementation of different blocks in different semiconductor technologies. For example, the power amplifier may be formed by a GaAs process, while the associated control and/or bias circuitry may be formed by a CMOS process.

Long-emitting rays and/or other on-chip passive devices can consume large chip areas. Thus, low cost, small size, and/or high performance of RF modules may be achieved using multi-chip module (MCM) and/or System In Package (SiP) assembly techniques. Lamination techniques may be used for MCM assembly, where the emission lines are implemented on a laminated substrate. Conductor losses in such transmission lines may have a significant impact on the performance of any of the elements in the MCM. Thus, laminate plating techniques can significantly affect RF performance.

The cost of lamination techniques can be driven by the materials selected for performance and/or assembly needs. Rfsips that use gold (Au) wire bonding to connect RF circuit elements to the transmission line can use a variety of different surface treatment platings (e.g., lower loss, more expensive NiAu (e.g., due to thicker Au), or higher loss, less expensive NiPdAu). Therefore, there is a need for cost-effective, high performance techniques for RF transmission lines.

And still other aspects relate to apparatus and methods for tantalum nitride terminated through-wafer vias. In a particular embodiment, a tantalum nitride (TaN) stop layer is formed on a first or front side of a gallium arsenide (GaAs) wafer, and a gold conductive layer is formed over the TaN stop layer. Thereafter, through-wafer vias are etched into the second or backside of the GaAs wafer so as to extend through the GaAs wafer and the first or inner portion of the TaN stop layer to reach the gold conductive layer. In a particular embodiment, the through-wafer via is electroplated with a nickel vanadium (NiV) barrier layer, a gold seed layer, and a copper layer. During through-wafer via formation, a second or outer portion of the TaN stop layer is maintained and configured to surround the interface between the gold conductive layer and the copper layer so as to inhibit diffusion of copper into the GaAs wafer.

TaN-terminated through-wafer vias can provide improved metal adhesion and reduced copper migration relative to schemes using silicon nitride terminations and sputtered barrier layers. Furthermore, in particular implementations, the use of a TaN stop layer to terminate the through-wafer via may permit the location or positioning of the through-wafer via to be moved without changing fabrication or lithography masks associated with transistor structures formed on the front side of the GaAs wafer. Configuring through-wafer vias to be movable without changing photolithographic masks associated with the transistors may increase design flexibility and/or reduce time and cost associated with incremental tuning (incementalfix) or factory-out-of-product inspection (tape-out) of integrated circuit designs including through-wafer vias.

In addition to the above, still further aspects of the present invention relate to packaged semiconductor structures, and more particularly to structures that provide Radio Frequency (RF) isolation and/or electromagnetic radiation.

The packaged semiconductor component may include integrated shielding technology within the package. To form a shield, which may be referred to as a "faraday cage," the top conductive layer may be electrically connected to the bottom conductive layer by vias. For example, the bottom conductive layer may be a ground plane and the vias may connect the top conductive layer to ground. The vias may provide electrical connection between the top and bottom conductive layers, and also serve as part of the shield itself. However, vias can consume a significant amount of area in the package. At the same time, the vias may affect the strength of the ground connection of the shield.

Continuing with the above, additional aspects of the present invention relate to semiconductor device packaging, and more particularly to electromagnetic and/or radio frequency interference shielding of semiconductor devices.

In Radio Frequency (RF) communication systems, RF devices are generally required to be isolated from electromagnetic (radio frequency) interference (EMI) generated by other RF devices in order to maintain proper device performance. Similarly, RF devices typically need to be isolated from electromagnetic interference received from or transmitted to the environment.

The traditional way to isolate the RF device from this electromagnetic interference is to cover the RF device with a grounded metal enclosure commonly referred to as a "can". However, this solution is costly and lacks design flexibility. In addition, metal can add significant size to the device footprint on the printed circuit board and also add weight to the printed circuit board.

Implementing one or more of the features, attributes or characteristics described in further detail in the various sections below of the disclosure may achieve desirable linearity and PAE in a power amplifier system. Furthermore, implementing one or more features described in the following disclosure in a power amplifier system may enable a desired FOM and/or other metrics by which a power amplifier is assessed. Although some features of the present disclosure are described in connection with a power amplifier module for illustrative purposes, those skilled in the art will appreciate that the principles and advantages described herein may be applied to other portions of a power amplifier system, such as in a power amplifier die, a substrate for use with a power amplifier die, and a wireless communication device including a power amplifier, and in any and all other applications as would be appreciated by one of ordinary skill in the art.

Disclosure of Invention

I. Introduction to

The power amplifier may boost the power of a Radio Frequency (RF) signal having a relatively low power. Thereafter, the boosted RF signal may be used for a variety of purposes, such as driving an antenna of a transmitter.

Power amplifiers are used in a variety of RF wireless communication devices. As one example, a power amplifier may be included in a mobile phone to amplify an RF signal for transmission. For example, in mobile phones with Time Division Multiple Access (TDMA) architectures, such as those found in the global system for mobile communications (GSM), Code Division Multiple Access (CDMA), and wideband code division multiple access (W-CDMA) systems, power amplifiers may be used to amplify RF signals.

Power Added Efficiency (PAE) is a metric used to assess power amplifiers. Linearity is another metric used to assess power amplifiers. PAE and/or linearity may be a metric by which a customer determines which power amplifiers to purchase. For example, a customer may not purchase a power amplifier having a PAE below a certain level due to the effect of the PAE on the customer's products. For example, a lower PAE may reduce the battery life of a mobile device (e.g., a mobile phone). For example, linearity may be measured by the Adjacent Channel Power Ratio (ACPR) and/or the alternate channel power ratio (ACPR 2). Achieving both high PAE and high linearity can be difficult. However, customers typically desire high PAE and high linearity. Figure of merit (FOM) is a metric that can reflect both PAE and linearity.

Wire bond pad system and related methods

Systems and methods are disclosed to reduce the cost of RFIC packaging by using nickel/palladium/gold (Ni/Pd/Au) surface plating materials for the RFIC product. To reduce costs, the gold layer in the Ni/Pd/Au surface plating is thinner than the gold layer in the Ni/Au surface plating. However, Ni/Pd/Au has a much higher radio frequency sheet resistance than Ni/Au due to the thin palladium and gold layers and the ferromagnetic nature of nickel. This contributes to reduced effective current sheet thickness and increased current crowding on the RF signal, and may (in some embodiments) result in more RF loss of the RF signal traveling through the Ni/Pd/Au plated surface than is found on the RF signal traveling through the Ni/Au plated surface. These losses can affect product performance and yield.

Other systems and methods to reduce RF losses associated with lower cost Ni/Pd/Au surface plating for RFICs are disclosed. In some embodiments of the design layout, the RF line/trace surfaces, edges and sidewalls in the wire bond regions are open to the plating process and are thus plated with a Ni/Pd/Au surface treatment layer. Due to the skin effect and eddy current effects on the RF current traveling through the plated wire bond region, most of the RF current continues on the trace edges and sidewalls of the plated wire bond region. Since most of the RF current continues on the trace edges and sidewalls, the plated trace edges and sidewalls contribute more to the RF loss. To reduce RF losses, some embodiments reconfigure the solder mask to cover the trace edges and sidewalls in the wire bond regions so that the trace edges and sidewalls are not plated with a Ni/Pd/Au surface finish. The copper trace edges and sidewalls around the wire bond regions that are free of the Ni/Pd/Au plating provide a low resistive path for RF current around the Ni/Pd/Au wire bond pads and, thus, reduce RF signal loss associated with the Ni/Pd/Au surface plating of the RFIC substrate.

Certain embodiments relate to a method of fabricating a Radio Frequency Integrated Circuit (RFIC) module including providing a substrate having at least one copper trace with a wire bond surface. The method further includes forming a solder mask opening of a wire bond pad directly over a bonding surface of the copper trace, the wire bond pad having at least one edge and at least one sidewall. The method further includes forming a solder mask directly over at least one edge and at least one sidewall of the wire bond pad, electroplating the copper trace with a nickel layer, electroplating the nickel layer with a palladium layer, and electroplating the palladium layer with a gold layer to form a nickel/palladium/gold wire bond pad. The nickel/palladium/gold wire bonding pad has at least one edge and at least one sidewall that do not contain nickel, palladium, and gold layers.

According to several embodiments, the present invention relates to a wire bond pad for a Radio Frequency Integrated Circuit (RFIC) module. The wire bond pads include a layer of nickel plated over wire bond surfaces of copper traces formed on an upper surface of a substrate of an RFIC module. The wire bond pad further includes a palladium layer electroplated over the nickel layer and a gold layer electroplated over the palladium layer. The wire bond pad has a wire bond region, at least one edge adjacent to the wire bond region, and at least one sidewall adjacent to the at least one edge, the at least one edge and the at least one sidewall being free of a nickel layer, a palladium layer, and a gold layer.

According to various embodiments, an apparatus for fabricating a Radio Frequency Integrated Circuit (RFIC) module includes means for providing a substrate having at least one copper trace with a wire bond surface and means for forming a solder mask opening of a wire bond pad directly over the bond surface of the copper trace, the wire bond pad having at least one edge and at least one sidewall. The apparatus further includes means for forming a solder mask directly over at least one edge and at least one sidewall of the wire bond pad, means for electroplating a copper trace with a nickel layer, means for electroplating the nickel layer with a palladium layer, and means for electroplating the palladium layer with a gold layer to form a nickel/palladium/gold wire bond pad. The nickel/palladium/gold wire bonding pad has at least one edge and at least one sidewall that do not contain nickel, palladium, and gold layers.

For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

Apparatus and method for reducing the effects of high RF loss coatings

Systems and methods are disclosed to reduce the cost of RFIC packaging by using nickel/palladium/gold (Ni/Pd/Au) surface plating materials for the RFIC product. To reduce costs, the gold layer in the Ni/Pd/Au surface plating is thinner than the gold layer in the Ni/Au surface plating. However, Ni/Pd/Au has a much higher radio frequency sheet resistance than Ni/Au due to the thin palladium and gold layers and the ferromagnetic nature of nickel. This contributes to reduced effective current sheet thickness and increased current crowding on the RF signal, and may (in some embodiments) result in more RF loss of the RF signal traveling through the Ni/Pd/Au plated surface than is found on the RF signal traveling through the Ni/Au plated surface. These losses can affect product performance and yield.

Other systems and methods to reduce RF losses associated with lower cost Ni/Pd/Au surface plating for RFICs are disclosed. In some embodiments of the design layout, the RF line/trace surfaces, edges and sidewalls in the wire bond regions are open to the plating process and are thus plated with a Ni/Pd/Au surface treatment layer. Due to the skin effect and eddy current effects on the RF current traveling through the plated wire bond region, most of the RF current continues on the trace edges and sidewalls of the plated wire bond region. Since most of the RF current continues on the trace edges and sidewalls, the plated trace edges and sidewalls contribute more to the RF loss. To reduce RF losses, some embodiments reconfigure the solder mask to cover the trace edges and sidewalls in the wire bond regions so that the trace edges and sidewalls are not plated with a Ni/Pd/Au surface finish. The copper trace edges and sidewalls around the wire bond regions that are free of the Ni/Pd/Au plating provide a low resistive path for RF current around the Ni/Pd/Au wire bond pads and, thus, reduce RF signal loss associated with the Ni/Pd/Au surface plating of the RFIC substrate.

Additionally, systems and methods are disclosed to reduce RF losses associated with high RF loss bond pads of on-die capacitors, resistors, inductors, or other passive devices of an RFIC. In some embodiments, the RFIC includes an on-die capacitor, resistor, inductor, or other passive device. Capacitors or passive devices are bonded to the copper traces carrying the RF current. For example, when high RF loss bond pads (e.g., Ni/Pd/Au bond pads) are used to connect passive devices to circuit traces of an RFIC module, the high RF loss bond pads generate RF signal losses when RF current flows through them. Placing capacitors, resistors, inductors, or other passive devices of the RF upper traces on the die relative to the RF signal output of the RFIC reduces RF losses associated with passive device bond pads on the die.

In a particular embodiment, an electronic circuit module configured to reduce signal loss is disclosed. The module includes an electronic circuit device having an output signal and a current associated with the output signal. The electronic circuit device includes a first lead, a second lead, and an integrated circuit die having an on-die passive component. The electronic circuit module further includes a substrate including a trace for conducting the electrical current. The trace has a first bond pad electrically connected to an upstream signal path of the first lead and a second bond pad electrically connected to a downstream signal path of the second lead. The electronic circuit device is configured such that an on-die passive component is electrically connected to the first lead and an output signal is electrically connected to the second lead. Thereby directing the current away from the first bond pad. In one embodiment, the electronic circuit module is a radio frequency integrated circuit module and the signal loss is a radio frequency signal loss. In another embodiment, the electronic circuit device is a radio frequency electronic circuit device, the output signal is a radio frequency output signal and the current is a radio frequency current.

According to a number of embodiments, an electronic circuit device is configured to reduce signal loss. The device includes: an integrated circuit die having an on-die passive component; an output signal having an associated current; a first lead electrically connected to a first bond pad located on an upstream signal path of a trace on a substrate; and a second lead electrically connected to a second bond pad on a downstream signal path on the trace. The electronic circuit device is configured such that an on-die passive component is electrically connected to the first lead and an output signal is electrically connected to the second lead. Thereby directing the current away from the first bond pad.

According to various embodiments, a method for reducing signal loss in an electronic circuit module is disclosed. The method includes fabricating an electronic circuit device including an integrated circuit die having an on-die passive component and generating an output signal from the electronic circuit device. The output signal has an associated current. The method further includes forming first and second leads on the electronic circuit device, forming first and second bond pads on a substrate, and forming traces on the substrate to provide conductive paths to conduct current between the first and second bond pads. The trace has an upstream signal path associated with the first bond pad and a downstream signal path associated with the second bond pad. The method further includes electrically connecting the first lead to the first bond pad, electrically connecting the second lead to the second bond pad, and configuring the electronic circuit device such that an on-die passive component is electrically connected to the first lead and an output signal is electrically connected to the second lead. Thereby directing the current away from the first bond pad.

In an embodiment, an apparatus for reducing signal loss in an electronic circuit module is disclosed. The apparatus includes means for fabricating an electronic circuit device including an integrated circuit die having an on-die passive component and means for generating an output signal from the electronic circuit device. The output signal has an associated current. The apparatus further includes means for forming first and second leads on the electronic circuit device, means for forming first and second bond pads on a substrate, and means for forming traces on the substrate to provide conductive paths to conduct current between the first and second bond pads. The trace has an upstream signal path associated with the first bond pad and a downstream signal path associated with the second bond pad. The apparatus further includes means for electrically connecting the first lead to the first bond pad, means for electrically connecting the second lead to the second bond pad, and means for configuring the electronic circuit device such that an on-die passive component is electrically connected to the first lead and an output signal is electrically connected to the second lead. Thereby directing the current away from the first bond pad.

For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

Bipolar transistor with collector comprising grading

The innovations described in the technical solutions each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the invention, some salient features will now be discussed briefly.

One aspect of the invention is a bipolar transistor comprising a collector, a base and an emitter disposed over the collector. The collector has at least about 3 x 10 in a first collector region adjacent the base¹⁶cm^-3The doping concentration of (c). The collector also has another collector region below the first collector region. The other collector region includes at least one grading in which the doping concentration increases away from the first collector region.

In a particular embodiment, another collector region includes a first grading and a second grading in which a doping concentration increases away from the base at a different rate than in the first grading. According to some of these embodiments, the bipolar transistor may have a gain of at least about 29dBm at a frequency within a frequency band centered around about 833 MHz. According to a number of embodiments, at the same current density, the second grading of the bipolar transistor may be configured to increase BvCEX of the bipolar transistor compared to the same transistor without the second grading. In various embodiments, the doping concentration in the first grading is graded from about an order of magnitude less than the doping concentration of the first collector region to less than the doping concentration of the first collector region. According to some of these embodiments, the doping concentration in the second grading ranges from about the maximum doping concentration in the first grading to a doping concentration at least about one order of magnitude less than the doping concentration of the subcollector below the second grading. In some embodiments, the first grading spans a second collector region proximate to the first collector region and having a thickness that is about twice as much as a thickness of the first collector region. According to a particular embodiment, the second grading spans a third collector region having a thickness greater than a thickness of the first collector region and less than a thickness of the second collector region. In various embodiments, the collector consists essentially of the first collector region, the second collector region, and the third collector region. According to some embodiments, the bipolar transistor also includes a sub-collector below the collector. According to a particular embodiment, the first grading adjoins the second grading and the doping concentration is approximately the same on both sides of the border of the first grading and the second grading.

In a particular embodiment, the thickness of the first collector region is selected from aboutToThe range of (1). According to some of these embodiments, the doping concentration of the first collector region is selected from about 3 × 10¹⁶cm^-3To 9X 10¹⁶cm^-3The range of (1).

According to a number of embodiments, the doping concentration in the first collector region is at least about 6 x 10¹⁶cm^-3。

According to some embodiments, the base has a thickness of less than aboutIs measured. In some of these embodiments, the base has a thickness selected from about 3.5 x 10¹⁹cm^-3To 7X 10¹⁹cm^-3Doping concentration of the range of (a).

In several embodiments, the bipolar transistor is a Heterojunction Bipolar Transistor (HBT).

According to some embodiments, the bipolar transistor is a GaAs transistor.

Another aspect of the invention is a power amplifier module comprising a bipolar transistor. The bipolar transistor has a collector, a base, and an emitter. The collector has a doping concentration at a junction with the base such that the power amplifier has an alternative channel power ratio (ACPR2) of no greater than about 65 dBc. The collector also has at least a first grading in which the doping concentration increases away from the base.

According to a particular embodiment, the ACPR2 is no greater than about 65dBc when the power amplifier is operating within a frequency band centered around approximately 833 MHz.

In a number of embodiments, the collector also includes a second grading that is further from the base than the first grading. According to some embodiments, the second grading is configured to increase BvCEX of the bipolar transistor compared to the same transistor without the second grading, at the same current density.

According to a number of embodiments, the doping concentration in the collector at the junction with the base is at least about 3 x 10¹⁶cm^-3。

In a particular embodiment, the collector includes a first region abutting the base, the first region having at least about 3 x 10¹⁶cm^-3And is selected from aboutToA thickness of the range of (1). According to some of these embodiments, the doping concentration in the first region of the collector is from about 3 x 10¹⁶cm^-3To 9X 10¹⁶cm^-3Is selected within the range of (1).

Yet another aspect of the invention is a power amplifier die including a bipolar transistor having a collector, a base adjacent the collector, and an emitter. The collector has at least about 3 x 10 at a junction with the base¹⁶cm^-3The doping concentration of (c). The collector also has at least a first grading in which the doping concentration increases away from the base.

Another aspect of the invention is a mobile device comprising an antenna, a battery, and a power amplifier. The power amplifier includes a heterojunction bipolar transistor having a collector, a base, and an emitterA tube. The collector comprises a base adjacent to the base and having at least about 3 x 10¹⁶cm^-3Of a first doping concentration. The collector also includes a second collector region proximate the first collector region and having a first grading in which a doping concentration increases away from the base. The collector also includes a third collector region proximate the second collector region and having a second grading in which a doping concentration increases away from the base at a different rate than the first grading. The first doping concentration, the first grading, and the second grading are configured to improve linearity of the power amplifier.

Yet another aspect of the invention is a method of forming a bipolar transistor. The method comprises the following steps: forming a sub collector; forming a collector region having at least one grading with a doping concentration that decreases away from the sub-collector; and forming a base adjacent to and abutting the bipolar transistor and having at least about 3 x 10 at an interface with the base ¹⁶cm^-3Different collector regions of doping concentration.

For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

Dual mode power amplifier control with tri-mode input/output interface

According to some embodiments of the invention, this aspect of the invention relates to a dual mode control interface that may be used to provide both a Radio Frequency Front End (RFFE) serial interface and a general purpose input/output (GPIO) interface within a single digital control interface die. In a particular embodiment, the dual mode control interface or digital control interface may communicate with a power amplifier. Further, the dual mode control interface may be used to set a mode of the power amplifier.

According to a particular embodiment, the dual mode control interface includes an RFFE core configured to provide an RFFE serial interface. Further, the dual mode control interface includes a voltage input/output (VIO) pin configured to receive a VIO signal. This VIO signal determines whether the operating mode of the RFFE core is set to one of an active state and an inactive state. When the RFFE core is set to the inactive state, the dual-mode control interface is configured to provide a general purpose input/output (GPIO) interface. Additionally, the dual mode control interface includes a combinational logic block configured to provide an enable signal and a mode signal to the enable level shifter and the mode level shifter, respectively. Further, the dual mode control interface includes a power-on reset configured to select the enable signal and the mode signal to be provided to the enable level shifter and the mode level shifter, respectively, based on the VIO signal.

For some implementations, the dual mode interface includes a clock/mode pin configured to provide a clock signal to the RFFE core when the RFFE core is set to an active state and a mode signal to the combinational logic block when the RFFE core is set to an inactive state. Additionally, the dual mode interface includes a data/enable pin configured to provide a data signal to the RFFE core when the RFFE core is set to an active state and an enable signal to the combinational logic block when the RFFE core is set to an inactive state.

In some variations, the data/enable pin is further configured to provide an address signal to the RFFE core, the address signal associated with a register of the RFFE core.

According to some other related embodiments of the present invention, the dual mode interface includes a plurality of level shifters. Each level shifter of the plurality of level shifters may be configured to receive a register signal from the RFFE core. The register signal may be associated with a value stored in one of a plurality of registers associated with the RFFE core.

Process compensated HBT power amplifier bias circuit and related methods

In some implementations related to this aspect of the disclosure, the disclosure relates to a Power Amplifier (PA) configuration that uses passive devices on the amplifier die to effectively sense die-dependent parameters (e.g., β) and compensate for associated effects (e.g., quiescent current variations) to improve performance and/or reduce part-to-part variation of the product. In some embodiments of the present invention, such a PA configuration may include a silicon bias die and an HBT amplifier die. Traditionally, the silicon die will produce a reference current for the PA die that is approximately constant with respect to the temperature of the PA die and that varies substantially only by the tolerance of the discrete resistors.

In a certain implementation of the present invention, this discrete reference resistor may be replaced by an integrated resistor on the HBT die. In some embodiments of the present invention, this integrated resistor may be formed with HBT device base material and may exhibit sheet resistance characteristics that track process β. Based on this resistance, the reference current can be configured to track β and cancel or reduce the "diode-stack" sensitivity to β.

In other embodiments related thereto, the aforementioned base resistor (Rb) type may be configured to generate a high temperature coefficient that may be compensated by bias generation circuitry within the silicon control die such that the voltage applied across the reference resistor increases with ambient temperature. The resulting reference current from the amplifier may be substantially constant over a selected range of ambient temperatures and substantially tracks HBT process beta.

Device and method for a structure with HBT and FET

An embodiment of a semiconductor structure comprises: a Heterojunction Bipolar Transistor (HBT) comprising a collector layer over a substrate, the collector layer comprising a semiconductor material; and a Field Effect Transistor (FET) located over the substrate, the FET including a channel formed in the semiconductor material forming the collector layer of the HBT.

In some embodiments of this aspect of the invention, the semiconductor material forming the collector layer of the HBT and the channel of the FET may comprise p-type gallium arsenide. In some embodiments, the semiconductor structure may further include an etch stop layer segment located over the collector layer of the HBT and the channel of the FET. In some embodiments, the etch stop layer may comprise indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and may have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges may also be implemented. In some embodiments, such an etch stop layer may comprise any material having etch sensitivity to, for example, a channel layer of the FET. Such a material may be implemented in an appropriate thickness or within an appropriate thickness range in order to achieve similar results as the aforementioned example materials InGaP or InGaAs.

According to other embodiments of the invention, the invention relates to a semiconductor structure having a Heterojunction Bipolar Transistor (HBT) comprising a collector layer located over a substrate and an emitter layer located over the substrate. The collector layer includes a first semiconductor material of a first conductivity type (P), and the emitter layer includes a second semiconductor material of a second conductivity type (N). The semiconductor structure further includes a first Field Effect Transistor (FET) located over the substrate. The first FET includes a channel formed in the first semiconductor material forming the collector layer of the HBT. The semiconductor structure further includes a second Field Effect Transistor (FET) located over the substrate. The second FET includes a channel formed in the second semiconductor material forming the emitter layer of the HBT.

In some embodiments of the present invention, the first semiconductor material forming the collector layer of the HBT and the channel of the first FET may comprise p-type gallium arsenide, and the second semiconductor material forming the emitter layer of the HBT and the channel of the second FET may comprise n-type gallium arsenide. In some embodiments, the semiconductor structure may further comprise a first etch stop layer segment over the collector layer of the HBT and the channel of the first FET and a second etch stop layer segment over the emitter layer of the HBT and the channel of the second FET. The first and second etch stop layer segments may include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and may have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges may also be implemented. In some embodiments, such etch stop layers may comprise any material having etch sensitivity to, for example, channel layers of the first and second FETs. Such a material may be implemented in an appropriate thickness or within an appropriate thickness range in order to achieve similar results as the aforementioned example materials InGaAs or InGaP.

In a number of implementations, the invention relates to a method comprising forming a Heterojunction Bipolar Transistor (HBT) comprising a collector layer located above a substrate and an emitter layer located above the substrate. The collector layer includes a first semiconductor material of a first conductivity type (P), and the emitter layer includes a second semiconductor material of a second conductivity type (N). The method further includes forming a first Field Effect Transistor (FET) over the substrate. The first FET includes a channel formed in the first semiconductor material forming the collector layer of the HBT. The method further includes forming a second Field Effect Transistor (FET) over the substrate. The second FET includes a channel formed in the second semiconductor material forming the emitter layer of the HBT.

In some implementations, the first semiconductor material forming the collector layer of the HBT and the channel of the first FET can include p-type gallium arsenide, and the second semiconductor material forming the emitter layer of the HBT and the channel of the second FET can include n-type gallium arsenide. In some implementations, the method can further include forming a first etch stop layer segment over the collector layer of the HBT and the channel of the first FET and forming a second etch stop layer segment over the emitter layer of the HBT and the channel of the second FET. The first and second etch stop layer segments may include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and may have a thickness range between 10 nanometers (nm) and 15 nm.

According to some implementations, the invention relates to a method comprising forming a Heterojunction Bipolar Transistor (HBT) comprising a collector layer located above a substrate. The collector layer includes a semiconductor material. The method further includes forming a Field Effect Transistor (FET) located over the substrate. The FET includes a channel formed in the semiconductor material forming the collector layer of the HBT.

In some implementations, the semiconductor material forming the collector layer of the HBT and the channel of the FET can include p-type gallium arsenide. In some implementations, the method can further include forming an etch stop layer segment over the collector layer of the HBT and the channel of the FET. The etch stop layer may include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and may have a thickness range between 10 nanometers (nm) and 15 nm.

According to some embodiments, the invention relates to a die having an Integrated Circuit (IC). The die includes circuitry configured to process a Radio Frequency (RF) signal. The die further includes an assembly of Heterojunction Bipolar Transistors (HBTs) and Field Effect Transistors (FETs) configured to facilitate operation of the circuit. The HBT comprises a collector layer comprising a semiconductor material located over a substrate. The FET includes a channel located over the substrate and formed in the semiconductor material forming the collector layer of the HBT.

In some embodiments, the circuitry configured to process RF signals may include power amplifier circuitry, controller circuitry for the power amplifier circuitry, or a controller for switching circuitry. In some embodiments, the assembly can further include a second FET having a channel located above the substrate and formed in the same semiconductor material as the emitter of the HBT. The first FET may comprise a pFET and the second FET may comprise an nFET. In some embodiments, the substrate may comprise gallium arsenide (GaAs).

In several embodiments, the present invention relates to a packaged module for a Radio Frequency (RF) device. The module includes a package substrate and an Integrated Circuit (IC) formed on a die and mounted on the package substrate. The IC includes an assembly of Heterojunction Bipolar Transistors (HBTs) and Field Effect Transistors (FETs) configured to facilitate operation of the IC. The HBT includes a collector layer comprising a semiconductor material located over a die substrate. The FET includes a channel located over the die substrate and formed in the semiconductor material forming the collector layer of the HBT. The module further includes one or more connections configured to facilitate the transfer of power to and RF signals from the IC.

According to other related embodiments of the invention, the assembly may further include a second FET including a channel located above the die substrate and formed in the same semiconductor material as the emitter of the HBT. The first FET may comprise a pFET and the second FET may comprise an nFET.

According to some other embodiments related thereto, the invention relates to a wireless device having an antenna and a Radio Frequency Integrated Circuit (RFIC) configured to process RF signals received from the antenna and for transmission through the antenna. The wireless device further includes a Power Amplifier (PA) circuit configured to amplify the RF signal. The PA circuit includes an assembly of a Heterojunction Bipolar Transistor (HBT) and a Field Effect Transistor (FET). The HBT comprises a collector layer comprising a semiconductor material located over a substrate. The FET includes a channel located over the substrate and formed in the semiconductor material forming the collector layer of the HBT.

In still further related embodiments of the invention, the PA may be configured to operate as a high power BiFET amplifier capable of operating at a reference voltage lower than the reference voltage of a bipolar transistor PA. In some embodiments, the substrate may comprise gallium arsenide (GaAs).

Other embodiments are also provided. Other systems, methods, features and advantages of the invention will be or become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

RF power amplifier with semiconductor resistor

In many situations, it is desirable to reduce the cost of Radio Frequency (RF) devices, such as Power Amplifiers (PAs). Removing process steps and/or using "free" devices that do not involve additional processing steps are examples of how this cost reduction can be achieved. As described in further detail herein below, semiconductor resistors may provide such advantageous cost reductions. Other advantages may also be achieved with semiconductor resistors, as also described herein. For example, depending on the available resistance values, a smaller resistor footprint may be provided, which in turn may help shrink the die size. This reduction in die size may further reduce cost. In another example, some semiconductor resistors may be sensitive to conditions of the same semiconductor material that also forms the resistor.

In some implementations of this aspect of the invention, some or all of the thin film (e.g., TaN) resistors associated with the semiconductor die and the IC thereon may be replaced with semiconductor resistors. In some implementations, such semiconductor resistors can be fabricated from one or more of the actual layers forming a layer-stack device, such as a Heterojunction Bipolar Transistor (HBT). Such resistors can be fabricated without additional processing steps in fabricating the HBT. Since several such resistors can be fabricated from different layers of the stack, such as the emitter layer, the base layer of the HBT, and the ion implanted base layer, flexibility in resistance value and die size reduction is possible.

In other implementations of the invention, fabricating a semiconductor resistor having one or more features as described herein may be accomplished without additional processing steps or with minimal modification of process steps when compared to fabricating a stacked structure on a given die. Although various examples are described herein in the context of HBTs, it should be understood that similar resistor structures and fabrication methods may be applied to other configurations. For example, additional layers may be formed for fabricating devices including the HBT and one or more other transistor structures. Examples of such devices include, but are not limited to, U.S. patent No. 6,906,359 entitled "BIFET including an FET with increased linearity and manufacturability" (BIFET including afe thovingmingrea linear inediatyln n-lateral), and PCT publication No. WO2012/061632 entitled "devices and methods related to structures having an HBT and an FET" (devicescandmethodologiestrandtostrucutschhavingbtanfet).

According to other embodiments, one or more features of the present disclosure may be implemented in a III-V semiconductor die. In some embodiments, such III-V semiconductor dies may include GaAs-based dies. Transistors and/or other stack structures formed on such GaAs based dice may or may not include HBTs.

As described herein, a number of advantageous features may be provided by a semiconductor resistor. For example, other advantages may include desirable features where different Temperature Coefficient of Resistance (TCR) values are provided by selection of materials associated with the resistor layer. In another example, the size of the resistor may be optimized or configured in a desirable manner due to this range of possible resistance values, such as a sheet resistance of about 8 ohms/square (e.g., a subcollector) to about 1, 000 ohms/square (e.g., an implanted base layer). In yet another example, the RF attenuation (roll-off) of the resistors may be selected and/or tuned depending on which resistor is selected (e.g., by modifying how to bias the third terminal on the device).

XI Signal Path termination

One aspect of the invention is a power amplifier module including a power amplifier die, a load line, and a harmonic termination circuit. The power amplifier die includes one or more power amplifiers configured to amplify an input signal at a power amplifier input and generate an amplified output signal at a power amplifier output. The power amplifier die also has a plurality of output pins. The load line is configured to match an impedance at the power amplifier output at a fundamental frequency of the amplified output signal. The load line is electrically coupled to a first group of one or more of a plurality of output pins of the power amplifier die external to the power amplifier die. The harmonic termination circuit is separate from the load line. The harmonic termination circuit is configured to terminate with a phase corresponding to a harmonic frequency of the amplified output signal. The harmonic termination circuit is electrically coupled to a second group of one or more other pins of the plurality of output pins of the power amplifier die external to the power amplifier die.

In a particular implementation of the present disclosure, the harmonic termination circuit can include one or more interconnects coupled to the second group of one or more other pins of the power amplifier die external to the power amplifier die. According to some of these implementations, the one or more interconnects may include wire bonds. Alternatively or additionally, the load line may include one or more other interconnects coupled to the first group of one or more pins of the power amplifier die external to the power amplifier die. According to various implementations, a different number of interconnects may be coupled to the first group of one or more pins of the power amplifier die than the second group of one or more other pins of the power amplifier die.

According to a number of implementations, the first group of one or more pins of the power amplifier die can be electrically coupled to first conductive traces on a substrate, and the second group of one or more pins of the power amplifier die are electrically coupled to second conductive traces on the substrate, wherein the first conductive traces are included in a different signal path than the second conductive traces external to the power amplifier die. In some of these implementations, the harmonic termination circuit may include: wire bonds having a first end and a second end, the first end coupled to the first group of one or more pins of the power amplifier die; a second conductive trace on the substrate, the second conductive trace coupled to the second end of the wire bond; and a capacitor having a first end and a second end, the first end coupled to the second conductive trace and the second end coupled to a reference voltage.

The harmonic frequency of the amplified output signal may be, for example, a second harmonic frequency of the amplified output signal or a third harmonic frequency of the amplified output signal.

According to various implementations, the power amplifier module may also include another harmonic termination circuit separate from the load line and the harmonic termination circuit, the other harmonic termination circuit configured to terminate with a phase corresponding to another harmonic frequency of the amplified output signal. According to a particular implementation, the harmonic termination circuit may be in parallel with the other harmonic termination circuit.

According to a particular implementation, the power amplifier module may also include an input matching network configured to match an impedance at a power amplifier input and a separate harmonic termination circuit configured to terminate at a phase of a harmonic frequency of an input signal.

In some implementations, portions of the harmonic termination circuit may be implemented within the power amplifier die.

Another aspect of the present invention is a mobile device, comprising: a battery configured to power the mobile device; a power amplifier die; a load line; a harmonic termination circuit; and an antenna electrically coupled to the load line, the antenna configured to transmit an amplified RF signal. The power amplifier die includes a power amplifier configured to amplify a Radio Frequency (RF) input signal received at a power amplifier input node and to generate the amplified RF signal at a power amplifier output node. The load line is configured to match an impedance at the power amplifier output node at a fundamental frequency of the amplified RF signal. The harmonic termination circuit is separate from the load line. The harmonic termination circuit is configured to terminate with a phase corresponding to a harmonic frequency of the amplified RF signal. The harmonic termination circuit and the load line have different electrical connections to a power amplifier output node external to the power amplifier die.

Another aspect of the invention is an apparatus including a die and a substrate configured to receive the die. The die includes at least one active circuit element configured to drive an output signal to an output node. The substrate includes a first conductive trace and a second conductive trace. The first and second conductive traces are part of different signal paths on the substrate. The first conductive trace is included in a load line configured to match an impedance at an output node at a fundamental frequency of an output signal. The second conductive trace is included in a harmonic termination circuit separate from the load line. The harmonic termination circuit is configured to terminate with a phase corresponding to a harmonic frequency of the output signal.

In a particular implementation, the substrate may include a third conductive trace included in another harmonic termination circuit configured to terminate with a phase corresponding to a different harmonic frequency of the output signal.

According to some implementations, the apparatus can also include a wire bond configured to electrically couple an output node of the die to the second conductive trace, and the wire bond can be included in the harmonic termination circuit.

According to a number of implementations, the apparatus can also include a capacitor mounted to the substrate, wherein the capacitor is electrically coupled to the second conductive trace and the capacitor is included in the harmonic termination circuit.

Yet another aspect of the invention is a method of manufacturing a module. The method comprises the following steps: coupling a power amplifier die to a package substrate, the power amplifier die including a power amplifier configured to receive an input signal and generate an amplified output signal; forming a first interconnect between the power amplifier die and a first conductive trace on the package substrate, the first interconnect included in a first termination circuit configured to match an impedance of a fundamental frequency of the amplified output signal; and forming a second interconnect between the power amplifier die and a second conductive trace on the package substrate, the second interconnect being separate from the first interconnect, the first conductive trace being separate from the second conductive trace, and the second interconnect being included in a second termination circuit configured to terminate in a phase corresponding to a harmonic of the amplified output signal.

In some implementations, forming the first interconnect can include wire bonding a pad of the power amplifier die to the first conductive trace on the package substrate.

For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

X. transmission line for high performance radio frequency applications

One aspect of the present invention is a Radio Frequency (RF) transmit line configured for use in a Radio Frequency (RF) circuit. The RF transmission line includes a bonding layer, a barrier layer, and a diffusion barrier layer, and a conductive layer. The bonding layer has a bonding surface and is configured to receive an RF signal. The barrier layer is configured to prevent contaminants from entering the bonding layer. The barrier layer is proximate to the bonding layer. The diffusion barrier layer is configured to prevent contaminants from entering the bonding layer. The diffusion barrier layer is proximate to the barrier layer. The diffusion barrier layer has a thickness that allows a received RF signal to penetrate the diffusion barrier layer to a conductive layer proximate to the diffusion barrier layer.

In some implementations, the bonding layer, the barrier layer, and the diffusion barrier layer can be embodied in a surface treatment coating. According to a particular implementation, the bonding layer may include gold. In various implementations, the bonding surface can be configured for wire bonding. According to a number of implementations, the barrier layer can include palladium.

According to a particular implementation, the diffusion barrier layer may include nickel. In some implementations, the thickness of the diffusion barrier layer can range from about 0.04um to about 0.7 um. According to a number of implementations, the thickness of the diffusion barrier layer can be no more than about 0.5 um. According to various implementations, the thickness of the diffusion barrier layer can be no more than about 0.35 um. According to a particular implementation, the thickness of the diffusion barrier layer may not exceed about 0.75 um. In some implementations, the thickness of the diffusion barrier layer can be less than a skin depth of nickel at a frequency of about 0.45 GHz.

According to some implementations of the invention, the thickness of the diffusion barrier may be less than a skin depth of the diffusion barrier layer at a frequency of about 0.45 GHz.

According to several implementations related thereto, the conductive layer can include one or more of copper, aluminum, or silver. For example, in particular embodiments, the conductive layer may comprise copper. In various implementations, substantially all of the received RF signal may propagate in the conductive layer.

According to a particular implementation, the bonding layer may be gold, the barrier layer may be palladium, and the diffusion barrier layer may be nickel. In some of these implementations, the thickness of the diffusion barrier layer may be in a range from about 0.04um to about 0.7 um. According to a number of implementations, the thickness of the diffusion barrier layer can be no more than about 0.5 um. According to a particular implementation, the thickness of the diffusion barrier layer may not exceed about 0.35 um. According to some implementations, the thickness of the diffusion barrier layer may not exceed about 0.75 um.

Another aspect of the invention is a diffusion barrier layer configured for use in an RF transmission line. The diffusion barrier layer includes a material and has a thickness. The thickness of the diffusion barrier layer is sufficiently small so as to allow RF signals to penetrate the diffusion barrier layer.

In a particular embodiment of this aspect of the invention, the material comprises nickel. According to some of these implementations, the thickness of the diffusion barrier layer may be in a range from about 0.04um to about 0.7 um. According to a number of implementations, the thickness of the diffusion barrier layer can be no more than about 0.5 um. According to some implementations, the thickness of the diffusion barrier layer may not exceed about 0.35 um. According to a particular implementation, the thickness of the diffusion barrier layer may not exceed about 0.75 um. In various implementations, the thickness of the diffusion barrier layer may be less than a skin depth of nickel at a frequency of about 0.45 GHz.

According to several implementations related thereto, the thickness of the diffusion barrier layer can be about less than a skin depth of the material at a frequency of about 0.45 GHz.

According to some implementations, substantially all RF signals penetrating the diffusion barrier layer may travel in a conductive layer proximate the diffusion barrier layer.

In various implementations, the material and/or the thickness of the diffusion barrier layer can prevent contaminants from passing through the diffusion barrier layer.

Another aspect of the invention is a mobile device that includes a transmission line, an antenna, and a battery. The emitter line includes a bonding layer, a barrier layer, a diffusion barrier layer, and a conductive layer. The bonding layer has a bonding surface. The barrier layer is proximate to the bonding layer. The diffusion barrier is a layer proximate to the barrier layer. The conductive layer is proximate to the diffusion barrier layer. The barrier layer and the diffusion barrier layer are configured to prevent conductive material from the conductive layer from entering the bonding layer. The diffusion barrier layer has a thickness sufficiently small so as to allow an RF signal to penetrate the diffusion barrier layer and propagate in the conductive layer. The antenna is coupled to the transmit line and configured to transmit an RF output signal. The emission line is configured to extend an amount of time that the battery is discharged.

According to a particular implementation, the mobile device may include a power amplifier having an output coupled to the transmit line. In some of these implementations, the output of the power amplifier may be coupled to the transmit line via a wire bond. According to various implementations, the transmit line may be configured to transmit an RF signal from the power amplifier to an RF switch. According to some implementations, the transmit line may be configured to transmit an RF signal from the power amplifier to a filter.

According to a number of implementations, the mobile device may include a filter having an output coupled to the transmission line. In some implementations, the transmit line can be configured to transmit an RF signal from the filter to an RF switch. According to various implementations, the transmit line may be configured to transmit RF signals from the filter to the antenna.

According to some implementations, the mobile device may include an RF switch having an output coupled to the transmit line. In a particular implementation, the transmit line is configured to transmit an RF signal from the RF switch to the antenna. According to various implementations, the transmit line is configured to transmit an RF signal from the RF switch to a filter.

According to certain specific implementations of the present disclosure, the diffusion barrier layer may include nickel. In some of these implementations, the thickness of the diffusion barrier layer may be in a range from about 0.04um to about 0.7 um. In a number of implementations, the thickness of the diffusion barrier layer can be no more than about 0.5 um. In some implementations, the thickness of the diffusion barrier layer can be no more than about 0.35 um. In a particular implementation, the thickness of the diffusion barrier layer may not exceed about 0.75 um. In various implementations, the thickness of the diffusion barrier layer may be less than a skin depth of nickel at a frequency of about 0.45 GHz.

In a number of implementations, the thickness of the diffusion barrier layer can be less than a skin depth of the material at a frequency of about 0.45 GHz. According to certain specific implementations, substantially all RF signals may travel in the conductive layer of the transmission line. According to some implementations, the bonding layer, the barrier layer, and the diffusion barrier layer may be embodied in a surface treatment coating.

Another aspect of the invention is a laminated panel comprising a substrate. The substrate includes a transmit line configured for transmitting an RF signal. The emitter line has a bonding layer, a barrier layer, a diffusion barrier layer, and a conductive layer. The bonding layer has a bonding surface configured for bonding with a conductor separated from the conductive layer. The barrier layer is configured to prevent contaminants from entering the bonding layer. The diffusion barrier layer includes a material and has a thickness such that contaminants are prevented from diffusing through the diffusion barrier layer and between the conductive layer and the bonding layer. The thickness of the diffusion barrier layer is sufficiently small so as to allow an RF signal from a conductor to penetrate to the conductive layer.

According to a particular implementation, the diffusion barrier layer may be nickel. In some of these implementations, the diffusion barrier layer may have a thickness less than a skin depth of nickel at a frequency of about 0.45 GHz.

In a number of implementations, the bonding layer can include gold, the barrier layer can include palladium and the diffusion barrier layer can include nickel. In some of these implementations, the thickness of the diffusion barrier layer may be less than about 0.75 um.

Another aspect of the invention is a module comprising a substrate, a first RF component, and a second RF component. The substrate includes a conductor and an emission line. The emitter line has a bonding layer, a barrier layer, a diffusion barrier layer, and a conductive layer. The bonding layer has a bonding surface configured to bond with the conductor. The barrier layer and the diffusion barrier layer are configured to prevent contaminants from entering the bonding layer. The thickness of the diffusion barrier layer is sufficiently small so as to allow an RF signal from the conductor to penetrate to the conductive layer. The first RF component is coupled to the substrate and configured to generate an RF signal. The second RF component is coupled to the substrate and configured to receive RF signals from the first component via the transmission line.

In a particular embodiment, the substrate is a laminate substrate. According to some of these implementations, the substrate may include a surface treatment plating including the bonding layer, the barrier layer, and the diffusion barrier layer.

According to a number of implementations, the diffusion barrier layer can include nickel. In a number of implementations, the thickness of the diffusion barrier layer can be no more than about 0.7 um. In some embodiments, the thickness may not exceed about 0.35 um. In a particular implementation, the thickness of the diffusion barrier layer may not exceed about 0.75 um. In various implementations, the thickness of the diffusion barrier layer may be less than a skin depth of nickel at a frequency of about 0.45 GHz. According to a particular embodiment, the conductive layer may include copper. In some implementations, the thickness of the diffusion barrier layer can be less than a skin depth of the material at a frequency of about 0.45 GHz.

According to various implementations, the bonding layer is configured for wire bonding and the conductor can be electrically coupled to the bonding layer via wire bonding.

According to a particular implementation, substantially all RF signals may propagate from the first RF component to the second RF component in the conductive layer.

In various implementations, the first RF component may include a power amplifier. According to some of these implementations, the second RF component may include a filter and/or an RF switch.

According to some implementations, the first RF component may include an RF switch. According to some of these implementations, the second RF component may include a power amplifier and/or a filter.

In certain other implementations, the first RF component may include a filter. According to some of these implementations, the second RF component includes a power amplifier and/or an RF switch.

According to a number of implementations, the barrier layer can be positioned between the bonding layer and the diffusion barrier layer.

Yet another aspect of the invention is an RF transmission line comprising a conductive layer and a surface treatment plating on the conductive layer. The surface treatment plating includes a gold layer, a palladium layer proximate the gold layer, and a nickel layer proximate the palladium layer. The nickel layer has a thickness that allows an RF signal received at the gold layer to penetrate the nickel layer and propagate in the conductive layer. In still other implementations, the gold layer is configured for wire bonding.

In some other embodiments, the thickness of the nickel layer may range from about 0.04um to about 0.7 um. According to a number of embodiments, the thickness of the nickel layer can be no more than about 0.5 um. According to particular embodiments, the thickness of the nickel layer may not exceed about 0.35 um. According to some embodiments, the thickness of the nickel layer may not exceed about 0.75 um.

According to certain additional implementations, the thickness of the nickel layer may be less than a skin depth of nickel at a frequency of about 0.45 GHz. According to some implementations, the conductive layer may include one or more of copper, aluminum, or silver. For example, the conductive layer may include copper.

According to a number of implementations, substantially all of the RF signal can propagate in the conductive layer.

For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of these aspects of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein throughout.

XI tantalum nitride terminated through-wafer vias

Apparatus and methods of tantalum nitride terminated through-wafer vias are described herein and are considered in connection with one or more of the other aspects, features or characteristics of the invention. In a specific implementation thereof, a tantalum nitride (TaN) stop layer is formed on a first or front side of a gallium arsenide (GaAs) wafer, and a gold conductive layer is formed over the TaN stop layer. Thereafter, through-wafer vias are etched into the second or backside of the GaAs wafer so as to extend through the GaAs wafer and the first or inner portion of the TaN stop layer to reach the gold conductive layer. In a particular implementation considered in conjunction therewith, the through-wafer via is electroplated with a nickel vanadium (NiV) barrier layer, a gold seed layer, and a copper layer. During through-wafer via formation, a second or outer portion of the TaN stop layer is maintained and configured to surround the interface between the gold conductive layer and the copper layer so as to inhibit diffusion of copper into the GaAs wafer.

TaN-terminated through-wafer vias can provide improved metal adhesion and reduced copper migration relative to schemes using silicon nitride terminations and sputtered barrier layers. Furthermore, in particular implementations, the use of a TaN stop layer to terminate the through-wafer via may permit the location or positioning of the through-wafer via to be moved without changing fabrication or lithography masks associated with transistor structures formed on the front side of the GaAs wafer. Configuring the through-wafer vias to be movable without changing photolithographic masks associated with the transistors may increase design flexibility and/or reduce time and costs associated with progressive adjustment or factory inspection of finished products of integrated circuit designs including the through-wafer vias.

XII via density and placement in radio frequency shielding applications

One aspect of the invention is a method for determining via placement. The method includes obtaining electromagnetic interference data about an initial via placement of a Radio Frequency (RF) component. The RF component is positioned between a first conductive layer and a second conductive layer. A via is included in the connection between the first conductive layer and the second conductive layer. The via and the first and second conductive layers form at least a portion of an RF isolation structure surrounding the RF component. The method also includes determining an updated via placement based at least in part on the initially placed electromagnetic interference data.

In some embodiments of the present invention, determining updated via placement may include: identifying a selected defined region around a perimeter of the RF component based on the electromagnetic interference data of the initial placement, the selected defined region associated with higher electromagnetic interference as compared to other defined regions around the perimeter of the RF component in the initial placement; and increasing the density of vias in the selected defined region in the updated placement as compared to the density of vias in the selected defined region in the initial placement. Alternatively or additionally, the method may comprise: identifying a defined region around a perimeter of the RF component associated with a permissible level of electromagnetic interference in the initial placement based on the electromagnetic interference data of the initial placement; and reducing the density of vias in the defined region in the updated placement as compared to the density of vias in the initial placement. According to a particular embodiment, the electromagnetic interference data of the initial via placement corresponds to unshielded RF components.

The method of the invention may be repeated any suitable number of times. For example, the method may comprise: obtaining electromagnetic interference data for updated via placements around the RF component; and determining another updated via placement based at least in part on the updated placed electromagnetic interference data.

According to some embodiments, electromagnetic interference data may be obtained for at least two different operating modes of the RF component in the initial via placement.

Another aspect of the invention of the present disclosure is a packaged module. The packaged module includes a substrate configured to receive at least one component. The packaged module also includes a Radio Frequency (RF) component coupled to a major surface of the substrate. The packaged module includes a first conductive layer disposed below the RF component, wherein the first conductive layer is configured at ground potential. The packaged module includes a plurality of vias disposed around the RF components in the substrate. The plurality of vias has a higher density in a first area of the packaged module than a second area of the packaged module, wherein the first area is associated with higher electromagnetic interference than the second area. The packaged module includes a second conductive layer disposed over the RF component. The second conductive layer is electrically coupled to the plurality of vias such that the first conductive layer, the plurality of vias, and the second conductive layer form at least a portion of an RF isolation structure surrounding the RF component.

In a particular embodiment of the present invention, the first region is disposed along a periphery of the packaged module and the second region is disposed along the periphery of the packaged module. According to some of these embodiments, the first region and the second region have about the same width in a dimension substantially parallel to an outer edge of the packaged module. The plurality of vias may be aligned along the periphery of the packaged module. According to a particular embodiment, the first region may have a highest via density in any region along a periphery of the packaged module that has at least as large an area as the first region. In some embodiments, the first region may have about the same area as the second region.

According to several embodiments of this aspect of the invention, the RF component may be configured to emit more radiation to the first region than to the second region. Alternatively or additionally, the packaged module is configured such that the first region is exposed to more radiation than the second region. In a particular embodiment, the first region may correspond to a hot spot of the packaged module and the second region may correspond to a low-emissivity region of the packaged module. Alternatively or additionally, the first region may be more sensitive to external electromagnetic interference than the second region.

In a particular embodiment related thereto, the packaged module can also include a conductive feature forming at least a portion of an electrical connection between the plurality of vias and the second conductive layer, the RF isolation structure including the conductive feature. For example, the conductive features may include wire bonds or metal cans. According to some embodiments, the RF component may comprise a power amplifier.

Another aspect of the invention is a packaged module comprising a substrate, an RF device, first and second conductive layers, and a plurality of vias. The substrate is configured to receive at least one component. The RF device is coupled to a major surface of the substrate. The first conductive layer is disposed below the RF component and is configured at a ground potential. The plurality of vias is disposed around the RF component. The plurality of vias has a higher density in a first region surrounding the RF assembly than a second region surrounding the RF assembly that has about the same area as the first region. The first region is more sensitive to external radiation than the second region. The second conductive layer is disposed over the RF component. The second conductive layer is electrically coupled to a plurality of vias such that the first conductive layer, the plurality of vias, and the second conductive layer form at least a portion of an RF isolation structure surrounding the RF component.

Yet another aspect of the disclosure is a wireless device that includes an antenna, a packaged module, and another module. The antenna is configured to facilitate transmission and/or reception of Radio Frequency (RF) signals. The packaged module is in communication with the antenna. The packaged module includes a substrate having a ground plane and a plurality of vias in the substrate disposed along a periphery of the packaged module. Vias of the plurality of vias are spaced closer together in a hot spot than in a low-e region along the periphery of the packaged module. The packaged module includes RF circuitry coupled to a major surface of the substrate. The packaged module also includes a second conductive layer disposed over the RF circuitry. The second conductive layer is electrically coupled to a plurality of vias such that the ground plane, the plurality of vias, and the second conductive layer form at least a portion of an RF isolation structure surrounding the RF circuitry. The other module is in communication with the packaged module.

In some embodiments of the present invention, the hot spot may be associated with electromagnetic interference generated by the packaged module and the plurality of vias may be configured to isolate the other module from electromagnetic interference associated with the hot spot. According to a particular embodiment, the hotspot may be associated with electromagnetic interference generated by the other module and the plurality of vias may be configured to shield the packaged module from electromagnetic interference associated with the hotspot.

According to a number of embodiments, the packaged module further includes a conductive feature forming at least a portion of an electrical connection between the plurality of vias and the second conductive layer, wherein the RF isolation structure includes the conductive feature. For example, the conductive features may include wire bonds.

For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, these aspects of the disclosure may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein above or below.

Semiconductor package with integrated interference shield

Features and embodiments of this aspect of the invention relate to a semiconductor device package and method of making the same that uses wire bonding process techniques to incorporate electromagnetic interference shielding into the device package. In one embodiment, a wire bonding process is used to form wire bond springs that are positioned around the device and coupled to conductive layers above and below the device, thereby forming an electromagnetic interference shield around the device. As discussed further below, the shape of the wire bond springs and the spring effect created by the wire bond springs enable a robust manufacturing process to form reliable electrical connections between conductive layers at the top of the molded package and ground planes in the substrate of the package. The use of these wire bond springs provides a flexible solution to the integrated emi shield that can be applied to any overmolded device.

One aspect of the invention relates to a packaged semiconductor module with integrated emi shielding. In one embodiment, the packaged semiconductor module includes: a substrate having a ground plane; an electronic device mounted on a surface of the substrate; a plurality of wirebond springs disposed around the electronic device and electrically coupled to the ground plane; a molding compound covering the electronic device and at least partially covering the plurality of wire bond springs; and a conductive layer disposed on a top surface of the molding compound and electrically coupled to at least some of the plurality of wirebond springs, wherein the plurality of wirebond springs, the conductive layer, and the ground plane collectively comprise the integrated electromagnetic interference shield.

In one example, the conductive layer comprises a silver filled epoxy. The wire bond springs may be made of various conductive materials, such as gold or copper wire. Each of the plurality of wirebond springs can include a continuous wire loop shaped to provide a spring effect that permits contact between the conductive layer and the wirebond spring to provide electrical coupling between the conductive layer and the wirebond spring. In one example, the electronic device is an RF device.

According to another embodiment of the present invention, a wirebond spring formed from a continuous wire loop comprises: a ball joint; partitioning the reverse curve; carrying out peak lifting; a convex region extending between the reverse-curved partition and the peak; a slanted tail region; and a substantially planar region extending between the peak and the sloped tail region, wherein the reverse-curved region is between the convex region and the ball joint. In one example, the peak is substantially vertical above the sigmoid partition. As discussed above, the wirebond springs can be formed from a variety of conductive materials, including gold or copper wires. In one example, a wirebond spring having this structure is used in the semiconductor module discussed above.

Another aspect of the invention relates to a semiconductor module package with integrated emi shielding. In one embodiment, the semiconductor module package includes: a substrate; first and second metallized connection points disposed on a first surface of the substrate; and a wirebond spring comprising a continuous wire extending between the first metalized connection point and the second metalized connection point. The wire bond spring includes: a ball bond electrically connected to the first metalized connection point; partitioning the reverse curve; carrying out peak lifting; a convex region extending between the reverse-curved partition and the peak; a substantially planar region proximate the peak; and an angled tail region extending between the substantially planar region and the second metallized connection point. In one example, the semiconductor module package further includes a ground plane disposed on the substrate and electrically coupled to at least one of the first and second metalized connection points. In another example, the semiconductor module package further includes an electronic device and a plurality of additional wirebond springs substantially identical to the wirebond springs, wherein the plurality of wirebond springs are positioned on the substrate around a perimeter of the electronic device. In another example, the semiconductor module package further includes: a molding compound covering the electronic device and at least partially covering the plurality of wire bond springs; and a conductive layer disposed on a surface of the molding compound and electrically connected to at least some of the plurality of wirebond springs, wherein the ground plane, the conductive layer, and at least some of the plurality of wirebond springs collectively form the integrated electromagnetic interference shield.

Another aspect of these features of the invention relates to a method of manufacturing a module with integrated emi shielding. According to one embodiment, the method comprises: connecting an electronic device to a substrate; providing a metallization on the substrate; forming a plurality of wirebond springs connected to the metallization; performing a transfer molding process to encapsulate the electronic device in a molding compound and at least partially cover the plurality of wirebond springs with the molding compound; and disposing a conductive layer on a surface of the molding compound, the conductive layer electrically connected to at least some of the plurality of wirebond springs. In one example, the method further comprises: prior to disposing the conductive layer on the surface of the mold compound, ablating the surface of the mold compound to expose areas of at least some of the plurality of wirebond springs. In another example, providing metallization includes providing a ground plane and at least one wire bond contact region electrically connected to the ground plane. In another example, forming the plurality of wirebond springs includes: depositing a wire ball on the metal oxide; forming a wire loop by drawing wire from the wire ball to form the wire loop to have a first end and a second end connected to the wire ball; and connecting the second terminal to the metal oxide. In another example, depositing the conductive layer on the surface of the molding compound includes printing a silver-filled epoxy on the surface of the molding compound.

According to another embodiment of the invention, an electronic module comprises: a substrate; an electronic device disposed on the substrate; and an integrated EMI shield formed of a plurality of discrete structures disposed substantially around the electronic device, the structures having a minimum pitch defined by a fraction of a length of a signal to be shielded by the integrated EMI shield. In one example, the fraction of the length is 1/20. In another example, the plurality of discrete structures includes a plurality of wire bond springs, as discussed below.

Further aspects, embodiments, and advantages of these exemplary aspects and embodiments are discussed in detail below. Moreover, it is to be understood that both the foregoing information and the following detailed description are merely illustrative examples of various aspects and embodiments and are intended to provide an overview or framework for understanding the nature and character of the claimed aspects and embodiments. Any embodiments disclosed herein may be combined with any other embodiments in any manner consistent with the objects, aims, and needs disclosed herein, and references to "an embodiment," "some embodiments," "an alternate embodiment," "various embodiments," "one embodiment," and so forth are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment. The appearances of such terms herein are not necessarily all referring to the same embodiment. The accompanying drawings are included to provide illustration and a further understanding of the various aspects, features and characteristics of the various embodiments, and are incorporated in and constitute a part of this specification. The drawings, together with the remainder of the specification, serve to explain the principles and operations of the various described and claimed aspects and embodiments.

Various aspects, features and characteristics of the improved power amplifiers, power amplifier modules, and related systems, devices and methods described herein are obtained in accordance with the present disclosure, wherein for one particular embodiment of the present disclosure, there is provided a power amplifier including a power amplifier with GaAs bipolar transistorsAn amplifier module, the GaAs bipolar transistor having a collector, a base adjacent the collector, and an emitter, the collector having at least about 3 x 10 at a junction with the base¹⁶cm^-3The collector further having at least a first grading in which the doping concentration increases away from the base. In this embodiment, the module will further include an RF transmit line driven by the power amplifier, the RF transmit line including a conductive layer and a surface treatment plating on the conductive layer, the surface treatment plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is approximately less than the skin depth of nickel at 0.9 GHz.

In the above embodiment, the power amplifier module may advantageously further comprise an output matching network having a first termination circuit configured to match a fundamental frequency of an output of the power amplifier; and a second termination circuit configured to terminate at a phase of a harmonic of the output of the power amplifier, wherein the first termination circuit includes at least a portion of the RF transmit line.

According to one particular aspect of the invention, the power amplifier may be included on a power amplifier die having a tantalum nitride terminated through-wafer via. In this embodiment, the power amplifier die may further advantageously include: a gallium arsenide (GaAs) substrate; a gold layer disposed on a first side of the GaAs substrate; and a copper layer disposed on a second side of the GaAs substrate opposite the first side, wherein the tantalum nitride terminated through-wafer via is configured to electrically connect the gold layer to the copper layer. For additional embodiments of the present invention, the power amplifier die may further include a tantalum nitride termination region configured to surround at least a portion of an interface between the copper layer and the gold layer so as to inhibit diffusion of copper from the copper layer into the GaAs substrate.

In any of the above embodiments, the GaAs bipolar transistor may advantageously be implemented as a Heterojunction Bipolar Transistor (HBT) included on a power amplifier die and the power amplifier die may further include a resistor formed from at least one HBT layer.

Any of the above embodiments may alternatively further comprise: a wire bond in contact with the gold layer of the RF transmission line; at least one edge adjacent to the wire bond; and at least one sidewall adjacent to the at least one edge, the at least one sidewall being free of the nickel layer of the RF emission line, the palladium layer of the RF emission line, and the gold layer of the RF emission line.

In the above particularly preferred embodiment, the power amplifier module may further advantageously further comprise a combination of: (1) a dual mode control interface having a front end core configured to provide a serial interface; (2) a voltage input/output (VIO) pin configured to receive a VIO signal that determines whether an operating mode of the front-end core is set to one of an active state and an inactive state, the dual-mode control interface configured to provide a general purpose input/output (GPIO) interface when the front-end core is set to the inactive state; (4) a combinational logic block configured to provide an enable signal and a mode signal to the enable level shifter and the mode level shifter, respectively; and (5) a power-on reset configured to select the enable signal and the mode signal to be provided to the enable level shifter and the mode level shifter, respectively, based on the VIO signal.

To achieve other advantages associated with the above embodiments, the power amplifier module may further include an RF isolation structure including wire bonds disposed along a periphery of the power amplifier module.

According to another broad aspect of the invention, there is also provided a power amplifier module comprising a power amplifier configured to receive an RF input signal and generate an amplified RF output signal, the power amplifier comprising a GaAs bipolarA transistor, said GaAs bipolar transistor having a collector, a base adjacent said collector, and an emitter, said collector having at least about 3 x 10 at a junction with said base¹⁶cm^-3The collector further having at least a first grading in which the doping concentration increases away from the base; and the power amplifier module further includes an output matching network in combination with the power amplifier, the output matching network including: a first termination circuit configured to match an impedance of a fundamental frequency of the amplified RF output signal; and a second termination circuit separate from the first termination circuit, the second termination circuit configured to terminate with a phase corresponding to a harmonic frequency of the amplified RF output signal. In this embodiment, the power amplifier may drive an RF transmit line having a diffusion barrier layer comprising nickel and having a thickness of less than about 0.5 μm. And wherein a wire bond may be provided that electrically connects the output of the power amplifier to the RF transmit line, wherein the wire bond is included in the first termination circuit. Alternatively, such an embodiment may advantageously further include a dual mode control interface configured to provide both a Radio Frequency Front End (RFFE) serial interface and a tri-mode general purpose input/output (GPIO) interface on a single die. And optionally in combination with the dual mode control interface, the power amplifier module may further include an RF isolation structure having wire bonds disposed along the periphery of the power amplifier module.

According to yet another main aspect of the present invention, there is alternatively provided a power amplifier module having: (1) a power amplifier configured to receive an RF input signal and generate an amplified RF signal; (2) an RF transmit line configured to propagate the amplified RF signal, the RF transmit line comprising: a gold layer configured to receive the amplified RF signal; a palladium layer proximate the gold layer; and a diffusion barrier layer proximate to the palladium layer; and a conductive layer proximate to the diffusion barrier layer, the diffusion barrier layer comprising nickel and having a thickness about less than a skin depth of nickel at 0.45 GHz; (3) first terminationCircuitry configured to match an impedance of a fundamental frequency of the amplified RF signal, the first termination circuitry including at least a portion of the RF transmit line; and (4) a second termination circuit separate from the first termination circuit, the second termination circuit configured to terminate with a phase corresponding to a harmonic frequency of the amplified RF signal, the power amplifier electrically coupled to the first termination circuit by means of at least one wire bond and the power amplifier electrically coupled to the second termination circuit by means of a different number of wire bonds than the first termination circuit. In this alternative embodiment, the power amplifier may advantageously comprise a GaAs bipolar transistor having a collector, a base adjacent the collector, and an emitter, the collector having at least about 3 x 10 at the junction with the base ¹⁶cm^-3The collector further having at least a first grading in which the doping concentration increases away from the base. Any version of the power amplifier module of this particular embodiment may advantageously further comprise: a dual-mode control interface configured to provide both a Radio Frequency Front End (RFFE) serial interface and a general purpose input/output (GPIO) interface on a single die; and an RF isolation structure in combination with or in place of the dual mode control interface, the RF isolation structure including a wire bond disposed along a periphery of the power amplifier module.

In a further preferred embodiment of the invention as regards the RF module, there is provided a power amplifier module comprising: (1) a substrate configured to receive a plurality of components, the substrate having an RF transmission line thereon, the RF transmission line having an electrically conductive layer and a surface treatment plating on the electrically conductive layer, the surface treatment plating having a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer having nickel and having a thickness less than a skin depth of nickel at a frequency of about 0.45 GHz; (2) a first die coupled to the substrate, the first die having a power amplifier including an output electrically connected to the gold layer of the RF transmission line, the first die further having passive components including properties dependent on one or more conditions of the first die; and the present module further includes (3) a second die coupled to the substrate, the second die having bias generation circuitry configured to generate a bias signal based at least in part on an indicator of the property of the passive component of the first die.

According to another aspect of the invention, particular embodiments of the module described in the above paragraph may further include an output matching network having a first termination circuit configured to match a fundamental frequency of an output of the power amplifier; and a second termination circuit configured to terminate at a phase of a harmonic of the output of the power amplifier, the first termination circuit including at least a portion of the RF transmit line. And in combination with or instead of the above, the module can be configured such that the first die has tantalum nitride terminated through-wafer vias and/or includes HBT devices and resistors formed from at least one HBT layer. As an additional aspect of this embodiment, the power amplifier module of the present disclosure may optionally further include an RF isolation structure having a plurality of vias in the substrate disposed around the power amplifier and a desired number of wire bonds disposed along a periphery of the power amplifier module, the plurality of vias having a higher density in a first area of the power amplifier module than a second area of the power amplifier module, wherein the first area is associated with higher electromagnetic interference than the second area.

According to yet another preferred embodiment of the present invention, there is advantageously provided, for a particular application, a power amplifier module including a substrate configured to receive a plurality of components and further configured in accordance with the following. The substrate has a surface treatment plating comprising a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer. The diffusion barrier layer advantageously comprises nickel and has a thickness that is about less than the skin depth of nickel at 0.45 GHz. This embodiment will also include, in combination with the above, a power amplifier die having a power amplifier and at least one tantalum nitride terminated through-wafer via. Here, the power amplifier is configured to receive an RF input signal and is also configured to generate an amplified RF signal. Finally, as a primary element of the present invention, this embodiment will further advantageously include, in combination with all of the previous elements of the present invention, a termination circuit configured to terminate in the phase of a harmonic of the amplified RF signal, wherein this termination circuit is provided with at least one wire bond configured to electrically couple the output of the power amplifier to the gold layer of the surface treatment plating.

In embodiments described in only paragraphs above this paragraph, the power amplifier die of the present invention may advantageously include: a passive component on a die; a first lead electrically connected to the on-die passive component; and a second lead configured to receive the amplified RF signal. In the particular implementation, a first portion of the surface treatment plating may be electrically connected to the first lead and a second portion of the surface treatment plating may be electrically connected to the second lead to thereby conduct current from the first portion of the surface treatment plating when so desired. In any of these embodiments, the power amplifier die may include heterojunction bipolar transistors and resistors, optionally including a layer of heterojunction bipolar material. And alternatively or in combination with the above, the power amplifier may comprise a GaAs bipolar transistor having a collector, a base adjacent the collector, and an emitter, wherein the collector has at least about 3 x 10 at a junction with the base¹⁶cm^-3And the collector further has at least a first grading in which the doping concentration increases away from the base. In one particular embodiment above, the power amplifier module may further advantageously include, when so desired: (1) a dual mode control interface having a front end core configured to provide a serial interface; (2) a voltage input/output (VIO) pin configured to receive a VIO signal, wherein the VIO signal determines that an operating mode of the front-end core is set to An active state or an inactive state, wherein the dual mode control interface is configured to provide a general purpose input/output (GPIO) interface when the front end core is set to the inactive state; (3) a combinational logic block configured to provide an enable signal and a mode signal to the enable level shifter and the mode level shifter, respectively; and (4) a power-on reset configured to select the enable signal and the mode signal to be provided to the enable level shifter and the mode level shifter, respectively, based on the VIO signal.

This application hereby incorporates by reference the full disclosure of the following applications: united states provisional patent application No. 61/659,848 entitled "power amplifier module" (powerampifieldodule) filed on day 14/6/2012; united states provisional patent application No. 61/659,701 entitled "PROCESS compensated HBT power amplifier bias circuit and method" (PROCESS-compensated HBT power amplifier biasing circuit and method) filed on day 14/6/2012; and us provisional patent application No. 61/659,834 entitled "RF power amplifier with semiconductor resistor" (rfpowerramp @ positive voltage capacitor) filed on 14/6/2012.

This application also hereby incorporates by reference the entire disclosure of the following applications: united states patent application No. 13/040,127 entitled "wire bond pad system and method" (wirebondpaddsystetmandmethod), filed on 3/2011; united states patent application No. 13/040,137 entitled "apparatus and method for reducing the effects of high RF loss plating" (apparatusandmethods for treating copper plating) filed on 3/2011; united states patent application No. 13/460,521 entitled "bipolar transistor with graded collector" (bipolar transistor) filed on 30/4/2012; U.S. patent application No. 13/658,488 entitled "dual mode power amplifier control interface with dual mode general purpose input/output interface" (dual mode power amplifier circuit) filed on day 10/23 of 2012; U.S. patent application No. 13/658,522 entitled "dual mode power amplifier control interface with tri-mode general input/output interface" (dual mode power amplifier circuit) filed on day 10/23 of 2012; united states patent application No. 13/543,472 entitled "signal path termination" (signaling) filed on 8.7.2011; U.S. patent application No. 12/939,474 entitled "bipolar and FET device structure" (bipolaranddfetdevicestrure) filed on 11/4/2010; united states patent application No. 13/288,427 entitled "device and method related to a structure having an HBT and a FET" (devicescandmethodologiesetasttowuchuttuschuthavingbtanfet) filed on 3/11/2011; U.S. patent application No. 13/464,775 entitled "transmission line for high performance radio frequency applications" (transmissionin line organic light emitting manceradar frequency enhanced yapplications) filed on 5, 4/2012; U.S. patent application No. 13/485,572 entitled "via density and placement in radio frequency shielding applications" (viadensatonatdplacementradiofrequency resonance imaging applications) filed on 31/5/2012; united states patent application No. 13/893,605 entitled "system and method for providing electromagnetic interference shielding for integrated circuit modules" (system and method for providing electromagnetic interference shielding for integrated circuit modules) filed on 5, 14/2013; united states patent application No. 13/893,614 entitled system and method for controlling electromagnetic interference of an integrated circuit module (system and method for controlling electromagnetic interference) filed on 14/5/2013; and us patent application No. 13/904,566 entitled semiconductor package with metallic coating layer (semiconductor package) filed on 29.5.2013.

In addition, the present application hereby incorporates by reference the entire disclosure of the following applications: international application No. PCT/US2008/071832 entitled "integrated EMI shielded wire-bonded spring connection and manufacturing method" (wireboun dspringcontractorusandmethod for manufacturing a wire-bonded spring connection and manufacturing method) filed on 31/7/2008; and international application No. PCT/US201I/059208, entitled "apparatus and method relating to a structure having an HBT and a FET" (devicescandmethodologieassociated lattostrucuthavingbtanndfet), filed on 3/11/2011.

Drawings

Other aspects and features of the present invention, as well as additional features contributing thereto and advantages arising therefrom, will be apparent from the following description of preferred embodiments of the invention shown in the accompanying drawings, in which:

fig. 1 is a block diagram of a power amplifier module;

fig. 2 illustrates an enlarged portion of an exemplary IC module including wire bond pads, in accordance with a particular embodiment;

FIG. 3 shows a flow diagram of an exemplary process for forming wire bond pads;

FIG. 4 illustrates a cross-section of Ni/Pd/Au wire bond pads on the IC module of FIG. 2, according to a specific embodiment of the invention;

Fig. 5 depicts an enlarged portion of an exemplary RFIC module including wire bond pads, in accordance with a particular embodiment;

FIG. 6 presents a flow diagram of an exemplary process for forming Ni/Pd/Au wire bond pads, according to a specific embodiment of the present disclosure;

fig. 7 illustrates a cross section of Ni/Pd/Au wire bond pads on the RFIC module of fig. 5, in accordance with an embodiment of the invention;

FIG. 8 is a graph comparing RF loss for traces having edge/sidewall exposed surfaces to edge/sidewall plated surfaces;

9A, 9B, 9C, 9D, 9E, and 9F illustrate exemplary layouts of wire bond regions with minimized edges and sidewalls exposed to plating;

fig. 10 shows an enlarged portion of an RFIC module having an RFIC that includes an on-die passive device, according to an embodiment of the invention;

fig. 11 illustrates an enlarged portion of an RFIC module having an RFIC that includes an on-die passive device according to another embodiment of the invention;

FIG. 12A depicts an illustrative cross-section of a bipolar transistor according to a specific embodiment of the invention;

FIG. 12B is a graph of example doping concentrations for the portion of the bipolar transistor of FIG. 12A;

FIG. 12C is a diagram illustrating example materials corresponding to portions of the bipolar transistor of FIG. 12A;

FIG. 13 is a graph illustrating the relationship between breakdown voltage and current density for the bipolar transistor of FIG. 12A and a state of the art bipolar transistor;

FIG. 14A shows an illustrative cross-section of a bipolar transistor according to another embodiment of the invention;

FIG. 14B is a graph of example doping concentrations for the portion of the bipolar transistor of FIG. 14A;

FIG. 14C is a diagram showing example materials corresponding to portions of the bipolar transistor of FIG. 14A;

FIG. 14D depicts an illustrative cross-section of a bipolar transistor according to another embodiment of the invention;

FIG. 14E is a graph of example doping concentrations for the portion of the bipolar transistor of FIG. 14D;

FIG. 14F is a diagram illustrating example materials corresponding to portions of the bipolar transistor of FIG. 14D;

FIG. 15 is an illustrative process flow diagram for fabricating a bipolar transistor in accordance with an embodiment of the method of the present invention;

FIG. 16 is a block diagram of one embodiment of a power amplifier module including a bipolar transistor having one or more features described herein;

FIG. 17 is an illustrative block diagram of one particular wireless device according to the present disclosure including the power amplifier module of FIG. 16;

FIG. 18 is a block diagram of another embodiment of a wireless device, according to a particular aspect of the present disclosure;

FIG. 19 illustrates an embodiment of a digital control interface implemented according to a particular aspect of the present disclosure;

FIG. 20 is a schematic diagram of an embodiment of a level shifter implemented in accordance with the present invention;

FIG. 21 is a flow chart of a process for operation of a digital control interface according to an aspect of the present invention;

FIG. 22 is a block diagram of yet another embodiment of a wireless device, according to a particular aspect of the present disclosure;

FIG. 23 illustrates another embodiment of a present digital control interface, according to certain other aspects of the present disclosure;

FIG. 24 is a schematic diagram of an embodiment of a combinational logic block according to the present invention as implemented in the digital control interface of FIG. 23;

FIG. 25 presents yet another embodiment of the digital control interface of the present invention implemented in accordance with an additional level shifting function;

FIG. 26 is another embodiment of a current combinational logic block implemented in the digital control interface of FIG. 25;

FIG. 27 is a diagrammatic representation of a semiconductor die including an integrated circuit, die-dependent components, and bias circuitry in accordance with one embodiment of the present invention;

FIG. 28 represents a dual die configuration of the assembly of FIG. 27;

FIG. 29 shows a dual die configuration utilizing HBT dies and Si dies;

figure 30 is a schematic representation of a power amplifier circuit according to the present invention;

Figure 31 is a schematic and block diagram of one particular configuration of a power amplifier circuit including a resistance for generating a bias signal, in accordance with the present invention;

FIGS. 32, 33 and 34 are graphs showing how the resistance of FIG. 31 is related to beta parameter and temperature;

FIG. 35 shows an example of a V-I circuit to generate a compensated control signal in accordance with this disclosure;

FIG. 36 is a graph illustrating different plots of output voltage versus temperature for different Vbatt settings for the V-I circuit of FIG. 35;

FIGS. 37A and 37B show graphs of quiescent current versus temperature for a first stage and a second stage of an uncompensated power amplifier example;

38A and 38B are graphs of quiescent current versus temperature for the first and second stages of the compensated power amplifier of the present invention;

FIG. 39 shows a plot of calculated gain versus power output at different example temperatures;

FIG. 40 presents plots of gain versus power output for different combinations of the varied parameters described with reference to FIGS. 38A and 38B;

fig. 41A is a plan view of a power amplifier module implemented in accordance with another particular embodiment of the invention;

fig. 41B is a side view of the power amplifier module of fig. 41A;

FIG. 42 schematically depicts an example of a particular embodiment of a wireless device implemented according to a particular aspect of the present disclosure;

Figure 43 is a diagram illustrating a cross-sectional view of a structure including a BiFET exemplified by the present invention;

FIG. 44 is a drawing showing a cross-sectional view of an alternative embodiment of the structure of FIG. 43;

FIG. 45 shows steps of a process according to the present invention that may be implemented to fabricate the structure of FIG. 43;

FIG. 46 presents process steps of the present invention that can be implemented to fabricate the structure of FIG. 44;

figure 47 shows process steps of one embodiment of the invention that can be implemented to fabricate the HBT of figures 43 and 44;

FIG. 48 shows steps of a process of the present invention that may be implemented to fabricate the FET of FIG. 43 and the first FET of FIG. 44;

FIG. 49 shows process steps according to aspects of the invention that may be implemented to fabricate the second FET of FIG. 44;

figure 50 is a block diagram showing that a semiconductor die having circuitry, such as Power Amplifier (PA) circuitry, for some embodiments of the invention may include a BiFET device having one or more features as described herein;

fig. 51 is a block diagram showing that a semiconductor die having PA controller and/or switch controller circuitry may include a BiFET device having one or more features as described herein in some embodiments;

FIG. 52 is a block diagram showing that a packaged module may include a die having one or more features as described herein in some embodiments;

FIG. 53 is a block diagram showing that in some embodiments a wireless device may include a module, such as a packaged module (FIG. 52), having one or more features as described herein;

figure 54 schematically shows a semiconductor die with an integrated circuit;

figure 55 shows an example of an HBT having a layer stack formed on a semiconductor substrate in accordance with the present invention;

figures 56A, 56B, 56C, 56D, 56E, 56F and 56G present embodiments of semiconductor resistors that can be formed using the various layers associated with the HBT of figure 55;

56A-1, 56B-1, 56C-1, 56D-1, 56E-1, 56F-1, and 56G-1 are electrical schematic diagrams of the semiconductor resistors of FIGS. 56A, 56B, 56C, 56D, 56E, 56F, and 56G, respectively;

FIG. 57A is a side view of a semiconductor structure including a resistive region according to the present invention;

FIG. 57B is a top plan view of the structure of FIG. 57A showing the terminals of the resistive region provided therein;

FIG. 57C is a schematic representation of a resistor formed from the resistive region of FIG. 57A;

FIG. 58 shows the resistor of FIG. 57C connected to a transistor;

FIGS. 59A, 59B, and 59C are schematic representations of different embodiments of the circuit element of FIG. 58;

FIG. 60 is a schematic and block diagram representation of a semiconductor resistor formed on a die in accordance with the present invention;

FIG. 61A is a schematic block diagram of an illustrative wireless device;

FIG. 61B is a schematic block diagram of another illustrative wireless device;

FIG. 61C is a block diagram of an illustrative power amplifier module that may be used in the wireless device of FIGS. 61A and 61B;

figure 62 is a schematic and circuit block diagram showing a power amplifier system with termination circuitry according to an embodiment of the present disclosure;

FIG. 63A is a block diagram illustrating an example power amplifier module with a termination circuit according to another embodiment of the invention;

FIG. 63B illustrates an example substrate, according to a specific embodiment of the invention;

64A, 64B, and 64C show simulation results comparing the performance of the embodiment of FIG. 63A with a conventional implementation;

FIG. 65 is a block diagram illustrating a die and an example termination circuit according to another embodiment of the invention;

FIG. 66 is a process flow diagram of an illustrative method of manufacturing a module in accordance with yet another embodiment of the invention;

FIG. 67A is a cross-section of an embodiment of a transmission line according to certain aspects of the present invention;

FIG. 67B shows schematically the example transmission lines of FIG. 67A;

FIG. 68A is a side view of a wire bond attached to the transmission wire of FIG. 67A;

FIG. 68B illustrates an example of a substrate including the transmission line of FIG. 67A;

FIG. 68C shows an example of an array comprising the plurality of substrates of FIG. 68B;

FIG. 69 is a schematic block diagram of an example module including the transmit line of FIG. 67A;

70A, 70B, 70C, and 70D are graphs illustrating relationships among the emission lines of FIG. 67A and other emission lines implemented in the module of 69;

FIG. 71 is a block diagram of two Radio Frequency (RF) components coupled to each other via the transmission line of FIG. 67A;

72A, 72B, 72C, 72D, 72E, and 72F are schematic block diagrams of various example RF components that may be electrically coupled to one another via the transmit lines of FIG. 67A;

FIG. 73 is a schematic block diagram of another example mobile device implemented in accordance with the present invention to include the transmission line of FIG. 67A;

figure 74A is a plan view of a wafer according to one embodiment of the present invention;

FIG. 74B is an enlarged plan view of a portion of the wafer of FIG. 74A;

FIG. 75A illustrates the formation of a passivation layer over a first or front side of a substrate in accordance with the present invention;

FIG. 75B shows a photoresist layer being formed and patterned over the passivation layer and used to pattern the passivation layer in accordance with the present invention;

FIG. 75C depicts the formation of a tantalum nitride (TaN) stop layer using a photoresist layer as a mask, in accordance with the present invention;

FIG. 75D depicts the removal of the photoresist layer and the formation of a conductive layer over the TaN stop layer, in accordance with the present invention;

FIG. 75E shows a carrier plate being attached to the front side of the substrate and a photoresist layer being formed and patterned on the back side of the substrate, as taught herein;

FIG. 75F depicts the formation of a through-wafer via into the substrate from the backside, in accordance with this aspect of the invention;

FIG. 75G illustrates the removal of the photoresist layer and the formation of a barrier layer over the through-wafer via as part of one embodiment of the backside process of the present invention;

FIG. 75H shows forming a seed layer over a barrier layer and a copper layer over the seed layer;

FIG. 75I depicts removal of the carrier plate from the front side of the wafer;

FIG. 76A is a top plan view of an illustrative packaged module in accordance with the present invention;

FIG. 76B shows a cross-section of the packaged module of FIG. 76A taken along line A-A of FIG. 76A;

FIG. 77 shows process steps of the invention that may be implemented to fabricate a packaged module including a die with an Integrated Circuit (IC);

78A and 78B show a front side and a back side of an example laminated panel configured to receive a plurality of dies to form a packaged module;

FIGS. 79A, 79B, and 79C show various views of a laminated substrate configured to produce panels of individual modules in accordance with the present invention;

FIG. 80 shows an example of a fabricated semiconductor wafer having a plurality of dies to be singulated for mounting on a laminate substrate;

FIG. 81 depicts an individual die showing example electrical contact pads for facilitating connectivity when mounted on a laminate substrate;

FIGS. 82A and 82B show top and side views of a laminate substrate prepared for mounting example Surface Mount Technology (SMT) devices;

FIGS. 83A and 83B show top and side views of an example SMT device mounted on a laminate substrate;

FIGS. 84A and 84B show top and side views of a laminated substrate prepared for mounting dice according to the present invention;

FIGS. 85A and 85B show top and side views of a die mounted on a laminate substrate;

FIGS. 86A and 86B show top and side views of a die electrically connected to a laminate substrate by wire bonds in accordance with the present invention;

FIGS. 87A and 87B show top and side views of a wire bond formed on a laminate substrate and configured to facilitate Electromagnetic (EM) isolation between a region defined by the wire bond and a region outside the wire bond;

FIG. 88 shows a side view of a molding configuration for introducing molding compound to an area above a laminate substrate in accordance with the present invention;

FIG. 89 shows a side view of an overmold formed via the molding configuration of FIG. 88;

FIG. 90 shows the front side of a panel with an overmold;

fig. 91 shows a side view of how an upper portion of an overmold may be removed to expose an upper portion of an EM isolation wire bond;

FIG. 92A shows an image of a portion of a panel with a portion of the overmold having its upper portion removed to better expose the upper portion of the EM isolation wire bond;

FIG. 92B is a drawing similar to FIG. 92A showing the application of a metallic paint sprayed on top of the panel to form a conductive surface with the exposed upper portion of the EM isolation line;

FIG. 93 shows a side view of a conductive layer formed over an overmold such that the conductive layer is in electrical contact with an exposed upper portion of an EM isolation wire bond;

FIG. 94 shows an image of a panel in which the conductive layer may be sprayed with a metallic coating, according to the teachings of the present disclosure;

FIG. 95 shows individual packaged modules cut from a panel;

FIGS. 96A, 96B and 96C show diagrams of individual packaged modules;

FIG. 97 is a block diagram showing one or more of the modules installed on a wireless telephone board that may include one or more features as described herein;

FIG. 98A is a flow diagram of a process that may be implemented to mount a packaged module having one or more features as described herein on a circuit board (such as the phone board of FIG. 97);

FIG. 98B is a block diagram depicting a circuit board with a packaged module mounted thereon;

FIG. 98C is a block diagram showing a wireless device having a circuit board with a packaged module mounted thereon;

FIG. 98D depicts an electronic device with a Radio Frequency (RF) isolation structure;

FIG. 99A is a flow chart of an illustrative process of determining via placement in accordance with certain embodiments of the invention;

FIG. 99B is a flow chart of an illustrative process for determining via placement in accordance with another embodiment of the invention;

FIGS. 100A and 100B are illustrative electromagnetic interference (EMI) distribution profiles corresponding to different via placements;

FIG. 100C is a graphical illustration of the EMI data in FIGS. 100A and 100B;

fig. 101 is a graph illustrating a relationship between via density and reverse radiation power;

FIGS. 102A and 102B are top plan views of substrates with via placements corresponding to the EMI distribution profiles shown in FIGS. 100A and 100B, respectively;

FIG. 103 is a flow chart pertaining to process steps illustrating one example of a method of providing integrated EMI shielding as part of a packaging process in accordance with aspects of the present invention;

Figure 104 is a side view of one example of an electronic module including a substrate and one or more dies mounted thereto;

fig. 105 is a cross-sectional side view of one example of a device package incorporating an integrated EMI shield in accordance with an aspect of the present invention;

fig. 106A is a cross-sectional side view of another example of a device package incorporating an integrated EMI shield in accordance with an aspect of the disclosure;

FIG. 106B is a plan view of a portion of a device package illustrating a continuous wire bond trace in accordance with an aspect of the present invention;

FIG. 107 is an illustration of one example of a wire bond spring according to an aspect of the present invention;

FIG. 108 is a flow chart illustrating one example of a method of forming a wire bond spring in accordance with aspects of the present invention;

FIG. 109 is a detailed enlarged view of one example of a wire bond spring according to aspects of the present invention;

FIG. 110 is a diagram similar to FIG. 109 illustrating deformation of a wirebond spring during a transfer molding process in accordance with an aspect of the present invention;

FIG. 111 is a cross-sectional side view image of one example of a wire bond spring incorporated in a device package, according to an aspect of the present invention; and

fig. 112 is a plan view image of one example of a wire bond spring in accordance with aspects of the present invention.

Detailed Description

I. Introduction to

Referring now to FIG. 1, a schematic block diagram of an illustrative module 101 according to the present invention is shown. The module 101 may achieve a desired level and/or range of linearity and a desired PAE. Module 101 may include some or all portions of a power amplifier system. The module 101 may be referred to as a multi-chip module and/or a power amplifier module. Module 101 may include a substrate 102, one or more dies (including power amplifier die 103), one or more circuit elements, a matching network 104, and the like, or any combination thereof. As illustrated in fig. 1, the one or more dies can include a power amplifier die 103 and a controller die, such as a power amplifier bias control die 106.

Module 101 may include multiple dies and/or other components attached and/or coupled to substrate 102. For example, the other components may include Surface Mount Components (SMCs) and/or components formed from the substrate 102, such as inductors formed from substrate traces. In some implementations, the substrate 102 can be a multi-layer substrate configured to support the die and/or components and provide electrical connectivity to external circuitry when the module 101 is mounted on a circuit board (e.g., a phone board). Thus, the substrate 102 may be configured to receive multiple components, such as dies and/or separate passive components. As illustrated in fig. 1, power amplifier die 103, power amplifier bias control die 106, capacitor 107, and inductor 108 are attached to substrate 102. The substrate 102 may be a laminated substrate with a surface treatment plating.

Power amplifier die 103 may be any suitable die for implementing a power amplifier. According to some embodiments of the invention, the power amplifier die may be coupled to the substrate 102 by means of one or more wire bonds. For example, such wire bonding may include any combination of the features described in section II below. In a particular implementation, these wire bonds may electrically connect the power amplifier die 103 to RF transmit lines including any combination of the features described below in section X. Such a transmission line may be implemented on the substrate 102. Alternatively or additionally, the one or more wire bonds may be included in one or more of the termination circuits described in section IX.

In a number of implementations, the power amplifier die 103 is a gallium arsenide (GaAs) die. In some of these implementations, the GaAs die includes transistors formed using a Heterojunction Bipolar Transistor (HBT) process including, for example, a bipolar field effect transistor (BiFET) process. According to various embodiments of the present disclosure, one or more of such transistors may include any combination of the features of the transistors described below in section IV. Alternatively or additionally, the power amplifier die 103 including GaAs transistors formed by the HBT process may also include resistors formed by the HBT process, such as resistors including any combination of the features as described in section VIII below.

Power amplifier die 103 may receive an RF signal via input pin RF _ IN of module 101. Power amplifier die 103 may include one or more power amplifiers, including, for example, a multi-stage power amplifier configured to amplify RF signals. The power amplifier die 103 may advantageously include an input matching network, a first power amplifier stage (which may be referred to as a driver amplifier), an inter-stage matching network, a second power amplifier stage (which may be referred to as an output amplifier), a biasing circuit, or any combination thereof. Those skilled in the art will appreciate that a power amplifier die may include one or more power amplifier stages. Furthermore, in particular implementations of the present disclosure, the input matching network and/or the interstage matching network may be external to the power amplifier die 103. Although fig. 1 illustrates one power amplifier die 103 in module 101, it should be further understood that two or more power amplifier dies may be included in module 101 in other implementations of the invention.

According to a particular implementation of the present disclosure, a power amplifier may include a first power amplifier stage and a second power amplifier stage. The first stage and/or the second stage may include one or more bipolar transistors. In a particular embodiment of the present disclosure, one or more of these bipolar transistors may include any combination of the features described in section IV below herein. The RF input signal may be provided to the first power amplifier stage by means of an input matching network. The input matching network may receive a first bias signal. The first bias signal may be generated on the power amplifier bias control die 106 as illustrated in fig. 1. In some other implementations (not illustrated), the first bias signal may be generated on the power amplifier die 103 or external to the module 101. The first power amplifier stage may amplify the RF input and provide the amplified RF input to the second power amplifier stage via the inter-stage matching circuit. The interstage matching circuit may include a separate termination circuit to match the fundamental frequency of the RF signal and terminate with the phase of the harmonic of the RF signal, according to any combination of features described in appendix G. The interstage matching circuit may receive a second stage bias signal. The second bias signal may be generated on the power amplifier bias control die 106 as illustrated in fig. 1. In some other implementations (not illustrated in fig. 1), the second bias signal may be generated on the power amplifier die 103 or external to the module 101. The second power amplifier stage may generate an amplified RF output signal.

The amplified RF output signal may be provided to an output pin RFOUT of the power amplifier die 103 via an output matching network 104. According to a particular embodiment of the present disclosure, the amplified RF output signal may be provided to and/or from the output matching network 104 via an RF transmit line having any combination of the features described in further detail below in section X. A matching network 104 may be provided on the module 101 to help reduce signal reflections and/or other signal distortions. For example, the output matching network 104 may include a separate termination circuit to match the fundamental frequency of the RF signal and terminate with the phase of the harmonic of the RF signal, according to any combination of features described herein below in section IX.

The power amplifier die 103 may include one or more on-die passive circuit elements, such as capacitors, resistors, or inductors. For example, the power amplifier die 103 may include one or more resistors. In some embodiments, the power amplifier die 103 can include one or more semiconductor resistors including any combination of the features described below in section VIII.

Alternatively or additionally, the power amplifier die 103 may include features related to reducing the effects of high RF loss plating, including, for example, any combination of the features described below in section III. As one example, the power amplifier die 103 may include a first lead electrically connected to the on-die passive circuit element and a second lead electrically connected to the output signal to direct current away from a bond pad electrically connected to the first lead.

Power amplifier die 103 may include a dual mode power amplifier. According to some embodiments of the present disclosure, one or more dies may include any combination of the features of the dual mode power amplifier control interface described below in section V. The dual mode power amplifier control interface may be implemented on the power amplifier die 103 and/or another die, such as the power amplifier bias control die 106.

As further illustrated in fig. 1, the module 101 may include a power amplifier bias control die 106 mounted to the substrate 102. In a particular embodiment of the present disclosure, the power amplifier bias control die 106 may generate the power amplifier bias control signal by implementing any combination of the features described in section VI herein below based on an indicator of a property of the power amplifier die 103 (e.g., an indicator of process variation of the power amplifier die 103). Power amplifier bias CONTROL die 106 may also generate power amplifier bias CONTROL signals based on CONTROL data received on CONTROL pin CONTROL of module 101, such as CONTROL data indicative of the power mode of a power amplifier disposed on power amplifier die 103.

As also illustrated in fig. 1, one or more circuit elements of the power amplifier module 101 may include a capacitor 107 and/or an inductor 108. The one or more circuit elements may be mounted to the substrate 102 and/or implemented on the substrate 102. For example, the inductor 108 may be implemented on the substrate 102 as a trace on the substrate 102 or as a Surface Mounted Component (SMC) mounted to the substrate 102. The inductor 108 may operate as a choke inductor and may be disposed between a supply voltage received on a supply voltage pin VCC and the power amplifier die 103. Inductor 108 may provide a supply voltage received on supply voltage pin VCC to a power amplifier on power amplifier die 103 while choking and/or blocking high frequency RF signal components. The inductor 108 may include a first end electrically connected to the supply voltage pin VCC and a second end electrically connected to a collector of a bipolar transistor associated with the power amplifier die 103. The capacitor 107 may act as a decoupling capacitor. As illustrated in FIG. 1, capacitor 107 includes a first end electrically connected to a first end of inductor 108 and a second end electrically coupled to ground, which in a particular implementation is provided using a ground pin (not illustrated in FIG. 1) of module 101. The capacitor 107 may provide a low impedance path to the high frequency signal, thereby reducing noise of the power amplifier supply voltage, improving power amplifier stability and/or improving the performance of the inductor 108 as an RF choke. In some implementations, the capacitor 107 may comprise SMC.

Module 101 may also include one or more power supply pins and/or one or more reference voltage pins that may be electrically connected to, for example, power amplifier die 103. The power amplifier die 103 may include one or more through-wafer vias. The through-wafer via may be electrically coupled to a supply pin configured at ground potential. The through-wafer via can include any combination of the features of the through-wafer via described below in section XI. For example, the through-wafer via may be a tantalum nitride terminated through-wafer via. One or more power supply pins may provide a supply voltage (e.g., a power high or VCC supply voltage) to the power amplifier.

According to a particular embodiment, the module 101 may advantageously include an RF shielding and/or RF isolation structure. For example, the module may include any combination of the features described herein below in sections XII and XIII to provide such RF shielding or RF isolation structures.

Module 101 may be modified to include more or fewer components, including, for example, additional power amplifier dies, capacitors, and/or inductors. For example, module 101 may include one or more additional matching networks. As another example, module 101 may include an additional power amplifier die and additional capacitors and inductors configured to operate as decoupling capacitors and choke inductors. The module 101 may be configured to have additional pins, such as in implementations in which separate power supplies are provided to an input stage disposed on the power amplifier die 101 and/or implementations in which the module 101 operates across multiple frequency bands.

Wire bond pad system and related methods

To reduce the RF losses associated with high RF loss plating (such as, for example, Ni/Pd/Au plating), in some embodiments, the solder mask is reconfigured to block plating of the edges and sidewalls of the wire bond regions. Leaving the edges and sidewalls of the wire bond regions free of high RF loss plating (e.g., Ni/Pd/Au plating) provides a path for RF current to flow around the high resistivity material, which reduces RF signal loss associated with the high resistivity plating material. As indicated above, these aspects of the invention may be combined with other aspects of the invention to even further improve the performance of the power amplifier module and the device in which the power amplifier module is used.

Wire bonding is a technique for connecting a circuit device, for example, an Integrated Circuit (IC) die, to the next level of the package. These circuit devices typically include a plurality of small conductive leads/pads electrically connected to wire bond pads on conductors embedded in the device package or substrate, for example by solder ball bonding, wedge bonding, or the like. Wire bond pads on the substrate provide electrical connections between the IC and the substrate, permitting the IC to interface with the outside world. In either type of wire bonding, the wire is attached at both ends using some combination of heat, pressure, and ultrasonic energy to make a weld.

A plurality of copper patterns are formed on a substrate electrically connected to the circuit patterns, and a filler (e.g., a dielectric) is filled between the copper patterns such that upper surfaces of the copper patterns are exposed. However, bare copper cannot be easily soldered or bonded and needs to be plated with a material that facilitates soldering or bonding. The areas that should not be soldered/bonded are covered with a material to resist plating. In general, solder resist refers to a polymer coating that acts as a mask and prevents the plating material from adhering to the masked copper traces. A surface plating material is electroplated onto the top layer of the exposed copper traces to provide wire bond pads. In some applications, the wire bond pads are adapted to be wire bonded directly over active circuitry to avoid damaging fragile devices and to reduce metal resistance of the power integrated circuit.

Referring now to FIG. 2, a portion of an IC module 109 is illustrated that includes an IC111, a substrate 121, copper traces 112, wire bond pads 113, 114, and bond wires 116, according to one particular embodiment of the invention. The IC is wire bonded to wire bond pads 113 and 114 by wires 116. In the illustrated embodiment, wire bond pad 113 is a 6 wire bond pad and wire bond pad 114 is a 3 wire bond pad. In other embodiments, a different number of wires 116 may be attached to the wire bond pads 113 and 114. Wire bond pads 113 and 14 include a bonding region 119, sidewalls 117, and edges 118.

Fig. 3 illustrates a flow diagram of an exemplary process 122 for forming wire bond pads. Process 122 is described with respect to the embodiment illustrated in fig. 2. Statement 123 begins with a substrate 121 formed with dielectric and conductor layers 112, including traces 112 on an upper surface of substrate 121, to form circuit paths, as known to those skilled in the art of semiconductor fabrication.

At statement 124, process 122 applies a solder mask to the region of IC module 109 that is to be maintained free of plating material, as may be known to those skilled in the art of semiconductor fabrication. The solder mask openings define regions to which the plating material will adhere. In some embodiments, the solder mask opening exposes the wire bond regions 119, sidewalls 117, and edges 118 of the wire bond pads 113 and 114 to the plating material. In other embodiments of the present invention, the wire bond regions 119, sidewalls 117, and edges 118 of the traces 112 and wire bond pads 113 and 114 are open to the electroplating process.

At statement 126, the exposed areas of the copper traces 112 (without the solder mask) are electroplated with a plating material to form the wirebond pads 113 and 114, as may be known to those skilled in the art of semiconductor fabrication.

In an embodiment of the present invention, the plating material is nickel/gold (Ni/Au). At statement 126, a nickel layer is electroplated over the copper traces 112 and a gold layer is electroplated over the nickel layer. Examples of electroplating techniques include, for example, immersion deposition, electrolytic plating, electroless plating, and the like.

In a particular embodiment of the present invention, the copper traces are between about 5 microns and about 50 microns thick, and preferably about 20 microns. The nickel layer in the Ni/Au plating is between about 2.5 microns to about 7.6 microns thick, and more preferably between about 5 microns to about 7 microns. The gold layer is about 0.70+/-0.2 microns thick and more preferably about 0.5+/-0.1 microns.

Traditionally, Ni/Au has become the standard surface plating material for Radio Frequency Integrated Circuit (RFIC) products. Radio Frequency (RF) is an oscillation rate in the range of about 30kHz to about 300 GHz. In one embodiment, RFIC111 is wire bonded to Ni/Au wire bond pads 113 and 114 plated on the surface of substrate 121 to form electrical connections of RFIC111 to its package. However, the increase in gold prices has increased the packaging costs associated with Ni/Au surface plating.

To reduce packaging costs, nickel/palladium/gold (Ni/Pd/Au) plated materials are used to form the wire bond pads of RFICs. In one embodiment, RFIC111 is wire bonded to Ni/Pd/Au wire bond pads 113 and 114 plated on the surface of substrate 121 to form electrical connections of RFIC111 to its package. The Ni/Pd/Au plating uses less gold than the Ni/Au plating material and as the gold price increases, the Ni/Pd/Au plating is advantageously less costly than the Ni/Au plating material.

As shown in fig. 4, which illustrates a cross-section of a Ni/Pd/Au wire bond pad 113 on the surface of a substrate 121, for example, according to an embodiment of the invention. The Ni/Pd/Au wire bond pads 113 as shown in fig. 4, which may be applied to any other bond pad in the module, such as 114 of fig. 2, include a nickel layer 127, a palladium layer 128, and a gold layer 129.

Referring now to fig. 3 and 4, at statement 126, a nickel layer 127 is electroplated over copper traces 112; a palladium layer 128 is electroplated over the nickel layer 127, and a gold layer 129 is electroplated over the palladium layer 128. Examples of electroplating techniques include, for example, immersion deposition, electrolytic plating, electroless plating, and the like.

In the embodiment of the invention illustrated in FIG. 4, the height H of the copper traces 112_CuBetween about 5 microns and about 50 microns, and preferably 20 microns. Height H of nickel layer 127_NiBetween about 2.5 microns and about 7.6 microns, and more preferably between about 5 microns and about 7 microns. Height H of palladium layer 128_PdIs about 0.09+/-0.06 microns and more preferably is about 0.1+/-0.01 microns. Height H of gold layer 129_AuIs about 0.10+/-0.05 microns and more preferably is about 0.1+/-0.01 microns.

However, due to the ferromagnetic nature of the thin palladium 128 and gold 129 layers and the nickel layer 127, the Ni/Pd/Au plated surface at radio frequencies has a higher sheet resistance than the Ni/Au plated surface. Sheet resistors are suitable for two-dimensional systems where thin films (such as, for example, surface-treated coatings of semiconductors) are considered two-dimensional entities. Which is similar to the resistivity in a three-dimensional system. When the term sheet resistance is used, the current must flow along the plane of the sheet rather than perpendicular to the plane of the sheet.

In the Ni/Au wire bond pad embodiment described above, the sheet resistance of Ni/Au is about 30m Ω/square at 2GHz, while the sheet resistance of Ni/Pd/Au in the Ni/Pd/Au wire bond pad embodiment described above and illustrated in FIG. 4 is about 150m Ω/square at 2 GHz. Thus, instead of Ni/Au plating material, plating the wire bond pads 113 and 114 with Ni/Pd/Au plating material may result in additional RF loss. This in turn can affect product performance and yield. In some embodiments, Ni/Pd/Au plated surfaces can potentially increase RF losses by about 0.1dB to about 0.4dB, or equivalently affect power efficiency by about 1% to about 4%.

Furthermore, the oscillating signal is subject to skin effect. The skin effect is the tendency of an alternating current to distribute itself within a conductor such that the current density near the surface of the conductor is greater than at its core. That is, current tends to flow at the skin of the conductor at an average depth called the skin depth. The skin effect causes the effective resistance of the conductor to increase with the frequency of the current because many conductors carry very little current. The skin effect is due to eddy currents induced by the alternating current. As the frequency of the signal increases (e.g., to RF frequency), the skin depth decreases. In addition, eddy currents also cause crowding of alternating RF currents at the edges of the conductor. Thus, a major portion of the RF current travels on the edges and sidewalls of the conductor 112.

Fig. 5 illustrates an enlarged portion of an RFIC module 131, according to another embodiment of the invention, the RFIC module 131 including an RFIC132, a substrate 141, copper traces 133, wire bond pads 134 and 136, and bond wires 116. RFIC132 is wire bonded to wire bond pads 134 and 136 by bond wires 116. In the illustrated embodiment, wire bond pad 134 is a 6 wire bond pad and wire bond pad 136 is a 3 wire bond pad. In other embodiments, other numbers of wires 116 (e.g., 1, 2, 3, 4, 5, or more than 6, for example) may be attached to the wirebond pads 134 and 136. The wire bond pads 136 include a bonding region 139, sidewalls 137, and edges 138.

To reduce RF signal loss, the fabrication process may limit the Ni/Pd/Au wire bond pads 134 to, for example, bond regions 139, leaving the sidewalls 137 and edges 138 free of Ni/Pd/Au plating material. Most of the RF current travels through the unplated edges and sidewalls surrounding the plated wire bond region 139 rather than traveling through the plated edges 138 and sidewalls 137 as illustrated in fig. 2 and 4. Therefore, the RF loss is reduced.

In fig. 6, a flow diagram of an exemplary process 142 for forming Ni/Pd/Au wire bond pads 134 and 136 according to another embodiment of the invention is shown. Process 142 is described with respect to the embodiment illustrated in fig. 5. Statement 143 begins with substrate 141 formed with dielectric and conductor layers 133, including traces 133 on the upper surface of substrate 141 (fig. 7), to form circuit paths, as may be known to those skilled in the art of semiconductor fabrication.

At statement 144, in an embodiment, the solder mask is reconfigured to cover the edge 138 and sidewalls 137 of the exemplary ground bond pad 134. In another embodiment, the solder mask is reconfigured to cover the traces 133 and the edges 138 and sidewalls 137 of the wire bond pads. The solder mask opening covers wire bond region 139 such that wire bond region 139 is open to the plating process while edge 138 and sidewalls 137 are not open to the plating process. In embodiments of the present invention, the width of the edge 138 covered by the solder mask should be at least wider than the solder mask opening alignment tolerance. In another embodiment, the width of the edge 138 covered by the solder mask is about 10 to 200 microns, and preferably 50 to 100 microns.

At statement 146, process 142 applies the reconfigured solder mask to RFIC module 131, as may be known to those skilled in the art of semiconductor fabrication.

At statement 147, process 142 electroplates RFIC module 131 with a Ni/Pd/Au plating material to form wire bond pads, as may be known to those skilled in the art of semiconductor fabrication. Examples of electroplating techniques include, for example, immersion deposition, electrolytic plating, electroless plating, and the like.

As an example of further details related to the present invention, FIG. 7 illustrates a cross-section of an exemplary Ni/Pd/Au wire bond pad 134 on a surface of a substrate 141 in accordance with an embodiment of the present invention. The Ni/Pd/Au wire bond pads 134 as shown include a nickel layer 148, a palladium layer 149, and a gold layer 151. As illustrated in FIG. 7, the edges 138 and sidewalls 137 of the Ni/Pd/Au wire bond pads 134 are free of Ni/Pd/Au plating.

Referring now to fig. 6 and 7 together, a nickel layer 148 is electroplated over the copper traces 133; palladium layer 149 is electroplated over nickel layer 148 and gold layer 151 is electroplated over palladium layer 149. Examples of electroplating techniques include, for example, immersion deposition, electrolytic plating, electroless plating, and the like.

In the embodiment illustrated in FIG. 7, the height H of the copper traces 133_CuBetween about 5 microns and about 50 microns, and preferably about 20 microns. Height H of nickel layer 148_NiBetween about 2.5 microns and about 7.6 microns, and more preferably between about 5 microns and about 7 microns. Height H of palladium layer 149_PdIs about 0.09+/-0.06 microns and more preferably is about 0.1+/-0.01 microns. Height H of gold layer 151_AuIs about 0.10+/-0.05 microns and more preferably is about 0.1+/-0.01 microns.

Fig. 8 is a graph 152 comparing the RF loss of traces having edge/sidewall exposed surfaces to edge/sidewall plated surfaces in accordance with an embodiment of the present invention. Graph 152 shows power loss in decibels (dB) along the y-axis or vertical axis and frequency in gigahertz (GHz) along the x-axis or horizontal axis. The power loss of the RF signal is calculated as 10log at frequencies ranging from about 1.40GHz to about 2.25GHz ₁₀[RFpowerout/RFpowerin]。

Graph 152 includes lines 153, 156, 158, 161, and 163 representing power loss of RF signals through various traces on the RFIC substrate. Line 153 indicates the RF power loss of the RF signal through the bare copper trace (no surface treatment layer). At about 1.9GHz, the power loss is about 0.614dB, as indicated by point 154.

Line 156 indicates the power loss of the RF signal through the copper traces including Ni/Au bond pads having their edges and sidewalls free of plating, while line 158 indicates the power loss through the copper traces including Ni/Au bond pads having their edges and sidewalls plated with Ni/Au plating material. Point 157 on line 156 indicates a power loss of about 0.729dB at about 1.9GHz, and point 159 on line 158 indicates a power loss of about 0.795dB at about 1.9 GHz.

Line 161 indicates the power loss of the RF signal through the copper traces including Ni/Pd/Au bond pads having their edges and sidewalls free of plating, while line 163 indicates the power loss through the copper traces including Ni/Pd/Au bond pads having their edges and sidewalls plated with a Ni/Pd/Au plating material. Point 162 on line 161 indicates a power loss of about 0.923dB at about 1.9GHz and point 164 on line 163 indicates a power loss of about 1.191dB at about 1.9 GHz.

Referring to the embodiment illustrated in fig. 8, the bare copper traces (lines 153) provide minimal power loss and the traces (lines 163) including Ni/Pd/Au bond pads with plated edges and sidewalls provide maximal RF power loss. The traces with the Ni/Au bond pads (lines 156, 158) produce less power loss to the RF signal than the traces with the Ni/Pd/Au bond pads (lines 161, 163). The traces with exposed edges and sidewalls (line 156) produce less power loss than the traces with plated edges and sidewalls (line 158) compared to the traces with Ni/Au bond pads. Similarly, traces with Ni/Pd/Au bond pads comprising exposed edges and sidewalls (line 161) generate less power loss to RF signals than traces with Ni/Pd/Au bond pads plated edges and sidewalls (line 163). As indicated by arrow 166, in one embodiment, the RF power loss of the RF signal through the Ni/Pd/Au bond pads without having their edges and sidewalls plated with Ni/Pd/Au plating material is about 0.26dB less than the RF power loss of the RF signal through the Ni/Pd/Au bond pads with edges and sidewalls plated with Ni/Pd/Au plating.

In a particular embodiment of the present invention, there is a minimum width of the plated wire bond region 139 exposed to the process 142 to achieve a successful and reliable wire bond connection. Fig. 5 and 7, described above, illustrate embodiments of wire bond pads 134 and 136 that fit within a uniform width of copper trace 133. In other words, the width of the plated wire bond region 139 and the width of the unplated edges 138 and sidewalls 137 do not exceed the uniform width of the traces 133 in the region of the wire bond pads 134 and similarly apply to the wire bond pads 136 and the region of the traces 133 adjacent to the respective wire bond pads.

With respect next to fig. 9A-9F, an exemplary layout of wire bond pads is illustrated, wherein the minimum width of the plated bond regions 139 and the width of the at least one unplated edge 138 exceed the uniform width of the traces 133 in the region of the respective wire bond pad and the region of the traces 133 adjacent to the wire bond pad. In one embodiment, if the minimum size requirement of the wire bond region 139 is not met after covering the edge 138 of the wire bond pad with a solder mask so that it remains free of plating, the width of the trace 133 may be increased proportionally with the minimum edge exposure to meet the size requirement.

More specifically, fig. 9A-9D illustrate exemplary layouts of wire bond pads with exposed edges 138 and sidewalls 137 surrounding the wire bond pads. In an embodiment of the present invention for a particular desired application, if the minimum size requirement of wire bond region 139 is not met after covering edge 138 of the wire bond pad with a solder mask so that it remains free of plating, the width of trace 133 can be deformed with minimum edge exposure to meet the wire bond region 139 size requirement. In other words, the layout of the wire bond regions meets or is larger than the minimum dimensions set by the design rules of the substrate technology, while minimizing the plated edges and sidewalls of the copper traces that comprise the bond regions. Thus, RF current flows through a minimum distance on the highly resistive plated edge and sidewalls. In fig. 9A-9D, the traces 133 expand in width in the region of the wire bond pads to accommodate the wire bond regions 139. Furthermore, the extended traces 133 permit the wirebond pads to maintain a covered edge 138 and sidewalls 137 (not illustrated) during the solder mask process, which in turn permits the complete wirebond pads to maintain an exposed edge 138 and sidewalls 137 along all perimeters of the respective wirebond pads.

Fig. 9E and 9F illustrate exemplary layouts in which the traces 133 include wire bond pads, but the circuit layout considerations limit pad size and prevent coverage of the edge 138 with a solder mask during the masking process. In one embodiment, the traces 133 deform with the wire bond pads to accommodate the wire bond regions 139. In another embodiment, the traces 133 are deformed in the region of the wire bond pads to accommodate the wire bond region 139. In fig. 9E, trace 133 deforms with one wire bond pad to accommodate 3-wire bond region 139. In fig. 9F, the traces 133 are deformed with two wire bond pads each having a bond pad region 139 to accommodate two 2 wire bond regions 139, as shown. Thus, the deformed traces 133 permit a minimum length of the plated edges and sidewalls, or in other words, a length of the unplated edges and sidewalls, to be maximized to reduce RF losses and maintain a desired bondable area for the wire bond pads.

As an advantage of the invention, to reduce cost, in some embodiments Ni/Pd/Au is electroplated onto surface traces of the substrate of the RFIC module instead of Ni/Au to form wire bond regions. However, Ni/Pd/Au has a higher RF sheet resistance than Ni/Au, and this results in higher RF loss for signals traveling through the Ni/Pd/Au wire bond regions than for signals traveling through the Ni/Au wire bond regions. To reduce the RF losses associated with high RF loss plating (such as, for example, Ni/Pd/Au plating), in some embodiments, the solder mask is reconfigured to block plating of the edges and sidewalls of the wire bond regions. Leaving the edges and sidewalls of the wire bond regions free of high RF loss plating (e.g., Ni/Pd/Au plating) provides a path for RF current to flow through low resistivity material, which reduces RF signal loss associated with high resistivity plating material.

Although embodiments have been described with respect to Ni/Pd/Au surface plating, the disclosed systems and methods are applicable to any high RF loss surface plating, such as, for example, Sn, Pb, other surfaces of ferromagnetic materials, and so forth.

The above detailed description of specific embodiments is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or use systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes, blocks or steps may be implemented in a number of different ways. Further, while processes, blocks, or steps are sometimes shown as being performed in series, these processes, blocks, or steps may instead be performed in parallel, or may be performed at different times.

Those skilled in the relevant art will appreciate that the teachings of these aspects of the invention as provided herein may be applied to other systems and need not be applied only to the systems described hereinabove or hereinbelow. Thus, the elements and acts of the various embodiments described above can be combined in a wide variety of ways to provide multiple other embodiments.

Apparatus and method for reducing the effects of high RF loss coatings

To reduce RF losses associated with high Radio Frequency (RF) loss plating, such as, for example, nickel/palladium/gold (Ni/Pd/Au) plating, on-die passive devices associated with a Radio Frequency Integrated Circuit (RFIC), such as capacitors, resistors, or inductors, are placed in the RF upstream signal path relative to the RF signal output of the RFIC. By placing the passive devices on the die in the RF upstream signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bond pads. As indicated above, these aspects of the invention may be combined with other aspects of the invention to further improve the performance of the power amplifier module and the device in which the power amplifier module is used.

Wafer fabrication generally refers to the process of building integrated circuits on silicon or semiconductor wafers. There are many processes known to those skilled in the art of wafer fabrication (such as, for example, epitaxy, masking and etching, diffusion, ion implantation, deposition of polysilicon, dielectric fabrication, photolithography and etching, thin film deposition, metallization, glass passivation, probing and trimming of each die on the wafer, etc.) to form integrated circuits that meet any given design specification.

In a particular embodiment, it is desirable to locate on-die passive devices (e.g., resistors, capacitors, inductors, etc.) on an RFIC that further includes an RF output signal. The on-die passive devices may act as filters, tap filters, harmonic frequency traps, and the like in the RF circuit.

Referring now to fig. 10, an enlarged portion of RFIC module 167 including substrate 168 and RFIC174 is illustrated. The extra circuitry is omitted for simplicity. The substrate 168 includes RFIC circuit traces 169 and wirebond pads 171 and 172. In an embodiment of the present invention, wire bond pads 171 and 172 comprise Ni/Pd/Au. In another embodiment, wirebond pads 171 and 172 comprise a high RF loss plating material. In yet another embodiment, wire bond pads 171 and 172 comprise Ni/Au. In one embodiment, wire bond pads 171 and 172 are formed with plated edges and sidewalls, as illustrated in fig. 10. In another embodiment, wire bond pads 171 and 172 are formed with edges and sidewalls that are free of surface plating material.

The RFIC174 includes an RF output 176 and an on-die passive device 177 (e.g., a capacitor 177). The RF output 176 is located at a location on the RFIC174 from which RF output signals from the RFIC's internal circuitry exit the RFIC174 and are input into the RF circuitry of the module 167. In an embodiment, the layout of the RFIC174 is configured such that the capacitor 177 is placed in the RF circuitry 169 of the RF module 167 after the RF output 176. In this layout, when RF output 176 is wire bonded to wire bond pad 171 and on-die capacitor 177 is wire bonded to wire bond pad 172, on-die capacitor 177 is between RF output 176 of RFIC174 and the RF output of module 167.

Arrow 173 indicates the direction of the RF current of the RF signal. As shown, RF current flows from the RF output signal 176 to the RF output of the module 167. The portion of the RF trace 169 between the RF output signal 176 and the RF output of the module 167 is in the RF signal down path and the portion of the trace 169 above the RF output 176 that does not receive RF current is in the RF signal up path. In fig. 10, the capacitor bonding pad 172 is located in the RF downlink path. In other words, the RF current passes through the capacitor wire bond pad 172 as it travels from the RF output 176 to the rest of the circuitry on the substrate 168. In an embodiment of the present invention, passing the RF signal through a high RF loss plating material (e.g., Ni/Pd/Au capacitor bond pads 172) creates additional RF signal loss.

Fig. 11 illustrates an enlarged portion of RFIC module 178 including substrate 179 and RFIC 186. The extra circuitry is omitted for simplicity. Substrate 179 includes RFIC circuit traces 181 and wire bond pads 182 and 183. In a specific embodiment of the present invention, the wire bond pads 182 and 183 comprise Ni/Pd/Au. In another embodiment, wire bond pads 182 and 183 comprise a high RF loss plating material. In yet another embodiment, wire bond pads 182 and 183 comprise Ni/Au. In a particular embodiment of the present disclosure, the wire bond pads 182 and 183 are formed with plated edges and sidewalls, as illustrated in fig. 11. In another embodiment, wire bond pads 182 and 183 are formed with edges and sidewalls that are free of surface plating material.

The layout of the RFIC186 of fig. 11 has been reconfigured to reduce the RF losses associated with RF current flowing through the high RF loss bond pads of the on-die passive devices. The RFIC186 includes an RF output 187 and an on-die passive device, such as a capacitor 188. The RF output 187 is the location on the RFIC186 from which RF output signals from the RFIC's internal circuitry exit the RFIC186 and are input into the RF circuitry of the module 178. In an embodiment of the present invention, the layout of the RFIC186 is configured such that the capacitor 188 is placed in the RF circuitry 181 of the RF module 178 before the RF output 187. In this layout, when the RF output 187 is wire bonded to the wire bond pad 183 and the on-die capacitor 188 is wire bonded to the wire bond pad 182, the on-die capacitor 188 is not between the RF output 187 of the RFIC186 and the RF output of the module 178.

Arrow 173 again indicates the direction of the RF current of the RF signal. As shown, RF current flows from RF output signal 187 to the RF output of module 178. In fig. 11, the passive device bond pads 182 are located in the RF upstream path. In other words, the RF current does not pass through the passive device wirebond pads 182 when traveling from the RF output 187 to the rest of the circuitry on the substrate 179. Thus, in embodiments of the present invention, the on-die passive devices are placed in the layout of the RFIC186 such that the RF signal losses associated with placing the on-die passive device bond pads 182 in the RF signal downstream path are reduced in the RF upstream signal path for the bond pads 182 on the on-die passive device substrate 179.

To reduce cost, in some embodiments, Ni/Pd/Au is electroplated onto surface traces of the substrate of the RFIC module instead of Ni/Au to form wire bond regions. However, Ni/Pd/Au has a higher RF sheet resistance than Ni/Au, and this results in higher RF loss for signals traveling through the Ni/Pd/Au wire bond regions than for signals traveling through the Ni/Au wire bond regions. To reduce RF losses associated with high RF loss plating (e.g., Ni/Pd/Au plating, for example), on-die passive devices associated with the RFIC (e.g., capacitors, resistors, inductors, etc.) are placed in the RF upstream path relative to the RFIC output signal. By placing the IC with the passive devices in the RF signal upstream path, RF signal currents do not pass through the high RF loss bond pads of the passive devices when the module is assembled.

Although the particular embodiments presented herein have been described with respect to Ni/Pd/Au surface plating, the disclosed systems and methods are applicable to any high RF loss surface plating, such as, for example, Sn, Pb, other surfaces of ferromagnetic materials, and so forth. This detailed description of specific embodiments is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein in this section of the invention. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize, given the disclosure provided herein.

Bipolar transistor with collector comprising grading

This section of the invention relates to bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. One aspect of the invention is a bipolar transistor including a collector having a high doping concentration at the junction with the base and at least one grading in which the doping concentration increases away from the base. In some embodiments of the invention, the high doping concentration may be at least about 3 x 10¹⁶cm^-3. According to a particular embodiment, the collector includes two stages. Such bipolar transistors may be implemented in, for example, a power amplifier. As indicated above, these aspects of the invention may be combined with other aspects of the invention to better improve the performance of the power amplifier module and the device in which the power amplifier module is used.

As further generally described, aspects of this section of the disclosure relate to having a high doping concentration (e.g., at least about 3 x 10) in the first collector region adjoining the base¹⁶cm^-3) And at least one graded bipolar transistor in another collector region adjacent to the first collector region. The high dopant concentration in the first collector region of the bipolar transistor adjacent the base may improve second channel linearity metrics in the power amplifier system, such as ACPR2 and/or ACLR 2. However, the high doping concentration in the first collector region may also reduce the gain, e.g. RF gain, of the bipolar transistor. To offset the reduction in gain due to the high doping concentration in the first collector region, one or more steps may be included in another collector region to transition from the high doping concentration in the first collector region to the subcollector. In some embodiments of the present invention, the other collector region comprises two different gradations in which the doping concentration varies (e.g., increases) at different rates away from the base. Appropriate selection of the grading or grading (when more than a desired number of grading) and the doping concentration in the first collector region may result in desirable RF gain and durability characteristics of the bipolar transistor, particularly with the bipolar transistor including planar doping or grading This is especially true in the case of a ladder-doped collector structure.

Experimental data indicate that power amplifier systems including such bipolar transistors can meet stringent second channel linearity specifications and also meet RF gain specifications. For example, a power amplifier system including such a bipolar transistor may have a gain of ACPR2 of no greater than approximately-65 dBc and at least approximately 29dBm when operating at a frequency within a frequency band centered around approximately 833 MHz. In contrast, pure circuit design techniques that have attempted to achieve the desired levels of ACPR2 or ACLR2 have had limited success. Furthermore, other bipolar transistors with enhanced ACPR2 and/or ACLR2 have degraded RF gain.

Referring now to figure 12A, an illustrative cross-section of a bipolar transistor 189 according to one particular embodiment of the invention is shown. As illustrated, the bipolar transistor 189 is a Heterojunction Bipolar Transistor (HBT). A bipolar transistor 189 may be formed on the substrate 191. The substrate 191 may be a semiconductor substrate, such as a GaAs substrate. A bipolar transistor 189 may be disposed between isolation regions 193 and 195. Isolation regions 193 and 195 are non-conductive regions that can provide electrical isolation between bipolar transistor 189 and an adjacent transistor or other circuit element. For example, isolation regions 193 and 195 can each comprise trenches filled with nitride, polyimide, or other materials suitable for electrical isolation. Although not shown, it is understood that one or more buffer layers may be included between the substrate 191 and the subcollector 192. The one or more buffer layers may include a material that damages an implant that semi-insulates this material.

Bipolar transistor 189 may include a collector 194, a base 196, and an emitter 203. The collector 194 may include multiple collection regions with different doping profiles. For example, the collector 194 may include a first collector region 197 abutting the base 196 and another collector region 201 including at least one grading in which the doping concentration increases away from the first collector region 197. As illustrated in fig. 12A, another collector region 201 may include a second collector region 198 below the first collector region 197 and a third collector region 199 below the second collector region 198.

A first collector region 197 may abut the base 196 to form a collector-base junction. The collector-base junction may be a p-n junction. The first collector region 197 may comprise N + doped GaAs. The first collector region 197 may be a planar doped region. Thus, within the first collector region 197, the doping concentration may be substantially constant. The doping concentration in the first collector region 197 at the collector-base interface of the bipolar transistor 189 may affect the linearity of the system including the bipolar transistor 189. For example, the doping concentration of the first collector region 197, along with the thickness of the first collector region 197, may affect the ACPR2 and/or ACLR2 of the power amplifier system. The lower doping concentration of the first collector region 197, along with the smaller thickness of the first collector region 197, may not achieve the desired level of ACPR2 and/or ACLR 2. On the other hand, the higher doping concentration of the first collector region 197, along with the greater thickness of the first collector region 197, may degrade the gain of the bipolar transistor 189 such that a system including the bipolar transistor 189 does not meet a gain specification, such as an RF gain specification. In view of this tradeoff, particular values for the doping concentration of the first collector region 197 and the thickness of the first collector region 197 may need to be selected to achieve both a desired gain and a desired linearity. As an example, for GaAs bipolar transistor 189, fig. 12B indicates that first collector region 197 has a 6 × 10 ¹⁶cm^-3Doping concentration of andis measured.

The first collector region 197 may have a dopant concentration selected to meet ACPR2 and/or ACLR2 specifications for a power amplifier system including a bipolar transistor 189. As one example, the first collector region 197 may have a doping concentration selected such that a system including the bipolar transistor 189 has an ACPR2 of no greater than about-65 dBc and a gain of at least about 29dBm when operated at a frequency within a frequency band centered around approximately 833 MHz. In some embodiments, the first collector region 197 may have a thickness selected such that a system including the bipolar transistor 189 has a thickness no greater than approximately-55 dBc, no greater than approximately-57 dBcA doping concentration of ACPR2 of about-60 dBc, not greater than about-62 dBc, not greater than about-65 dBc, not greater than about-67 dBc, not greater than about-70 dBc, not greater than about-72 dBc, or not greater than about-75 dBc. These values of ACPR2 may preserve the entire range of output power of the system and/or one or more operating frequency bands within the RF frequency range. As one example, to meet some ACPR2 and/or ACLR2 specifications, the first collector region 197 may have at least about 3 x 10¹⁶cm^-3The doping concentration of (c).

In some particular embodiments of the present disclosure, the first collector region 197 may have a doping concentration of: at least about 3X 10 ¹⁶cm^-3At least about 3.5X 10¹⁶cm^-3At least about 4X 10¹⁶cm^-3At least about 4.5X 10¹⁶cm^-3At least about 5X 10¹⁶cm^-3At least about 5.5X 10¹⁶cm^-3At least about 6X 10¹⁶cm^-3At least about 6.5X 10¹⁶cm^-3At least about 7X 10¹⁶cm^-3At least about 7.5X 10¹⁶cm^-3At least about 8X 10¹⁶cm^-3At least about 8.5X 10¹⁶cm^-3Or at least about 9X 10¹⁶cm^-3. According to a particular embodiment, the first collector region 197 may have a doping concentration selected within one of the following ranges: about 3X 10¹⁶cm^-3To 9X 10¹⁶cm^-3About 3X 10¹⁶cm^-3To 8X 10¹⁶cm^-3About 3X 10¹⁶cm^-3To 7X 10¹⁶cm^-3About 3X 10¹⁶cm^-3To 6X 10¹⁶cm^-3About 3X 10¹⁶cm^-3To 5X 10¹⁶cm^-3About 4X 10¹⁶cm^-3To 9X 10¹⁶cm^-3About 4X 10¹⁶cm^-3To 8X 10¹⁶cm^-3About 4X 10¹⁶cm^-3To 7X 10¹⁶cm^-3About 4X 10¹⁶cm^-3To 6X 10¹⁶cm^-3About 4X 10¹⁶cm^-3To 5X 10¹⁶cm^-3About5×10¹⁶cm^-3To 9X 10¹⁶cm^-3About 5X 10¹⁶cm^-3To 8X 10¹⁶cm^-3About 5X 10¹⁶cm^-3To 7X 10¹⁶cm^-3About 5X 10¹⁶cm^-3To 6X 10¹⁶cm^-3About 6X 10¹⁶cm^-3To 9X 10¹⁶cm^-3About 6X 10¹⁶cm^-3To 8X 10¹⁶cm^-3About 6X 10¹⁶cm^-3To 7X 10¹⁶cm^-3About 7X 10¹⁶cm^-3To 9X 10¹⁶cm^-3About 7X 10¹⁶cm^-3To 8X 10¹⁶cm^-3Or about 8X 10¹⁶cm^-3To 9X 10¹⁶cm^-3。

According to particular embodiments, the thickness of the first collector region 197 may be from aboutToIs selected within the range of (1). In some of these embodiments, the thickness of the first collector region 197 may be selected within one of the following ranges: aboutToAboutToAboutToAboutToAboutToAboutToAboutToOr aboutTo Any of these thickness ranges may be implemented in combination with any of the doping concentrations discussed earlier. In the bipolar transistor 189 of fig. 12A, the thickness of the first collector region 197 can be measured as the shortest distance between the base 196 and the other collector region 201.

The higher doping concentration in the first collector region 197 may reduce the RF gain of the bipolar transistor 189. To meet the RF gain specification of a system including the bipolar transistor 189, such as a power amplifier system, other changes to the characteristics of the bipolar transistor 189 may be required to offset this reduction in RF gain. One or more steps in the other collector region 201 of the bipolar transistor 189 may compensate for some or all of the loss in RF gain associated with the higher doping concentration in the first collector region 197. At the same time, the ACPR2 and/or ACLR2 specifications for power amplifier systems including bipolar transistor 189 may still be met.

The other collector region 201 may include multiple levels in which the doping varies at different rates. As illustrated in fig. 12A and 12B, another collector region 201 can include a second collector region 198 having a first grading and a third collector region 199 having a second grading. In the first grading, the doping concentration may increase in a direction away from base 196. The doping concentration may also increase in the second grading in a direction away from base 196. The doping concentration may increase in the second grading at a different rate than in the first grading. For example, as illustrated in fig. 12B, the doping concentration may increase at a greater rate in the second grading than in the first grading. In some other implementations of the invention, the first grading and the second grading may have respective doping concentrations that increase at substantially the same rate. For example, there may be a discontinuity in doping concentration where the collector transitions from the first grading to the second grading and/or there may be a collector region with planar doping between the first grading and the second grading. The first grading and/or the second grading may vary linearly or non-linearly (e.g., parabolically). In the example illustrated in fig. 12B, both the first and second levels may have linearly varying doping concentrations.

The second collector region 198 may comprise N-doped GaAs. The first grading may span the second collector region 198. The doping concentration in the second collector region 198 may increase away from the base 196 and the first collector region 197. In some embodiments, the doping concentration of the second collector region 198 adjacent to the first collector region 197 may begin at a doping concentration that is about an order of magnitude lower than the doping concentration of the first collector region 197. For example, as shown in fig. 12B, the doping concentration of the first collector region 197 may be about 6 x 10¹⁶cm^-3And the lowest doping concentration of the second collector region may be about 7.5 x 10¹⁵cm^-3. As also shown in fig. 12B, the second collector region 198 may have an approximate thicknessMay be formed from about 7.5 x 10 at the interface with the first collector region 197 and the doping concentration¹⁵cm^-3To 3 x 10 at the interface with the third collector area 199¹⁶cm^-3And (5) grading. In some embodiments, the doping concentration at the interface with the third collector region 199 may be substantially the same as the first grading encounters the second grading. This may reduce the discontinuity in capacitance associated with the collector 194. The first stage may reduce the base-to-collector capacitance and thus increase the gain, e.g., RF gain, of the bipolar transistor 189.

The third collector region 199 may comprise N-doped GaAs. The second grading may span the third collector area 199. The doping concentration in the third collector region 199 may increase away from the second collector region 198. The doping concentration of the third collector region 199 adjacent to the second collector region 198 may have a doping concentration approximately equal to the maximum doping concentration of the second collector region 198. As also shown in fig. 12B, the second collector region 198 may have an approximate thickness May be formed from about 3 x 10 at the interface with the second collector region 198 and the doping concentration¹⁶cm^-3To 6 x 10 at the interface with the subcollector 192¹⁶cm^-3And (5) grading. In some embodiments, the maximum doping concentration of the third collector region 199 may be about two orders of magnitude lower than the doping concentration of the sub-collector 192. For example, as shown in fig. 12B, the maximum doping concentration of the third collector region 199 may be about 6 x 10¹⁶cm^-3And the doping concentration of the subcollector 192 may be about 5 x 10¹⁸cm^-3。

The doping concentration of the third collector region 199 at the interface with the subcollector 192 can determine the breakdown voltage from collector to emitter, with the base having a resistor coupled to a potential. This breakdown voltage may be referred to as "BV_CEX". Higher BV_CEXA Safe Operating Area (SOA) may be increased. In a third collector region 199 at the interface with the subcollector 192Higher doping can reduce SOA. Doping the third collector region 199 too low at the interface with the subcollector 192 may result in too steep a breakdown current, thus reducing the robustness of the bipolar transistor 189. In a particular embodiment, the doping concentration in the third collector region 199 at the interface with the subcollector 192 can be from about 5 x 10¹⁶cm^-3To 9X 10¹⁶cm^-3Is selected within the range of (1). Such doping concentrations may create a desired BV for the bipolar transistor 189 _CEXValue and/or desired SOA. With respect to BV associated with bipolar transistor 189_CEXMore details of the values will be provided with reference to fig. 13.

Base 196 may comprise P + doped GaAs. Base 196 may be thinner and/or have a higher doping concentration than bases in other bipolar transistors used in the power amplifier system. Reducing the thickness of base 196 and increasing the doping concentration of base 196 can increase the RF gain and maintain the DC gain approximately the same. For example, in a particular implementation, the doping concentration of base 196 may be from about 2 x 10¹⁹cm^-3To 7X 10¹⁹cm^-3Is selected within the range of (1). The thickness of base electrode 196 may be from aboutToIs selected within the range of (1). In some embodiments, the thickness of base electrode 196 may be from aboutToIs selected within the range of (1). Any base thickness selected from the ranges disclosed herein may be implemented in combination with any of the base doping concentrations selected from the ranges disclosed herein. As an example, base 196 may have a thickness of 5.5 × 10¹⁹cm^-3Doping concentration of andis measured. In the bipolar transistor 189 of fig. 12A, the thickness may be the shortest distance between the emitter 203 and the first collector region 197.

The doped product and the thickness of base 196 may be referred to as the "sweet plum number". In some embodiments, the number of globes may be approximately constant, such that the bipolar transistor 189 may have an approximately constant value of β. For example, increasing the thickness of base 196 within a selected range may be accompanied by a corresponding decrease in the doping concentration of base 196 to keep the number of sweet plums approximately constant. As another example, reducing the thickness of base 196 within a selected range may be accomplished with a corresponding increase in the doping concentration of base 196 to keep the number of gammagens approximately constant. Reducing the thickness of base 196 and increasing the doping of base 196 may result in an insignificant change in the resistance associated with base 196. For example, the thickness of base 196 is selected from Is changed intoAnd the doping concentration of the base 196 is changed from 4 x 10¹⁹cm^-3Changed to 5.5X 10¹⁹cm^-3May have an insignificant effect on the resistance of base 196.

The bipolar transistor 189 may include a collector contact 208 to the collector, a base contact 209 to the base 196, and an emitter contact 212 to the emitter 202. These contacts may provide electrical connections to and/or from the bipolar transistor 189. Contacts 208, 209, and 212 may be formed of any suitable conductive material. As illustrated in fig. 12A, the emitter contact 212 can be disposed over the top contact 207, the bottom contact 206, and the emitter cap 202.

The bipolar transistor 189 may include a subcollector 192 over a substrate 191. The sub-collector 192 may be below another collector region 201. For example, as illustrated in fig. 12A, the subcollector 192 can be disposed between the third collector region 199 and the substrate 191. The subcollector 192 can adjoin a third collector region 199. The subcollector 192 may be flatA surface doped region. In some embodiments, the doping concentration of subcollector 192 may be at least one or two orders of magnitude higher than the highest doping concentration of third collector region 199. As shown in FIG. 12B, in a particular embodiment, the subcollector 192 can have an approximate size of 5 × 10¹⁸cm^-3And has a doping concentration of at least about Is measured. A collector contact 208 that physically contacts the subcollector 192 may provide an electrical connection to the collector 194.

Fig. 12C is a diagram 200 illustrating example materials corresponding to portions of the bipolar transistor 189 of fig. 12A. The dashed lines between fig. 12A and 12C are included to indicate that the material in the legend 200 corresponds to a particular portion of the bipolar transistor 189. The legend 200 indicates that, in a particular embodiment, the substrate 191 can be semi-insulating GaAs, the subcollector 192 can be N + GaAs, the third collector region 199 can be N-GaAs, the second collector region 198 can be N-GaAs, the first collector region 197 can be N + GaAs, the base 196 can be P + GaAs, the emitter 203 can be N-InGaP, the emitter cap 202 can be N-GaAs, the bottom contact 206 can be N + GaAs, and the top contact 207 can be InGaAs. It should be understood that in some embodiments, one or more of the regions of the bipolar transistor 189 may include suitable alternative materials in place of the example materials provided in the legend 200. Further, in any of the bipolar transistors described herein, n-type doping and p-type doping may be interchanged through some or all of the transistors. Accordingly, any combination of features described herein may be applied to NPN transistors and/or PNP transistors.

Experimental data indicates that power amplifier systems including the bipolar transistor 189 of fig. 12A currently have met linearity specifications including ACPR2 and ACLR2 and meet RF gain specifications that are particularly challenging. Furthermore, experimental data indicates that the bipolar transistor 189 of fig. 12A has desirable durability qualities, such as BV for example_CEXValue and Safe Operating Area (SOA) indication.

FIG. 13 is a diagram illustrating the bipolar transistor 10 of FIG. 12ABV of 0 and conventional bipolar transistor_CEXA graph of the relationship with current density. In fig. 13, the "+" symbol represents data corresponding to the bipolar transistor 189 and the "o" symbol represents data corresponding to a state of the art bipolar transistor. As mentioned earlier, BV_CEXCan represent the breakdown voltage from collector to emitter in a bipolar transistor where the base has a resistor coupled to a potential.

In FIG. 13, SOA is illustrated by BV_CEXThe area under the curve. When the bipolar transistor corresponds to BV_CEXThe bipolar transistor reaches the point of its breakdown when operating at the voltage and current densities of the curves. In addition, when the bipolar transistor is higher than its corresponding BV_CEXThe bipolar transistor collapses during operation with the voltage and current densities of the curves.

The data in fig. 13 indicates that the bipolar transistor 189 is below the corresponding BV at a particular current density_CEXBV on the curve_CEXOperating at a voltage of value operates within the SOA. The data in fig. 13 also indicate that the bipolar transistor 189 is below the corresponding BV at a particular voltage level_CEXWhen operating at a current density of above current density operates within the SOA. In addition, as long as the voltage and current density combination is below BV_CEXCurves, then the bipolar transistor should operate within the SOA. As shown in fig. 13, the bipolar transistor 189 has a larger SOA than a conventional bipolar transistor. The bipolar transistor 189 has increased durability compared to conventional bipolar transistors because it has a larger SOA and can operate at higher current densities and voltages without breakdown. Accordingly, the bipolar transistor 189 has desirable durability characteristics.

Fig. 14A depicts an illustrative cross-section of a bipolar transistor 213 according to another embodiment. The bipolar transistor 213 of fig. 14A is substantially the same as the bipolar transistor 189 of fig. 12A, except that the collector region 217 of fig. 14A is different from the other collector region 201 of fig. 12A. More specifically, the collector region 217 herein shown in fig. 14A has a different doping profile than the other collector region 201 of fig. 12A. Fig. 14B is a graph showing illustrative doping concentrations for portions of the bipolar transistor 213 of fig. 14A.

The bipolar transistor 213 may similarly include a collector 194 having a first collector region 197 and another collector region 217. The first collector region 197 may include any combination of the features described with reference to the first collector region 197 of fig. 12A. The other collector region 217 may include a single grading in which the doping concentration varies (e.g., increases) away from the base 196.

To meet the RF gain specification of a system (e.g., a power amplifier system) including the bipolar transistor 213, a single grading in the other collector region 217 of the bipolar transistor 213 may compensate for some or all of the loss in RF gain associated with the higher doping concentration in the first collector region 197. At the same time, the ACPR2 and/or ACLR2 specifications for power amplifier systems including the bipolar transistor 213 may still be met. The other collector region 217 can include a second collector region 214 and a third collector region 216, as illustrated in fig. 14A and 14B. In other embodiments, for example, as shown in fig. 14D-14F, the planar doped portions may be omitted from the collector region 217.

As illustrated in fig. 14A and 14B, the collector region 217 may include a second collector region 214 having planar doping. The second collector region 214 may comprise N-doped GaAs. In some embodiments, the doping concentration of the second collector region 214 has a doping concentration that is about an order of magnitude lower than the doping concentration of the first collector region 197. According to a particular embodiment, the doping concentration of the second collector region may be selected from about 7.5 × 10 ¹⁵cm^-3To 1.5X 10¹⁶cm^-3The range of (1). The second collector region 214 may have a thickness selected from the group consisting ofToA thickness of the range of (1). In some embodiments, the doping concentration of the second collector region 214 may be approximately equal to the doping concentration of the third collector region 216 starting below itThe doping concentration of the level. This may reduce the discontinuity in capacitance associated with the collector 194.

The third collector region 216 may comprise N-doped GaAs. A single grading may span the third collector region 216. In other embodiments, a single grading may span the respective collector regions 219, for example as shown in fig. 14D-14F. The doping concentration in the third collector region 216 of fig. 14A may increase away from the base 196, the first collector region 197, and/or the second collector region 214. The doping concentration of the third collector region 216 adjacent to the second collector region 214 may have a doping concentration approximately equal to the doping concentration of the second collector region 214. The third collector region 216 may have a thickness selected from the group consisting ofToA thickness of the range of (1). The doping concentration in the third collector region 216 may be from about 7.5 x 10 at the interface with the second collector region 214¹⁵cm^-3To at least about 5 x 10 at the interface with the subcollector 192¹⁶cm^-3And (5) grading. In some embodiments, the maximum doping concentration of the third collector region 216 may be about two orders of magnitude lower than the doping concentration of the sub-collector 192.

With continued reference to fig. 14A, the doping concentration of the third collector region 216 at the interface with the subcollector 192 may determine BV_CEX. The higher doping in the third collector region 216 at the interface with the subcollector 192 may reduce SOA. Doping the third collector region 216 too low at the interface with the subcollector 192 may result in too steep a breakdown current, thus reducing the robustness of the bipolar transistor 213. In a particular embodiment, the doping concentration in the third collector region 216 at the interface with the subcollector 192 may be from about 5 x 10¹⁶cm^-3To 9X 10¹⁶cm^-3Is selected within the range of (1). Such doping concentrations may result in a desirable BV for the bipolar transistor 213_CEXValue and/or desired SOA.

As shown in the legend 200 of fig. 14C, the bipolar transistor 213 may be formed of substantially the same material as the bipolar transistor 189, with a different doping profile in the collector 194.

Fig. 14D depicts an illustrative cross-section of a bipolar transistor 218 according to another embodiment of the invention. The bipolar transistor 218 of fig. 14D is substantially the same as the bipolar transistor 213 of fig. 14A, except that the collector region 219 of fig. 14D is different from the collector region 217 of fig. 14A. More specifically, the grading spans the collector region 219 in fig. 14D. The collector 194 of the bipolar transistor 218 may be comprised of a first collector region 197 and another collector region 219. As illustrated in fig. 14D, the collector 194 of the bipolar transistor 218 includes only the first collector region 197 and the other second collector region 219. Fig. 14E is a graph showing illustrative doping concentrations for the portion of the bipolar transistor 218 of fig. 14D. As shown in the legend 200 of fig. 14F, the bipolar transistor 218 may be formed of substantially the same material as the bipolar transistor 189 and/or the bipolar transistor 213, with different doping profiles in the collector 194.

The bipolar transistor 218 may include a collector 194 having a first collector region 197 and another collector region 219. The first collector region 197 may include any combination of the features described with reference to the first collector region 197 of fig. 12A. The collector region 219 may include a single grading in which the doping concentration varies (e.g., increases) away from the base 196 and across the entire collector region 219.

To meet the RF gain specification of a system including the bipolar transistor 218 (e.g., a power amplifier system), a single grading in the collector region 219 of the bipolar transistor 218 may compensate for some or all of the loss in RF gain associated with the higher doping concentration in the first collector region 197. At the same time, the ACPR2 and/or ACLR2 specifications for power amplifier systems including bipolar transistor 218 may still be met. The grading in the other collector region 219 may increase the BV of the bipolar transistor 218_CEXAnd/or an SOA. For example, in a particular embodiment, the doping concentration in the collector region 219 may have a concentration at the interface with the subcollector 192 that may be from about 5 x 10¹⁶cm^-3To 9X 10¹⁶cm^-3With a selected doping concentration within the range of (a). The collector region 219 may have any suitable thickness or grading as described herein to achieve one or more features described herein. In some embodiments, the collector region may have a thickness selected from the group consisting of ToA thickness of the range of (1). According to a particular embodiment, the grading in the collector 219 may be from about 7.5 x 10 at the interface with the first collector region 197¹⁵cm^-3At least about 5 x 10 to an interface near subcollector 192 or at the child pole¹⁶cm^-3And (5) grading.

Fig. 15 is an illustrative flow diagram of a process 221 for forming a bipolar transistor in accordance with an embodiment of a method related to the present invention. It should be understood that any of the processes discussed herein may include more or fewer operations, and the operations may be performed in any order as desired. Further, one or more acts of the processes may be performed in series or in parallel. The process 221 may be performed when forming the bipolar transistor 189 of fig. 12A, the bipolar transistor 213 of fig. 14A, the bipolar transistor 218 of fig. 14D, or any combination thereof. At block 222, a subcollector of a bipolar transistor is formed. The subcollector can include any combination of the features of the subcollector described herein (e.g., subcollector 192). At block 223, a collector region including at least one grading may be formed. The at least one grading may be formed by any suitable doping method known in the art. The collector region may be adjacent to the sub-collector, for example, directly above the sub-collector in the orientation of fig. 12A, 14A and 14D. The collector region may include any combination of the features described herein with reference to the other collector regions 201, 217, and/or 219. For example, in some embodiments, the collector region may have two gradations. The at least one grading of the collector region may increase the RF gain and/or increase the ruggedness of the bipolar transistor. For example, at least one stage may compensate for a first collector Some or all of the reduction in gain of the bipolar transistor caused by the high doping concentration in the region. At block 224, a different collector region having a high doping concentration may be formed adjacent to the base. The high doping concentration may be any of the doping concentrations of the first collector region 197 described herein, for example, at least about 3.0 x 10¹⁶cm^-3. Furthermore, the high doping concentration and thickness of the first collector region may collectively improve one or more second channel linearity metrics.

FIG. 16 is a schematic block diagram of a module 226 that may include the one or more bipolar transistors 189 of FIG. 12A, the one or more bipolar transistors 213 of FIG. 14A, the one or more bipolar transistors 218 of FIG. 14D, or any combination thereof. Module 226 may be some or all of a portion of a power amplifier system. In some implementations, the module 226 can be referred to as a multi-chip module and/or a power amplifier module. Module 226 may include a substrate 227 (e.g., a package substrate), a die 228 (e.g., a power amplifier die), a matching network 229, and the like, or any combination thereof. Although not illustrated, in some implementations, module 226 can include one or more other dies and/or one or more circuit elements coupled to substrate 227. For example, the one or more other dies may include a controller die that may include a power amplifier bias circuit and/or a direct current/direct current (DC/DC) converter. For example, example circuit elements mounted on a package substrate may include any desired number of inductors, capacitors, impedance matching networks, and the like, or any combination thereof.

Module 226 can include multiple dies and/or other components mounted on and/or coupled to module 226 of substrate 227. In some implementations, the substrate 227 can be a multi-layer substrate configured to support the die and/or components and provide electrical connectivity to external circuitry when the module 226 is mounted on a circuit board (e.g., a phone board).

The power amplifier die 228 may receive an RF signal at an input pin RF _ IN of the module 226. The power amplifier die 228 may include one or more power amplifiers including, for example, a multi-stage power amplifier configured to amplify RF signals. The power amplifier die 228 may include an input matching network 231, a first stage power amplifier 232 (which may be referred to as a Driver Amplifier (DA)), an inter-stage matching network 233, a second stage power amplifier 234 (which may be referred to as an Output Amplifier (OA)), or any combination thereof.

The power amplifier may include a first stage power amplifier 232 and a second stage power amplifier 234. First stage power amplifier 232 and/or second stage power amplifier 234 may include one or more bipolar transistors 189 of fig. 12A, one or more bipolar transistors 213 of fig. 14A, one or more bipolar transistors 218 of fig. 14D, or any combination thereof. Moreover, bipolar transistor 189 of fig. 12A, bipolar transistor 213 of fig. 14A, and/or bipolar transistor 218 of fig. 14D may help satisfy power module 226 and/or power amplifier die 228 to meet any of the linearity and/or RF gain specifications described herein.

The RF input signal may be provided to a first stage power amplifier 232 via an input matching network 231. The matching network 231 may receive the first stage bias signal. The first bias signal may be generated on PA die 228, external to PA die 228 in module 226, or external to module 226. The first stage power amplifier 232 may amplify the RF input and provide the amplified RF input to the second stage power amplifier 234 via the inter-stage matching circuit 233. The inter-stage matching circuit 233 may receive a second stage bias signal. The second stage bias signal may be generated on PA die 228, external to PA die 228 in module 226, or external to module 226. The second stage power amplifier 234 may generate an amplified RF output signal.

The amplified RF output signal may be provided to an output pin RF _ OUT of the power amplifier die 228 via an output matching network 229. A matching network 229 may be provided on the module 226 to help reduce signal reflections and/or other signal distortions. The power amplifier die 228 may be any suitable die. In some implementations, the power amplifier 228 die is a gallium arsenide (GaAs) die. In some of these embodiments, the GaAs die has transistors formed using a Heterojunction Bipolar Transistor (HBT) process.

The module 226 may also include one or more power supply pins that may be electrically connected to, for example, the power amplifier die 228. In some implementations, the one or more power supply pins can supply voltages (e.g., V) that can have different voltage levels_SUPPLY1And V_SUPPLY2) To the power amplifier. Module 226 may include circuit elements, such as inductors, which may be formed, for example, by traces on a multi-chip module. The inductor may operate as a choke inductor and may be disposed between a supply voltage and the power amplifier die 228. In some embodiments, the inductor is surface mounted. Additionally, the circuit element may include a capacitor electrically connected IN parallel with the inductor and configured to resonate at a frequency near the frequency of the signal received on pin RF _ IN. In some implementations, the capacitor can include a surface mount capacitor.

The module 226 may be modified to include more or fewer components, including, for example, additional power amplifier dies, capacitors, and/or inductors. For example, module 226 may include one or more additional matching networks 229. As another example, module 226 may include an additional power amplifier die and additional capacitors and inductors configured to operate as parallel LC circuits disposed between the additional power amplifier die of module 226 and power supply pins. The module 226 may be configured to have additional pins, such as in implementations in which separate power supplies are provided to the input stage disposed on the power amplifier die 228 and/or implementations in which the module 226 operates across multiple frequency bands.

Module 226 may have a low voltage positive bias supply of about 3.2V to 4.2V, good linearity (for example, satisfying any of the second channel linearity specifications described herein), high efficiency (for example, about 40% PAE at 28.25 dBm), large dynamic range, small and low profile packaging (for example, 3mm x 0.9mm with a 10 pad configuration), shut down power control, support for low collector voltage operation, digital enable, no reference voltage required, CMOS compatible control signals, integrated directional couplers, or any combination thereof.

In some embodiments of the present invention, module 226 is a power amplifier module that is a fully matched 10-pad surface mount module developed for Wideband Code Division Multiple Access (WCDMA) applications. This small and efficient module can package a full 1920MHz to 1980MHz bandwidth coverage into a single compact package. The module 226 can provide desirable talk time advantages to the mobile phone due to the high efficiency obtained across the entire power range. Module 226 can satisfy the stringent spectral linearity requirements for High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), and Long Term Evolution (LTE) data transmission with high power added efficiency. Directional couplers may be integrated into module 226 and may thus eliminate the need for external couplers.

Die 228 may be a power amplifier die embodied in a single gallium arsenide (GaAs) Microwave Monolithic Integrated Circuit (MMIC) that includes all of the active circuitry of module 226, such as one or more bipolar transistors 189 of fig. 12A, one or more bipolar transistors 213 of fig. 14A, one or more bipolar transistors 218 of fig. 14D, or any combination thereof. The MMIC may include on-board bias circuitry as well as input matching network 231 and inter-stage matching network 233. Output matching network 229 may have a 50 ohm load embodied as separate from die 228 within the package of module 226 to increase and/or optimize efficiency and power performance.

Module 226 can be fabricated with a GaAs Heterojunction Bipolar Transistor (HBT) BiFET process that provides all positive voltage DC supply operation while maintaining high efficiency and good linearity, for example, meeting any of the second channel linearity specifications described herein. The primary bias to module 226 may be supplied by any three Ni-Cd batteries, a single Li-ion battery, or other suitable battery having an output selected from the range of about 3.2V to 4.2V, either directly or via intermediate components. In some embodiments, no reference voltage is required. Powering down may be accomplished by setting the enable voltage to zero volts. According to some embodiments, no external supply side switch is required, since the typical "off" leakage is a few microamperes with full primary voltage supplied by the battery.

Any of the devices, systems, methods, and apparatus described herein may be implemented in a variety of electronic devices, such as mobile devices (which may also be referred to as wireless devices). FIG. 17 is a schematic block diagram of an example mobile device 236 that may include the one or more bipolar transistors 189 of FIG. 12A, the one or more bipolar transistors 213 of FIG. 14A, the one or more bipolar transistors 218 of FIG. 14D, or any combination thereof.

Examples of mobile device 236 may include, but are not limited to, cellular telephones (for example, smart phones), laptop computers, tablet computers, Personal Digital Assistants (PDAs), electronic book readers, and portable digital media players. For example, the mobile device 236 may be a multi-band and/or multi-mode device (e.g., a multi-band/multi-mode mobile phone) configured to communicate using, for example, Global System for Mobile (GSM), Code Division Multiple Access (CDMA), 3G, 4G, and/or Long Term Evolution (LTE).

In a particular embodiment, the mobile device 236 may include one or more of the following: switching component 237, transceiver component 238, antenna 239, power amplifier 241, which may include one or more bipolar transistors 189 of fig. 12A, one or more bipolar transistors 213 of fig. 14A, one or more bipolar transistors 218 of fig. 14D, control component 242, computer-readable medium 243, processor 244, battery 246, and supply control block 247.

The transceiver component 238 may generate RF signals for transmission via an antenna 239. Further, the transceiver component 238 may receive incoming RF signals from an antenna 239.

It should be understood that various functionalities associated with the transmission and reception of RF signals may be realized by one or more components collectively represented in fig. 17 as transceiver 238. For example, a single component may be configured to provide both transmit and receive functionality. In another example, the transmit and receive functionality may be provided by separate components.

Similarly, it should be further appreciated that various antenna functionalities associated with the transmission and reception of RF signals may be realized by one or more components collectively represented as antenna 239 in fig. 17. For example, a single antenna may be configured to provide both transmit and receive functionality. In another example, transmit and receive functionality may be provided by separate antennas. In yet another example, different frequency bands associated with the mobile device 236 may be provided with different antennas.

In fig. 17, one or more output signals from the transceiver 238 are depicted as being provided to the antenna 239 via one or more transmit paths. In the example shown, different transmit paths may represent output paths associated with different frequency bands and/or different power outputs. For example, the two example power amplifiers 241 shown may represent amplification associated with different power output configurations (e.g., low power output and high power output) and/or amplification associated with different frequency bands.

In fig. 17, one or more detected signals from antenna 239 are depicted as being provided to transceiver 238 via one or more receive paths. In the example shown, different receive paths may represent paths associated with different frequency bands. For example, the four example paths shown may represent quad-band capabilities that some mobile devices 236 are capable of.

To facilitate switching between receive and transmit paths, the switching component 237 may be configured to electrically connect the antenna 239 to a selected transmit or receive path. Thus, the switching component 237 may provide a number of switching functionalities associated with the operation of the mobile device 236. In a particular embodiment, the switching component 237 may include a number of switches configured to provide functionality associated with, for example, switching between different frequency bands, switching between different power modes, switching between transmit and receive modes, or some combination thereof. The switching component 237 may also be configured to provide additional functionality including filtering of signals. For example, switching component 237 may include one or more duplexers.

The mobile device 236 may include one or more power amplifiers 241. The RF power amplifier may be used to boost the power of RF signals having relatively low power. Thereafter, the boosted RF signal may be used for a variety of purposes, including driving an antenna of the transmitter. The power amplifier 241 may be included in an electronic device, such as a mobile phone, to amplify an RF signal for transmission. For example, in a mobile phone having an architecture for communicating under 3G and/or 4G communication standards, a power amplifier may be used to amplify RF signals. Managing amplification of RF signals may be desirable because the desired transmit power level may depend on how far away the user is from the base station and/or the mobile environment. The power amplifier may also be used to help adjust the power level of the RF signal over time in order to prevent transmission signal interference during the assigned reception time slots. The power amplifier module may include one or more power amplifiers.

FIG. 17 shows that in a particular embodiment, a control component 242 can be provided, and such component can include circuitry configured to provide various control functionality associated with operation of the switching component 237, the power amplifier 241, the supply control 247, and/or other operating components.

In a particular embodiment of the present disclosure, the processor 244 may be configured to facilitate implementation of the various functionalities described herein. Computer program instructions associated with the operation of any of the components described herein may be stored in computer readable memory 243, which may direct processor 244, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions that implement various operating features of the mobile devices, modules, etc., described herein.

The illustrated mobile device 236 also includes a supply control block 247 that may be used to provide a supply of power to one or more power amplifiers 241. For example, the supply control block 247 may include a DC/DC converter. However, in a particular embodiment, the supply control block 247 may include other blocks, such as, for example, an envelope tracker configured to vary a supply voltage provided to the power amplifier 241 based on an envelope of an RF signal to be amplified.

The supply control block 247 may be electrically connected to the battery 246, and the supply control block 247 may be configured to vary the voltage provided to the power amplifier 241 based on the output voltage of the DC/DC converter. The battery 246 may be any suitable battery for use in the mobile device 236, including, for example, a lithium ion battery. With the at least one power amplifier 241 including the one or more bipolar transistors 189 of fig. 12A, the one or more bipolar transistors 213 of fig. 14A, the one or more bipolar transistors 218 of fig. 14D, or any combination thereof, power consumption of the battery 246 may be reduced and/or reliability of the power amplifier 241 may be improved, thereby improving performance of the mobile device 236.

Some of the above-described embodiments have provided examples in connection with modules and/or electronic devices, such as mobile phones, that include power amplifiers. However, the principles and advantages of the embodiments may be used in any other system or device that requires a bipolar transistor with a high level of second channel linearity without sacrificing RF gain.

Systems implementing one or more aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, portions of consumer electronics, electronic test equipment, and the like. More specifically, an electronic device configured to implement one or more aspects of the present disclosure may include, but is not limited to, an RF transmitting device, any portable device with a power amplifier, a mobile phone (for example, a smart phone), a telephone, a base station, a femto cell, a radar, a device configured to communicate according to a wireless fidelity and/or bluetooth standard, a television, a computer monitor, a computer, a handheld computer, a tablet computer, a laptop computer, a Personal Digital Assistant (PDA), a microwave, a refrigerator, an automobile, a stereo, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi-function peripheral device, Wrist watches, clocks, etc. Portions of the consumer electronic product may include multi-chip modules (including RF transmission lines), power amplifier modules, integrated circuits (including RF transmission lines), substrates (including RF transmission lines), and the like, or any combination thereof. Further, other examples of electronic devices may also include, but are not limited to, memory chips, memory modules, circuits for optical networks or other communication networks, and disk drive circuits. Further, the electronic device may contain unfinished products.

Dual mode power amplifier control with tri-mode input/output interface

This section of the disclosure, according to some embodiments thereof, relates to a dual mode control interface that may be used to provide both a Radio Frequency Front End (RFFE) serial interface and a tri-mode general purpose input/output (GPIO) interface within a single digital control interface die. In a particular embodiment, the dual mode control interface or digital control interface may communicate with a power amplifier. Further, the dual mode control interface may be used to set a mode of the power amplifier. As indicated above, these aspects of the invention may be combined with other aspects of the invention to further improve the performance of the power amplifier module and the device in which the power amplifier module is used.

When introducing new standards or modifying existing standards, it is often necessary to introduce new components or modify existing components to use the new or updated standards. For example, using a circuit for supporting multiple configuration modes within a module (e.g. a power amplifier module)A front end (RFFE) standard serial interface may mean that a device manufacturer wishing to support a new standard may need to use a new front end component that supports the RFFE standard. Utensil for cleaning buttockA manufacturer of front-end components that have customers using the RFFE standard and customers using a different standard, such as a general purpose input/output (GPIO) interface, must manufacture two separate components. This can be costly because, for example, more time and human resources must be spent to produce both types of front-end devices.

Furthermore, a device manufacturer who wishes to support two standards may typically need to redesign its product to fit two or more components to support the standards. This may not only require more physical space, but it may also result in greater power consumption, as multiple interface components may each consume power, for example.

Advantageously, embodiments of this section of the present invention provide a system and method for implementing multiple standards in a single die without increasing the size of the die or the number of pins required to support a front-end interface. Furthermore, in some embodiments, power consumption is not increased compared to devices using components implementing a single interface standard. Furthermore, embodiments of the present invention provide a single interface component or die to support the RFFE serial interface, the GPIO interface, or both interfaces without any modification to existing devices. In a particular implementation, the size and pin count of a single component may remain the same as a die implementing only one of the RFFE interface and the GPIO interface.

In particular embodiments of the present invention, the interface component or digital control interface includes an implementationFunctional RFFE core of serial interface. This RFFE core may be configured to receive power from a voltage input/output (VIO) pin. In a number of implementations, the RFFE core may cease receiving power when not in use. When the RFFE core is not powered, the digital control interface may be configured to use pins that provide signals to the RFFE core as a GPIO interface. By using combinational logic, the digital control interface can control whether signals that would be associated with the use of the RFFE serial interface or GPIO interface are to be controlled Provided to, for example, a power amplifier. Advantageously, in a particular embodiment, by combining the RFFE serial interface and the GPIO interface on a single die, it is possible to seamlessly employ the RFFE serial standard without alienating any manufacturer that still uses the GPIO interface. More details regarding combining the RFFE serial standard with the GPIO interface are described herein.

A. Electronic device

Fig. 18 illustrates an embodiment of a wireless device 248 in accordance with aspects of the present invention. The application of the invention is not limited to wireless devices and can be applied to any type of electronic device with or without a power amplifier. For example, embodiments may be applied to wired devices, weather sensing devices, RADAR, SONAR, microwave ovens, and any other device that may include a power amplifier. Furthermore, embodiments of the invention may be applied to devices that may include one or more components controlled via a front-end interface. For example, embodiments of the invention may be applied to Switch Mode Power Supply (SMPS) devices that may be used for power amplifier supply regulation, Antenna Switch Module (ASM), and antenna load tuning module, to name a few. Although the invention is not limited to wireless devices or controlling power amplifiers, to simplify discussion, several embodiments will be described with respect to wireless device 248 and power amplifier module 249.

Wireless device 248 may include a power amplifier module 249. The power amplifier module 249 may generally include any component or device having a power amplifier 251 and a power amplifier controller 252 for controlling the power amplifier 251. Although not so limited, controlling the power amplifier 251 generally refers to setting, modifying, or adjusting the amount of power amplification provided by the power amplifier 251. In some implementations, the power amplifier 251 can include a power amplifier controller 252. Further, the power amplifier module 249 may be a single component that includes the functionality of the power amplifier controller 252 and the power amplifier 251. In other implementations, wireless device 248 may include power amplifier 251 and power amplifier controller 252 as separate and distinct components.

Further, wireless device 248 may include a digital control interface 253. In some embodiments, the power amplifier module 249 includes a digital control interface 253. In general, digital control interface 253 may include any type of control interface that can support multiple types of front-end interfaces. For example, the illustrated digital control interface 253 may supportA Radio Frequency (RF) front end (RFFE) serial interface 254 and a general purpose input/output (GP1O) interface 256. In a number of embodiments, the digital control interface 253 can support multiple types of front end interfaces so that the interfaces can coexist on the same component die without requiring circuit design changes or bonding changes. Furthermore, in some embodiments, the digital control interface 253 may support multiple front-end interfaces without increasing the number of interface pins or connection points exposed for use by the wireless device 248. Advantageously, in several embodiments, the digital control interface 253 can be used with devices that support different interface standards without modifying the digital control interface 253. For example, the illustrated digital control interface 253 of FIG. 18 may support without modifying the digital control interface 253 GPIO or a combination of the two.

In a particular implementation, the digital control interface 253 may serve as an intermediary or manager between the power amplifier module 249 and a signal source that determines or sets the operating mode of the power amplifier module 249, the power amplifier controller 252, the power amplifier 251, or any other component that may be controlled by the digital control interface 253. The signal source may include any component configured to provide a signal to the digital control interface 253 that may cause the digital control interface 253 to determine or set, for example, an operating mode of the power amplifier module 249. For example, as illustrated in fig. 18, the signal source may be a transceiver 257. Alternatively or additionally, the signal source may include a baseband chip 258, a Digital Signal Processor (DSP)259, or any other component that may provide one or more signals to the digital control interface 253 to cause the digital control interface 253 to set the operating mode of the power amplifier module 249 or the power amplifier 251.

In one example of a scenario where the mode of the power amplifier 251 is set, the transceiver receives a signal from, for example, the antenna 261 or the DSP 259. In response to receiving the signal, transceiver 257 may provide one or more signals to digital control interface 253 associated with setting the operating mode of power amplifier 251. Digital control interface 253 may determine, based on the received signal from transceiver 257, whether the received signal is associated with RFFE serial interface 254 or GPIO interface 256. Digital control interface 253 may then process the received signal using the identified interface (e.g., RFFE serial interface 254, GPIO interface 256, or any other interface that digital control interface 253 may include). Then, based on the results of processing the received signal, the digital control interface 253 can provide a mode setting signal to the power amplifier control 252, which can set the mode of the power amplifier 251 based on the mode setting signal.

In general, the mode setting of power amplifier 251 corresponds to the rate or amount of power amplification of the signal that is then provided to the components of the device (e.g., wireless device 248). This signal may be provided to power the component or for processing by the component of the wireless device 248. The power amplifier module may receive power from a power supply 262. The power amplifier module 249 may then distribute power to a number of components included in the wireless device 248 as illustrated through a power distribution bus 263.

Wireless device 248 may include a number of additional components. At least some of these additional components may receive power via a power distribution bus 263. Further, at least some of the additional components may be in communication with digital control interface 253 and may cause digital control interface 253 to modify settings of power amplifier module 249. For example, wireless device 248 may include a digital-to-analog converter (DAC)264, a display processor 266, a central processor 267, a user interface processor 268, an analog-to-digital converter 269, and memory 271.

Further, the components of the wireless device 248 illustrated in fig. 18 are provided as an example. Wireless device 248 may include other components. For example, wireless device 248 may include an audio processor, a gyroscope, or an accelerometer. Further, various illustrated components may be combined into fewer components or separated into additional components. For example, DAC264 and ADC269 may be combined into a single component, and baseband chip 258 may be combined with transceiver 257. As another example, the transceiver 257 may be decomposed into separate receiver and transmitter.

B. Digital control interface

FIG. 19 illustrates a particular embodiment of a digital control interface identified as digital control interface 272, according to an aspect of the present invention. Digital control interface 272 includes both an RFFE serial interface and a GPIO interface. Advantageously, in a particular embodiment, the digital control interface 272 may be implemented in the same size package having the same number of pins as a control interface including one of the RFFE serial interface and the GPIO interface. The ability to combine multiple interface types within a single chip without expanding the size of the chip is particularly advantageous for applications that use or require small packages, such as applications that may require 3mm by 3mm modules.

Digital control interface 272 includes a processor configured to provideThe functional RFFE core 273 of the serial interface. In addition, the digital control interface 272 includes several input pins: VIO pin 274, clock/mode pin 276, and data/enable pin 277.

The VIO pin 274 is configured to receive a signal indicating whether the digital control interface 272 should operate as an RFFE serial interface or a GPIO interface. In the illustrated embodiment, the digital control interface 272 operates as an RFFE serial interface when the VIO pin 274 receives a logic high signal and as a GPIO interface when the VIO pin 274 receives a logic low signal. However, in some implementations, the digital control interface 272 may be configured to operate as an RFFE serial interface when the VIO pin 274 receives a logic low signal and as a GPIO interface when the VIO pin 274 receives a logic high signal. The logic low signal may be associated with any value defined to be low (e.g., 0 volts, -5 volts, or other). Similarly, the logic high signal may be associated with any value defined to be high (e.g., 0 volts, +5 volts, or otherwise). In some implementations, the logic low signal may be associated with connecting the VIO pin 274 to ground. Similarly, in some cases, the logic high signal may be associated with connecting the VIO pin 274 to a voltage source.

In addition to setting the operating mode of the digital control interface 272, the VIO pin 274 may provide power from a power source, such as the power supply 262 (fig. 18), to the RFFE core 273. Thus, in some embodiments, when the VIO pin 274 is set to logic low or ground, the RFFE core 273 is not powered and the digital control interface 272 is configured to act as a GPIO interface. On the other hand, in some embodiments, when the VIO pin 274 is set to logic high or connected directly or indirectly to a power source, power is provided to the RFFE core 273 and the digital control interface 272 is configured to function as an RFFE serial interface.

Further, the digital control interface 272 includes a power on reset 278, which may be implemented in hardware, software, or a combination of the two. The power-on reset 278 is configured to facilitate resetting the RFFE core 273. In some embodiments, the power on reset 278 may be used as a reversal delay function. The inverse delay function is configured to provide sufficient time for setting one or more logic blocks and/or one or more registers associated with the RFFE core 273 to a known condition or value when the digital control interface 272 is configured as an RFFE serial interface. While the length of time may be application specific in some cases, the length of time may be based on hardware design and/or implementation characteristics in other cases. For example, the amount of time required may depend on the clock frequency, the size of the logic components, the type of component directly or indirectly connected to the digital control interface 272, and so on. Further, setting logic blocks and/or registers to known values may occur when initializing the RFFE core 273 or taking the RFFE core 273 out of a reset state.

In some implementations, the power on reset 278 can be configured to provide a select signal to the combinational logic block 279. For example, assume that the digital control interface 272 is configured to operate as a GPIO interface when the VIO pin 274 receives a logic low signal and as an RFFE serial interface when the VIO pin 274 receives a logic high signal. Continuing with this example, when the VIO pin 274 receives a logic low signal, the selection signal provided by the power on reset 278 may cause the combinational logic block 279 to output signals input to the data/enable pin 277 and the clock/mode pin 276 to the enable level shifter 282 and the mode level shifter 283, respectively. Alternatively, if the VIO pin 274 receives a logic high signal, the selection signal provided by the power on reset 278 may cause the combinational logic block 279 to output the signal provided by the RFFE core 273 to the enable level shifter 282 and the mode level shifter 283. In a particular embodiment, the combinational logic block 279 may delay or otherwise modify signals received from the data/enable pin 277 and the clock/mode pin 276 or the RFFE core 273 before outputting the signals to the level shifter.

Further, in some cases, the power-on reset 278 may be configured to place one or more of the level shifters 281 in a default state. For example, when the RFFE core 273 is in a reset state, the level shifter 281 may be placed in a default or reset state. In some designs, the power on reset 278 may be connected to a default high pin associated with each level shifter configured to be high during the GPIO interface mode and to a default low pin associated with each level shifter configured to be low during the GPIO interface mode. In some implementations, setting level shifter 281 into a default state can cause level shifter 281 to output a value based on a default input signal provided by default pin 284. Although the default pin 284 is illustrated as receiving a default input signal, in a number of embodiments the default pin 284 is tied to one of a default high and default low input. Thus, in some cases, the default value may be preconfigured, while in other cases, the default value may be variable based on configuration or operation. In some designs, it is possible that each level shifter 281 may be associated with a different default value or signal. Alternatively, each level shifter 281 may be associated with the same default value or signal.

Each of the level shifters 281 may be powered through the Vcc pin 287. In some implementations, each level shifter 281 may be separately connected to a power supply. Alternatively, a single level shifter 281 may be directly or indirectly connected to a power supply, and the remaining level shifters 281 may obtain power through a connection to the level shifter 281 or to other components of the power supply. Further, the level shifters 282 and 283 may each be connected to a power supply in a similar manner, or may be connected to a level shifter or may provide power to other components of the level shifters 282 and 283. In a particular embodiment, the level shifters 281, 282, and 283 are configured to adjust a voltage level of a received signal and output a modified signal. Although not so limited, the level shifters 281, 282, and 283 may adjust the voltage levels of the received signals to substantially match the voltage applied at the Vcc pin 287.

Although fig. 19 illustrates two level shifters 281, the invention is not so limited. The RFFE core 273 may communicate directly or indirectly with one, two, three, or any desired number of additional level shifters 281. Furthermore, in some cases, digital control interface 272 includes as many level shifters 281 as the number of registers (not shown) that RFFE core 273 includes. Each register may provide a signal associated with the register's value to a corresponding level shifter 281. In some cases, there may be more or fewer level shifters 281 than registers. For example, each level shifter 281 may be associated with two registers. In this example, logic within RFFE core 273 can determine which register's value is provided to the corresponding level shifter 281. As a second example, the RFFE core 273 may include additional registers included for use internal to the RFFE core 273. In this example, not all registers of RFFE core 273 may be associated with level shifter 281. Level shifters 281, 282, and 283 are described in more detail below with respect to fig. 20.

As indicated previously, the RFFE core 273 may include a set of registers (not shown). In a particular case, the set of registers may be set to an unknown value. For example, the set of registers may be set to an unknown value when the wireless device 248 is powered for the first time. As a second example, in an implementation in which the VIO pin 274 is used as both a power supply for the RFFE core 273 and a mode selector between RFFE and GPIO modes, the set of registers may be set to unknown values when the digital control interface 272 is first transitioned from a GPIO interface to an RFFE serial interface. To ensure that registers are set to known values when the RFFE core 273 is initially powered up or taken out of reset, the RFFE core 273 may be configured to set the values of each of the set of registers to the values provided by a set of binding defaults 286. In a particular implementation, the bundling defaults 286 may be equivalent to values provided to the default pins 284.

The RFFE core 273 may be configured to receive a clock signal from the clock/mode pin 276. This clock signal may be set to any frequency or signal shape based on the implementation of the RFFE core 273. In some implementations, the clock signal may be a square wave having a frequency of 26MHz or below 26 MHz. Further, the data interface of the RFFE core 273 may be bi-directional. Accordingly, the RFFE core 273 may receive data from the data/enable pin 277 at a data input of the RFFE core 273. Similarly, the RFFE core 273 may provide data from the data output of the RFFE core 273 to the data/enable pin 277. As illustrated in fig. 19, both data inputs and data outputs may be buffered by buffers 288 and 289. In some embodiments, the buffer may be a tri-state buffer. In some implementations, the output enable of RFFE core 273 is configured to control buffers 288 and 289 to enable both data outputs and data inputs to share the same line to and from data/enable pin 277. Thus, in some examples, when data is read from RFFE core 273, buffer 288 enables data flow while buffer 289 blocks data flow or is set to a high impedance. Similarly, in some examples, when data is written to RFFE core 273, buffer 289 enables data flow while buffer 288 blocks data flow or is set to a high impedance.

The following are non-limiting examples of use cases for the digital control interface 272. Other operations and uses are possible according to various embodiments described herein. In one example use case, a logic low signal is received at the VIO pin 274. Such a signal may be received from transceiver 257 (fig. 18), for example. Receipt of a logic low signal causes digital control interface 272 to operate as a GPIO interface. Thus, in this example, the RFFE core 273 is inactive. Further, the combinational logic block 279 passes signals received at the clock/mode pin 276 and the data/enable pin 277 to the mode level shifter 283 and the enable level shifter 282, respectively. Level shifters 282 and 283 provide the signals to power amplifier controller 252 after modifying the voltage levels of the signals. Power amplifier controller 252 (fig. 18) controls power amplifier 251 based on the signals received from level shifters 282 and 283 to set the amplification level of the signal received by power amplifier 251, such as a signal provided by power supply 262 or transceiver 257. Power amplifier controller 252 may also receive a signal associated with a default from level shifter 281. If so, power amplifier controller 252 may ignore the signal from level shifter 281 or may control power amplifier 251 based in part on the signal received from level shifter 281.

As a second example use case, with continued reference to fig. 18 and 19, a logic high signal is received at the VIO pin 274. Such a signal may be received from baseband chip 258 of fig. 18, for example. Receipt of a logic low signal causes the digital control interface 272 to operate as an RFFE serial interface. Thus, in this example, the RFFE core 273 is active and the combinational logic block 279 passes the mode and enable signals received from the RFFE core 273 to the mode level shifter 283 and the enable level shifter 282, respectively. Level shifters 282 and 283 provide the signals to power amplifier controller 252 after modifying the voltage levels of the signals. The power amplifier controller 252 may control the power amplifier 251 based in part on the signals received from the level shifters 282 and 283. In a particular embodiment, the power amplifier controller 252 may disregard the signals of the level shifters 282 and 283 when the digital control interface 272 is operating as an RFFE serial interface.

Continuing with the second example use case, the RFFE core 273 may receive a clock signal from the clock/mode pin 276 and an address signal from the data/enable pin 277. Alternatively or additionally, the RFFE core 273 may receive a data signal from the data/enable pin 277. In some cases, the data signal is received after the address signal. Alternatively, the data signal may be received before the address signal. Further, in embodiments where digital control interface 272 includes separate address pins (not shown), RFFE core 273 may receive address signals and data signals at least partially in parallel.

The RFFE core 273 may use a clock signal to synchronize the operation of one or more components associated with the RFFE core 273. Further, a clock signal may be used to facilitate identifying the register address and data associated with the signal received from the data/enable pins 277. The RFFE core 273 may use the address signal to identify a register associated with the RFFE core 273. The RFFE core 273 may then store the data associated with the data signal at a register. In some embodiments, the RFFE core 273 may modify existing data at a register based on the data signal. Furthermore, in some cases, a signal received at the data/enable pin 277 may control the RFFE core 273 or cause the RFFE core 273 to modify its operation.

In a particular embodiment, the RFFE core 273 may provide one or more signals to the level shifter 281. The signals provided by the RFFE core 273 may be associated with values and/or signals stored at registers associated with the RFFE core 273. Further, level shifter 281 may then provide the signal and/or a modified version of the signal to power amplifier controller 252. Power amplifier controller 252 sets the configuration of power amplifier 251 based at least in part on the signal from level shifter 281 (and in some cases, based at least in part on the signal from mode level shifter 283 and/or enable level shifter 282).

Generally, the signals received at the VIO pin 274, clock/mode pin 276 and data/enable pin 277 are digital signals. However, in some embodiments, one or more of the received signals may be analog signals. For example, the signal received at the VIO pin 274 may be an analog signal. Further, each of the components illustrated in FIG. 19 may be included in a single chip or die (e.g., digital control interface 253). Advantageously, in a particular embodiment, each of the components that include digital control interface 272 in a single die enables a wireless device (e.g., wireless device 248) to have the capability to use an RFFE serial interface, a GPIO interface, or both types of interfaces without requiring multiple chips. By using a single chip instead of multiple chips, particular embodiments may reduce power consumption and reduce the footprint required for the control interface of the power amplifier 251 or any other module that may use a control interface.

C. Level shifter

Fig. 20 illustrates an embodiment of a level shifter 291 according to an aspect of the present invention. Embodiments of level shifters 281, 282, and 283 may be equivalent or substantially equivalent to level shifter 291. In some implementations, the level shifters 281, 282, and 283 may be different in design from the level shifter 291. However, each of the level shifters is capable of modifying the voltage of an input signal. In some cases, the voltage of the input signal is shifted or modified to match the voltage provided at Vcc pin 287 (fig. 19). In other cases, the voltage of the input signal is shifted or modified in a range between the input voltage and the voltage provided at the Vcc pin 287.

During operation, the level shifter 291 can receive an input signal at input 292. Such an input signal may generally comprise any signal such that its voltage level is modified. Thus, for example, the input signals may include one or more of the signals previously described with respect to FIG. 19. For example, the input signal may be a signal provided from the RFFE core 273 (including from one of the registers associated with the RFFE core 273). As a second example, the input signal may be a signal provided by combinatorial logic block 279.

The input signal received at input 292 is provided to latch 293. The latch 293 may comprise any type of flip-flop. For example, as illustrated in fig. 20, the latch 293 may be a nand-based RS flip-flop. However, other types of flip-flops are possible. For example, the latch 293 may be a nor-based RS flip-flop. In a particular embodiment, the latch 293 ensures non-overlapping outputs from the latch 293. Ensuring non-overlapping outputs ensures that each pair of NFET transistors 294 are not activated at the same time. In some embodiments, two parallel signal paths with delay elements may be used to ensure that each pair of NFET transistors 294 are not activated at the same time.

With some implementations, the latch 293 provides two signals, one from each of the NAND gates (e.g., a set signal and a reset signal). Each of the signals may be provided to a pair of NFET transistors 294. NFET transistor 294 may be enabled by a signal from latch 293. When activated, the NFET transistor sets the state of the cross-coupled pair PFET transistor 296. The cross-coupled pair PFET transistor 296 causes the voltage level of the input signal to be level shifted. This level shifted signal is then provided at an output 297 to the power amplifier controller 252 or the power amplifier 251 shown in fig. 18, for example. In some embodiments, the NFET transistor 294 may be a PFET transistor and the PFET transistor 296 may be an NFET transistor, such as when a negative output voltage operation may be desired.

In some embodiments of the present invention, it is possible that no signal is provided at input 292 or that the signal is substantially zero. In such embodiments, NFET transistor 294 may be set or enabled by a default signal provided by default low input 298 and/or default high input 299. Although fig. 20 illustrates two defaults (default high input 299 and default low input 298), in several embodiments, only a single default signal is provided to the level shifter 291. If the desired output 297 is high during reset, the default high input 299 will be configured to provide a signal during reset. If instead the level shifter 291 is expected to provide a low output during reset, the default low input 298 will be configured to provide a signal during reset. The default input, which is not configured to set the NFET transistor 294 during reset, may be tied to ground, or may not be present in a particular implementation. In some implementations, default low input 298 and/or default high input 299 are preconfigured or connected to a signal generator that provides a predetermined signal. Alternatively, the default low input 298 and/or the default high input 299 may be connected to the power on reset 278 shown in fig. 19. In some embodiments, one or both of the default inputs 298 and 299 may be optional. For example, in some cases, the enable level shifter 282 and the mode level shifter 283 receive signals at their inputs.

D. Procedure for operating a digital control interface

FIG. 21 shows a flow diagram of a process 301 for operating a digital control interface, in accordance with an aspect of the present invention. Process 301 may be implemented by any type of digital control interface configured to operate as an RFFE serial interface and as a GPIO interface. For example, process 301 may be implemented by digital control interface 253 (fig. 18) and digital control interface 272 (fig. 19). Further, in some embodiments, process 301 may be implemented by any type of digital control interface configured to operate in different interface modes. Although the implementation of process 301 is not so limited, process 301 will be described as being implemented by digital control interface 272 of fig. 19 to simplify the discussion.

At block 302, process 301 begins when, for example, digital control interface 272 receives signals at VIO pin 274, clock/mode pin 276, and data/enable pin 277. In some embodiments, the signals received at one or more of the clock/mode pin 276 and the data/enable pin 277 may be delayed, may be noise, or may be ignored until the digital control interface 272 completes the initialization process.

At block 303, the signal received at the VIO pin 274 is provided to the RFFE core 273. In some embodiments, a signal from the VIO pin 274 powers the RFFE core 273. Further, the signal from the VIO pin 274, or lack thereof, may cause the RFFE core 273 to not receive power. In addition to providing the VIO signal to the RFFE core 273, block 303 may also include providing the VIO signal to a power on reset 278. In some embodiments, a power on reset 278 (fig. 19) may provide a signal from the VIO pin 274 to the combinational logic block 279. Further, the power on reset 278 may provide a delayed or modified signal to the combinational logic block 279 after delaying or otherwise modifying the signal from the VIO pin 274. Similarly, in particular embodiments, the power-on reset 278 may provide the VIO signal, a delayed version of the VIO signal, or a modified version of the VIO signal to a reset input associated with the RFFE core 273.

At block 304 shown in fig. 21, the signal received at the clock/mode pin 276 is provided to a combinational logic block 279. Similarly, at block 306, the signal received at the data/enable pin 277 is provided to a combinational logic block 279. Further, at block 307, a mode signal from an RFFE mode register associated with the RFFE core 273 is provided to the combinational logic block 279. Similarly, at block 308, an enable signal from an RFFE enable register associated with the RFFE core 273 is provided to the combinatorial logic block 279. During particular operating states, the signals provided at blocks 307 and 308 may be noise or may be some known or unknown signal that does not affect the operation of digital control interface 272. Furthermore, in some operating states, it is possible that no signal is to be provided at blocks 307 and 308. For example, in implementations in which RFFE core 273 is not powered, such as when digital control interface 272 is operating as a GPIO interface, it is possible that no signal is to be provided at blocks 307 and 308. In some implementations, blocks 307 and 308 may be optional.

At decision block 309, the digital control interface 272 determines whether the VIO signal is logic high. In a particular implementation, determining whether the VIO signal is a logic high includes configuring the digital control interface 272 based on the VIO signal. Configuring digital control interface 272 includes adjusting the operation of portions of digital control interface 272 and adjusting the flow of signals within digital control interface 272, as further described with respect to the remaining blocks of fig. 21.

If the VIO signal is not a logic high at decision block 309, the digital control interface 272 operates as a GPIO interface and the process 301 proceeds to block 311 where the RFFE core 273 is placed in a reset mode. This reset mode may be an active reset in which the RFFE core 273 maintains a known or unknown value in its register and outputs a value from its output port. Alternatively, if a logic low VIO signal is provided, for example by grounding the VIO pin 274 or by disconnecting the VIO pin 274 from the power supply, power to the RFFE core 273 is stopped while in the reset mode.

At block 312 of FIG. 21, the signal from the clock/mode pin 276 provided at block 304 is provided to a mode level shifter 283. Similarly, at block 313, the signal from the data/enable pin 277 provided at block 306 is provided to the enable level shifter 282. In a particular implementation, the signals provided to the level shifters at blocks 312 and 313 may be selected based on or based on the signal provided to the combinational logic block 279 by the power on reset 278. Further, in some cases, the signals provided to the level shifters 283 and 282 at blocks 312 and 313, respectively, may be delayed or modified by the combinational logic block 279 prior to providing the signals to the level shifters 283 and 282.

At block 314, the digital control interface 272 maintains a default value at the RFFE register level shifter 281. These default values are provided via default pins 284. In a number of implementations, the default value can be application specific. Further, the default values may be preconfigured and/or hard coded. Alternatively, the default value may be generated or determined based on operation of one or more of the digital control interface 272 and/or components associated with the wireless device 248. In a particular embodiment, block 314 may be optional.

If the VIO signal is logic high at decision block 309, the digital control interface 272 operates as an RFFE serial interface and the process 301 proceeds to block 316 where the RFFE core 273 is taken out of reset mode. In some cases, process 301 is performed when wireless device 248 is powered or initialized for the first time after a period of unpowered. In such cases, block 316 may be performed as part of the initialization of digital control interface 272. Further, block 316 may also include initializing the RFFE core 273 instead of or in addition to bringing the RFFE core 273 out of reset mode. Removing the RFFE core 273 from the reset mode may be a delayed process to provide sufficient time for stabilizing and/or initializing one or more registers, signals, and/or components associated with the RFFE core 273. This delay process may be controlled and/or implemented by the power-on reset 278. In some embodiments, block 316 may be optional.

At block 317, process 301 includes configuring internal registers (not shown) associated with RFFE core 273 to a default set of values. These default values may be provided by a binding default 286. Alternatively, the default value may be determined based on internal logic associated with the RFFE core 273 and set in response to signals received from one or more of the VIO pin 274, the clock/mode pin 276, and the data/enable pin 277.

At block 318, a mode signal from the RFFE core 273 is provided to the mode level shifter 283. This mode signal may be associated with or obtained from a mode register of the RFFE core 273. Alternatively or additionally, the mode signal may be based, at least in part, on one or more of the following, including: a signal received from the clock/mode pin 276, a signal received from the data/enable pin 277, a value based on the bundling default 286, and logic internal to the RFFE core 273.

Further, at block 319, an enable signal from the RFFE core 273 is provided to the enable level shifter 282. This enable signal may be associated with or obtained from an enable register of the RFFE core 273. Alternatively or additionally, the enable signal may be based at least in part on one or more of: a signal received from the clock/mode pin 276, a signal received from the data/enable pin 277, a value based on the bundling default 286, and logic internal to the RFFE core 273.

In a particular implementation of the present disclosure, the signals provided to the level shifters at blocks 318 and 319 may be selected based on or based on the signal provided to the combinational logic block 279 by the power on reset 278. Further, in some cases, the signals provided to the level shifters 283 and 282 at blocks 318 and 319, respectively, may be delayed or modified by the combinational logic block 279 prior to being provided to the level shifters 283 and 282.

At block 321, process 301 includes providing an RFFE register value or signal associated with the RFFE register to an RFFE level shifter 281. The RFFE register values are from registers associated with the RFFE core 273. In general, the registers of block 321 are different registers, although in some cases these registers may include the registers described above with respect to blocks 318 and 319. In addition, the mode of the power amplifier 251 is set or specified using the value provided by the register. When in the GPIO interface mode, the digital control interface 272 may be limited to specifying two modes, e.g., high and low, associated with two voltage values and/or two power amplification levels. In embodiments where the digital control interface includes additional pins, the digital control interface 272 may be capable of specifying the additional mode when in GPIO mode. When in the RFFE serial interface mode, the digital control interface 272 may set or specify different modes for the power amplifier 251 based on a value clocked into the RFFE core 273, a value stored in a register associated with the RFFE core 273, or a combination of the two.

Whether the VIO signal is logic high or logic low, the output of the mode level shifter 283 is provided to the power amplifier 251 at block 322. Similarly, whether the VIO signal is logic high or logic low, the output of the enable level shifter 282 is provided to the power amplifier 251 at block 322. In a particular embodiment, the outputs of the mode level shifter 283 and the enable level shifter 282 are provided to the power amplifier controller 252. The power amplifier controller 252 may then configure the power amplifier 251 based at least in part on the received signals from the mode level shifter 283 and the enable level shifter 282.

At block 324, the output of RFFE level shifter 281 is provided to power amplifier 251. Alternatively, the output of RFFE level shifter 281 may be provided to power amplifier controller 252, which may then configure power amplifier 251 based at least in part on the received signal from RFFE level shifter 281. When digital control interface 272 is operating as a GPIO interface, the output of RFFE level shifter 281 may be based at least in part on a default value or signal received at default pin 284. In contrast, when the digital control interface 272 is operating as an RFFE serial interface, the output of the RFFE level shifter 281 may include a value stored in a register associated with the RFFE core 273 based at least in part on a value or signal received from the RFFE core 273. In some embodiments, one or more of blocks 322, 323, and 324 may be optional. For example, when digital control interface 272 is operating as a GPIO interface, level shifter 281 may not provide a value to power amplifier 251 or power amplifier controller 252.

E. Second electronic device

Fig. 22 illustrates an alternative embodiment of a wireless device, referred to herein as wireless device 326, implemented according to aspects of the present invention. In some implementations of the invention, some or all of the embodiments described above with respect to wireless device 248 may be applied to wireless device 326.

Wireless device 326 may include a power amplifier module 327. Power amplifier module 327 may generally include any component or device having a power amplifier 328, a power amplifier controller 329 for controlling power amplifier 328, a mode selector 330, and a digital control interface 331. Although not so limited, controlling the power amplifier 328 generally refers to setting, modifying, or adjusting the amount of power amplification provided by the power amplifier 328.

As with digital control interface 253 of fig. 18, digital control interface 331 shown herein may include any type of control interface that may support multiple types of interfaces for controlling power amplifier 328 and/or for configuring power amplifier controller 329 to control power amplifier 328. For example, the digital control interface 331 may include a serial interface 332 and a GPIO interface 333. The serial interface 332 may comprise any type of serial interface. For example, the serial interface can be an RFFE serial interface (to name a few) (e.g., Serial interface), Serial Peripheral Interface (SPI) bus, 3-wire serial bus, or I²And C, a bus. In some implementations, some or all of the embodiments described above with respect to digital control interface 253 can be applied to digital control interface 331.

In a number of embodiments, the digital control interface 331 can include multiple interface types on the same component die without requiring circuit design changes or bonding changes of existing component die configurations (e.g., existing power amplifiers, existing power amplifier modules, existing transceivers, or other components that can provide control signals to or receive control signals from the digital control interface). Further, in some embodiments, digital control interface 331 may support multiple interfaces without increasing the number of interface connections (e.g., pins, leads, wires, ball grid arrays, etc.) exposed for use by wireless device 326 or power amplifier module 327. Advantageously, in several embodiments, digital control interface 331 may be used with devices that support different interface standards without modifying digital control interface 331. For example, the illustrated digital control interface 331 of fig. 22 may be used with devices that support serial interfaces, GPIO interfaces, or a combination of the two without modifying the digital control interface. In some cases, digital control interface 331 may switch between different interface types during operation.

Mode selector 330 may include any device or component configured to select a mode of operation of digital control interface 331. Selecting an operating mode of digital control interface 331 may include selecting a type of interface that digital control interface 331 uses to communicate with power amplifier controller 329. For example, the mode selector 330 may select or configure the digital control interface 331 to function as a serial interface or a GPIO interface. This selection may be based on signals received from antenna 338, transceiver 334, baseband chip 336, or any other signal source that may provide signals that may be used to select an interface type or determine an interface type to select from the available interface types for digital control interface 331.

Further, in a particular implementation, digital control interface 331 may set an operating mode of power amplifier 328, either directly or via power amplifier controller 329, based on one or more signals received from a signal source. In a particular embodiment, the digital control interface 331 receives one or more signals from, for example, the antenna 338, the transceiver 334, the baseband 336, or the DSP337 that cause the digital controller interface 331 to set the operating mode of the power amplifier 328 while receiving a signal from the mode selector 330 that selects an operational interface type of the digital control interface 331. Alternatively, digital control interface 331 may receive one or more signals from mode selector 330 that cause digital control interface 331 to set the operating mode of power amplifier 328 and a signal that selects the operational interface type of digital control interface 331. Mode selector 330 may receive some or all of the signals from, for example, antenna 338, transceiver 334, baseband 336, or DSP 337. Alternatively or in addition, the mode selector 330 may generate some or all of the signals provided to the digital control interface 331 based on one or more signals received from, for example, the antenna 338, the transceiver 334, the baseband 336, or the DSP 337.

In one example of a scenario for setting the mode of power amplifier 328, transceiver 334 receives a signal from, for example, antenna 338 or DSP 337. In response to receiving the signal, transceiver 334 may provide one or more signals to mode selector 330. Based on one or more signals received from transceiver 334, mode selector 330 may configure digital control interface 331 to operate as a serial interface or a GPIO interface. Further, the transceiver 334 can provide one or more signals to the digital control interface 331 that processes signals in serial mode or GPIO mode based on the mode specified by the mode selector 330. Based on the results of processing the signals, the digital control interface 331 may provide one or more mode setting signals to the power amplifier controller 329, which may set the mode of the power amplifier 328 based on the mode setting signals. Alternatively, the digital control interface 331 may set the mode of the power amplifier 328.

In some implementations, the power amplifier 328 may include one or more of a power amplifier controller 329, a digital control interface 331, and a mode selector 330. For some implementations, the power amplifier controller 329 may include one or more of a digital control interface 331 and a mode selector 330. Further, in some cases, the digital control interface may include a mode selector 330. Further, power amplifier module 327 may be a single component that includes the functionality of mode selector 330, digital control interface 331, power amplifier controller 329, and power amplifier 328. Alternatively, power amplifier module 327 may include a plurality of components including the functionality of mode selector 330, digital control interface 331, power amplifier controller 329, and power amplifier 328. In still other implementations, wireless device 326 may include one or more components including the functionality of mode selector 330, digital control interface 331, power amplifier controller 329, and power amplifier 328.

Similar to the power amplifier module 249 of fig. 18, the power amplifier module 327 shown in fig. 22 may receive power from a power supply 339. Power amplifier module 327 may then distribute the power to a number of components included in wireless device 326 via, for example, power distribution bus 341.

In a particular embodiment, the power supply 339 includes combinatorial logic and/or one or more processors that enable the power supply 339 (in some cases) to configure one or more elements of the power amplifier module 327. For example, in some cases, the power supply 339 may provide one or more signals to the digital control interface 331 to enable the digital control interface 331 to configure the power amplifier 328. Further, the power supply 339 may provide the signal to, for example, a digital control interface 331 based on the output of the power amplifier 328, thereby forming a feedback loop between the power amplifier module 327 and the power supply 339.

Wireless device 326 may include a number of additional components. At least some of these additional components may receive power via a power distribution bus 341. For example, wireless device 326 may include a digital-to-analog converter (DAC)342, a display processor 343, a central processor 344, a user interface processor 346, an analog-to-digital converter (ADC)347, and a memory 348. At least some of the additional components may be in communication with digital control interface 331 and may cause digital control interface 331 to modify settings of power amplifier module 327, power amplifier 328, and/or power amplifier controller 329. Additionally, at least some of the additional components may be in communication with the mode selector 330 and cause the mode selector 330 to select the mode of operation of the digital control interface 331.

F. Second digital control interface

FIG. 23 illustrates an embodiment of the digital control interface 331 of FIG. 22, as implemented in accordance with certain aspects of the present disclosure. In some implementations, some or all of the embodiments described above with respect to digital control interface 253 and digital control interface 272 can be applied to digital control interface 331.

Digital control interface 331 includes serial interface 332, GPIO interface 333, and a number of input pins. These input pins may include a VIO pin 351, a clock/mode pin 352, and a data/enable pin 353.

The VIO pin 351 may be configured to receive a signal that sets the digital control interface 331 to operate as a serial interface or a GPIO interface. In the illustrated embodiment, digital control interface 331 operates as a serial interface when VIO pin 351 receives a logic high signal and operates as a GPIO interface when VIO pin 351 receives a logic low signal. However, in some implementations, the digital control interface 331 may be configured to operate as a serial interface when the VIO pin 351 receives a logic low signal and as a GPIO interface when the VIO pin 351 receives a logic high signal. The logic low signal may be associated with any value defined to be low (e.g., 0 volts, -5 volts, or other). Similarly, the logic high signal may be associated with any value defined to be high (e.g., 0 volts, +5 volts, or otherwise). In some implementations, the logic low signal may be associated with connecting the VIO pin 351 to ground. Similarly, in some cases, the logic high signal may be associated with connecting the VIO pin 351 to a voltage source.

Further, the VIO pin 351 may be configured to provide power from a power source, such as power supply 339 (fig. 22), to the serial interface core 349. Thus, in some embodiments, when the VIO pin 351 is set to logic low or ground, the serial interface core 349 is not powered and the digital control interface 331 is configured to function as a GPIO interface. On the other hand, in some embodiments, when the VIO pin 351 is set to logic high or connected directly or indirectly to a power supply, power is provided to the serial interface core 349 and the digital control interface 331 is configured to function as a serial interface. In some implementations, some or all of the embodiments described above with respect to the VIO pin 274 may be applied to the VIO pin 351.

The serial interface 332 may include a front end core or a serial interface core 349. Further, the serial interface 332 may include a power on reset 354, a pair of buffers 368 and 369, and a number of level shifters 357. The GPIO interface 333 may include a combinational logic block 356 and a pair of level shifters 358 and 359. When the digital control interface 331 is acting as a serial interface, components of the serial interface 332 are active or operative to provide a serial interface and one or more components of the GPIO interface 333 may be inactive. Similarly, when digital control interface 331 functions as a GPIO interface, components of GPIO interface 333 are active or operative to provide a GPIO interface and one or more components of serial interface 332 may be inactive.

However, in a particular embodiment, when digital control interface 331 is acting as a serial interface, digital control interface 331 may use one or more components of GPIO interface 333 to facilitate providing the serial interface, and thus, one or more components of GPIO interface 333 may be functional or operative to provide the serial interface. Similarly, in a particular embodiment, when digital control interface 331 is acting as a GPIO interface, digital control interface 331 can use one or more components of serial interface 332 to facilitate providing the GPIO interface, and thus, one or more components of serial interface 332 can be functional or operative to provide the GPIO interface. For example, in some implementations, the combinational logic block 356 may include a multiplexer controlled by a power on reset 354. Furthermore, in this example, the combinational logic block 356 may provide different signals to the level shifters 358 and 359 based on the operating mode of the digital control interface 331 and thus the value output by the power on reset 354. Thus, in this example, while the power on reset 354 is typically part of the serial interface 332, the power on reset 354 may serve as part of a GPIO interface when the digital control interface is in a GPIO interface mode. Similarly, in this example, while the combinatorial logic block 356 and the level shifters 358 and 359 are typically part of the GPIO interface 333, the combinatorial logic block 356 and one or more of the level shifters 358 and 359 may be operable to help provide a serial interface when the digital control interface 331 is in a serial interface mode.

The power on reset 354 may be implemented in hardware, software, or a combination of the two. Further, the power on reset 354 may be configured to facilitate resetting the serial interface core 349. In some embodiments, the power on reset 354 may be used as an inverting delay function. The inverse delay function is configured to provide sufficient time for one or more logic blocks and/or one or more registers associated with the serial interface core 349 to be set to a known condition or value when the digital control interface 331 is configured as a serial interface. While the length of time may be application specific in some cases, the length of time may be based on hardware design and/or implementation characteristics in other cases. For example, the amount of time required may depend on the clock frequency, the size of the logic component, the type of component directly or indirectly connected to the digital control interface, and so forth. Further, setting logic blocks and/or registers to known values may occur when the serial interface core 349 is initialized or the serial interface core 349 is taken out of a reset state.

In some implementations, the power on reset 354 can be configured to provide a select signal to the combinational logic block 356. For example, assume that digital control interface 331 is configured to operate as a GPIO interface when VIO pin 351 receives a logic low signal and as a serial interface when VIO pin 351 receives a logic high signal. Continuing with this example, when the VIO pin 351 receives a logic low signal, the selection signal provided by the power on reset 354 may cause the combinational logic block 356 to output signals based on inputs to the data/enable pin 353 and the clock/mode pin 352 to the enable level shifter 358 and the mode level shifter 359, respectively. For example, the combinational logic block 356 may decode signals received from the clock/mode pin 352 and the data/enable pin 353 and provide the decoded signals to the enable level shifter 358 and the mode level shifter 359.

If the VIO pin 351 receives a logic high signal instead of a logic low signal in this example, the select signal provided by the power on reset 354 may cause the combinational logic block 356 to output a signal based on the signal received from the serial interface core 349 to the enable level shifter 358 and the mode level shifter 359. In a particular embodiment, the combinational logic block 356 may delay or otherwise modify signals received from the data/enable pin 353 and the clock/mode pin 352 or the serial interface core 349 before outputting the signals to the level shifters 358 and 359.

In some cases, the power on reset 354 may be configured to place one or more of the level shifters 357 in a default or reset state. This may occur, for example, when the serial interface core 349 is in a reset state. In some designs, the power on reset 354 may be connected to a default high pin associated with each level shifter configured to be high during the GPIO interface mode and to a default low pin associated with each level shifter configured to be low during the GPIO interface mode. In some implementations, setting level shifter 357 into a default state may cause level shifter 357 to output a value based on a default input signal provided by default pin 361. Although the default pin 361 is illustrated as receiving a default input signal, in a number of embodiments the default pin 361 is tied to one of a default high and a default low input. Thus, in some cases, the default values may be pre-configured, while in other cases, the default values may be application specific and may vary based on the configuration or operation of the digital control interface 331 or the power amplifier module. In some designs, it is possible that each level shifter 357 may be associated with a different default value or signal. Alternatively, each level shifter 357 may be associated with the same default value or signal.

Each of the level shifters 357 may be powered through Vcc pin 363. In some implementations, each level shifter 357 may be separately connected to a power supply. Alternatively, a single level shifter 357 may be connected directly or indirectly to a power supply, and the remaining level shifters 357 may obtain power through connections to the level shifter 357 or other components connected to the power supply. Further, level shifters 358 and 359 may each be connected to a power supply in a similar manner, or may be connected to a level shifter or may provide power to other components of level shifters 358 and 359. In a particular embodiment, the level shifters 357, 358, and 359 are configured to adjust voltage levels of received signals and output modified signals. Although not so limited, the level shifters 357, 358, and 359 can adjust the voltage levels of the received signals to substantially match the voltage applied at the Vcc pin 363.

In some implementations, some or all of the embodiments described above with respect to the power on reset 278 may be applied to the power on reset 354. Similarly, in some implementations, some or all of the embodiments described above with respect to level shifter 284 may be applied to level shifter 357. Furthermore, in some implementations, some or all of the embodiments described above with respect to level shifters 282 and 283 may be applied to level shifters 358 and 359, respectively. Additionally, some or all of the embodiments described above with respect to level shifter 291 with reference to FIG. 20 above may be applied to the level shifters 357, 358, and 359 shown herein in FIG. 23.

The serial interface core 349 may generally include circuitry or logic that enables the serial interface core to provide a serial interface. In some embodiments, the serial interface core 349 may include an RFFE core (e.g., RFFE core 273). Further, in some examples, serial interface core 349 may include some or all of the embodiments described above with respect to RFFE core 273.

As with the RFFE core 273, the serial interface core 349 may include a set of registers (not shown). In a particular case, the set of registers may be set to an unknown value. For example, the set of registers may be set to an unknown value when the wireless device 326 is powered for the first time. As a second example, in an implementation in which the VIO pin 351 is used as both a power supply for the serial interface core 349 and a mode selector between the serial interface mode and the GPIO interface mode, the set of registers may be set to unknown values the first time the digital control interface 331 transitions from the GPIO interface to the serial interface. To ensure that registers are set to known values when the serial interface core 349 is initially powered up or brought out of a reset state, the serial interface core 349 may be configured to set the values of each of the set of registers to the values provided by a set of bundling defaults 362. In a particular implementation, bundling defaults 286 (FIG. 19) may be equivalent to providing values to default pins 361.

In a particular embodiment, the serial interface core 349 may be configured to receive a clock signal from the clock/mode pin 352. This clock signal may be set to any frequency or signal shape based on the implementation of the serial interface core 349. In some implementations, the clock signal may be a square wave having a frequency of 26MHz or below 26 MHz. Further, the data interface of the serial interface core 349 may be bidirectional. Thus, the serial interface core 349 may receive data from the data/enable pins 388 at the data input of the serial interface core 349. Similarly, the serial interface core 349 may provide data from the data output of the serial interface core 349 to the data/enable pin 353. As illustrated in fig. 23, both data inputs and data outputs may be buffered by buffers 368 and 369. In some embodiments, the buffer may be a tri-state buffer. Further, the output enable of the serial interface core 349 may be configured to control the buffers 368 and 369 to enable both data out and data in to share the same line to and from the data/enable pin 353. Thus, in some examples, when data is read from the serial interface core 349, the buffer 368 enables data flow while the buffer 369 prevents data flow or is set to a high impedance. Similarly, in some examples, when data is written to the serial interface core 349, the buffer 369 enables data flow while the buffer 368 blocks data flow or is set to a high impedance.

The combinational logic block 356 generally includes any logic that causes the digital control interface 331 to provide an enable signal and a mode signal to the enable level shifter 358 and the mode level shifter 359, respectively. In some embodiments, the combinatorial logic block 356 includes logic to enable decoding of signals. The combinatorial logic block 356 may then provide the decoded signal to one or both of the level shifters 358 and 359. In some examples, the combinatorial logic block 356 of this embodiment may include some or all of the embodiments described above with respect to the combinatorial logic block 279 shown in fig. 19.

In some implementations, the digital control interface 331 can perform the process 301 described above with respect to fig. 21. In such implementations, operations associated with the RFFE core may instead be performed by the serial interface core 349. For example, block 311 may include placing the serial interface core 349 in a reset mode. As a second example, block 321 may include providing serial interface register values or signals associated with registers of the serial interface core 349 to the serial interface level shifter 357.

G. Combinational logic block

FIG. 24 illustrates further details of an embodiment of the combinatorial logic block 356 shown in FIG. 23 and implemented in accordance with aspects of the present invention. As described above, the combinational logic block 356 may be configured to output an enable signal and a mode signal to the level shifters 358 and 359, respectively. Further, the combinational logic block 356 includes logic that determines whether the enable and mode signals are based on inputs received from the serial interface core 349 or inputs received from the clock/mode pin 352 and the data/enable pin 353. In some cases, when digital control interface 331 is operating as a GPIO interface, the enable signal and the mode signal may be based on inputs received via additional logic or devices (not shown) that receive input signals from clock/mode pin 352 and data/enable pin 353. Similarly, in some cases, when digital control interface 331 is operating as a serial interface, the enable signal and the mode signal may be based on inputs received via additional logic or devices (not shown) that receive signals from serial interface core 349. In some cases, the additional logic or device may process the signals before providing them to the combinational logic block 356.

As illustrated in FIG. 24, combinatorial logic block 356 includes multiplexer 378 and multiplexer 379. Multiplexer 378 may provide an enable signal to enable level shifter 358 and multiplexer 379 may provide a mode signal to mode level shifter 359. Each of the multiplexers may be controlled by a reset signal received from the reset input 377 to the combinational logic block 356. As described above, the reset signal may be received from the power on reset 354, and in some cases, may be an inverted version of the signal received from the VIO pin 351.

As previously described, in some embodiments, digital control interface 331 operates as a GPIO interface when the reset signal received at reset input 377 for combinational logic block 356 is a logic high or '1'. In such cases, multiplexer 378 outputs a signal received at data/enable input 376, and multiplexer 379 outputs a signal received at clock/mode input 374. As illustrated by the small squares, in some cases, inputs for data/enable input 376 and clock/mode input 374 may be received from data/enable pin 353 and clock/mode pin 352, respectively, without any intervening logic or components. In other embodiments, additional logic may be present between pin 352 and pin 353 (FIG. 23) and between input 374 and input 376, respectively.

In some embodiments, the combinational logic block 356 may include an and gate 381 between the data/enable input 376 and the multiplexer 378 and/or an and gate 382 between the clock/mode input 374 and the multiplexer 379. Although some embodiments include an AND gate, the output of the multiplexer does not change because the reset input 377 is logic high at the input of the select data/enable input 376 and the clock/mode input 374. In a particular embodiment, an AND gate is included to reduce or eliminate digital noise caused by the frequencies of the signals and/or the proximity of the signal paths to each other. The data and clock signals may be high speed digital signals, which may be as fast as 26MHz in some implementations, in some cases. In other cases, the signal may be faster or slower than 26MHZ and may be application dependent. The and gate may be used to limit the number of nodes that toggle at the rate of the signal, thereby limiting the amount of clock energy that may degrade the RF performance aspect of one or more devices (e.g., power amplifier controller 329, power amplifier 328, etc.) in communication with combinatorial logic block 356. In some cases, an and gate may introduce a delay that enables synchronization of one or more signals. In particular embodiments, the and gate may be optional.

Although the combinational logic block 356 of FIG. 24 includes AND gates, it is possible for the combinational logic block 356 to include other types of logic in addition to or in place of the AND gates 381 and 382. For example, combinatorial logic block 356 may include one or more and gates, nand gates, inverters, or gates, nor gates, or xor gates between inputs 376 and 374, and multiplexers 378 and 379, respectively.

When the reset signal received at reset input 377 for combinational logic block 356 is a logic low or '0', digital control interface 331 operates as a serial interface. In such cases, multiplexer 378 outputs the signal received at serial enable input 372, and multiplexer 379 outputs the signal received at serial mode input 373.

Although fig. 24 does not illustrate any additional logic than has been previously described, in some implementations, the combinatorial logic block 356 may include additional logic components. For example, additional gates may be included to reduce noise, delay the timing of the signal, or store previous signals.

H. Third digital control interface

Referring next to FIG. 25, another embodiment of a digital control interface, referred to herein as digital control interface 383, as implemented in accordance with other aspects of the present invention is shown. In some cases, digital control interface 383 can replace digital control interface 331 (illustrated in fig. 23) of wireless device 326 (illustrated in fig. 22). In some implementations, some or all of the embodiments described above with respect to digital control interface 253, digital control interface 272, and digital control interface 331 can be applied to current digital control interface 383. To simplify the discussion, elements that are common between digital control interface 331 and digital control interface 383 are not repeated below.

Advantageously, in particular embodiments, digital control interface 383 may support three modes when configured as a GPIO interface. In some cases, by enabling digital control interface 383 to support three modes when configured as a GPIO interface, digital control interface 383 is able to support more power amplifier modes than a signal control interface using a separate mode and an enable pin. Furthermore, in some cases, additional modes may be supported without adding additional pin inputs and without extending the package size of the digital control interface. In some implementations, these advantages may be achieved by replacing the data/enable pin 353 of the digital control interface 331 with a pin that provides a second mode input and by modifying the combinational logic block 356 to interpret the fourth available mode as an unenabled signal.

As illustrated in fig. 25, the digital control interface 383 may include a clock/mode 0 pin 384 and a data/mode 1 pin 386. Pins 384 and 386 may be configured in a manner similar to pins 352 and 353, respectively, of digital control interface 331. However, when the digital control interface 383 is configured as a GPIO interface, the clock/mode 0 pin 384 may provide the first mode signal to the combinational logic block 388 and the clock/mode 1 pin 386 may provide the second mode signal to the combinational logic block 388.

The GPIO interface 387 may include two mode level shifters, a mode 0 level shifter 389 and a mode 1 level shifter 391. When the signal output by the enable level shifter 358 indicates that the power amplifier 328 (fig. 22) should be enabled, the signals output by the two mode level shifters may be used by the power amplifier controller 329 to set the amplification level of the signal received by the power amplifier 328. In some embodiments, the power amplifier 328 is enabled regardless of the output of the level shifter 358 that is enabled. In some such cases, the output of the enable level shifter 358 may be used by the power amplifier controller 329 to determine whether to adjust the mode of the power amplifier 328 based on the outputs of the two mode level shifters 389 and 391.

As will be described in more detail below with respect to FIG. 26, the signal supplied to the enable level shifter 358 may be based on signals received at mode pins 384 and 386. Further, in some cases, the serial interface core 349 may provide three signal connections to the combinational logic block 388, as illustrated in FIG. 25. In other cases, the serial interface core 349 may provide more or fewer signal lines to the combinational logic block 388. In such cases, the signal lines may be combined or decomposed using one or more logic blocks and based at least in part on the number of level shifters that receive output signals from the combinational logic block 388.

I. Second combinational logic block

FIG. 26 illustrates an alternative embodiment of a current combinational logic block, designated herein as combinational logic block 388, that may be implemented according to still further aspects of the present invention. In some embodiments, the combinational logic block 388 may include some or all of the features or characteristics as previously described with respect to the combinational logic block 356.

Similar to the combinational logic block 356, the combinational logic block 388 includes logic that determines whether the enable and mode signals are based on inputs received from the serial interface core 349 or inputs received from the clock/mode 0 pin 384 and the data/mode 1 pin 386. In some cases, when digital control interface 383 is operating as a GPIO interface, the enable signal and the mode 0 and mode 1 signals may be based on inputs received via additional logic or devices (not shown) that receive input signals from clock/mode 0 pin 384 and data/mode 1 pin 386. Similarly, in some cases, when digital control interface 383 is operating as a serial interface, the enable signal and the mode 0 and mode 1 signals may be based on inputs received via additional logic or devices (not shown) that receive signals from serial interface core 349. In some cases, the additional logic or device may process the signals before providing them to the combinational logic block 388.

As illustrated in FIG. 26, the combinational logic block 388 includes three multiplexers. The multiplexer 401 may provide an enable signal to the enable level shifter 358. When digital control interface 383 is configured as a serial interface, multiplexer 401 outputs an enable signal that is received from serial interface core 349 via serial enable input 396. When digital control interface 383 is configured as a GPIO interface, multiplexer 401 outputs an enable signal that is based on the logical OR of the signals received from clock/mode 0 input 393 and data/mode 1 input 394. A logical or may be obtained via an or gate 407 illustrated in fig. 26. However, other logical equivalents are possible, such as by using NOR gates and inverters.

Multiplexer 402 may provide a first mode signal or a mode 0 signal to mode 0 level shifter 389. Similarly, the multiplexer 403 may provide a second mode signal or a mode 1 signal to the mode 1 level shifter 391. When digital control interface 383 is configured as a serial interface, multiplexer 402 outputs a mode 0 signal that is received from serial interface core 349 via serial mode 0 input 397. Likewise, when digital control interface 383 is configured as a serial interface, multiplexer 403 outputs a mode 1 signal that is received from serial interface core 349 via serial mode 1 input 398.

When digital control interface 383 is configured as a GPIO interface, multiplexer 402 outputs a logical and of the signal received at clock/mode 0 input 393 and the reset signal received at reset input 399. Similarly, when digital control interface 383 is configured as a GPIO interface, multiplexer 403 outputs a logical and of the signal received at data/mode 1 input 394 and the reset signal received at reset input 399. A logical and may be obtained through and gates 404 and 406. However, other logical equivalents are possible, such as by using NAND gates and inverters. The use of and gates 404 and 406 may reduce or eliminate digital noise as previously described with respect to fig. 24.

Each of the multiplexers may be controlled by a reset signal received from reset input 399. In other words, the select signal provided to the multiplexer may be a reset signal. As described above, the reset signal may be received from the power on reset 354, and in some cases may be an inverted version of the signal received from the VIO pin 351. When the reset signal is a logic '1', digital control interface 383 is configured as a GPIO interface, and the multiplexer outputs signals as described above for the GPIO interface mode. When the reset signal is a logic '0', the digital control interface 383 is configured as a serial interface, and the multiplexer outputs the GPIO signals as described above for the serial interface mode.

As previously described, the digital control interface 383 using the combinational logic 388 can provide three different modes to the power amplifier controller 329 and/or the power amplifier 328 by using the values of the mode 0 pin 384 and the mode 1 pin 386 to determine whether to output the enable signal instead or to dedicate a separate pin to the enable control signal. When one of the three configured modes is selected, the combinational logic block 388 is configured to output an enable signal. When the fourth mode is selected, the combinational logic block 388 is configured to output a not enabled signal. Table 1, presented below, illustrates one non-limiting example of the output of the combinational logic block 388 to the level shifter based on the value of the mode pin when the digital control interface 383 is configured as a GPIO interface. The mode settings of table 1 correspond to settings of the power amplifier controller 329 based on the outputs of the mode 0 signal and the mode 1 signal to the mode 0 level shifter 389 and the mode 1 level shifter 391, respectively.

TABLE 1

Mode 0	Mode 1	Activation of	Mode setting
				0	0	Whether or not	-
0	1	Is that	1
				1	0	Is that	2
1	1	Is that	3

In some embodiments, digital control interface 383 may perform a modified version of process 301 shown in fig. 21. For example, in some cases, block 318 may include providing first and second mode signals from the serial interface core to the first mode level shifter 389 and the second mode level shifter 391, respectively. Furthermore, in some cases, block 312 includes providing a first mode signal from clock/mode pin 384 to first mode level shifter 389 and a second mode signal from data/mode pin 386 to second mode level shifter 391. In a particular embodiment, by providing two mode signals, digital control interface 383 may provide three modes when operating as a GPIO interface instead of two.

In some embodiments, the operations of block 313 may be modified to provide the first mode signal and the second mode signal to the combinational logic block 388 from the clock/mode pin 384 and the data/mode pin 386, respectively. The combinational logic block 388 may then determine whether to provide an enable signal to the enable level shifter 358 based on the first and second mode signals, thereby enabling the digital control interface 383 to output the enable signal to the power amplifier controller 329 without a dedicated enable pin. Advantageously, in certain situations, by eliminating the need for an enable pin, the digital control interface may support more modes for configuring the power amplifier by repurposing the enable pin as a second mode pin.

J. Additional embodiments

In some embodiments, the digital control interface includes a voltage input/output (VIO) pin configured to receive a VIO signal. Further, the digital control interface may include a front end core configured to provide a serial interface. The front-end core may be in an active state when the VIO signal satisfies a first logic level and in an inactive state when the VIO signal satisfies a second logic level. Further, the digital control interface may be configured to provide a general purpose input/output (GPIO) interface when the front-end core is set to an inactive state. In addition, the digital control interface may include a combinational logic block configured to provide an enable signal to the enable level shifter and a mode signal to the mode level shifter. Further, the digital control interface may include a clock/mode pin and a data/enable pin. The clock/mode pin may be configured to provide a clock signal to the front-end core when the front-end core is set to an active state and a mode signal to the combinational logic block when the front-end core is set to an inactive state. The data/enable pin may be configured to provide a data signal to the front-end core when the front-end core is set to an active state and an enable signal to the combinational logic block when the front-end core is set to an inactive state. Further, the digital control interface may include a power-on reset configured to select a source of an enable signal and a mode signal provided to the enable level shifter and the mode level shifter, respectively, based on the VIO signal. With some implementations, the front-end core includes a radio frequency front-end (RFFE) core.

In some cases, the data/enable pin is further configured to provide an address signal to the front-end core when the front-end core is set to an active state, the address signal being associated with a register of the front-end core.

In some implementations, the digital control interface can include a plurality of register level shifters. Each register level shifter of the plurality of register level shifters may be configured to receive a register signal from the front end core and output the register signal, thereby enabling the power amplifier to be configured based on the register signal associated with a value stored in one of a plurality of registers associated with the front end core. In some cases, the at least one register level shifter is further configured to receive a default signal during the reset state. Furthermore, the power-on reset block may be further configured to place the at least one register level shifter in a reset state. In some cases, the power-on reset block may be further configured to provide a delayed reset signal to the front-end core.

In a particular embodiment, the digital control interface includes a first buffer and a second buffer. A first buffer may be connected between the data/enable pin and the output port of the front-end core, and a second buffer may be connected between the data/enable pin and the input port of the front-end core. Furthermore, the first buffer may be configured to enable reading of data from the front-end core and the second buffer may be configured to enable providing of data to the front-end core. Both the first buffer and the second buffer may be tri-state buffers. In some designs, the connection between the first buffer and the data/enable pin is a shared path with the connection between the second buffer and the data/enable pin. The first buffer and the second buffer may be further configured to prevent data from flowing through the first buffer and the second buffer simultaneously.

Some embodiments of the invention may be configured to implement a method for providing multiple control interfaces in a digital control interface including a front-end core and a combinational logic block. The method may include receiving a VIO signal at a VIO input to a digital control interface and determining whether the VIO signal is logic high. In response to determining that the VIO signal is a logic high, the method may include configuring the digital control interface to function as a serial interface by: providing a clock signal from a clock input to a front-end core; providing a data signal from a data input to a front-end core; and selecting the first enable signal and the first mode signal at the combinational logic block for output to the enable level shifter and the mode level shifter. Both the first enable signal and the first mode signal may be received from the front-end core. In response to determining that the VIO signal is a logic low, the method may include configuring the digital control interface to function as a general purpose input/output (GPIO) interface by: providing a second enable signal from the enable input to the combinational logic block; providing a second mode signal from the mode input to the combinational logic block; and selecting the second enable signal and the second mode signal at the combinational logic block for output to the enable level shifter and the mode level shifter.

In some implementations, the method may include reconfiguring the front-end core from a reset state to an active state in response to determining that the VIO signal is a logic high. Reconfiguring the front-end core from the reset state to the active state may include configuring a set of internal registers of the front-end core to default values. With some implementations of the method, at least one register from the set of internal registers is configured to be different from a default value of at least one other register from the set of internal registers.

Further, the method may include providing an output of an enable level shifter and an output of a mode level shifter to a power amplifier controller, thereby enabling the power amplifier controller to configure a power amplifier based on the output of the enable level shifter and the output of the mode level shifter. Additionally, the method may include placing the front-end core in a reset mode in response to determining that the VIO signal is logic low. Placing the front-end core in a reset mode may include maintaining a default value at a set of register level shifters.

Particular aspects of the disclosure in this section may be included as part of a power amplifier and power amplifier module, and thus advantageously used in a wireless mobile device as described in detail herein above. The power amplifier may include a digital control interface and a mode selector configured to provide a VIO signal to the digital control interface. The VIO signal may be configured to set a mode of the digital control interface. In a particular implementation, a digital control interface includes: a voltage input/output (VIO) pin configured to receive a VIO signal; and a front-end core configured to provide a serial interface. The front-end core may be in an active state when the VIO signal satisfies a first logic level and in an inactive state when the VIO signal satisfies a second logic level. The digital control interface may be configured to provide a general purpose input/output (GPIO) interface when the front-end core is set to an inactive state. Further, the digital control interface may include: a combinational logic block configured to provide an enable signal to the enable level shifter and a mode signal to the mode level shifter; and a clock/mode pin configured to provide a clock signal to the front-end core when the front-end core is set to an active state and a mode signal to the combinational logic block when the front-end core is set to an inactive state. Further, the digital control interface may include a data/enable pin configured to provide a data signal to the front-end core when the front-end core is set to an active state and an enable signal to the combinational logic block when the front-end core is set to an inactive state. In some cases, the digital control interface includes a power-on reset block configured to select sources of enable and mode signals provided to the enable and mode level shifters, respectively, based on the VIO signal. In some implementations, the power amplifier control module also includes a power amplifier and a power amplifier controller configured to receive an enable signal from the enable level shifter and a mode signal from the mode level shifter and provide a control signal to the power amplifier based on the mode signal. The control signal may specify an operating mode of the power amplifier.

In some implementations of the present power amplifier module, the data/enable pin is further configured to provide an address signal to the front-end core when the front-end core is set to an active state. The address signals may be associated with registers of the front-end core. Further, in some cases, the digital control interface includes a plurality of register level shifters. Each register level shifter of the plurality of register level shifters may be configured to receive a register signal from a front end core and output the register signal, thereby enabling the power amplifier to be configured based on the register signal. The register signal may be associated with a value stored in one of a plurality of registers associated with the front-end core. Moreover, in some cases, the at least one register level shifter is further configured to receive a default signal during the reset state. The power-on reset block may be configured to place the at least one register level shifter in a reset state.

In some embodiments, the digital control interface includes a voltage input/output (VIO) pin configured to receive a VIO signal. The VIO signal may correspond to one of the first logic level and the second logic level. Further, the digital control interface may include: a clock/mode pin configured to receive a first signal corresponding to one of a first logic level and a second logic level; and a data/mode pin configured to receive a second signal corresponding to one of the first logic level and the second logic level. Additionally, the digital control interface may include a general purpose input/output (GPIO) interface module and a serial interface module. In some cases, the GPIO interface module includes an enable level shifter, a first mode level shifter, a second mode level shifter, and a combinational logic block. The combinational logic block may be configured to provide an enable signal to the enable level shifter for output to the power amplifier controller. Further, the combinational logic block may be configured to provide the first mode signal to the first mode level shifter for output to the power amplifier controller and the second mode signal to the second mode level shifter for output to the power amplifier controller. The enable signal may correspond to an enable logic value when one or more of the first signal and the second signal corresponds to a first logic level and the VIO signal corresponds to a second logic level. In addition, when the VIO signal corresponds to the second logic level, the first mode signal may correspond to the first signal and the second mode signal may correspond to the second signal. In some cases, the power amplifier controller is configured to control the power amplifier based at least in part on the first mode signal and the second mode signal. Some implementations of the serial interface module include a serial interface core and a reset logic block. The serial interface core may be configured to provide a serial interface when the VIO signal corresponds to a first logic level, and the reset logic block may be configured to place the serial interface core in a reset mode when the VIO signal corresponds to a second logic level.

In some embodiments, the enable signal corresponds to the not-enabled logic value when the first signal and the second signal each correspond to a second logic level and the VIO signal corresponds to the second logic level. Further, the enable signal may correspond to a serial enable value received from the serial interface core when the VIO signal corresponds to the first logic value. In addition, the first mode signal may correspond to a first serial mode signal received from the serial interface core when the VIO signal corresponds to a first logic value, and the second mode signal may correspond to a second serial mode signal received from the serial interface core when the VIO signal corresponds to the first logic value.

With some implementations of the invention, the data/mode pin is further configured to provide an address signal to the serial interface core when the VIO signal corresponds to the first logic level. The address signal may be associated with a register of the serial interface core. Additionally, the clock/mode pin may be further configured to provide a clock signal to the serial interface core when the VIO signal corresponds to the first logic level.

In some embodiments, the digital control interface includes a plurality of register level shifters. Each register level shifter of the plurality of register level shifters may be configured to receive a register signal from the serial interface core and output the register signal to the power amplifier controller. In some cases, this enables the power amplifier controller to configure the power amplifier based on the register signal. The register signal may be associated with a value stored in one of a plurality of registers associated with the serial interface core.

In some embodiments, the serial interface module further comprises a first buffer and a second buffer. When the buffer control signal is set to a first value, the first buffer may be configured to enable reading of data from the serial interface core and the second buffer is configured to prevent writing of data to the serial interface core. Further, when the buffer control signal is set to a second value, the first buffer may be configured to prevent data from being read from the serial interface core and the second buffer is configured to enable data to be written to the serial interface core. In some cases, the buffer control signal is generated by a serial interface core.

Some embodiments of the invention may be configured to implement a method for providing multiple control interfaces in a digital control interface including a GPIO interface module and a serial interface module, which may include a serial interface core. The method may include receiving a VIO signal at a VIO input to a digital control interface and determining whether the VIO signal corresponds to a logic high value. In response to determining that the VIO signal corresponds to a logic high value, the method may include configuring the digital control interface to function as a serial interface by: providing a clock signal from a clock input to a serial interface core; providing a data signal from a data input to a serial interface core; and selecting, at the combinational logic block, the first enable signal to output to the enable level shifter, the first mode signal to output to the first mode level shifter, and the second mode signal to output to the second mode level shifter. The first enable signal, the first mode signal, and the second mode signal may each be received from the serial interface core. In response to determining that the VIO signal corresponds to a logic low value, the method may include configuring the digital control interface to function as a general purpose input/output (GPIO) interface by: providing a first input signal and a second input signal to a combinational logic block; and selecting the second enable signal to output to the enable level shifter, the third mode signal to output to the first mode level shifter, and the fourth mode signal to output to the second mode level shifter at the combinational logic block. The second enable signal may be based on a logical operation of the first input signal and the second input signal. Further, the third mode signal may be based at least in part on the first input signal, and the fourth mode signal may be based at least in part on the second input signal.

In some cases, the indicated method includes reconfiguring the serial interface core from a reset state to an active state in response to determining that the VIO signal corresponds to a logic high value. Reconfiguring the serial interface core from the reset state to the active state may include configuring a set of internal registers of the serial interface core to default values.

Further, the method may include providing an output of an enable level shifter, an output of a first mode level shifter, and an output of a second mode level shifter to a power amplifier controller, thereby enabling the power amplifier controller to configure a power amplifier based on the output of the first mode level shifter and the output of the second mode level shifter when the output of the enable level shifter corresponds to an enable value. Further, the method may include placing the serial interface core in a reset mode in response to determining that the VIO signal corresponds to a logic low value. Placing the serial interface core in the reset mode may include loading a set of default values into a set of registers of the serial interface core.

Certain aspects of the present disclosure may be included as part of a power amplifier. A power amplifier may include a digital control interface, a power amplifier controller, and a mode selector configured to provide a VIO signal to the digital control interface. In some cases, the VIO signal is configured to set a mode of the digital control interface and may correspond to one of the first logic level and the second logic level. The digital control interface may include: a voltage input/output (VIO) pin configured to receive a VIO signal; a clock/mode pin configured to receive a first signal corresponding to one of a first logic level and a second logic level; and a data/mode pin configured to receive a second signal corresponding to one of the first logic level and the second logic level. Further, the digital control interface may include a general purpose input/output (GPIO) interface module that may include an enable level shifter, a first mode level shifter, a second mode level shifter, and a combinational logic block. In some cases, the combinational logic block is configured to provide an enable signal to the enable level shifter for output to the power amplifier controller. The combinational logic block may be further configured to provide the first mode signal to the first mode level shifter for output to the power amplifier controller and the second mode signal to the second mode level shifter for output to the power amplifier controller. The enable signal may correspond to an enable logic value when one or more of the first signal and the second signal corresponds to a first logic level and the VIO signal corresponds to a second logic level. In some cases, the first mode signal corresponds to the first signal and the second mode signal corresponds to the second signal when the VIO signal corresponds to the second logic level. Additionally, the digital control interface may include a serial interface module that may include a serial interface core and a reset logic block. The serial interface core may be configured to provide a serial interface when the VIO signal corresponds to a first logic level, and the reset logic block may be configured to place the serial interface core in a reset mode when the VIO signal corresponds to a second logic level. Further, the power amplifier controller may be configured to receive an enable signal from the enable level shifter, a first mode signal from the first mode level shifter, and a second mode signal from the second mode level shifter. Additionally, the power amplifier controller may control the power amplifier by providing a control signal to the power amplifier based at least in part on the first mode signal and the second mode signal. This control signal may specify the operating mode of the power amplifier.

In some embodiments, a wireless device may include a power amplifier module. The power amplifier module may include one or more of the previously described embodiments. Further, the wireless device may include: a power supply configured to power the power amplifier module; and a transceiver configured to provide a control signal to a mode selector of the power amplifier module.

In some embodiments, the digital control interface includes a voltage input/output (VIO) pin configured to receive a VIO signal. Further, the digital control interface may include a general purpose input/output (GPIO) interface module and a serial interface module. The GPIO interface module may include an enable level shifter, a first mode level shifter, a second mode level shifter, and a combinational logic block. The combinational logic block may be configured to provide an enable signal to the enable level shifter for output to the power amplifier controller. The combinational logic block may be further configured to provide the first mode signal to the first mode level shifter for output to the power amplifier controller and the second mode signal to the second mode level shifter for output to the power amplifier controller. The serial interface module may include a serial interface core and a reset logic block. The serial interface core may be configured to provide a serial interface when the VIO signal corresponds to a first logic level. Further, the reset logic block may be configured to place the serial interface core in a reset mode when the VIO signal corresponds to the second logic level. Further, the GPIO interface module may be configured to provide the GPIO interface when the VIO signal corresponds to the second logic level.

In a particular implementation, the digital control interface may also include a clock/mode pin configured to receive a first signal corresponding to one of the first logic level and the second logic level. Further, the digital control interface may include a data/mode pin configured to receive a second signal corresponding to one of the first logic level and the second logic level. In some cases, the enable signal may correspond to an enable logic value when one or more of the first signal and the second signal corresponds to a first logic level and the VIO signal corresponds to a second logic level. In addition, when the VIO signal corresponds to the second logic level, the first mode signal may correspond to the first signal and the second mode signal may correspond to the second signal. In some embodiments, the power amplifier controller is configured to control the power amplifier based at least in part on the first mode signal and the second mode signal.

While specific embodiments of the invention have been described in this section, these embodiments are presented by way of example only, and are not intended to limit the scope of the invention or any claims. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure, and these aspects of the disclosure as disclosed in this section may be combined with other aspects of the disclosure to further improve the performance of power amplifiers, power amplifier modules, and mobile devices in which they are used.

HBT power amplifier bias circuit and method for process compensation

This section of the invention relates to a system for biasing a power amplifier, the power amplifier comprising: a first die including a power amplifier circuit and passive components having electrical properties that depend on one or more conditions of the first die; and a second die including a bias signal generation circuit configured to generate a bias signal based at least in part on a measurement of the electrical property of the passive component of the first die. As indicated above, these aspects of the invention may be combined with other aspects of the invention to further improve the performance of the power amplifier module and the device in which the power amplifier module is used.

Referring now to fig. 27, a Radio Frequency (RF) configuration 408 is shown including a semiconductor die 409 having an Integrated Circuit (IC)411 formed thereon. In some implementations as described herein, die 409 may include die dependent components 412 having one or more operating parameters that depend on one or more conditions associated with die 409. Operation of at least a portion of IC411 may be facilitated by bias circuit 413 located external to die 409. Non-limiting examples of such die dependent components are described in more detail herein below.

As further shown in fig. 27, the die-dependent component 412 may be coupled to the bias circuitry 413 such that the bias circuitry 413 may be operated based at least in part on the condition of the die-dependent component 412. Since this condition of die-dependent component 412 represents a condition of die 409, operating the bias circuit in the foregoing manner may allow IC411 to operate in an improved manner. Various examples of such die dependent operation are described in more detail later herein.

FIG. 28 shows that in some implementations, the IC411 and die dependent component 412 of FIG. 27 can be formed on a first semiconductor die 409 and the bias circuit 413 (FIG. 27) can be formed on a second semiconductor die 414. Examples of types of first die 409 and second die 414 are discussed in more detail below.

Referring next to FIG. 29, an example of the two separate dies 409 and 414 of FIG. 28 is shown. First die 409 may be a Heterojunction Bipolar Transistor (HBT) processing technology based die 416. As further shown in fig. 29, the IC formed on this die may include a Power Amplifier (PA) circuit 415 implemented in IC 411. As further shown in FIG. 29, the process dependent component 412 may include a process dependent resistance 412 having an inter-die connection with the bias circuit 413 while the PAIC has a similar connection with the bias circuit 413.

FIG. 29 further shows that the second die 414 can be a die 417 based on silicon processing technology. Bias circuit 413 is shown formed on this die. Although various examples are described herein in the context of HBTs and silicon dies, it should be understood that one or more features of the present invention may also be applied in other types of dies in combination. It should also be understood that although described in the context of PA operation and biasing of such a PA, one or more features of the present disclosure may also be applied to other types of ICs and controls of such ICs.

In the context of HBT-based PA dies and bias circuits on separate silicon dies, the standard "diode-stacked" bias configurations used in many linear HBT power amplifier designs typically exhibit sensitivity to device β, which results in significant quiescent current variations of the amplifier. Variations in quiescent current can affect performance parameters such as gain, linearity, and current drain. Product yield may also degrade due to variations in these parameters.

Inability to handle, or a reduction in the ability to handle, such beta sensitivity may result in operating configurations requiring increased biasing of the reference circuit, which generally increases the current drain of the product. In some cases, more complex circuit designs may be applied to the diode stack biasing approach, which typically increases circuit area and current consumption. Alternative biasing methods other than diode stack topologies may be used, however, these methods may typically compromise bandwidth, degrade noise, and/or require external passive components.

Figure 30 shows an example linear HBTPA die 418 with the aforementioned standard "diode-stacked" bias configuration. For purposes of illustration, the example PA die 418 is shown to include two stages 419 and 421. It is understood that the number of stages may be more or less than two. The first stage 419 is shown receiving RF signals to be amplified from the RFIN node 422 through the input matching circuit 423. The output of the first stage 419 is shown passing to the second stage 421 via an interstage circuit 424 that provides matching and harmonic termination. The output of second stage 421 is shown passing to RFOUT node 427 via output matching and harmonic termination circuit 426.

In the example shown in fig. 30, each PA stage 419 and 421 is shown receiving DC bias current from a CMOS bias circuit (not shown) through respective inputs 428 and 429. The bias current is shown provided to a 2 Vbe diode mirror with a diode stack to generate the bias signal. This design topology demonstrates sensitivity to process β, which can lead to increased part-to-part variation in quiescent current, affecting gain, efficiency, and linearity.

In some implementations, the disclosure relates to a PA configuration that utilizes passive devices on the amplifier die to effectively sense die-dependent parameters (e.g., β) and compensate for associated effects (e.g., quiescent current variations) to improve performance and/or reduce part-to-part variation of the product. In some embodiments, such a PA configuration may include a silicon bias die and an HBT amplifier die. Traditionally, the silicon die will produce a reference current for the PA die that is approximately constant with respect to the temperature of the PA die and that varies substantially only by the tolerance of the discrete resistors.

In some implementations of the invention, this discrete reference resistor may be replaced by an integrated resistor on the HBT die. In some embodiments, such an integrated resistor may be formed with HBT device base material, and may exhibit sheet resistance characteristics that track process β. Based on this resistance, the reference current can be configured to track β and cancel or reduce the "diode-stack" sensitivity to β.

In some embodiments, the aforementioned base resistor (Rb) type may be configured to generate a high temperature coefficient that may be compensated by bias generation circuitry within the silicon control die such that the voltage applied across the reference resistor increases with ambient temperature. The resulting reference current from the amplifier may be substantially constant over a selected range of ambient temperatures and substantially tracks HBT process beta.

Figure 31 shows an example configuration 408 in which HBTPA die 416 includes a resistor 412 whose resistance Rb is process dependent. This resistor may be used as a reference resistance for generating the bias signals for the two example PA stages 415a and 415 b. In view of the present disclosure, it should be readily understood that one or more features associated with the generation of a reference resistance and a bias signal based on such a reference resistance may be applied to PA configurations having a greater or lesser number of stages.

In the example configuration 408 of FIG. 31, one end of the reference resistor 412 is shown connected to the V-I circuit 432 and the other end is shown connected to ground. V-I circuit 432 is depicted on silicon die 417 and is shown to facilitate current sources 433 and 434 to provide bias signals to first PA stage 415a and second PA stage 415 b. Such bias signals may be compensated for variations in one or more conditions of HBTPA die 416, as described herein. An example of how the V-I circuit 432 may be configured and operated along with a Proportional To Absolute Temperature (PTAT) voltage reference 431 and a reference resistor 412 is described in more detail herein below.

Fig. 32, 33, and 34 show how a measurement of the resistance associated with the reference resistor 412 (Rref and also referred to as Rb) can detect changes in the beta parameter and temperature. Figure 32 shows a graph of the 1/Rb values of HBT dies formed on different wafers (W2-W10). Figure 33 shows a plot of the beta values of the same HBT dies formed on example wafers W2-W10. Several observations can be made. For example, it can be seen in fig. 33 that there can be die-to-die variation in the beta parameter within a given wafer. There may also be significant variation in the beta parameter between different wafers. Similarly, there can be significant die-to-die and wafer-to-wafer variations in 1/Rb observed in FIG. 32.

Empirically, it can also be seen in FIGS. 32 and 33 that the inter-wafer value of 1/Rb is related to the value of β. For example, a decrease in the average β value for wafers W2-W5 corresponds to an increase in the average 1/Rb value for the same wafer. This shows that the trend of the increase/decrease of 1/Rb at β decrease/increase continues through the example sample of the wafer.

While not wishing or intending to be bound by any particular theory, some theories associated with the base resistance Rb and beta parameters may be considered. The base resistance Rb can be expressed as a sheet resistance R_bshThe sheet resistance can be expressed as

R_bsh＝1/(qμ_pN_Aw_b)

(1)

Whereinq is the carrier charge, μ_nFor N-type carrier mobility, N_AIs a net impurity concentration, and w_bIs the base layer thickness. The beta parameter may be expressed as beta_maxOf DC current gain, wherein

β_max＝(N_E/N_B)(v_nB/v_pE)e[^ΔEv/v^(kT)]＝(N_E/N_B)(D_n/D_p)(w_E/w_B)e[^ΔEv^/(kT)]

(2A)

For A1GaAs and Si, where N_EAnd N_BIs the emitter and base doping concentration, w_EAnd w_BIs the emitter and base thickness, and Δ E_vIs the effective valence band barrier height. In some cases, the DC current gain of InGaP may be expressed as

β＝(v_nB/w_b)τ(N_b)，

(2B)

This can be manipulated to show

(β/R_bsh)＝qN_Ew_Eμ_ne^[ΔEv^/(kT)]。

(2C)

In equation 2C, the parameters on the right side are emitter dependent and thus may not vary significantly within the base process. Thus, for variations in the base (which is where most of the variations in Rb and β occur for HBTs), the β parameter β and the base resistance Rb may respond approximately equally or in a similar manner, such that the ratio of the two parameters may be substantially constant. Thus, measurement of the change in Rb can provide information about the change in β for the change that occurred in the base.

Figure 34 shows a plot of reference resistance (Rref) versus operating temperature for different power output settings (in dBM) of an HBTPA. When considering these graphs, it can be observed that the relationship between Rref and temperature is approximately linear.

As described with reference to fig. 31-34, the base resistance of a PA die (e.g., HBTPA die) varies with temperature and/or base layer parameters. In some implementations, this resistance can be used as a reference resistance to generate a control signal (e.g., a bias signal) that compensates for variations associated with temperature and/or base layer parameters. FIG. 35 shows an example V-I circuit 432 that can generate such compensated control signals.

With continuing reference now to FIG. 35, an example V-I circuit 432 is shown formed on a silicon die 417 and may be configured to receive a Proportional To Absolute Temperature (PTAT) signal (e.g., approximately 0.6V) from a PTAT source 431. This signal, which is typically independent of temperature and process parameters of the HBTPA die, can be provided to the base resistor (412 in figure 31). For example, the current provided to base resistor 412 may vary depending on the value of base resistance (Rb). In the example shown, the 0.6PTAT voltage provided to the example Rb value of 6 kOmega results in approximately 408 μ A current drawn. This current can be used to generate an output voltage from the V-I circuit to generate a reference current Ire in the form of a PA circuit to be provided to the HBT die.

FIG. 36 shows a plot of measured output voltage from the V-I circuit versus temperature for different Vbatt settings (2.9V, 3.4V, 3.9V, 4.4V). Similar to the substantially linear relationship between reference resistance and temperature, the V-I output voltage is also substantially proportional to the base temperature of the HBTPA die.

Examples of benefits that may be realized from one or more features of the present disclosure are described with reference to fig. 37A-40. To simulate the performance of a power amplifier under different conditions, the following parameters are varied between normal, high and low values: beta parameter, energizing voltage Vbe, Ft parameter, resistance and capacitance. The "uncompensated" design of fig. 37A and 37B corresponds to the example configuration of fig. 30, and the "compensated" design of fig. 38A and 38B corresponds to the example configuration of fig. 31.

Fig. 37A and 37B show graphs of quiescent current versus temperature for the first and second stages of an uncompensated PA example described herein. Different graphs correspond to different combinations of varying parameters. In each of the first and second level simulations, the quiescent current varied by about +/-50%.

Fig. 38A and 38B show graphs of quiescent current versus temperature for the first and second stages of the compensated PA examples described herein. Different graphs correspond to different combinations of varying parameters. The quiescent current varies by about +/-10% for the first stage. The quiescent current varies by about +/-7% for the second stage. After a considered review, it can be observed that the relative amount of change in quiescent current in the compensated configuration is substantially less than that of the uncompensated configuration for both stages.

Fig. 39 and 40 show examples of improvements in gain characteristics that may be provided by reduced variation in quiescent current. FIG. 39 shows plots of calculated gain (dB) versus power output (dBm) at three example temperatures (-20 deg.C, 25 deg.C, 85 deg.C). For each temperature, the middle curve corresponds to the normal configuration; the upper curve corresponds to the quiescent current at + 10% and the lower curve corresponds to the quiescent current at-10%. It should be noted that 10% is the worst case change for the compensated configuration described with reference to fig. 38. It can be seen that the +/-10% change in quiescent current is generally constant with temperature; and thus may result in good compression performance characteristics.

Fig. 40 shows plots of gain versus power output for different configurations of the varied parameters described with reference to fig. 38A and 38B. Here, it can be seen that all compensated gain curves desirably fit within a window of 28dB +/-3 dB.

In some implementations according to these aspects of the invention, the base resistor having one or more features as described herein can be a semiconductor resistor formed on a III-V semiconductor die (e.g., HBT die). Additional details regarding such resistors are described below in section VIII of the present disclosure.

In some embodiments of the present disclosure, a PA and a bias die having one or more features described herein may be implemented in a packaged module. An example of such a module is shown in fig. 41A (plan view) and 41B (side view). Module 436 is shown to include a package substrate 437. Such a package substrate may be configured to receive a plurality of components, and may include, for example, a laminate substrate. The components mounted on the package substrate 437 may include one or more dies. In the example shown, a PA die (e.g., HBTPA die 416) and a bias die (e.g., silicon bias die 417) are shown mounted on package substrate 437. PA die 416 may include PA circuitry 415 and base resistor 412 as described herein; and the bias die 417 may include V-I circuitry 432 also described herein. The dies 416 and 417 may be electrically connected to other portions of the module by connections, such as bond wire bonds 443, and may be electrically connected to each other. Such wire bonds may be formed between contact pads 441 formed on the die and contact pads 438 formed on the package substrate 437. In some embodiments, one or more Surface Mount Devices (SMDs) 442 may be mounted on the package substrate 437 to facilitate various functionalities of the module 436.

According to an embodiment, RF shielding features, such as shield wire bonds 444, may be provided to facilitate RF shielding of one or more components, such as die 416, die 417, and/or SMD 442. Such an RF shield may inhibit RF signals or noise from passing between such components and regions outside of the module 436. In the context of shield wire bonds 444, such wire bonds may be formed on the contact pads 439 such that the shield wire bonds 444 generally form a perimeter around a desired region (e.g., near the perimeter of the module 436). The size and spacing of such shield wire bonds may be selected to provide desired RF shielding properties.

In some embodiments, a three-dimensional RF shielding structure may be provided as follows. As shown in fig. 41B, the shield wire bonds 444 may be electrically connected to the ground plane 440 below the surface of the package substrate 437. Such connections between the shield wire bonds 444 and the ground plane 440 may be facilitated by contact pads 439 and connection features 450 (e.g., vias). The above shield wire bond 444, conductive layer (e.g., conductive paint layer) 445 may be provided such that the conductive layer 445 is electrically connected with an upper portion of the shield wire bond 444. Thus, conductive layer 445, shield line bond 444, and ground plane 440 may form a three-dimensional RF shield structure.

According to some embodiments of the invention, the space between package substrate 437 and conductive layer 445 may be filled with an over-mold structure 446. Such an over-molded structure may provide a number of desirable functionalities, including protection of components and wire bonds from external elements and easier handling of the packaged module 436.

In some implementations, a device and/or circuitry having one or more features described herein may be included in an RF device (e.g., a wireless device). Such a device and/or circuitry may be implemented directly in a wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device may include, for example, a cellular telephone, a smartphone, a handheld wireless device with or without telephone functionality, a wireless tablet, and other similar devices that provide corresponding functionality.

Referring next to fig. 42, an example wireless device 447 having one or more advantageous features described herein is schematically depicted. In the context of biasing of PAs as described herein, a PA die 416 having one or more PAs may be part of the module 436. Here, four PAs are illustrated in die 416 for exemplary purposes. This module may also include a bias die 417 having one or more features as described herein. In some embodiments of the present disclosure, such a PA module may facilitate multi-band operation of wireless device 447, for example.

The PAs in module 436 may receive their respective RF signals from a transceiver 454, which may be configured and operated in a known manner to generate RF signals to be amplified and transmitted and to process the received signals. The transceiver 454 is shown interacting with a baseband subsystem 453 configured to provide conversion between data and/or voice signals, which are appropriate for a user, and RF signals, which are appropriate for the transceiver 454. The transceiver 454 is also shown connected to a power management component 451 that is configured to manage power for operation of the wireless device. This power management may also control the operation of the baseband subsystem 453 and the PA module 436.

Baseband subsystem 453 is shown connected to a user interface 448 to facilitate various inputs and outputs for voice and/or data provided to and received from a user. Baseband subsystem 453 can also be connected to memory 449, which is configured to store data and/or instructions to facilitate operation of the wireless device and/or to provide a user with a region of information storage.

In an example wireless device 447, the output of the PA of module 436 may be matched by a matching network and routed to antenna 458 via its respective duplexer 456 and band selection switch 457. In some embodiments, each duplexer may allow transmit and receive operations to be performed simultaneously using a common antenna (e.g., 458). In fig. 42, the received signal is shown routed to an "Rx" path (not shown) that may include, for example, a Low Noise Amplifier (LNA).

A number of other wireless device configurations may utilize one or more features described herein. For example, the wireless device need not be a multi-band device. In another example, the wireless device may include additional antennas (e.g., diversity antennas) and additional connectivity features (e.g., wireless fidelity, bluetooth, and GPS).

The above detailed description of embodiments of the invention provided in this section is not intended to be exhaustive or to limit the invention to the precise form disclosed herein. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. The teachings of the disclosure provided herein are applicable to other systems and are therefore not intended to be necessarily limited to the systems described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

Device and method for a structure with HBT and FET

This section of the present invention relates to a semiconductor structure comprising: a Heterojunction Bipolar Transistor (HBT) comprising a collector layer over a substrate, the collector layer comprising a semiconductor material; and a Field Effect Transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material forming the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in semiconductor material forming an emitter of the HBT. One or more of the foregoing features may be implemented in devices such as dies, packaged modules, and wireless devices. Those skilled in the art of the present invention will readily appreciate that these aspects of the present invention may be combined with other aspects of the present invention to further improve the performance of the power amplifier module and the devices in which the power amplifier module is used.

Although described with particular reference to devices fabricated in the gallium arsenide (GaAs) material system, the structures described in this section may be fabricated using other III-V semiconductor materials, such as indium phosphide (InP) and gallium nitride (GaN). Further, any of a variety of semiconductor growth, formation, and processing techniques may be used to form layers and fabricate the structure or structures described herein. For example, the semiconductor layer may be formed using the following techniques: molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD) (also sometimes referred to as organometallic vapor phase epitaxy (OMVPE)), or any other technique. Furthermore, the thicknesses of the various semiconductor layers described below are close, and may be varied to be thicker or thinner than described. Similarly, the doping levels of the doped semiconductor layers described herein below are relative.

Aspects of the invention presented in this section relate to a semiconductor structure comprising: bipolar devices (e.g., Heterojunction Bipolar Transistors (HBTs)); and a p-type field effect transistor (pFET) integrated on the common substrate, the pFET commonly referred to as a BiFET and formed in a GaAs material system. Embodiments also include complementary BiFET (BiCFET) comprising a p-type FET (pFET) and an n-type FET (nFET) integrated with the HBT in a GaAs material system. The following description contains specific information pertaining to embodiments of the present invention. Those skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application.

The drawings discussed herein and the accompanying detailed description are directed to merely exemplary embodiments of the invention. Although structure 459, discussed further herein below, illustrates an exemplary BiFET including NPNHBT and pFET located over a substrate in a semiconductor die, the invention is also applicable to devices including PNPHBT and NFET; NPNHBT and both nFET and pFET; and PNPHBT and BiFETs for both nFETs and pFETs.

Referring now to fig. 43, shown is a schematic diagram illustrating a cross-sectional view of an exemplary structure including an exemplary BiFET according to one embodiment of the invention. Structure 459 includes BiFET461, isolation regions 466, 467, and 469, and substrate 464 which may be a semi-insulating GaAs substrate. The BiFET461 includes: HBT462 located over substrate 464 between isolation regions 466 and 467; and a pFET463 located over the substrate 464 between the isolation regions 467 and 469. Isolation regions 466, 467, and 469 provide electrical isolation from other devices on substrate 464 and may be formed in a manner known in the art.

HBT462 includes a subcollector layer 471, a first collector layer segment 472, a second collector layer segment 473, an optional etch stop layer segment 474, a base layer segment 476, an emitter layer segment 477, an emitter cap layer segment 478, a bottom contact layer segment 479, a top contact layer segment 481, a collector contact 482, a base contact 484, and an emitter contact 486.

For purposes of the description herein, the emitter may include one or more portions associated with the emitter stack. In the example HBT configuration 462 of fig. 43, such an emitter stack can include an emitter layer 477, an emitter cap layer 478, a bottom contact layer 479, and a top contact layer 481. Thus, an emitter as described herein can include emitter layer 477 and/or emitter cap layer 478.

Also for purposes of illustration herein, an example HBT topology is described in the context of GaAs/InGaP. It should be understood, however, that one or more features of the present invention may also be applied to other material systems for HBTs including, for example, indium phosphide (InP), antimonide, or nitride-based materials.

pFET463 includes back gate contact 468, lightly doped N-type GaAs segments 488, lightly doped P-type GaAs segments 489, optional etch stop layer segments 491 (typically comprising lightly doped N-type or P-type InGaP), source and drain contact layers 492 and 493 (typically comprising heavily doped P-type GaAs), gate contact 494, source contact 497, and drain contact 498. Alternatively, the optional etch stop layer segments 491 may be undoped. In an embodiment of the present invention, HBT462 may be an NPNHBT integrated with pFET463 in a complementary arrangement. In another embodiment, HBT462 may be a PNPHBT integrated with an nFET, or may be a PNPHBT or NPNHBT integrated with pFET463 and with an nFET. In embodiments of the present invention, pFET463 can be a depletion mode FET or an enhancement mode FET.

Subcollector layer 471 is on substrate 464 and may comprise heavily doped N-type GaAs. The subcollector layer 471 may be formed by using a Metal Organic Chemical Vapor Deposition (MOCVD) process or other processes. The first collector segment 472 and the collector contact 482 are on the sub-collector layer 471. First collector layer segment 472 may comprise lightly doped N-type GaAs. The second collector segment 473 may include lightly doped P-type GaAs. The first collector segment 472 and the second collector segment 473 can be formed using a MOCVD process or other processes. The collector contact 482 may be formed of an appropriate metal or combination of metals that may be deposited and patterned over the subcollector layer 471.

An optional etch stop layer segment 474 may be located over the second collector segment 473 and may comprise lightly doped N-type or P-type InGaP. Alternatively, the optional etch stop layer segments 474 may be undoped. Etch stop layer segments 474 may be formed using a MOCVD process or other processes.

Base layer segments 476 are located over etch stop layer segments 474 and may comprise heavily doped P-GaAs. Base layer segments 476 may be formed by using a MOCVD process or other processes.

Emitter segment 477 and base contact 484 are situated over base segment 476. Emitter segments 477 may comprise lightly doped N-type indium gallium phosphide (InGaP) and may be formed on base segments 476 by using a MOCVD process or other processes. Base contact 484 can comprise a suitable metal or combination of metals that can be deposited and patterned over base layer segments 476. Emitter cap segments 478 are located on emitter segments 477 and may comprise lightly doped N-type GaAs. The emitter cap segments 478 may be formed by using a MOCVD process or other processes.

Bottom contact layer segment 479 is located over emitter cap layer segment 478 and may comprise heavily doped N-GaAs. Bottom contact layer segment 479 may be formed by using a MOCVD process or other processes.

Top contact layer segment 481 is located on bottom contact layer segment 479 and may comprise heavily doped indium gallium arsenide N-type (InGaAs). The top contact layer segment 481 can be formed by using a MOCVD process or other processes. The emitter contact 486 is located on the top contact layer segment 481 and may comprise an appropriate metal or combination of metals that may be deposited and patterned over the top contact layer segment 481.

During operation of HBT462, current flows from emitter contact 486 through top contact layer segment 481, bottom contact layer segment 479, emitter cap layer segment 478, emitter layer segment 477 and into base layer segment 476, and is indicated by arrows 483.

To form pFET463 in the collector of HBT462, lightly doped P-type GaAs layer segment 489 is positioned over lightly doped N-type GaAs layer segment 488, which is positioned over heavily doped N-type GaAs layer segment 487. A back gate contact 468 is formed over the heavily doped N-type GaAs layer segments 487 to form the back gate for pFET 463. Back gate contact 468 may comprise a suitable metal or combination of metals that may be deposited and patterned over heavily doped N-type GaAs layer segments 487.

Lightly doped N-type GaAs layer segments 488 are substantially similar in composition and formation to first collector layer segments 472 discussed above. Lightly doped P-type GaAs layer segment 489 is substantially similar in composition and formation to second collector layer segment 473 discussed above.

Lightly doped P-type GaAs layer segment 489 forms the channel of pFET 463. Etch stop layer segments 491 are located on lightly doped P-type GaAs layer segments 489 and may comprise lightly doped N-type or P-type InGaP. Alternatively, the etch stop layer segments 491 may be undoped. Etch stop layer 491 may be formed on lightly doped P-type GaAs layer 489 using a MOCVD process or other suitable process. When implemented, the etch stop layer segments 491 may have a thickness between about 10 nanometers (nm) and about 15 nm. In one embodiment, pFET463 may be an enhancement mode FET and etch stop layer segment 491 may have a thickness of less than 10 nm.

The source and drain contact layers 492 and 493 are located over the etch stop layer segments 491 and may comprise heavily doped P-GaAs to form source and drain regions, respectively. The source contact layer 492 and the drain contact layer 493 may be formed by using a MOCVD process or other processes. Source contact 497 and drain contact 498 are located over etch stop layer segment 491. Source contact 497 and drain contact 498 may comprise platinum gold ("PtAu") or other suitable metal and may be formed in a manner known in the art. The gate contact 494 is located over the etch stop layer segment 491 in the gap 496 (which is formed between the source contact layer 492 and the drain contact layer 493) and may comprise an appropriate metal or combination of metals. The gap 496 may be formed by selectively etching through the InGaAs layer and the GaAs layer using an appropriate etch chemistry, stopping on the etch stop layer segments 491. After the formation of the gap 496, a gate contact 494 may be formed on the etch stop layer segment 491 in a manner known in the art. In one embodiment, FET463 may be an enhancement mode FET and gate contact 494 may be formed directly on lightly doped P-type GaAs layer segment 489. In the illustrated embodiment, an appropriate etch chemistry may be used to selectively etch through etch stop layer segments 491 and stop on lightly doped P-type GaAs layer segments 489.

Thus, by forming pFET463 in a layer that includes the collector of HBT462, the pFET and NPNHBT can be integrated, resulting in a complementary BiFET.

Referring next to FIG. 44, shown is a schematic diagram illustrating a cross-sectional view of an alternative embodiment of the structure of FIG. 43. Structure 499 shown in fig. 44 comprises a BiCFET structure that includes HBT502, pFET503, and nFET 504. Elements and structures in fig. 44 that are similar to corresponding elements and structures in fig. 43 will not be described in detail again.

The BiCFET501 comprises: HBT502 located between isolation region 506 and isolation region 507; a pFET503 located between the isolation region 507 and the isolation region 509; and an nFET504 located between the isolation region 509 and the isolation region 510.

HBT502 comprises sub-collector layer segment 511, first collector layer segment 512, second collector layer segment 513, optional etch stop layer segment 514, base layer segment 516, emitter layer segment 517, emitter cap layer segment 518, second optional etch stop layer 519, bottom contact layer segment 521, top contact layer segment 522, collector contact 523, base contact 524, and emitter contact 525.

As illustrated herein, the emitter can include one or more portions associated with the emitter stack. In the example HBT configuration 502 of fig. 44, such an emitter stack can include an emitter layer 517, an emitter cap layer 518, a second etch stop layer 519, a bottom contact layer 521, and a top contact layer 522. Thus, the emitter as described herein may include emitter layer 517 and/or emitter cap layer 518.

As also described herein, an example HBT topology is described in the context of GaAs/InGaP. It should be understood, however, that one or more features of the present invention may also be applied to other material systems for HBTs including, for example, indium phosphide (InP), antimonide, or nitride-based materials.

pFET503 contains a lightly doped P-GaAs layer segment 529 located over a lightly doped N-GaAs layer segment 527 located over a heavily doped N-GaAs layer segment 526. A back gate contact 508 is formed on the heavily doped N-type GaAs layer segment 526 to form the back gate of pFET 503. Back gate contact 508 may be formed of an appropriate metal or combination of metals that may be deposited and patterned over heavily doped N-type GaAs layer segments 526.

The lightly doped P-type GaAs layer segment 529 forms the channel of the pFET 503. Etch stop layer segments 531 are located over lightly doped P-type GaAs layer segments 529 and may comprise lightly doped N-type or P-type InGaP. Alternatively, the optional etch stop layer segments 531 may be undoped. Etch stop layer segments 531 may be formed on lightly doped P-type GaAs layer segments 529 by using a MOCVD process or other suitable process. When implemented, the etch stop layer segments 531 may have a thickness between about 10 nanometers (nm) and about 15 nm. Source contact layer 533 and drain contact layer 538 are located on etch stop layer segments 531 and may comprise heavily doped P-type GaAs to form source and drain regions, respectively. Source and drain contacts 542 and 544 are located on the etch stop layer segments 531 above their respective contact layers 533 and 538. A gate contact 541 is located over the etch stop layer segments 531 in the gap 540 (which is formed between the source region 533 and the drain region 538) and may comprise an appropriate metal or combination of metals.

To form nFET504 in a layer that includes the emitter of HBT462, lightly doped P-type GaAs layer segment 530 is positioned over lightly doped N-type GaAs layer segment 528, which is positioned over heavily doped N-type GaAs layer segment 526. Lightly doped N-type GaAs layer segment 528 is substantially similar in composition and formation to first collector layer segment 472 discussed above with respect to fig. 43. Lightly doped P-type GaAs layer segments 530 are substantially similar in composition and formation to second collector layer segments 473 discussed above in fig. 43.

Etch stop layer segments 532 are located over lightly doped P-type GaAs layer segments 530 and are similar to etch stop layer segments 531.

Heavily doped P-type GaAs layer segments 534 are located over etch stop layer segments 532 and are substantially similar in composition and formation to base layer segments 476 discussed above. A back gate contact 536 is formed over the heavily doped P-type GaAs layer segment 534 to form the back gate of nFET 504. Back gate contact 536 may comprise a suitable metal or combination of metals that may be deposited and patterned over heavily doped P-type GaAs layer segments 534. Lightly doped N-type InGaP segments 537 are located on the heavily doped P-type GaAs segments 534 and are substantially similar in composition and formation to the emitter layer segments 477 discussed above.

Lightly doped N-type GaAs layer segments 539 are located on lightly doped N-type InGaP layer segments 537 and are substantially similar in composition and formation to emitter cap segment 478 discussed above. The lightly doped N-type GaAs layer segment 539 forms the channel of the nFET 504. Second optional etch stop layer segment 543 is located over lightly doped N-type GaAs layer segment 539 and may comprise lightly doped N-type or P-type InGaP. Alternatively, the second optional etch stop layer segment 543 may be undoped. A second optional etch stop layer segment 543 may be formed on lightly doped N-type GaAs layer segment 539 using a MOCVD process or other suitable process. In embodiments of the invention, the second optional etch stop layer segment 543 may have a thickness between about 10nm and about 15 nm. In an embodiment, the nFET504 can be an enhancement mode FET and the etch stop layer segment 543 can have a thickness less than 10 nm.

Source region 546 and drain region 547 are located over second optional etch stop layer segment 543 and may comprise heavily doped N-GaAs. The source region 546 and the drain region 547 may be formed by using a MOCVD process or other processes. Contact layer segments 548 and 549 are positioned over source region 546 and drain region 547, respectively, and can comprise heavily doped N-type InGaAs. Contact layer segments 548 and 549 can be formed using a MOCVD process or other processes.

Source contact 551 and drain contact 552 are on top contact layer segments 547 and 548, respectively. A gate contact 553 is located over the second optional etch stop layer segment 543 in the gap 554. The gap 554 may be formed by selectively etching through the InGaAs and GaAs layers using an appropriate etch chemistry, stopping on the second optional etch stop layer segment 543. After forming the gap 554, a gate contact 553 may be formed over the second optional etch stop layer segment 543 in a manner known in the art. In an embodiment of the present invention, the nFET504 can be an enhancement mode FET and the gate contact 553 can be formed directly on the lightly doped N-type GaAs layer segment 539. In such an embodiment, an appropriate etch chemistry may be utilized to selectively etch through the second optional etch stop layer segment 543 and stop on the lightly doped N-type GaAs layer segment 539.

Thus, a BiCFET can be fabricated that includes complementary pFETs 503 and nFETs 504 formed on a GaAs substrate with NPN or PNPHBT.

In some embodiments as described herein, some or all of the etch stop layers (e.g., 474, 491, 514, 519, 531, 532, and 543) may include indium gallium phosphide (InGaP) or indium gallium arsenide (InGaAs). The etch stop layer may have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges may also be implemented. In some embodiments, some or all of the aforementioned etch stop layers may comprise any material having etch sensitivity to, for example, a channel of a FET. Such a material may be implemented in an appropriate thickness or within an appropriate thickness range in order to achieve similar results as the aforementioned example materials InGaP or InGaAs.

Figure 45 shows a process 555 that may be implemented to fabricate the example BiFET461 of figure 43 or a portion of the example BiCFET501 of figure 44. In block 556, a semiconductor substrate may be provided. In some embodiments, such a semiconductor layer may comprise one or more layers disclosed herein, including a semi-insulating GaAs layer (e.g., example layers 464 and 505 of fig. 43 and 44). In block 557, a Heterojunction Bipolar Transistor (HBT) may be formed so as to include a collector layer disposed over a substrate. In some embodiments, such a collector layer may comprise one or more layers disclosed herein, including a p-GaAs layer (473 in FIG. 43 and 513 in FIG. 44). In block 558, a Field Effect Transistor (FET) may be formed so as to include a channel region disposed over the substrate and formed of the same material as the collector layer of the HBT. In some embodiments, such a channel region may comprise one or more layers disclosed herein, including a p-GaAs layer (489 in FIG. 43 and 529 in FIG. 44). In some implementations, other structures associated with HBTs (e.g., bases, emitters, and contacts) and FETs (e.g., sources, drains, and contacts) can be formed.

Figure 46 shows a process 559 that can be implemented to fabricate the example BiCFET501 of figure 44. In block 561, a semiconductor substrate may be provided. In some embodiments, such a semiconductor layer may comprise one or more layers disclosed herein, including a semi-insulating GaAs layer (such as the example layer 505 of fig. 44). In block 562, a subcollector layer may be formed over a substrate layer. In some embodiments, such a subcollector layer may comprise one or more layers disclosed herein, including n + GaAs layers (511 and/or 526 in fig. 44). In block 563, an HBT may be formed over the subcollector layer. In some embodiments, such an HBT may be formed so as to include the example layers described herein with reference to FIG. 44, including collectors 513, 512 (e.g., p-GaAs), base 516 (e.g., p + GaAs), emitter 517 (e.g., n-InGaP), and emitter cap 518 (e.g., n-GaAs). In block 564, a first FET may be formed over the subcollector layer such that its channel region is formed of the same material as the collector region of the HBT. In some embodiments, such a first FET may be formed so as to include the example layers described herein with reference to fig. 44, including a channel layer 529 (e.g., p-GaAs), a source contact layer 533 (e.g., p + GaAs), and a drain contact layer 538 (e.g., p + GaAs). In block 566, a second FET may be formed over the subcollector layer such that its channel region is formed of the same material as the emitter cap region of the HBT. In some embodiments, such a second FET may be formed so as to include the example layers described herein with reference to fig. 44, including channel layer 539 (e.g., n-GaAs), source contact layer 546 (e.g., n + GaAs), and drain contact layer 547 (e.g., n + GaAs).

Fig. 47, 48, and 49 show processes that may be more specific examples than the processes described with reference to fig. 45 and 46 in the context of the example configurations of fig. 43 and 44. Figure 47 shows a process 567 that can be implemented to fabricate an HBT, such as the HBTs of figures 43 and 44. Fig. 48 shows a process 581 that may be implemented to fabricate a FET, such as the FETs of fig. 43 and 44. Fig. 49 shows a process 588 that may be implemented to fabricate a second FET, such as the second FET of fig. 44. For purposes of the description of fig. 47, 48 and 49, it will be assumed that a semiconductor substrate (e.g., semi-insulating GaAs) and a subcollector layer (e.g., n + GaAs) are provided.

Example processes 567, 581, and 588 may be performed sequentially, in parallel where appropriate, or in any combination thereof. Examples of such schemes of integrating an HBT with one or more FETs are described in more detail herein.

In the example process 567 of figure 47 in which the HBT is fabricated, a first collector layer (e.g., n-GaAs) may be formed on the sub-collector layer in block 568. In block 569, a second collector layer (e.g., p-GaAs) may be formed on the first collector layer. In block 571, a first etch stop layer (e.g., n-InGaP or p-InGaP) may be formed on the second collector layer. In block 572, a base layer (e.g., p + GaAs) may be formed on the first etch stop layer. In block 573, an emitter layer (e.g., n-InGaP) may be formed on the base layer. In block 574, an emitter cap layer (e.g., n-GaAs) may be formed on the emitter layer. In block 576, a second etch stop layer (e.g., n-InGaP or p-InGaP) may be formed on the emitter cap layer. In block 577, a bottom contact layer (e.g., n + GaAs) for the emitter may be formed on the second etch stop layer. In block 578, a top contact layer (e.g., InGaAs) of the emitter may be formed on the bottom contact layer. In block 579, contacts for the emitter, base, and collector may be formed in order to create an HBT configuration, such as the HBT configuration of figures 43 and 44 (462, 502).

In the example process 581 of fig. 48 in which the first FET (e.g., pFET) is fabricated, a doped layer (e.g., n-GaAs) may be formed on the subcollector layer in block 582. In block 583, a channel layer (e.g., p-GaAs) may be formed on the doped layer. In block 584, a first etch stop layer (e.g., n-InGaP or p-InGaP) may be formed on the channel layer. In block 586, source and drain contact layers (e.g., p + GaAs) may be formed on the first etch stop layer. In block 587, source, drain, gate, and back gate contacts may be formed in order to create a FET configuration, such as the example pfets 463 and 503 of fig. 43 and 44.

In the example process 588 of fig. 49 in which a second FET (e.g., nFET) is fabricated, a first doped layer (e.g., n-GaAs) may be formed on the sub-collector layer in block 589. In block 591, a second doped layer (e.g., p-GaAs) may be formed on the first doped layer. In block 592, a first etch stop layer (e.g., n-InGaP or p-InGaP) may be formed on the second doped layer. In block 593, a third doped layer (e.g., p + GaAs) may be formed on the first etch stop layer. In block 594, a fourth doped layer (e.g., n-InGaP) may be formed on the third doped layer. In block 596, a channel layer (e.g., n-GaAs) may be formed on the fourth doped layer. In block 597, a second etch stop layer (e.g., n-InGaP or p-InGaP) may be formed on the channel layer. In block 598, source and drain regions (e.g., n + GaAs) may be formed on the second etch stop layer. In block 599, source and drain contact layers (e.g., InGaAs) may be formed on the source and drain regions. In block 601, source, drain, gate and back gate contacts may be formed in order to create a FET configuration, such as the example nFET of fig. 44 (504).

In some implementations, the aforementioned integration of an HBT with one or more FETs can be accomplished in several ways, including a regrowth method, a two-step method, and/or a co-integration method. In the regrowth approach, regrowth may involve selective area, multilayer, and/or pre-patterned multilayer techniques. Selected region techniques may include growing one device, etching in one or more selected regions, and then growing another device in the selected regions. Multilayer technologies may include a single growth phase in which device layers are stacked rather than merged or shared. The pre-patterned multi-layer techniques may include selective etching of the substrate followed by deposition of two or more layers of the device.

In a two-step growth method, one device may be formed first, followed by the formation of another device adjacent to the first device. In the context of integrating three devices (such as the example of fig. 44), this two-step growth can be extended to a third-step growth that includes a third device.

In a co-integration approach, a single growth may result in a layer shared by two or more devices. In some implementations, the co-integration method can include a single growth-produced layer that constitutes a majority of the layers of two or more devices.

Figure 50 shows that in some embodiments, one or more features associated with the BiFET and/or biffet configurations described herein can be implemented as part of a semiconductor die 602. For example, such a die may include a Power Amplifier (PA) circuit 603 having one or more BiFET and/or biffet devices 604 as formed according to the structures and methods provided herein.

This PA circuit 603 may be configured so as to amplify an input RF signal (RF _ IN) to generate as an amplified output RF signal (RF _ OUT).

Fig. 51 shows another example die 606 that includes a PA circuit 607 controlled by a PA/switch controller 608. The controller 608 may be configured to include one or more BiFET and/or biffet devices 604 formed as in accordance with the structures and methods of the present invention.

Figure 52 shows that in some embodiments of the present invention, a die (such as the example die 606 of figure 51) can be implemented in the packaged module 609. The die 606 may include a PA607 and a controller 608 having a BiFET (and/or a BiCFET)604 with one or more of the advantageous features as described herein. Such a module may further include one or more connections 611 configured to facilitate the passage of signals and/or power to and from the die 606. Such a module may further include one or more package structures 612 that provide functionality such as protection (e.g., physical, electromagnetic shielding, etc.) to the die 606. Connections 611 and package structures 612 may be implemented according to other advantageous aspects of the present invention to further improve the performance of the power amplifier, power amplifier module, and wireless devices in which the power amplifier, power amplifier module are used.

Fig. 53 shows that in some embodiments, components such as die 606 of fig. 51 or module 609 of fig. 52 may be included in a wireless device 613 (such as a cellular telephone, smart phone, or other such wireless device that may benefit from advantageous aspects of the present disclosure). In fig. 53, packaged RF module 609 is depicted as part of wireless device 613; and this module is shown to include a BiFET and/or a biffet 604 having one or more features as described herein. In some embodiments, similar functionality may also be achieved with unpackaged dies having similar functionality. Wireless device 613 is depicted as including other common components such as RFIC616 and antenna 617. The wireless device 613 may also be configured to receive a power source, such as a battery 614.

While various embodiments of the invention have been described in this section, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the invention. For example, the invention herein is not limited to gallium arsenide material systems and may be combined with any other number of related, desired, or suitable aspects of the invention as described throughout this disclosure to even further improve the performance of integrated circuits, power amplifiers, power amplifier modules, and devices in which integrated circuits, power amplifiers, power amplifier modules are used.

RF power amplifier with semiconductor resistor

In many situations, it is desirable to reduce the cost of Radio Frequency (RF) devices, such as Power Amplifiers (PAs). Removing process steps and/or using "free" devices that do not involve additional processing steps are examples of how this cost reduction can be achieved. As described herein and throughout the present disclosure as related to other aspects of the present disclosure, semiconductor resistors may provide such advantageous cost reductions. Other advantages may also be realized with semiconductor resistors, as also described herein. For example, depending on the available resistance values, a smaller resistor footprint may be provided, which in turn may help shrink the die size. This reduction in die size may further reduce cost. In another example, some semiconductor resistors may be sensitive to conditions of the same semiconductor material that also forms the resistor. As indicated above, these aspects of the invention may be combined with other aspects of the invention to further improve the performance of the power amplifier module and the device in which the power amplifier module is used.

Continuing next to reference figure 54, semiconductor die 618 having Integrated Circuit (IC)619 is illustratively shown in accordance with other aspects of the present invention. In some embodiments of the present invention, such an IC may include one or more semiconductor resistors 621. Examples of such semiconductor resistors are described in more detail herein below.

Figure 55 shows an example of HBT622 having a layer stack formed on a semiconductor substrate 630, such as semi-insulating GaAs. As described herein by way of example, different layers of such a stack may be used as a semiconductor resistor. It should be understood that although such examples are described in the context of HBT structures, semiconductor resistors may also be formed based on layers associated with other types of stacked devices. Further, while various examples of layer materials are described in the context of the layer materials shown in fig. 55, it should be further understood that other materials may also be utilized.

As shown in fig. 55, a subcollector layer 623 (e.g., n + GaAs) may be formed over a substrate 630. Collector layer 624 (e.g., n-GaAs) may be formed over sub-collector layer 623. A base layer 625 (e.g., p + GaAs) may be formed over the collector layer 624. An emitter layer 626 (e.g., n-InGaP) may be formed over base layer 625. An emitter cap 627 (e.g., n-GaAs) may be formed over emitter layer 626. A bottom contact layer 628 (e.g., n + GaAs) may be formed over the emitter cap layer 627. A top contact layer 629 (e.g., InGaAs) may be formed over the bottom contact layer 628.

As further shown in fig. 55, a collector contact 631 can be formed on the sub-collector layer 623. A base contact 632 may be formed on the base layer 625. An emitter contact 633 can be formed on the top contact layer 629.

Figures 56A-56G show an example of a semiconductor resistor that can be formed using the various layers associated with the example HBT622 of figure 55. Fig. 56A-1 to 56G-1 are electrical schematic diagrams of the semiconductor resistors of fig. 56A to 56G, respectively. The resistance of the semiconductor resistor of fig. 56A-56G can be based on the contact resistance of the metal-semiconductor interface and the resistance of one or more semiconductor regions. In some implementations, the resistance of the semiconductor resistor can be based on the contact resistance of the metal-semiconductor interface and the resistance of two or more semiconductor regions.

In the example shown in figure 56A, semiconductor resistors 621 formed on die 618 can include isolated resistive regions 634 formed during the step of forming subcollector 623 of HBT 622. This resistive region may be formed of, for example, n + GaAs and is isolated from HBT622 and other portions of die 618 by isolation features 638 and 639. Electrical contacts 640 may be formed on the resistive region 634 to enable the semiconductor resistor 621 to be used in an electrical circuit.

In some implementations of the invention, resistive region 634 may be masked during formation of other upper layers of HBT 622. Upon completion of HBT622, the mask over resistive region 634 may be removed. Then, electrical contacts 640 for the resistive region 634 may be formed during the formation of other contacts (e.g., 631, 632, and 633).

Fig. 56A-1 is an electrical schematic diagram of the semiconductor resistor 106 of fig. 56A. As shown in FIG. 56A-1, the resistance between two electrical contacts 640 may be represented by the contact resistance R of the metal-semiconductor interface_C ^AModeling the contact resistance with the resistance of the resistive region 634 and another contact resistance R of the metal-semiconductor interface_C ^AAre connected in series. The contact resistance Rc of the metal-semiconductor interface can be equal toIn proportion of whereinIs the barrier height (which depends on the work function of the contact metal) and Nd is the doping concentration of the semiconductor material adjacent to the contact metal. The contact resistances in fig. 56A-1 to 56G-1 are different from each other when the semiconductor layers adjoining the electrical contact have different doping concentrations. The different contact resistances in fig. 56A-1 through 56G-1 may contribute to a semiconductor resistor 621 having a selected resistance value.

In the example shown in figure 56B, semiconductor resistors 621 formed on die 618 can include isolated resistive regions 645 formed during the step of forming collector 624 of HBT 622. The isolated resistive region 645 may be formed over the resistive region 634, as illustrated. This resistive region 645 may be formed of, for example, n-GaAs and is isolated from HBT622 and other portions of die 618 by isolation features 638 and 639. Electrical contacts 641 may be formed on resistive region 645 to enable semiconductor resistor 621 to be used in a circuit.

In some implementations, resistive region 645 may be masked during formation of other upper layers of HBT 622. Upon completion of HBT622, the mask over resistive region 645 may be removed. Next, electrical contacts 641 of resistive region 645 may be formed during formation of other contacts (e.g., 631, 632, 633).

Fig. 56B-1 is an electrical schematic diagram of the semiconductor resistor 621 of fig. 56B. The schematic diagram of fig. 56B-1 has a different contact resistance value than the schematic diagram of fig. 56A-1. In addition, the schematic of FIG. 56B-1 also includes the resistance of the resistive region 645 in parallel with the resistance of the resistive region 634. As shown in fig. 56B-2, the resistance between the two electrical contacts 641 may be represented by the contact resistance R of the metal-semiconductor interface_C ^BModeled, the contact resistance in series with the parallel resistance of the resistive regions 612 and 614, and further with another contact resistance R of the metal-semiconductor interface_C ^BAre connected in series.

In the example shown in figure 56C, semiconductor resistor 621 formed on die 618 can include an additional isolated resistive region 650 formed during the step of forming base 625 of HBT 622. This resistive region may be formed of, for example, p + GaAs and is isolated from HBT622 and other portions of die 618 by isolation features 638 and 639. Electrical contacts 642 may be formed on resistive region 650 to enable semiconductor resistor 621 to be used in a circuit.

In some implementations, resistive region 650 may be masked during formation of other upper layers of HBT 622. Upon completion of HBT622, the mask over resistive region 650 may be removed. Then, electrical contacts 642 for the resistive region 650 may be formed during the formation of the other contacts (e.g., 631, 632, and 633).

Fig. 56C-1 is an electrical schematic diagram of the semiconductor resistor 621 of fig. 56C. The schematic diagram of FIG. 56C-1 has a different contact resistance value than the schematic diagrams of FIGS. 56A-1 and 56B-1. The schematic of fig. 56C-1 includes a diode at the PN junction between the resistive region 645 and the resistive region 650. One of these diodes should be reverse biased. Thus, the resistance of resistive regions 634 and 645 should not contribute significantly to the resistance between electrical contacts 642. Thus, the resistance between electrical contacts 642 can be determined by the contact resistance R of the metal-semiconductor interface_C ^CIn proximity, the contact resistance is in series with the resistance of the resistive region 650 and further with another contact resistance R of the metal-semiconductor interface_C ^CAre connected in series.

In the example shown in figure 56D, semiconductor resistor 621 formed on die 618 can include isolated resistive region 655 formed during the step of forming emitter 626 of HBT 622. Such a resistive region may be formed of, for example, n-InGaP and isolated from HBT622 and other portions of die 618, as illustrated. Electrical contacts 643 may be formed over resistive region 655 to enable semiconductor resistor 621 to be used in an electrical circuit.

In some implementations, resistive region 655 may be masked during formation of other upper layers of HBT 622. Upon completion of HBT622, the mask over resistive region 655 may be removed. Electrical contact 643 of resistive region 655 may then be formed during formation of other contacts (e.g., 631, 632, and 633).

Fig. 56D-1 is an electrical schematic diagram of the semiconductor resistor 621 of fig. 56D. The schematic of FIG. 56D-1 includes a diode at the PN junction between resistive region 650 and resistive region 655. One of these diodes should be reverse biased. Thus, the resistance of resistive regions 634, 645, and 650 should not significantly contribute to the resistance between electrical contacts 643. Thus, the resistance between electrical contacts 643 may be determined by the contact resistance R of the metal-semiconductor interface_C ^DClose to, the contact resistance with the resistance of the resistive region 655 and another contact resistance R of the metal-semiconductor interface_C ^DAre connected in series.

In the example shown in figure 56E, semiconductor resistor 621 formed on die 618 can include an additional isolated resistive region 635 formed during the step of forming emitter cap 627 of HBT 622. Such a resistive region may be formed of, for example, n-GaAs and isolated from HBT622 and other portions of die 618, as illustrated. Electrical contacts 644 may be formed on the resistive region 635 so that the semiconductor resistor 621 may be used in a circuit.

In some implementations, resistive region 635 may be masked during formation of other upper layers of HBT 622. Upon completion of HBT622, the mask over resistive region 635 may be removed. The electrical contact 644 of the resistive region 635 may then be formed during the formation of other contacts, such as contacts 631, 632, and 633, for example.

Fig. 56E-1 is an electrical schematic diagram of the semiconductor resistor 621 of fig. 56E. The schematic of FIG. 56E-1 is similar to the schematic of FIG. 56D-1, except that the resistance of the resistive region 635 is included in parallel with the resistance of the resistive region 655 and the contact resistance of the metal-semiconductor interface is different. The resistance between the electrical contacts 644 may be determined by the contact resistance R of the metal-semiconductor interface_C ^EIn proximity, the contact resistance is in series with the parallel resistance of resistive regions 655 and 635, and further with another contact resistance R of the metal-semiconductor interface_C ^EAre connected in series.

In an example of the invention as next shown in figure 56F, semiconductor resistor 621 formed on die 618 can include an isolated resistive region 636 formed during the step of forming bottom contact layer 628 of HBT 622. Such a resistive region may be formed of, for example, n + GaAs and isolated from HBT622 and other portions of die 618, as illustrated. Electrical contacts 646 may be formed on the resistive region 636 so that the semiconductor resistor 621 may be used in a circuit.

In some implementations of the invention, resistive region 636 can be masked during formation of other upper layers of HBT 622. Upon completion of HBT622, the mask over resistive region 636 may be removed. Then, electrical contact 646 for resistive region 636 can be formed during the formation of other contacts, such as contacts 631, 632, and 633.

Fig. 56F-1 is an electrical schematic diagram of the semiconductor resistor 621 of fig. 56F. The schematic of FIG. 56F-1 is similar to the schematic of FIG. 56E-1, except that the resistance of the resistive region 636 is included in parallel with the resistances of the resistive regions 655 and 635 and the contact resistance of the metal-semiconductor interface is different. The resistance between contacts 646 may be determined by the contact resistance R of the metal-semiconductor interface_C ^FIn proximity, the contact resistance is in series with the parallel resistance of resistive regions 655, 635 and 636, and further with another contact resistance R of the metal-semiconductor interface_C ^FAre connected in series.

In the example shown in figure 56G, semiconductor resistors 621 formed on die 618 can include isolated resistive region 637 formed during the step of forming top contact layer 629 of HBT 622. Such resistive regions may be formed of, for example, n-InGaAs and isolated from HBT622 and other portions of die 618, as illustrated. Electrical contacts 647 can be formed on resistive region 637 to enable semiconductor resistor 621 to be used in a circuit.

In some implementations, resistive region 637 may be masked during formation of any other upper layers of HBT 622. Upon completion of HBT622, the mask over resistive region 637 can be removed. Then, electrical contacts 647 of resistive region 637 may then be formed during the formation of other contacts (e.g., contacts 631, 632, and 633).

Fig. 56G-1 is an electrical schematic diagram of the semiconductor resistor 621 of fig. 56G. The schematic of FIG. 56G-1 is similar to the schematic of FIG. 56F-1, except that the contact resistance of the metal-semiconductor interface is different and the resistance of resistive region 637 is included in parallel with the resistance of resistive regions 655, 635 and 636. The resistance between the electrical contacts 647 may be determined by the contact resistance R of the metal-semiconductor interface_C ^GIn proximity, the contact resistance is in series with the parallel resistance of resistive regions 655, 635, 636 and 637And further another contact resistance R with the metal-semiconductor interface_C ^GAre connected in series.

In the example configuration of figures 56A-56G, the resistive region of the top layer of resistor 621 may represent the corresponding layer in HBT622 stack. Thus, for example, the resistive region 645 corresponds to the collector 624. Similarly, resistive region 650 corresponds to base 625. The resistance of one or more resistive regions in resistor 621 may contribute to the overall resistance of resistor 621. In some cases, the resistance of two or more resistive regions in resistor 621 may contribute to the overall resistance of resistor 621. As discussed above, in some implementations, the lower layer may have a relatively small contribution to the resistance of the semiconductor resistor 621 as compared to the contribution from one or more upper layers that include electrical contacts. In some cases, the resistance of the top layer of resistor 621 may be correlated to a measurement of characteristics of the corresponding layer of HBT 622.

The example configuration of fig. 56A-56G shows that a selected one of some or all of the layers in a stacked device may be used to form a semiconductor resistor. This concept is schematically depicted in fig. 57A, where die 618 is shown to include a stacked device having multiple layers. Among the plurality of layers is a selected layer 651; and there may be additional layers collectively depicted above (collectively 652) and/or below as 649. To form the resistive region 654 corresponding to the selected layer 651, a layer 653 or layers collectively depicted as 653 may be formed separately during formation of the corresponding lower portion or portions 649. The desired resistive region 654 may then be formed during formation of the selected layer 651. If it is desired to form the upper portion 652 of the stack 648, the resistive region 654 may be masked during such formation steps. Upon completion of such steps, the mask can be removed to allow for the formation of electrical contacts 656. The resulting resistive region 654 with contacts 656 then forms a semiconductor resistor 621.

In some embodiments, the resistive region 654 may have: a thickness "t" that is substantially the same as the thickness of selected layer 651 of stack 648; and lateral dimensions "d 1" and "d 2," as shown in fig. 57A and 57B. Such dimensions may be selected to produce features such as a desired resistance and footprint size of resistor 621.

Fig. 57C shows that the semiconductor resistor 621 described with reference to fig. 57A and 57B can be schematically represented as a resistor having a resistance "R". Examples of how such a resistor may be utilized in different applications are described in more detail herein.

Fig. 58 shows that in some embodiments, semiconductor resistors 621 formed on a die and having one or more features described herein can be coupled with stacked devices, such as transistor 648 (e.g., HBT), formed on the same die. FIGS. 59A, 59B, and 59C show different example embodiments of the configuration of FIG. 58. In the illustrated example, semiconductor resistor 621 is shown to provide a ballast resistance for the base of HBT648 (fig. 59A), the emitter of HBT648 (fig. 59B in the context of an example NPN configuration), and the collector of HBT648 (fig. 59C). Additional details regarding semiconductor ballasting can be found in U.S. patent No. 5,378,922 entitled "hbt with semiconductor ballasting" (hbt with semiconductor ballasting), which is expressly incorporated herein by reference in its entirety and is considered part of the specification of the present application.

In some embodiments, a resistor 621 having one or more features as described herein may be coupled to the transistor 648 for purposes other than ballasting. In some embodiments, this resistor may be used in a circuit having a transistor; but not necessarily directly with the transistor.

In some embodiments, a resistor having one or more features as described herein may be implemented on a die and connected to another circuit located external to the die. For example, fig. 60 shows an example in which semiconductor resistors 621 are formed on die 618. One terminal (referenced 657) of resistor 621 is shown configured to be electrically connected to a location external to die 618, and the other terminal 658 is shown within die 618. Die 618 may include an integrated circuit (e.g., a power amplifier circuit) having one or more transistors 648; and this circuitry may be controlled from external circuitry, such as, for example, through terminal 659. The bias circuitry located external to die 618 may be such external circuitry. This bias circuit may be connected to resistor 621 and transistor 648 to allow operation of the transistor based on parameters obtained from resistor 621. Since resistor 621 may be formed of substantially the same material as the layers of transistor 648, this parameter associated with resistor 621 may track the conditions common to both transistor 648 and the resistor. An example of this condition tracking and its application is in section VI above.

As indicated above, fabricating a semiconductor resistor having one or more features as described herein may be accomplished without additional processing steps or with minimal modification of process steps when compared to fabricating a stacked structure on a given die. Although various examples are described herein in the context of HBTs, it should be understood that similar resistor structures and fabrication methods may be applied to other configurations. For example, additional layers may be formed for fabricating devices including the HBT and one or more other transistor structures. Examples of such devices include, but are not limited to, U.S. patent No. 6,906,359 and PCT publication No. WO2012/061632 as cited above in the summary of the invention section.

As discussed above, one or more features of the present invention may be implemented in a III-V semiconductor die. In some embodiments, such a III-V semiconductor die may comprise a GaAs based die. Transistors and/or other stack structures formed on such GaAs based dice may or may not include HBTs.

As previously indicated above, a number of advantageous features may be provided by semiconductor resistors. For example, other advantages may include desirable features where different Temperature Coefficient of Resistance (TCR) values are provided by selection of materials associated with the resistor layer. In another example, the size of the resistor may be optimized or configured in a desirable manner due to this range of possible resistance values, such as a sheet resistance of about 8 ohms/square (e.g., a subcollector) to about 1, 000 ohms/square (e.g., an implanted base layer). In yet another example, the RF attenuation of a resistor may be selected and/or tuned depending on which resistor is selected (e.g., by modifying how the third terminal on the device is biased).

In some embodiments, a die having one or more features described in this section may be implemented in a packaged module (such as packaged module 436 discussed above in section VI with respect to fig. 41A and 41B of the present disclosure). As discussed above, the module 436 of fig. 41A and 41B is shown to include a package substrate 437. Such a package substrate may be configured to receive a plurality of components, and may include, for example, a laminate substrate. The components mounted on the package substrate 437 may include one or more semiconductor dies. In the example shown, PA die 416 can implement HBTPA die 618 discussed in this section, and module 436 can similarly include a silicon bias die 417 as shown mounted on package substrate 437. The PA die 618 as implemented in the exemplary module 436 of fig. 41A and 41B may include a transistor 648 and a semiconductor resistor 621 as described in this section; and the bias die 417 may include circuitry configured to provide control signals to the PA die 618. In this embodiment, dice 618 and 417 may be electrically connected to other portions of the module and to each other by connections, such as bond wire bonds 443. Such wire bonds may be formed between contact pads 441 formed on the die and contact pads 438 formed on the package substrate 437. In some embodiments, one or more Surface Mounted Devices (SMDs) 442 may be mounted on the package substrate 437 to facilitate various functionalities of the module 436 as implemented with these aspects and features of the invention.

In some embodiments, RF shielding features, such as shield wire bonds 444, may be provided to facilitate RF shielding of one or more components, such as the current die HBT618, die 417, and/or SMD 442. Such an RF shield as discussed in the context of the present disclosure may inhibit RF signals or noise from passing between such components and regions outside of the module 436. In implementations of shield wire bonds 444, such wire bonds may be formed on contact pads 439 such that shield wire bonds 444 generally form a perimeter around a desired region (e.g., near the perimeter of module 436). The size and spacing of such shield wire bonds may be selected to provide desired RF shielding properties.

In some embodiments, a three-dimensional RF shielding structure may be provided as follows. As shown in fig. 41B, the shield wire bonds 444 may be electrically connected to the ground plane 440 below the surface of the package substrate 437. Such connections between the shield wire bonds 444 and the ground plane 440 may be facilitated by contact pads 439 and connection features 450 (e.g., vias formed in the substrate 437). The above shield wire bond 444 and a conductive layer (e.g., a conductive paint layer) 445 may be provided such that the conductive layer 445 is electrically connected with an upper portion of the shield wire bond 444. Thus, conductive layer 445, shield line bond 444, and ground plane 440 may form a three-dimensional RF shield structure.

In some embodiments of the present invention, the space between package substrate 437 and conductive layer 445 may be filled with the over-mold structure 446 discussed above. Such an over-molded structure may provide a number of desirable functionalities, including protection of components and wire bonds from external elements and easier handling of the packaged module 436.

Additional aspects of these RF shielding and overmolding structures according to aspects of the present invention are presented in further detail herein below in sections XII and XIII.

In some implementations of the invention, devices and/or circuits having one or more of the resistor features described herein may be included in an RF device (e.g., a wireless device). Such a device and/or circuitry may be implemented directly in a wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device may include, for example, a cellular telephone, a smartphone, a handheld wireless device with or without telephone functionality, a wireless tablet, and such like devices now known or hereafter implemented.

Referring now back to fig. 42, the PA module 436 described therein may be advantageously implemented with the PA die 618 discussed in this section. This module may also include a bias die 417 as previously described herein. In some embodiments, such a PA module may better facilitate multi-band operation of wireless device 447, for example.

As described above, the PA in module 436 may receive its respective RF signal from transceiver 454, which may be configured and operated in a known manner to generate an RF signal to be amplified and transmitted and to process the received signal. The transceiver 454 is shown interacting with a baseband subsystem 453 configured to provide conversion between data and/or voice signals, which are appropriate for a user, and RF signals, which are appropriate for the transceiver 454. The transceiver 454 is also shown connected to a power management component 451 that is configured to manage power for operation of the wireless device. This power management may also control the operation of baseband subsystem 453 and module 436.

Baseband subsystem 453 is shown connected to a user interface 448 to facilitate various inputs and outputs for voice and/or data provided to and received from a user. The baseband subsystem 453 may also be connected to memory 649, which is configured to store data and/or instructions to facilitate operation of the wireless device and/or to provide a user with a store of information.

In an example wireless device 447, the output of the PA of module 436 may be matched by a matching network and routed to antenna 458 via its respective duplexer 456 and band selection switch 457. In some embodiments, each duplexer may allow transmit and receive operations to be performed simultaneously using a common antenna (e.g., 458). In fig. 42, the received signal is shown routed to an "Rx" path (not shown) that may include, for example, a Low Noise Amplifier (LNA).

A number of other wireless device configurations may utilize one or more features described herein. For example, the wireless device need not be a multi-band device. In another example, the wireless device may include additional antennas (e.g., diversity antennas) and additional connectivity features (e.g., wireless fidelity, bluetooth, and GPS). Any such wireless devices may advantageously incorporate any of the resistor assemblies disclosed in this section such that any PA, PA module, or wireless device using the PA, PA module, may thereby enjoy the benefits, advantages, and improved performance associated therewith.

While various embodiments of the present disclosure and related features, aspects, and characteristics have been described in this section, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible so as to be within the scope of the present disclosure. For example, the invention herein is not limited to the materials or systems described, and may be further combined, integrated, assembled, or joined together, individually or otherwise, with any other number of relevant, desired, or suitable aspects of the invention as described throughout this disclosure, to even further improve the performance of integrated circuits, power amplifiers, power amplifier modules, and devices in which they are used.

IX. signal path termination

This section of the invention relates to a harmonic termination circuit that is separate from the load line. In one embodiment, the load line is configured to match an impedance at the power amplifier output at a fundamental frequency of the power amplifier output, and the harmonic termination circuit is configured to terminate with a phase corresponding to a harmonic frequency of the power amplifier output. According to a particular embodiment, the load line and the harmonic termination circuit may be electrically coupled to a power amplifier output external to the power amplifier die via different output pins of the power amplifier die. And further hereto, those skilled in the art of the present disclosure should readily appreciate that these aspects of the present disclosure can be combined with other aspects of the present disclosure to better improve the performance of power amplifier modules and devices in which power amplifier modules are used.

As generally described, aspects of the present disclosure relate to circuits configured to prevent reflection or reflections of a signal, such as termination circuits. More specifically, aspects of the disclosure herein relate to separate termination circuits configured to block portions of power of different frequency components of a reflected signal. Using the systems, apparatus, and methods described herein, electronic systems, such as systems including power amplifiers and/or systems configured to transmit Radio Frequency (RF) signals, may operate more efficiently and/or consume less power. For example, less energy may be converted to a harmonic frequency of the RF signal, and/or energy from a harmonic frequency component of the RF signal may be converted to energy at a fundamental frequency of the RF signal. Direct Current (DC) energy may be more efficiently converted to RF energy in accordance with one or more features described herein.

As discussed above, customers, such as Original Equipment Manufacturers (OEMs), typically desire high PAE and high linearity. The load line at the output of the power amplifier may affect PAE and linearity. The load line at the output power amplifier may be configured to increase and/or optimize linearity and/or PAE. This may include matching the fundamental frequency component and/or terminating one or more harmonic frequency components of the power amplifier output. This load line may be implemented by a termination circuit.

The power amplifier output may include a fundamental frequency component and one or more harmonic frequency components. Similarly, the input to the power amplifier or power amplifier stage may include a fundamental frequency component and one or more harmonic frequency components. Some conventional power amplifier systems have included a single termination circuit (e.g., a load line) to match the impedance of the fundamental frequency of the signal at the node and to terminate with a phase corresponding to the harmonic frequency of the signal at the node. However, tuning a single termination circuit to achieve both impedance matching the fundamental frequency of the amplified power amplifier output signal and phase termination at the harmonic frequency of the amplified power amplifier output signal in a manner that optimizes both PAE and linearity can be difficult. Thus, PAE may be reduced due to either optimizing an impedance that matches a fundamental frequency of the amplified power amplifier output or terminating the amplified power amplifier output with a phase of a harmonic frequency.

As described in this section, an electronic system may include two or more separate termination circuits that are each coupled to a node in a signal path, such as a power amplifier output or an input to a power amplifier stage. The first termination circuit may be configured to match an impedance of a fundamental frequency of a signal at the node. In some implementations, the first termination circuit can be included in a base load line. A second termination circuit, separate from the first termination circuit, may be configured to terminate with a phase corresponding to a harmonic frequency of the signal at the node. The circuit elements of the first termination circuit and the second termination circuit may be selected so as to improve PAE and linearity in the power amplifier system.

In some implementations of the invention, at least a portion of the first termination circuit and/or the second termination circuit can be embodied external to a die that includes circuit element(s) that drive an output node of the die, such as a power amplifier output of a power amplifier die. For example, the first termination circuit can include one or more interconnects (e.g., wire bonds) electrically connected to one or more pins of a power amplifier die coupled to a package substrate and one or more capacitors separate from the power amplifier die and coupled to the package substrate. Alternatively or additionally, the second termination circuit can include one or more interconnects (e.g., wire bonds) electrically connected to one or more pins of the power amplifier die and one or more other capacitors coupled to the package substrate. When multiple interconnects are included in the termination circuit, the interconnects may be coupled in parallel with each other. In at least one of the first and second termination circuits, one or more wire bonds may serve as inductive circuit elements and be coupled in series with one or more capacitors coupled to the package substrate.

Outside the die, the first termination circuit and the second termination circuit may have different electrical connections to the output node of the die. In a particular implementation, a first output pin of a die may be coupled to a first termination circuit by a first wire bond, and a second output pin of the die may be coupled to a second termination circuit by a second wire bond. In some of these implementations, a first number of wire bonds may couple the first termination circuitry to the pins of the die and a second number of wire bonds may couple the second termination circuitry to the pins of the die, where the first number is different than the second number. According to a number of other implementations, a first output pin of a die can be coupled to a first termination circuit through a first bump, and a second output pin of the die can be coupled to a second termination circuit through a second bump. In some of these implementations, a first number of bumps may couple the first termination circuit to the pins of the die and a second number of bumps may couple the second termination circuit to the pins of the die, where the first number is different than the second number.

The first termination circuit and the second termination circuit may include different signal paths external to the die. For example, the first termination circuit may include a first trace implemented on the package substrate, and the second termination circuit may include a second trace on the substrate. The first and second traces may be part of separate signal paths on the substrate. For example, in some implementations, the first trace may be part of an RF signal path and the second trace may be part of a DC signal path. The first and second traces can be electrically separated from each other outside the die.

Alternatively or additionally, within the die, the output nodes may be electrically coupled to the branch conductive features such that the outputs are provided to separate signal paths on the die. The separate signal paths may include a first path included in the first termination circuit and a second path included in the second termination circuit. In this manner, the first termination circuit and the second termination circuit may be individually tuned within the die during design of the die. For example, a first signal path in the die may lead to a first output pin of the die, and a second signal path may include a capacitor implemented on the die before leading to a second output pin. In one embodiment, the collector of the output stage of the power amplifier may be directly electrically coupled to both the first termination circuit and the second termination circuit through a conductive feature of the die.

By using two or more separate termination circuits, each termination circuit can be tuned to prevent reflection of the signal at a desired frequency. For example, the inductance and/or capacitance of each termination circuit may be selected such that each termination circuit blocks reflections of desired frequency components of the signal.

The methods, systems, and apparatus of signal path termination described in this section may be capable of achieving one or more of the following advantageous features, as well as other advantageous features. Advantageously, separate termination circuits configured to prevent reflections of two or more distinct frequency components of a signal may increase one or more of PAE, linearity, and baseband performance (e.g., wider wide frequency response and/or larger bandwidth) of the power amplifier. In some implementations, both the PAE and linearity of the power amplifier may be increased. In addition, the figure of merit (FOM) of the power amplifier may also be increased. Further, battery life may be extended, heat dissipated may be reduced, signal quality of signals for which reflection is prevented by a separate termination circuit may be increased, or any combination thereof. Even further advantages and improvements may be realized when the methods, systems, and apparatus for signal path termination described in this section are combined with other aspects of the invention as disclosed throughout this disclosure.

A. Wireless device

Referring now to FIG. 61A, a wireless device 661 is shown in a schematic block diagram that can be implemented to advantageously include the features of the present invention. Any of the systems, methods, and apparatuses for preventing reflection of two or more frequency components of a signal described herein may be implemented in a variety of electronic devices, such as wireless devices or mobile devices. Examples of wireless devices 661 include, but are not limited to, cellular telephones (e.g., smart phones), laptop computers, tablet computers, Personal Digital Assistants (PDAs), electronic book readers, portable digital media players, and other such devices now known or hereafter implemented. For example, the wireless device 661 can be a multi-band and/or multi-mode device (e.g., a multi-band/multi-mode mobile phone) configured to communicate using, for example, Global System for Mobile (GSM), Code Division Multiple Access (CDMA), 3G, 4G, Long Term Evolution (LTE), and the like, or any combination thereof.

In a particular embodiment, the wireless device 661 may include an RF front end 662, a transceiver component 663, an antenna 664, a power amplifier 665, a control component 666, a computer-readable medium 667, a processor 668, a battery 669, and a supply control block 670, or any combination thereof.

The transceiver component 663 may generate RF signals for transmission via the antenna 664. Further, the transceiver component 663 may receive incoming RF signals from the antenna 664.

It should be understood that various functionalities associated with the transmission and reception of RF signals may be realized by one or more components commonly represented in fig. 61A as transceiver 663. For example, a single component may be configured to provide both transmit and receive functionality. In another example, the transmit and receive functionality may be provided by separate components.

Similarly, it should also be understood that various antenna functionality associated with the transmission and reception of RF signals may be implemented by one or more components collectively represented in fig. 61A as antenna 664. For example, a single antenna may be configured to provide both transmit and receive functionality. In another example, transmit and receive functionality may be provided by separate antennas. In yet another example, different frequency bands associated with the wireless device 661 can be provided with different antennas.

As represented in fig. 61A, one or more output signals from transceiver 663 are depicted as being provided to antenna 664 via one or more transmit paths via RF front end 662. In the example shown, different transmit paths may represent output paths associated with different frequency bands and/or different power outputs. For example, the two example power amplifiers 665 shown may represent amplification associated with different power output configurations (e.g., low power output and high power output) and/or amplification associated with different frequency bands. In some implementations, one or more of the transmit paths may include one or more termination circuits therein.

In fig. 61A, one or more detected signals from an antenna 664 are depicted as being provided to a transceiver 663 via one or more receive paths. In the example shown, different receive paths may represent paths associated with different frequency bands. For example, the four example paths shown may represent quad-band capabilities that some wireless devices are capable of.

To facilitate switching between receive and transmit paths, the RF front end 662 can be configured to electrically connect the antenna 664 to a selected transmit or receive path. Thus, the RF front end 662 may provide a number of switching functionalities associated with the operation of the wireless device 661. In a particular embodiment, the RF front end 662 may include a number of switches configured to provide functionality associated with, for example, switching between different frequency bands, switching between different power modes, switching between transmit and receive modes, or some combination thereof. The RF front end 662 may also be configured to provide additional functionality including filtering of signals. For example, RF front end 662 may include one or more duplexers. Further, in some implementations, the RF front end 662 may include one or more termination circuits configured to prevent reflection of frequency components of the signal.

The wireless device 661 may include one or more power amplifiers 665. The RF power amplifier may be used to boost the power of RF signals having relatively low power. Thereafter, the boosted RF signal may be used for a variety of purposes, including driving an antenna of the transmitter. Power amplifier 665 may be included in an electronic device, such as a mobile phone, to amplify an RF signal for transmission. For example, in a mobile phone having an architecture for communicating under 3G and/or 4G communication standards, a power amplifier may be used to amplify RF signals. Managing amplification of RF signals may be desirable because the desired transmit power level may depend on how far away the user is from the base station and/or the mobile environment. The power amplifier may also be used to help adjust the power level of the RF signal over time in order to prevent transmission signal interference during the assigned reception time slots. The power amplifier module may include one or more power amplifiers.

FIG. 61A illustrates that, in a particular embodiment, a control component 666 can be provided and such component can be configured to provide various control functionality associated with operation of the RF front end 662, the power amplifier 665, the supply control 670, and/or other operational components.

In a particular embodiment, the processor 668 may be configured to facilitate implementation of the various processes described herein. For purposes of illustration, embodiments of the present invention may also be described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the actions specified in the flowchart and/or block diagram block or blocks.

In a particular embodiment, these computer program instructions may also be stored in a computer-readable memory 667 that can direct a computer or other programmable data processing apparatus to function in a particular manner such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the action specified in the flowchart and/or block diagram block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide operations for implementing the actions specified in the flowchart and/or block diagram block or blocks.

The illustrated wireless device 661 also includes supply controls 670 that can be used to provide a power supply to one or more of the power amplifiers 665. For example, the supply control 670 may be a DC/DC converter. However, in a particular embodiment, the supply control 670 may include other functions, such as, for example, an envelope tracker configured to vary a supply voltage provided to the power amplifier 665 based on an envelope of an RF signal to be amplified.

The supply control 670 may be electrically connected to the battery 669, and the supply block 670 may be configured to vary the voltage provided to the power amplifier 665 based on the output voltage of the DC/DC converter. The battery 669 can be any suitable battery for use in the wireless device 661, including, for example, a lithium ion battery. By reducing reflections of the output signal of the power amplifier 665, power consumption of the battery 669 may be reduced, thereby improving performance of the wireless device 661. For example, the termination circuit described herein may extend the amount of time it takes for the battery 669 to discharge.

FIG. 61B is a schematic block diagram of another illustrative wireless device 672 that may implement one or more aspects of this disclosure. In some implementations, the illustrative wireless device 672 of fig. 61B may be a mobile phone. Any combination of features of the termination circuit described herein may be implemented in, for example, a 2.5G module and/or a 3G/4G Front End Module (FEM) of wireless device 672, along with a power amplifier.

The illustrated wireless device 672 includes a main antenna 673, a switch module 674, a 2.5G module 676, a 3G/4G front end module 677, a LNA module 678, a diversity antenna 679, a diversity front end module 681, a transceiver 682, a Global Positioning System (GPS) _ antenna 683, a power management controller 684, a baseband application processor 686, a memory 687, a user interface 688, an accelerometer 689, a camera 691, a WLAN/FM Bluetooth system on a chip (SOC)692, a WLAN Bluetooth antenna 693, and an FM antenna 694. It should be understood that wireless device 672 may include more or fewer components than illustrated in fig. 61B.

Transceiver 682 may be a multimode transceiver. The transceiver 682 may be used to generate and process RF signals using a variety of communication standards, including, for example, global system for mobile communications (GSM), Code Division Multiple Access (CDMA), wideband CDMA (W-CDMA), enhanced data rates for GSM evolution (EDGE), other proprietary and non-proprietary communication standards, or any combination thereof. As illustrated, the transceiver 682 is electrically coupled to a 2.5G module 676 and a 3G/4G front end module 677. The power amplifiers in the 2.5G module 676 and the 3G/4G front end module 677 may boost the power of RF signals having relatively low power. Thereafter, the boosted RF signal may be used to drive the primary antenna 673. Such power amplifiers may include any of the termination circuits described herein to reduce reflections and/or noise at the input and/or output. The switch module 674 may selectively electrically couple the power amplifiers in the 2.5G module 676 and the 3G/4G front end module 677 to the primary antenna 673. The switch module 674 can electrically connect the primary antenna 673 to a desired transmit path.

In a particular implementation, the diversity front end module 681 and the diversity antenna 679 may help improve the quality and/or reliability of the wireless link by reducing line of sight loss and/or mitigating the effects of phase shifts, time delays, and/or distortions associated with signal interference of the primary antenna 673. In some embodiments, multiple diversity front end modules and diversity antennas may be provided to further improve diversity.

Wireless device 672 may include a WLAN/FM bluetooth SOC module 692 that may generate and process received WLAN bluetooth and/or FM signals. For example, the WLAN/FM Bluetooth SOC module 692 may be used to connect to a Bluetooth device (e.g., a wireless headset) and/or communicate via the Internet using a wireless access point or hotspot via the WLAN Bluetooth antenna 693 and/or the FM antenna 694.

The wireless device 672 may also include a baseband application processor 686 to process baseband signals. A camera 691, accelerometer 689, user interface 688, or the like, or any combination thereof, may be in communication with baseband application processor 686. Data processed by the baseband application processor may be stored in memory 687.

Although the termination circuit has been illustrated and described in the context of two examples of wireless devices, the termination circuit described in this section may be used in other wireless devices and electronics.

B. Module

Fig. 61C is a schematic block diagram of a power amplifier module 696. Although a power amplifier module having a power amplifier die will be discussed for illustrative purposes, it should be understood that the principles and advantages described herein may be applied to any suitable die and/or any suitable electronic module. Power amplifier module 696 may contain some or all parts of the power amplifier system. In a particular implementation, the power amplifier module 696 may be referred to as a multi-chip module. The power amplifier module 696 may include a package substrate 697, one or more power amplifier dies 698, a matching network 699, one or more other dies 700, and one or more circuit elements 701 coupled to the package substrate 697, and the like, or any combination thereof.

The one or more other dies 700 can include, for example, a controller die that can include a power amplifier bias circuit and/or a direct current/direct current (DC/DC) converter. Example circuit elements 701 mounted on a package substrate may include, for example, inductors, capacitors, and the like, or any combination thereof. The power amplifier module 696 may include a plurality of dies and/or other components attached to and/or coupled to a package substrate 697 of the power amplifier module 696. In some implementations, the substrate 697 can be a multi-layer substrate configured to support a die and/or other components and provide electrical connectivity to external circuitry when the power amplifier module 696 is mounted on a circuit board (e.g., a phone board). Thus, the substrate 697 may be configured to receive multiple components, such as a die and/or separate passive components. Substrate 697 can be a laminated substrate with a surface treatment coating.

The power amplifier die 698 may receive RF signals at one or more input pins of the power amplifier module 696. The power amplifier die 698 may include one or more power amplifiers, including, for example, a multi-stage power amplifier configured to amplify RF signals. The amplified RF signal may be provided to one or more output pins of the power amplifier die 698. The one or more output pins may be, for example, bond pads configured for wire bonding. A matching network 699 may be provided on the power amplifier module 696 to help reduce signal reflections and/or other signal distortions. The matching network 699 may include one or more termination circuits implementing any combination of the features described herein. Although the matching network is shown external to the power amplifier die 698, it should be understood that at least a portion of the matching network 699 may be implemented on the power amplifier die 698. The power amplifier die 698 may be any suitable die. In some implementations, the power amplifier die is a gallium arsenide (GaAs) die. In some of these embodiments, the GaAs die has transistors formed using a Heterojunction Bipolar Transistor (HBT) process.

One or more circuit elements 701 of the power amplifier module 696 may include capacitors and inductors. The inductor 701 may be implemented on the substrate 697 as traces on the substrate 697 or as a Surface Mount Component (SMC) mounted to the substrate 697. The inductor may be operated as a choke inductor and may be disposed at a supply voltage pin V_CCThe upper received supply voltage and the power amplifier die 698. The inductor may provide the power amplifier on the power amplifier die 698 at the supply voltage pin V_CCUp the received supply voltage while choking and/or blocking high frequency RF signal components. The inductor may include a supply voltage pin V electrically connected to_CCAnd a second terminal electrically connected to the collector of the bipolar transistor associated with the power amplifier die 698. The capacitor may act as a decoupling capacitor. The capacitor may include a first end electrically connected to the first end of the inductor and a second end electrically coupled to ground, which in a particular implementation is provided using a ground pin (not illustrated) of power amplifier module 696. The capacitor may provide a low impedance path to high frequency signals, thereby reducing noise of the power amplifier supply voltage, improving power amplifier stability and/or improving the performance of the inductor as an RF choke. In some implementations, the capacitor may include SMC.

Matching network 699 may include two or more termination circuits. In some implementations, the matching network 699 can include wire bonds to electrically connect input and/or output pins of the power amplifier die 698 to the package substrate 697. The wire bond may act as an inductive circuit element. Inductance can be increased by adding additional parallel wire bonds. The parallel wire bonds may each be coupled to a different pin of the power amplifier die 698. Inductance may be reduced by removing parallel wire bonds and/or adding series wire bonds. The matching network 699 may also include one or more conductive traces on a substrate 697 and one or more capacitors mounted on the substrate 697. Each termination circuit may include conductive traces and/or capacitors in series with one or more line bonds electrically connected to one or more pins of the power amplifier die 698. The capacitance and/or inductance values may be selected so as to prevent reflection of particular frequency components (e.g., from the antenna) due to impedance mismatches. This may advantageously increase PAE, power amplifier linearity, bandwidth across which the power amplifier operates within specification, FOM, and the like, or any combination thereof. Termination circuits that may be included in the matching network 699 are described in more detail herein below.

Power amplifier module 696 may be modified to include more or fewer components, including, for example, additional power amplifier dies, capacitors, and/or inductors. For example, power amplifier module 696 may include one or more additional matching networks 699. IN particular, there may be another matching network between RF _ IN and the input to the power amplifier die 698 and/or additional matching networks between power amplifier stages. As another example, power amplifier module 696 may include an additional power amplifier die and V configured to operate as disposed on the additional power amplifier die and module_CCAdditional capacitors and inductors of the LC circuit between the pins. The power amplifier module 696 may be configured to have additional pins, such as in implementations in which separate power supplies are provided to an input stage disposed on a power amplifier die and/or in which a multi-chip module operates across multiple frequency bandsIn the following embodiments.

C. Termination circuit

As used herein, termination circuit may refer to a circuit configured to block a portion of the power of a reflected signal (e.g., an RF signal). The termination circuit may be configured to reduce and/or minimize reflection of the signal by matching impedances. This may increase PAE and/or power amplifier gain. The termination circuit may include, for example, a load line configured to match an impedance of a fundamental frequency at a node and one or more harmonic termination circuits.

Referring to fig. 62, a circuit diagram of a power amplifier system having an example termination circuit will be described. Some or all of the portions of the power amplifier system may be implemented on the power amplifier module 696 of fig. 61C. As shown in fig. 62, power amplifier module 696 may include power amplifier stages 713 and/or 714 (e.g., GaAs bipolar transistors), power supply pins (e.g., V)_SUP1And V_SUP2) Inductor 716 and/or 717, matching networks 705 and 708, and input matching circuit 712, or any combination thereof. The RF input signal RF _ IN may be provided to the first stage power amplifier 713 via an input matching circuit 712. The first stage amplified RF signal may be generated by a first stage power amplifier 713. The first stage amplified RF signal may be provided to a second stage power amplifier 714 via an interstage power amplifier matching network 706. The second stage amplified RF signal may be generated by a second stage power amplifier 714. The second stage amplified RF signal may be provided to an output load via an output matching network 709. In some embodiments, the RF signal RF _ OUT provided to the output load may be provided to the output of the power amplifier module.

First stage power amplifier 713 may be coupled to a power supply (e.g., to supply V) via choke inductor 716 _SUP1Battery or other source). Similarly, second stage amplifier 714 may be coupled to a power supply via choke inductor 717 (e.g., to provide V)_SUP2The battery of (a). The first power amplifier stage 713 may be tuned at a base of the corresponding termination circuit to block the first stage amplified RF signalThe present frequency component and the reflection of one or more harmonic components of the first stage amplified RF signal consume less power from the power supply. Similarly, the second power amplifier stage 714 may consume less power from the power supply when the corresponding termination circuit is tuned to block reflections of the fundamental frequency component of the second stage amplified RF signal and one or more harmonic components of the second stage amplified RF signal.

As illustrated in fig. 62, the power amplifier module 696 may include a first matching network 705 and a second matching network 708. The first matching network 705 may include an inter-stage fundamental termination circuit 706 and an inter-stage harmonic termination circuit 707. Second matching network 708 may include output fundamental termination circuit 709 and output harmonic termination circuit 711. Any combination of the features of the second matching network 708 may be applied to the first matching network 705 as desired.

For illustrative purposes, the second matching network 708 will be described in more detail. The output base termination circuit 709 may be a base load line. The output base termination circuit 709 may be configured to block a portion of the power of the fundamental frequency component of the second stage amplified RF signal from being reflected from the load. The load may include, for example, an RF switch in the switch module 674 and an antenna 673. The output harmonic termination circuit 711 may be configured to prevent a portion of the power of one or more harmonic frequency components of the second stage amplified RF signal from leaking toward the load. More specifically, the output harmonic termination circuit 711 may include a termination circuit configured to prevent leakage of a portion of the power of the second harmonic frequency component of the second stage amplified RF signal toward the load. In some implementations, the output harmonic termination circuit 711 may alternatively or additionally include a termination circuit configured to prevent leakage of a portion of the power of the third harmonic frequency component of the second stage amplified RF signal toward the load. The principles and advantages of a separate termination circuit configured to prevent reflection of a portion of the power of the harmonic frequency components of the second stage amplified RF may be applied to any desired harmonic frequency component and/or any suitable number of harmonic frequency components. Although some embodiments are described with reference to harmonic frequencies, one or more features described herein may be applied to any desired frequency.

The termination circuit corresponding to the desired frequency component of the second stage amplified RF signal may include one or more inductive circuit elements in series with one or more capacitive circuit elements. The series circuit elements of the termination circuit may couple an input node of a base load line (e.g., output base termination circuit 709) to a ground reference voltage. The series circuit elements may include, for example, wire bonds, traces on a substrate, and surface mount capacitors. In a particular implementation, the series circuit element may include a wire bond having a first end coupled to an output pin of a die and a second end coupled to a conductive trace on a package substrate. According to some of these implementations, the series circuit element may also include a capacitor mounted on the package substrate. Such a capacitor may have a first end coupled to the conductive trace and a second end coupled to a reference voltage, such as ground potential. An effective inductance of the inductive circuit element and/or an effective capacitance of the capacitive circuit element may be selected to tune the termination circuit to prevent reflection of desired frequency components of the second stage amplified RF signal.

At node n1, the power amplifier output may include a fundamental frequency component and one or more harmonic frequency components. The RF output signal RF OUT provided to the output load may be the sum of each of these frequency components. A power amplifier output having a waveform effective for transmitting a signal may result in a desired linearity of the power amplifier. For example, it may be desirable to combine the frequency components of the power amplifier output at node n1 to form a perfect sine wave. Alternatively, or in addition, it may be desirable to prevent clipping of the output at the collector of the bipolar transistor of the power amplifier output stage 714.

The impedance at node n1 can be expressed by equations 3 and 4:

in equation 3, Z may represent the impedance at node n1, jx may represent the impedance of the transmission line between node n1 and the termination capacitor, and 1/jwC may represent the impedance of the termination capacitor. In equation 4, wL may represent the inductive component of the impedance of the transmission line, and 1/wC may represent the capacitive component of the transmission line at the fundamental frequency w. Thus, the transmission line may act as a capacitive and/or inductive circuit element. The transmission line may include one or more interconnects, for example, from one or more pins of the power amplifier die to conductive traces on the package substrate. The transmission line may also include a conductive trace on the package substrate.

The phase of the power amplifier output at node n1 may be shifted by adjusting the impedance of the transmit line. As one example, adding additional wire bonds coupling node n1 to conductive traces on the packaging substrate in parallel with one or more wire bonds may reduce the inductive impedance component of the transmit line. This may cause the phase of the impedance of a particular frequency to shift along the circuit for that particular frequency on the smith chart. Shifting the phase of the impedance, in turn, may adjust the capacitive and inductive components of the impedance, as represented by equations 3 and 4, for example. As another example, adjusting the length of the conductive traces on the package substrate may adjust the impedance of the transmission line. By adjusting the impedance of the transmit line and/or the capacitance of the termination capacitor in the harmonic termination circuit, the harmonic termination circuit can be configured to terminate at the phase of the harmonic frequency of the power amplifier output at node n 1.

In a particular implementation of the present invention, the impedance at node n1 may be approximately 0 (short circuit) at the second harmonic, and the impedance at node n1 may appear as a maximum or infinite (open circuit) at the third harmonic. For example, the short circuit impedance may be achieved by making the impedance equal to 0 in equations 3 and 4. As another example, when the capacitance of the transmit line is near zero, then the impedance will appear as an open circuit according to equations 3 and 4. In some other implementations, the impedance at node n1 may be an open circuit at the second harmonic and a short circuit at the third harmonic. Thus, the harmonic termination circuit can be configured to meet the needs of the desired application.

Referring to fig. 63A, a block diagram of another power amplifier system including an illustrative termination circuit in accordance with another embodiment will be described. Some or all of the portions of the power amplifier system illustrated in fig. 63A may be implemented on a power amplifier module 696. The power amplifier module 696 may include a power amplifier die 698 mounted on a package substrate 697. The power amplifier die 698 may include pins such as output pins 721 and 722. Although output pins 721 and 722 are each illustrated as a single pin, in a particular embodiment, these pins may each represent a group of two or more pins. The output of the power amplifier may be provided to output pins 721 and 722. Both output pins 721 and 722 may be coupled to node n1 of fig. 62. As illustrated in fig. 62, node n1 is coupled to the collector of a GaAs bipolar transistor, to the input of output matching network 709, and to the input of output harmonic termination circuit 711.

Power amplifier module 696 of fig. 63A includes an output fundamental termination circuit 709 that is separate from output harmonic termination circuit 711. Base termination circuit 709 and harmonic termination circuit 711 may have different electrical connections to the output node of the power amplifier external to power amplifier module 698 (e.g., node n1 in fig. 62). For example, different interconnects may electrically couple base termination circuit 709 and harmonic termination circuit 711 to different pins of power amplifier module 698. Base termination circuit 709 and harmonic termination circuit 711 may be included in separate signal paths on substrate 697. These separate signal paths may not be electrically connected to each other on the substrate 697 or via circuit elements external to the power amplifier module 698. Base termination circuit 709 and harmonic termination circuit 711 may be included in separate signal paths. For example, the output of the power amplifier may be provided to two or more separate signal paths, with one path going to the base termination circuit 709 and a different path going to the harmonic termination circuit 711. The two or more separate paths may include a DC path separate from an RF path, for example, as illustrated.

The basic termination circuit 709 may include one or more interconnects 719, such as wire bonds and/or bumps, coupling one or more output pins 722 to conductive traces of the package substrate 697. In implementations having more than one output pin 722, the interconnects 719 that electrically connect the pins 722 to conductive traces can be in parallel with each other. The number of interconnects 719 (e.g., wire bonds) may be adjusted to change the impedance of the output base termination circuit 709 in order to prevent reflection of desired frequency components of the signal on the signal path at the output pin 722. Including more interconnects 719 in parallel can reduce the effective inductance. The conductive traces may couple the interconnects 719 in series with the capacitors. The conductive traces may also add inductance and/or capacitance to the termination circuit, for example, as discussed above. The capacitance of the capacitor may be selected so as to prevent reflection of a desired frequency component of the signal on the signal path at the output pin 722. Alternatively or additionally, the effective capacitance of the termination circuit may be adjusted by including additional capacitors in series and/or parallel with the capacitor and/or by including other capacitive circuit elements. The effective inductance and effective capacitance of the termination circuit may be configured in combination with each other in order to increase the linearity and/or PAE of the power amplifier module 696. The effective inductance and effective capacitance may be determined, for example, based on the number of interconnects coupled to the output pins of the power amplifier die 698, the size (e.g., length) of the conductive traces on the substrate, and the capacitance of the capacitors mounted on the substrate.

The output harmonic termination circuit 711 includes one or more interconnects 718, such as wire bonds and/or bumps, that couple one or more output pins 721 to conductive traces of the package substrate 697. In implementations with more than one output pin 721, the interconnects 718 that electrically connect the pins 721 to the wire traces may be coupled in parallel. The number of interconnects 718 (e.g., wire bonds) included in the output harmonic termination circuit 711 may be configured separately from the number of interconnects 719 of the output fundamental termination circuit 709. In this way, the inductance of the different termination circuits may be tuned to increase the linearity and/or PAE of the power amplifier module 696. This may include matching the impedance of the fundamental frequency of the signal at the node in output fundamental termination circuit 709 and terminating with a phase corresponding to the harmonic frequency of the signal at the node in output harmonic termination circuit 711. The effective capacitances of the different termination circuits may also be configured separately and independently of each other. Since different termination circuits may be included in different signal paths, changes to either termination circuit may not affect the other termination circuit.

The conductive traces can couple interconnects (e.g., wire bonds) in series with one or more capacitive circuit elements (e.g., capacitors) in the output matching network illustrated in fig. 63A. The effective capacitance of the termination circuit may be selected so as to prevent reflection of a desired frequency component of the signal on the signal path at the output pin 721 that is different from the desired frequency component of the signal for which the output base termination circuit 709 is configured to prevent reflection. In a particular implementation, different termination circuits may include different conductive traces on the substrate 697 that may add inductance and/or capacitance to the respective termination circuits. The different conductive traces may be configured separately and independently of each other such that each conductive trace may provide a desired termination at a selected frequency. The effective inductance and effective capacitance of the termination circuit may be configured in combination with each other in order to increase the linearity and/or PAE of the power amplifier module 696.

FIG. 63B illustrates an example substrate 697, according to a specific embodiment of the invention. The substrate 697 can be a package substrate, such as a laminate substrate. The substrate 697 may be included in any of the modules discussed herein, such as the power amplifier module 696. The substrate 697 is configured to receive a plurality of components and includes conductive traces. The dashed lines in fig. 63B illustrate regions where the substrate 697 is configured to receive components. For example, as illustrated, the substrate 697 is configured to receive a power amplifier module 698 and a plurality of surface mount capacitors 726, 727 and 728. The illustrated substrate 697 also includes a first conductive trace 723 and a second conductive trace 724. As illustrated in fig. 63B, a separation 720 separates the first conductive trace 723 from the second conductive trace 724. The separation 720 may physically separate the first conductive trace 723 from the second conductive trace 724 at any suitable point to be applied. Thus, the first conductive trace 723 and the second conductive trace 724 are part of different signal paths on the substrate 697.

Substrate 697 can be configured to implement at least a portion of the termination circuit discussed herein. For example, the first conductive trace 723 may be included in a load line configured to match an impedance at an output node of the power amplifier die 698 at a fundamental frequency of the power amplifier output signal. As illustrated, the substrate 697 is also configured to receive a surface mount capacitor 726 that is part of the load line. The second conductive trace 724 may be included in a harmonic termination circuit separate from the load line. The harmonic termination circuit may be configured to terminate with a phase corresponding to a harmonic frequency of the power amplifier output. As illustrated, the second conductive trace 724 is configured to receive one or more surface mount capacitors 727 and 728 that are part of the harmonic termination circuit.

Fig. 64A, 64B, and 64C show simulation results comparing the performance of the power amplifier module 696 of fig. 63A with a conventional power amplifier with a single termination circuit. As shown in fig. 64A, the PAE is increased by about 2% to 3% in one embodiment of the power amplifier module 696 of fig. 63A compared to conventional designs over a frequency range of 1850MHz to 1910 MHz. Furthermore, in some simulations, the PAE has increased by 5% or more than 5%, according to the principles and advantages described herein. An increase in the PAE of the system may, for example, increase the amount of time a battery powering the system is discharged.

Fig. 64B shows the improvement in linearity as measured by the Adjacent Channel Power Ratio (ACPR) in one embodiment of the power amplifier module 696 of fig. 63A compared to a conventional design. As illustrated in FIG. 64B, ACPR is improved by about 2dB to 3dB over a frequency range of 1850MHz to 1910 MHz. Fig. 64A and 64B collectively show that the power amplifier system of fig. 63A can improve both PAE and ACPR simultaneously.

Figure of merit (FOM) is one way to characterize the overall quality of a power amplifier. Fig. 64C shows that over a frequency range of 1850MHz to 1910MHz, the FOM is increased from about 86 to about 90 in one embodiment of the power amplifier module 696 of fig. 63A, as compared to a conventional design. Further, in some implementations, the FOM has increased from about 82 to about 90 according to one or more of the principles and advantages described herein.

Moreover, an increase in PAE, ACPR, FOM, or any combination thereof has been demonstrated at a number of other frequency bands (e.g., 1710MHz to 1780 MHz). The analog data indicates that separate termination circuits for fundamental and harmonic frequency components of the signal can add PAE, ACPR, FOM, or any combination thereof, over multiple frequencies in the RF spectrum and other spectra. Additionally, improvements in PAE, ACPR, FOM, or any combination thereof have been shown within different power levels.

Referring to FIG. 65, a block diagram illustrating a die and an example termination circuit in accordance with another embodiment will be described. FIG. 65 illustrates that any suitable number of separate termination circuits can be implemented based on the desired application. Further, fig. 65 illustrates that multiple separate termination circuits can be implemented at multiple nodes within an electronic system, such as input pin(s) of a die and/or output pins of a die. Although fig. 65 illustrates a plurality of separate termination circuits at input pins of a die and output pins of the die, any combination of features of the separate termination circuits described herein may be applied to signals at other nodes of an electronic system, for example, within a die (e.g., a power amplifier die). Further, at least a portion of one or more of the separate termination circuits coupled to the nodes may be embodied within the die, according to a particular implementation. In some of these implementations, one or more of the separate termination circuits coupled to the node may be embodied external to the die.

As shown in fig. 65, electronic system 732 may include a die 733 and a plurality of termination circuits 743 and 747. Electronic system 732 may be included, for example, in the wireless device of fig. 61A or 61B, the power amplifier module of 61C, and the like, or any combination thereof. In some implementations, die 733 can be a power amplifier die 698. In other implementations, die 733 can include, for example, a frequency multiplier, mixer, or the like.

The die 733 may include a plurality of input pins 734 a-734 n and/or output pins 738 a-738 n. Separate termination circuits including any combination of the features described herein may be coupled to different pins and/or different groups of two or more pins. For example, the input termination circuits 743 a-743 n may each be configured to prevent reflection of different frequency components of signals at nodes coupled to one or more input pins of the die 733. Input termination circuits may be coupled to input pins 734 a-734 n, respectively, of die 733, as shown. In some implementations, the input termination circuit can be coupled to two or more input pins 734 of the die 733. Alternatively or additionally, two or more input termination circuits may be coupled to a single pin of die 733. Similarly, output termination circuits 747 a-747 n may each be configured to block reflection of different frequency components of signals at nodes including one or more output pins. Output termination circuitry may be coupled to output pins 738 a-738 n, respectively, of die 733. In some implementations, output termination circuitry can be coupled to two or more output pins 738 of die 733. Alternatively or additionally, two or more output termination circuits may be coupled to a single pin of die 733.

Any suitable number of input pins 734 a-734 n and/or output pins 738 a-738 n may be included on die 733. Further, any suitable number of input termination circuits 743 a-743 n and/or output termination circuits 747 a-747 n may be included in electronic system 732. In some implementations, the number of separate input termination circuits 743 a-743 n and/or separate output termination circuits 747 a-747 n may be selected based on the desired number of harmonic frequency components to be terminated.

FIG. 66 is a flow chart of an illustrative method 752 of manufacturing a module in accordance with yet another embodiment. It should be understood that any of the methods discussed herein may include more or fewer operations, and the operations may be performed in any order as desired. Further, one or more acts of the method may be performed in series or in parallel. For example, the actions at blocks 754 and 756 of method 752 may be performed serially or in parallel. The method 752 may be performed as part of manufacturing any of the modules discussed herein, such as the power amplifier module 696.

At block or step 753, a die can be attached to a substrate. For example, the power amplifier die 698 may be attached to the package substrate 697.

At block or step 754, a first interconnect can be formed between the die and the first conductive trace on the substrate. The first interconnect may be coupled to one or more output pins of the die. The first interconnect can include, for example, one or more wire bonds and/or one or more bumps. In a particular implementation, the first interconnect can include a wire bond bonded to a pad of the die. According to some of these embodiments, the wire bond may also be bonded to a surface treatment plating of the substrate. The first interconnect may be included in a first termination circuit configured to match an impedance of a fundamental frequency of an output signal of the die.

At block 756, a second interconnect can be formed between the die and the second conductive trace on the substrate. The second interconnect may be coupled to one or more output pins of the die. The second interconnects may include, for example, one or more wire bonds and/or one or more bumps. In a particular implementation, the second interconnects may include wire bonds bonded to pads of the die. According to some of these embodiments, the wire bond may also be bonded to a surface treatment plating of the substrate. The second interconnect may be included in a second termination circuit configured to terminate with a phase corresponding to a harmonic of the amplified output signal.

D. Applications of

Some of the embodiments described above in this section have provided examples in connection with wireless devices that include power amplifiers. However, the principles and advantages of the embodiments may be used in any other system or apparatus that requires two or more separate termination circuits configured to prevent reflections of two or more different frequency components of a signal. For example, a separate termination circuit may be implemented along with a multiplier (e.g., a frequency multiplier) and/or mixer instead of a power amplifier. As another example, separate termination circuits may be implemented at any point on the signal path where separate termination circuits for two or more different frequency components (e.g., fundamental frequency components and harmonic frequency components) are desirable.

Systems implementing one or more aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, portions of consumer electronics, electronic test equipment, any such similar products and equipment. More specifically, an electronic device configured to implement one or more aspects of the present disclosure may include, but is not limited to, an RF transmitting device, any portable device with a power amplifier, a mobile phone (for example, a smart phone), a telephone, a base station, a femto cell, a radar, a device configured to communicate according to a wireless fidelity standard, a television, a computer monitor, a computer, a handheld computer, a tablet computer, a laptop computer, a Personal Digital Assistant (PDA), a microwave, a refrigerator, an automobile, stereos, DVD players, CD players, VCRs, MP3 players, radios, camcorders, cameras, digital cameras, portable memory chips, washers, dryers, washer/dryers, copiers, facsimile machines, scanners, multifunction peripherals, wristwatches, and clocks, to name a few specific such devices. A portion of a consumer electronic product may include a multi-chip module, a power amplifier module, an integrated circuit including two or more termination circuits, a package substrate including one or more circuit elements, and so forth. Further, other examples of electronic devices may also include, but are not limited to, memory chips, memory modules, circuits for optical networks or other communication networks, and disk drive circuits. Further, the electronic device may contain unfinished products.

X. transmission line for high performance radio frequency applications

This section of the invention relates to a transmission line for high performance Radio Frequency (RF) applications. One such transmission line may include a bonding layer configured to receive an RF signal, a barrier layer, a diffusion barrier layer, and a conductive layer proximate to the diffusion barrier layer. The diffusion barrier layer may have a thickness that allows a received RF signal to penetrate the diffusion barrier layer to the conductive layer. In a particular embodiment of the invention, the diffusion barrier layer may be nickel. In some of these implementations, the emission line may include a gold bonding layer, a palladium barrier layer, and a nickel diffusion barrier layer. As indicated above, these aspects of the invention may be combined with other aspects of the invention to further improve the performance of the power amplifier module and the device in which the power amplifier module is used.

As generally described, aspects of the present invention relate to Radio Frequency (RF) transmission lines that include a diffusion barrier layer. The diffusion barrier layer may comprise a material and have a thickness such that contaminants are prevented from diffusing through the diffusion barrier layer. The thickness of the diffusion barrier layer may be sufficiently small such that RF signals penetrate the diffusion barrier layer and propagate in the conductive layer. For example, the thickness of the diffusion barrier layer may be less than the skin depth of the material at frequencies in the RF range (e.g., at a frequency selected from a range of about 0.45GHz to 20 GHz). In some implementations, the diffusion barrier layer can be nickel. According to some of these embodiments, the nickel diffusion barrier layer may have a thickness selected from a range of about 0.04um to 0.5 um. The RF transmission line may also include a bonding layer, a barrier layer for preventing contaminants from entering the bonding layer, and a conductive layer in which the RF signal propagates.

Particular implementations of the subject matter described in this section of the disclosure can be implemented to realize one or more of the following potential advantages, as well as other advantages. Using one or more features of the systems, apparatus, and methods described herein, an electronic system, such as a system including a power amplifier and/or a system configured to transmit and/or receive Radio Frequency (RF) signals, may operate more efficiently and/or consume less power. Alternatively or additionally, the signal quality of the RF signals in such systems may be improved. In some implementations, the amount of gold used to implement the emitter line can be reduced without significantly degrading electrical performance. In fact, according to particular implementations, simulation and experimental data indicate that the amount of gold used on the emitter line may be reduced and electrical performance may be improved.

The transmission line may be embodied on a package substrate or Printed Circuit Board (PCB) which may include a multilayer laminate. Multilayer laminated PCBs or package substrates are widely used in the RF industry. Most RF blocks, such as Low Noise Amplifiers (LNAs), mixers, Voltage Controlled Oscillators (VCOs), filters, switches, and all transceivers, may be implemented using semiconductor technology.

However, in an RF module (e.g., an RF front end module including power amplifiers, switches, filters, etc., or any combination thereof), single chip integration may be impractical due to the different blocks being implemented in different semiconductor technologies. For example, the power amplifier may be formed by a GaAs process, while the associated control and/or bias circuitry may be formed by a CMOS process. Electromagnetic interaction can degrade the electrical performance of the blocks, which can cause the system to fail electrical performance specifications. One reason for implementing RF modules in more than one chip is that on-chip passive devices, such as long-emitting rays, inductors, baluns (ba1un), transformers, etc., or any combination thereof, may have low Q factors and/or may consume large chip area. Thus, multi-chip module (MCM) and/or System In Package (SiP) assembly techniques may be used to achieve low cost, small size, and/or high performance in RF module applications.

Lamination techniques may be used for MCM assembly for cost effectiveness and/or conductor performance considerations. The lamination technique may include copper for use in the transmission line. The use of copper to propagate an electrical signal may be desirable due to the physical properties of copper. High Q transmission lines, inductors, transformers, and the like, or any combination thereof, may be implemented on the laminate substrate. For example, a power amplifier module, an output matching network, a harmonic filter, a coupler, etc., or any combination thereof, may be coupled to the laminate substrate. Conductor losses can have a significant impact on the performance of any of these elements. Therefore, lamination plating techniques can significantly affect RF losses.

The copper traces on the outer layer of the laminate may be covered with a solder mask, oxide, or other suitable material in areas where interconnections to external components are not desired. These interconnects may include solder joints for components and/or wire bond connections to the die. In the areas where solderability and/or wire bondability is preserved, the copper traces may be covered with an Organic Solderability Preservative (OSP) or a surface treatment plating. The metallurgical and/or metallic layer thickness of the surface treatment coating may depend on the function of the exposed region (e.g., the solder surface and/or the wire bond surface). The inert oxide-free surface may maintain solderability and/or wire bondability.

Such metallurgies for surface treating the plating typically include a diffusion barrier to prevent copper from diffusing to the plated surface and subsequently oxidizing during assembly due to exposure to air and/or elevated temperatures. Depending on the chemistry used, the diffusion barrier may be, for example, electroplated nickel (Ni) or electroless Ni (p). Conventionally, nickel having a thickness of about 2.5um to about 8um has been established as a sufficiently thick diffusion barrier layer of the laminate substrate to maintain solderability during thermal excursions encountered during MCM and/or SiP assembly. For gold (Au) wire bonding, electrolytic or electroless Au may be used to form a gold bonding layer having a thickness selected in the range from about 0.4um to 0.9 um. However, a thinner Au-impregnated layer over Ni typically does not provide a reliable Au wire bonding surface in high-throughput assembly operations. Electroless Ni/electroless palladium (Pd)/immersion Au have become available for soldering and wire bonding, including Au wire bonding. This can be a cost effective surface treatment layer due to the reduction in Au thickness. Electroless Ni/electroless Pd/immersion Au can increase conductor loss in exposed (surface treated plated) areas, especially at higher frequencies.

Electrolytic or electroless NiAu or NiPdAu plating techniques are currently used with laminated substrates. Electroless NiPdAu has been successfully implemented, although having relatively lossy electrical characteristics. While having higher cost due to thicker gold, some RF modules still use electrolytic or electroless NiAu with lower loss to achieve module performance, especially at higher frequencies (e.g., at frequencies above about 1.9GHz or 1.9 GHz).

A. Transmitting line

Reference is now made to FIG. 67A, which illustrates a cross-section of emission line 757, according to some embodiments of the invention. The cross-section shown in FIG. 67A may represent a cross-section of some or all of the portions of emission line 757. Emitter line 757 can include bonding layer 758, barrier layer 759, diffusion barrier layer 761, and conductive layer 762. The transmit line 757 may be implemented in an RF circuit and configured for transmitting an RF signal. The emission line 757 may be embodied on a laminate substrate. According to some implementations, the bonding layer 758, barrier layer 759, and diffusion barrier layer 761 can be considered surface treatment platings and the conductive layer 762 can be considered a conductive line. In some embodiments, the transmission line 757 can be at least about 5um, 10um, 15um, 20um, 25um, 50um, 75um, 100um, 250um, or 500um long.

In a particular implementation, the emission line 757 can include a gold bonding layer, a palladium barrier layer, a nickel diffusion barrier layer, and a copper conductive layer. For example, in some of these implementations, the emission line 757 may include: a gold bonding layer having a thickness of about 0.1 um; a palladium barrier layer having a thickness of about 0.1 um; a nickel diffusion barrier layer having a thickness selected from a range of about 0.04um to 0.5 um; and a copper conductive layer having a thickness of about 20 um. The surface treatment plating of the transmission line 757 may be formed by electroless nickel plating over the copper conductive layer, electroless palladium plating over nickel, and immersion gold plating over palladium. Other suitable processes and/or sub-processes for forming the surface treatment coating of such an emission line may alternatively be implemented. For example, a nickel diffusion barrier layer may be electroplated over a copper conductive layer.

While in a particular implementation, the emitter line 757 includes a gold bonding layer, a palladium barrier layer, a nickel diffusion barrier layer, and a copper conductive layer, it is understood that other materials may alternatively be used to implement one or more layers of the emitter line 757.

The bonding layer 758 of the emission line 757 may have a bonding surface configured for soldering and/or wire bonding. Bonding layer 758 may be configured to receive RF signals at a bonding surface. According to some embodiments, the pins of the die may be bonded to the bonding surface of the bonding layer 758. For example, the output of the power amplifier die may be bonded to the bonding surface of bonding layer 758 and transmitted to one or more RF components (e.g., filters and/or RF switches) via transmission line 757. The bonding layer 758 may comprise gold. In some embodiments, the thickness of the gold bonding layer may be selected from the range of about 0.05um to 0.15 um. According to a particular embodiment, the gold bonding layer may be about 0.1um thick.

The barrier layer 759 of the emitter line 757 may prevent contaminants from entering the bonding layer 758. The barrier layer 759 may be close to the bonding layer 758. In the orientation of fig. 67A, bonding layer 758 is disposed over barrier layer 759. In some implementations, a major surface of barrier layer 759 can directly contact a major surface of bonding layer 758, for example, as shown in fig. 67A. As illustrated in fig. 67A, barrier layer 759 may be between bonding layer 758 and diffusion barrier layer 761. Barrier layer 759 can include palladium. In some implementations, the thickness of the palladium barrier layer can be selected from a range of about 0.03um to 0.15 um. According to a particular implementation, the palladium barrier layer may be about 0.1um thick.

The diffusion barrier layer 761 of the emission line 757 may be configured to prevent contaminants from entering the bonding layer 758 and/or the barrier layer 759. For example, in some implementations, the diffusion barrier layer 761 can prevent copper from the copper conductive layer from diffusing to the gold bonding layer. The diffusion barrier layer 761 can provide an adhesive surface for the conductive layer 762. According to a particular implementation, the adhesion surface of the diffusion barrier layer 761 may be adhered to a copper conductive layer.

The diffusion barrier layer 761 may have a thickness that is sufficiently small so as to allow RF signals to propagate in the conductive layer 762. For example, the thickness of the diffusion barrier layer 761 may be less than the skin depth of the diffusion barrier layer 761 at frequencies in the RF range (e.g., at frequencies selected from a range of about 0.9GHz to 20 GHz). This may allow the RF signal to penetrate the diffusion barrier layer 761. In the case of a diffusion barrier layer 761 of a material and having a thickness less than the skin depth of the material at the desired frequency in the RF range, substantially all of the RF signal should travel in conductive layer 762 of transmission line 757, provided that the RF signal also penetrates bonding layer 758 and barrier layer 759. To allow RF signals to penetrate through the bonding layer 758, the thickness of the bonding layer 758 may be less than the skin depth of the material forming the bonding layer 758 at a desired frequency in the RF range. Similarly, to allow RF signals to penetrate barrier layer 759, the thickness of barrier layer 759 may be less than the skin depth of the material forming barrier layer 759 at a desired frequency in the RF range.

A diffusion barrier layer 761 may be between the bonding layer 758 and the conductive layer 762. In the orientation of fig. 67A, the barrier layer 759 is disposed over the diffusion barrier layer 761 and the diffusion barrier layer 761 is disposed over the conductive layer 762. In some implementations, a major surface of diffusion barrier layer 761 can directly contact a major surface of barrier layer 759 and/or conductive layer 762, for example, as shown in fig. 67A.

The diffusion barrier layer 761 may comprise nickel. In some implementations, the diffusion barrier layer 761 can be nickel. The nickel diffusion barrier layer may also prevent copper from the conductive layer from diffusing to the gold bonding layer. The thickness of the nickel barrier layer may be less than the skin depth of nickel at frequencies in the RF range. For example, the thickness of the nickel may be less than the skin depth of nickel at a frequency selected from the range of about 0.45GHz to 20 GHz. This may allow RF signals to penetrate through the diffusion barrier layer 761 to the conductive layer 762. According to some embodiments, the thickness of the nickel diffusion layer may be less than the skin depth of nickel at about 0.3GHz, 0.35GHz, 0.4GHz, 0.45GHz, 0.5GHz, 0.6GHz, 0.7GHz, 0.8GHz, 0.9GHz, 1GHz, 2GHz, 5GHz, 6GHz, 10GHz, 12GHz, 15GHz, or 20 GHz. When an alternative material is used for the diffusion barrier layer in place of nickel, the thickness of this diffusion barrier layer may be less than the skin depth of the alternative material at about 0.3GHz, 0.35GHz, 0.4GHz, 0.45GHz, 0.5GHz, 0.6GHz, 0.7GHz, 0.8GHz, 0.9GHz, 1GHz, 2GHz, 5GHz, 6GHz, 10GHz, 12GHz, 15GHz, or 20 GHz.

In some implementations, the thickness of the nickel diffusion barrier layer can be less than about 2um, 1.75um, 1.5um, 1.25um, 1um, 0.95um, 0.9um, 0.85um, 0.8um, 0.75um, 0.7um, 0.65um, 0.6um, 0.55um, 0.5um, 0.45um, 0.4um, 0.35um, 0.3um, 0.25um, 0.2um, 0.15um, 0.1um, 0.09um, 0.05um, or 0.04 um. In particular implementations, the thickness of the nickel diffusion barrier layer may be selected from one of the following ranges: about 0.04um to 0.7um, about 0.05um to 0.7um, about 0.1um to 0.7um, about 0.2um to 0.7um, about 0.04um to 0.5um, about 0.05um to 0.5um, about 0.09um to 0.5um, about 0.04um to 0.16um, about 0.05um to 0.15um, about 0.1um to 0.75um, about 0.2um to 0.5um, about 0.14um to 0.23um, about 0.09um to 0.21um, about 0.04um to 0.2um, about 0.05um to 0.5um, about 0.15um to 0.5um, or about 0.1um to 0.2 um. As one example, the thickness of the nickel diffusion barrier layer may be about 0.1 um. In all of these illustrative embodiments, the nickel diffusion barrier layer has a non-zero thickness.

The RF signal may propagate in the conductive layer 762 of the transmission line 757. For example, an RF signal may penetrate bonding layer 758, barrier layer 759, and diffusion barrier layer 761 to propagate in conductive layer 762. Substantially all of the RF signal may propagate in the conductive layer 762 of the transmission line 757. The conductive layer 762 may be adhered to an adhesion surface of the diffusion barrier layer 761. Conductive layer 762 may include any suitable material for propagating RF signals along transmission line 757. For example, the conductive layer may include copper, aluminum, silver, and the like, or any combination thereof. In a particular implementation, the conductive layer 762 may be copper. According to particular embodiments, the thickness of the conductive layer 762 may be selected from the range of about 10um to 50 um. In some of these embodiments, the thickness of the conductive layer may be selected from the range of about 15um to 30 um.

FIG. 67B schematically illustrates the example emission line of FIG. 67A. According to a particular implementation, the transmit lines 757 may include more than one transmit line 757 used to transmit RF signals from one node to another node. For example, the emission lines 757 illustrated in FIG. 67B may collectively implement the emission lines 757 of FIG. 69. The transmission line 757 in fig. 67B functions as a transmission line for transmitting an RF signal from the first node RFIN to the second node RF_OUTThe medium of (1). One or more transmit lines 757 may have one end coupled to a power rail, such as power (e.g., Vcc) or ground. As illustrated, the respective emission lines 757 may be via a capacitor C₁、C₂Or C₃Coupled to ground.

B. Skin depth calculation

As mentioned earlier, the diffusion barrier layer 761 of the transmission line 757 may comprise a material and have a thickness sufficiently small so as to allow RF signals to propagate in the conductive layer. Thus, the diffusion barrier layer 761 may have a thickness that is less than the skin depth of the material at the desired frequency. The skin depth can be represented by equation 5.

In equation 5, the skin depth, μ in meters can be expressed_oCan represent a value of 4 π × 10^-7Henry/meter (about 1.2566370614X 10)^-6Henry/meter), μ _rMay represent the relative permeability of the medium, ρ may represent the resistivity of the medium in Ω m (which may be equal to the reciprocal conductivity of the medium), and f may represent the frequency of the current propagating through the medium in Hz.

Table 2 below contains the plating thicknesses of the various layers of the three emission lines. The data in table 2 correspond to an emission line with a NiAu surface finish plating and two different emission lines with a NiPdAu surface finish plating comprising different nickel layer thicknesses. One of the emission lines with the NiPdAu surface treatment plating has a nickel thickness of 5um and the other emission line with the NiPdAu surface treatment plating has a nickel thickness of 0.1 um. A nickel thickness of 5um is within the range of acceptable nickel thicknesses that have been conventionally used (for example, from 2.5um to 8 um). In all three transmission lines corresponding to the data in table 2, the conductive layer was copper. The emission line with the NiPdAu surface treatment plating may have a cross section as shown in fig. 67A. The emission line with the NiAu surface treatment plating may have a cross section similar to fig. 67A (without barrier layers 759) with a gold layer bonding layer directly over the nickel diffusion barrier layer and a nickel layer directly over the copper conductive layer.

	NiPdAu(um)	Thin "Ni" -NiPdAu (um)	NiAu(um)
				Cu	21	21	21
Ni	5	0.1	5
				Pd	0.09	0.09	---
Au	0.1	0.1	0.4

TABLE 2 coating thickness

The skin depth of these three emission lines may be calculated using equation 5 and the material properties included in table 3 below. The relative permeability of nickel may vary depending on the process used to form the nickel layer. For example, the phosphorous content in an electroless nickel plating process can affect the relative permeability of nickel. The range of nickel permeability listed in table 3 may capture a typical range of nickel permeability.

	Resistivity, p (μ Ω -cm)	μr
			Cu	1.673	1
Ni	8.707	100 to 600
			Pd	10.62	1
Au	2.44	1

TABLE 3 Material Properties

The calculated skin depths for copper, nickel, palladium, and gold at six different frequencies in the RF range are shown in table 4 below.

TABLE 4 calculated skin depth

The data shown in table 4 indicates that most of the signals having frequencies of.045 GHz, 0.9GHz, 1.9GHz, 5GHz, 12GHz, or 20GHz should travel in nickel in the transmission line with NiAu surface treatment plating. Since the thickness of gold (i.e., 0.4um) is less than the skin depth of gold (i.e., 3.70um at 0.45GHz, 2.62um at 0.9GHz, 1.8um at 1.9GHz, 1.11um at 5GHz, 0.72um at 12GHz, and 0.56um at 20 GHz), and the thickness of nickel (i.e., 5um) is greater than the skin depth of nickel (i.e., 0.29um to 0.7um at 0.45GHz, 0.2um to 0.5um at 0.9GHz, 0.14um to 0.34um at 1.9GHz, 0.09um to 0.21um at 5GHz, 0.06um to 0.14um at 12GHz, and 0.04um to 0.11um at 20 GHz), the gold layer should travel in both the gold layer and the nickel signal at 0.45GHz, 0.9GHz, 1.9GHz, 12GHz, and 20 GHz. Since the thickness of nickel is greater than the skin depth in the frequency range from about 0.45GHz to 20GHz, signals in the frequency range should not penetrate the nickel layer. Since the skin depth should be small at higher frequencies, signals at frequencies greater than 20GHz should not penetrate the nickel layer yet. Since the thickness of gold (i.e., 0.4um) in an emission line having a NiAu surface treatment plating is thicker than the thickness (i.e., 0.1um) in an emission line having a NiPdAu surface treatment plating including a nickel thickness of 5um, relatively more signals are conducted in the NiAu emission line than the NiPdAu emission line having nickel of 5um in gold-to-nickel, thereby making the NiAu emission line less lossy compared to.

The data shown in table 4 also indicates that most of the signals with frequencies of 0.45GHz, 0.9GHz, 1.9GHz, 5GHz, 12GHz, or 20GHz should travel in nickel in an emission line with a NiPdAu surface treatment plating comprising a nickel thickness of 5 um. Since the thickness of gold (i.e., 0.1um) and the thickness of palladium (0.09um) are both less than their respective skin depths (i.e., 3.70um at 0.45GHz, 2.62um at 0.9GHz, 1.8um at 1.9GHz, 1.11um at 5GHz, 0.72um at 12GHz, and 0.56um at 20GHz for gold; 7.73um at 0.45GHz, 5.47um at 0.9GHz, 3.76um at 1.9GHz, 2.32um at 5GHz, 1.50um at 12GHz, and 1.16um at 20GHz for palladium), and the thickness of nickel (i.e., 5um) is greater than the skin depth of nickel (i.e., 0.29um to 0.7um at 0.45GHz, 0.2 to 0.9GHz, 0.5 to 0.04um at 0.09 to 0.14um at 0.06um at 0.9 GHz), most of the signals at 0.45GHz, 0.9GHz, 1.9GHz, 5GHz, 12GHz or 20GHz should therefore travel in nickel. Since the thickness of nickel is greater than the skin depth at a frequency range from about 0.45GHz to 20GHz, signals in the frequency range should not penetrate the nickel layer. Since the skin depth should be small at higher frequencies, signals at frequencies greater than 20GHz should not penetrate the nickel layer yet. Therefore, most of the RF signal electrically coupled to the NiPdAu emission line having a nickel thickness of 5um via the gold bonding surface should propagate in the nickel.

In contrast, the data shown in table 4 indicate that most of the signals with frequencies of 0.45GHz, 0.9GHz, 1.9GHz, 5GHz, 12GHz, or 20GHz should travel in copper in an emission line with a NiPdAu surface treatment plating comprising a nickel thickness of 0.1 um. Since the thickness of gold, palladium, and nickel are each less than their respective skin depths, most of the signals at 0.45GHz, 0.9GHz, 1.9GHz, 5GHz, 12GHz, or 20GHz should penetrate to copper. Since the skin depth is small at higher frequencies, signals at frequencies greater than 20GHz should also penetrate to the copper. Therefore, most of the RF signal electrically coupled to the NiPdAu emission line with 0.1um nickel thickness via the gold bonding surface should propagate in the copper.

As shown in table 3, copper has a resistivity that is about one-fifth the resistivity of nickel. Therefore, when transmitting signals at a frequency of 0.45GHz or above 0.45GHz, an emission line having a NiPdAu surface treatment plating including a nickel thickness of 0.1um should have a minimum resistance loss of three emission lines corresponding to the data in tables 1 and 3. The data in table 4 also indicates that a signal having a frequency of 20GHz may penetrate nickel having a thickness less than 0.11um, a signal having a frequency of 12GHz may penetrate nickel having a thickness less than 0.14um, a signal having a frequency of 5GHz may penetrate nickel having a thickness less than 0.2um, a signal having a frequency of 1.9GHz may penetrate nickel having a thickness less than 0.34um, a signal having a frequency of 0.9GHz may penetrate nickel having a thickness less than 0.5um, and a signal having a frequency of 0.45GHz may penetrate nickel having a thickness less than 0.7 um. Therefore, these signals should propagate in copper in an emission line with a NiPdAu surface treatment plating comprising a nickel thickness of 0.1um, provided that the gold thickness and the palladium thickness are less than the skin depth at the respective frequencies of the signals. Based on equation 5 and the data in tables 2 and 3, signals having frequencies up to about 22GHz should be able to penetrate to nickel having a thickness of about 0.1 um.

C. Wire bonding

In some implementations, the transmission line 757 can be electrically coupled to the lead of the die via a wire bond. A conductor (e.g., a wire) may provide the RF signal to the transmission line 757. Fig. 68A illustrates an example of a wire bonded to the transmission line 757 of fig. 67A. As illustrated in fig. 68A, the emission lines 757 can be included on a substrate 772. Die 774 may also be coupled to substrate 772. Wire 763 may electrically connect the bonding surface of bonding layer 758 of emitter 757 to die 774. In this manner, transmission line 757 may receive an RF signal at the bonding surface of bonding layer 758. The wire 763 can include a ball joint 764, a neck 766, a pull wire 767, a root 768, a suture joint 769 (or alternatively a wedge joint), or any combination thereof.

Some wire bonding specifications dictate that the wire 763 should have a minimum tensile strength without experiencing a particular failure or failures. For example, in some applications, wire bonding specifications dictate that the wire should have a tensile strength of at least 3g and a seamless wire pull failure mode after heat exposure (e.g., reflow or bake at 175 ℃ for 12 hours).

Experimental data was collected for 20um thick Au and 20um thick Cu wires. The Au wires were tested in three different emission lines including an emission line with a NiAu surface treatment plating and two different emission lines with NiPdAu surface treatment plating including different nickel layer thicknesses (5um and 0.1 um). Cu wires were tested in three different emission lines including an emission line with a NiAu surface treatment plating and two different emission lines with NiPdAu surface treatment plating including different nickel layer thicknesses (5um and 0.1 um). The surface treatment plating corresponds to the values shown in table 2 for NiAu and NiPdAu. Sample conditions for the experiment included standard assembly processes (surface mount adhesion and plasma) prior to wire bonding and extreme heat exposure to test Cu diffusion affecting wire bondability through the Ni diffusion barrier layer (surface mount adhesion and bake and plasma). Experimental data for the standard assembly process indicate that, depending on the wire diameter, all Au wires should exceed the 3g to 4g tensile strength specification after heat exposure. Experimental data from standard assembly processes also indicate that most Cu wires should exceed the 3g to 4g tensile strength specification, but the process parameters are not optimized. All wire pulls tested under extreme heat exposure met or exceeded the 3g pull strength specification and no-wire pull failure mode criteria. Thus, experimental data confirm the feasibility of wire bonding for NiPdAu surface treatment platings with a thickness of 0.1umNi for MCM.

D. Substrate and array

Fig. 68B illustrates an example of a substrate 772 including the emission line 757 of fig. 67A. The substrate 772 may include one or more emission lines 757. The substrate 772 may include any combination of features of the substrates described herein. For example, the substrate 772 can be a laminated substrate including a NiPdAu surface treatment plating.

Multiple substrates 772 can be fabricated at the same time with the same processing equipment. Fig. 68C illustrates an example of an array 773 including the plurality of substrates 772 of fig. 68B. In some implementations, the array 773 can be a laminated panel including a substrate 772 with transmit lines 757 configured for transmitting RF signals. Although the array 773 shown in fig. 68C includes twenty-five substrates 772, in other implementations, the array 773 can include any suitable number of substrates 772. For example, the emission lines 757 may be formed on the plurality of substrates 772 in a process that includes any combination of the features of the surface treatment plating techniques described herein. The individual substrates 772 may then be separated from one another after the formation of the emission lines 757, for example, by laser cutting, diamond sawing, or any other suitable method.

E. Electroplating technique

The NiPdAu electroplating technique with 0.1um nickel thickness can reduce cost. This electroplating technique may also improve RF performance or have minimal RF performance impact. As the data and calculations discussed earlier indicate, in NiPdAu plating with 0.1um nickel thickness, the amount of RF signal traveling in the gold, palladium, and nickel layers can be reduced and RF energy can be increased and/or maximized in conductive layers (e.g., copper layers) on the laminate while maintaining solderability and/or wire bondability. Other experimental data indicate that the no-surface-treatment plating (with all signals traveling in the copper layer) provides the lowest insertion loss.

One example of a NiPdAu electroplating technique is electroless NiPdAu. For electroless NiPdAu, if the nickel layer is thicker than the skin depth at the frequency of the RF signal, the signal cannot penetrate through the nickel layer, for example, as indicated by the calculations and data discussed earlier. If the nickel thickness is reduced to less than the skin depth of nickel (for example, to about 0.1um), the RF signal can penetrate through the nickel, palladium, and gold plating. Therefore, a major portion of the RF signal energy should be in the copper layer. Copper has substantially lower RF losses compared to gold, palladium and nickel. The RF in an emission line having a NiPdAu surface treatment plating comprising 0.1um thick nickel may be less than the RF loss in comparable emissions by means of electrolytic and/or electroless NiAu surface treatment plating. Thus, the overall electrical performance can be improved by surface treating the plating with NiPdAu with 0.1um thick nickel. In some implementations, the output matching network loss can be reduced from about 0.8dB to 0.5dB at 1.9GHz, which can improve PA power added efficiency by about 3%. This can translate into significant yield improvement and/or an increase in competitiveness of products including NiPdAu surface treatment plating with 0.1um thick nickel.

Experimental data was gathered for RF loss characteristics with two different impedances (6 ohms and 4 ohms) in the output matching network. Experimental data indicate that the loss is improved by about 0.2dB for a 6 ohm output matching network. Experimental data indicate that the loss is improved by about 0.3dB for a 4 ohm output matching network. An emission line comprising an electroless NiPdAu surface treatment plating having 0.1um Ni has lower losses than a comparable emission line or an electroless NiAu emission line having a standard electroless NiPdAu comprising 5um Ni.

F. Module

FIG. 69 is a schematic block diagram of a module 770 that may include the transmit line 757 of FIG. 67A. In some implementations, the module 770 may be referred to as a multi-chip module and/or a power amplifier module. The module 770 may include a substrate 772 (e.g., a package substrate), a die 774 (e.g., a power amplifier die), a matching network 775, and the like, or any combination thereof. Although not illustrated, in some implementations, the module 770 can include one or more other dies and/or one or more circuit elements coupled to the substrate 772. For example, the one or more other dies may include a controller die that may include a power amplifier bias circuit and/or a direct current/direct current (DC/DC) converter. For example, example circuit elements mounted on a package substrate may include inductors, capacitors, impedance matching networks, and the like, or any combination thereof.

The module 770 may include a plurality of dies and/or other components mounted on and/or coupled to a substrate 772 of the module 770. In some implementations, the substrate 772 can be a multi-layer substrate configured to support the die and/or components and provide electrical connectivity to external circuitry when the module 770 is mounted on a circuit board (e.g., a phone board). The substrate 772 can include a laminate having a surface treatment coating, for example, including any combination of the features of the laminate and/or surface treatment coating described herein. The substrate 772 may provide electrical connectivity between components via the emission line 757 including any combination of the features of the emission lines described herein. For example, as illustrated, the transmit line 757 may electrically connect the power amplifier die 774 to the output matching network 775.

Power amplifier die 774 may receive an RF signal at input pin RF _ IN of module 770. Power amplifier die 774 may include one or more power amplifiers including, for example, a multi-stage power amplifier configured to amplify RF signals. The power amplifier die 774 may include an input matching network 776, a first stage power amplifier 777 (which may be referred to as a Driver Amplifier (DA)), an inter-stage matching network 778, a second stage power amplifier 779 (which may be referred to as an Output Amplifier (OA)), a first stage bias circuit 780 configured to bias the first stage power amplifier 777, a second stage bias circuit 781 configured to bias the second stage power amplifier 779, or any combination thereof. The power amplifiers may include a first stage power amplifier 777 and a second stage power amplifier 779. The RF input signal may be provided to the first stage power amplifier 777 via an input matching network 776. The first stage power amplifier 777 may amplify the RF input and provide the amplified RF input to the second stage power amplifier 779 via the inter-stage matching circuit 778. The second stage power amplifier 779 may generate an amplified RF output signal.

The amplified RF output signal may be provided to an output pin RFOUT of the power amplifier die 774 via an output matching network 775. Any of the transmit lines 757 described herein may be implemented to couple the output of the power amplifier (e.g., the amplified RF output signal generated by the second stage power amplifier 779) and/or the output of the power amplifier die 774 to another component. Accordingly, any combination of the features of the diffusion barrier layer 761 described herein may also be implemented at the output of the power amplifier and/or the output of the power amplifier die 774. A matching network 775 may be provided on the module 770 to help reduce signal reflections and/or other signal distortions. Power amplifier die 774 may be any suitable die. In some implementations, the power amplifier 774 die is a gallium arsenide (GaAs) die. In some of these embodiments, the GaAs die has transistors formed using a Heterojunction Bipolar Transistor (HBT) process.

Module 770 may also include one or more power supply pins that may be electrically connected to, for example, power amplifier die 774. In some implementations, the one or more power supply pins can supply voltages (e.g., V) that can have different voltage levels_SUPPLY1And V_SUPPLY2) To the power amplifier. Module 770 may include circuit elements, such as inductors, which may be formed, for example, from traces on a multi-chip module. The inductor may operate as a choke inductor and may be disposed between a supply voltage and the power amplifier die 774. In some embodiments, the inductor is surface mounted. In addition, the circuit element may include a capacitor electrically connected in parallel with the inductor and configuredA capacitor that resonates at a frequency near the frequency of the signal received on pin RF _ IN. In some implementations, the capacitor can include a surface mount capacitor.

Module 770 may be modified to include more or fewer components, including, for example, additional power amplifier die, capacitors, and/or inductors. For example, the module 770 may include one or more additional matching networks 775. As another example, module 770 may include an additional power amplifier die and additional capacitors and inductors configured to operate as parallel LC circuits disposed between the additional power amplifier die of module 770 and power supply pins. The module 770 may be configured to have additional pins, such as in implementations where separate power supplies are provided to an input stage disposed on the power amplifier die 774 and/or implementations where the module 770 operates across multiple frequency bands.

Module 770 may have a low voltage positive bias supply of about 3.2V to 4.2V, good linearity, high efficiency (e.g., about 40% PAE at 28.25 dBm), large dynamic range, small and low profile package (e.g., 3mm x 0.9mm with a 10 pad configuration), turn off power control, support low collector voltage operation, digital enable, no reference voltage required, CMOS compatible control signals, integrated directional couplers, or any combination thereof.

In some implementations, module 770 is a power amplifier module that is a fully matched 10-pad surface mount module developed for Wideband Code Division Multiple Access (WCDMA) applications. This small and efficient module can package a full 1920MHz to 1980MHz bandwidth coverage into a single compact package. Module 770 can provide desirable talk time advantages to the mobile phone due to the high efficiency obtained across the entire power range. Module 770 can meet the stringent spectral linearity requirements for High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), and Long Term Evolution (LTE) data transmission with high power added efficiency. The directional coupler may be integrated into the module 770 and may thus eliminate the need for an external coupler.

Die 774 may be a power amplifier die embodied in a single gallium arsenide (GaAs) Microwave Monolithic Integrated Circuit (MMIC) that includes all of the active circuitry of module 770. The MMIC may include on-board bias circuitry as well as input matching network 776 and interstage matching network 778. The output matching network 775 may have a 50 ohm load embodied as separate from the die 774 within the package of the module 770 to increase and/or optimize efficiency and power performance.

Module 770 can be fabricated with a GaAs Heterojunction Bipolar Transistor (HBT) BiFET process that provides all positive voltage DC supply operation while maintaining high efficiency and good linearity. The primary bias to module 770 may be supplied by any three Ni-Cd batteries, a single Li-ion battery, or other suitable battery having an output selected from the range of about 3.2V to 4.2V, directly or via intermediate components. In some embodiments, no reference voltage is required. Powering down may be accomplished by setting the enable voltage to zero volts. According to some embodiments, no external supply side switch is required, since the typical "off" leakage is a few microamperes with full primary voltage supplied by the battery.

G. Module data

FIGS. 70A-70D are graphs illustrating the relationship of the emission line of FIG. 67A with other emission lines implemented in the module of FIG. 69. A module functionally similar to module 770 described in and illustrated with reference to fig. 69 was tested with the three transmit lines described above with reference to tables 2-4. The NiAu emission line has a nickel thickness of 5.5 um. The two NiPdAu emitting line surface treatment coating layers have different nickel thicknesses of 6um and 0.1um respectively. The emission line tested included a copper conductive layer having a thickness of about 25 um. In other aspects, the emission lines tested have the layer thicknesses and other properties described above with reference to tables 2-4.

As shown in the graphs of fig. 70A-70D, the emission line with NiPdAu surface treatment plating and a nickel thickness of 0.1um had the best performance of the three types of emission line testing, as measured by the figure of merit (FOM). In addition, the data contained in table 5 below indicates that the yield is comparable for the emission lines with NiPdAu surface treatment plating comprising a nickel thickness of 0.1um to the emission lines with NiPdAu surface treatment plating comprising a nickel thickness of 6 um.

Surface treatment coating	Yield of
		NiAu(5.5um Ni)	99.36％
NiPdAu(6um Ni)	96.86％
		Ni NiPdAu(0.1um Ni)	98.90％

TABLE 5 yield of different surface treatment coatings

The power amplifier may be evaluated based on several metrics, such as Adjacent Channel Power Ratio (ACPR), Power Added Efficiency (PAE), figure of merit (FOM), and the like, or any combination thereof. ACPR is a metric used to evaluate the linearity of a power amplifier. PAE is a metric used to evaluate the power efficiency of a power amplifier. For example, a lower PAE may reduce battery life of an electronic device (e.g., a mobile phone) that includes a power amplifier. FOM is one way to characterize the overall quality of a power amplifier.

Fig. 70A and 70B are graphs of ACPR and PAE, respectively, for the power amplifier of module 770 for high power, high frequency operation corresponding to three types of transmit lines. Table 6 summarizes some of the data from fig. 70A and 70B.

TABLE 6 FOM high Power, high frequency

Fig. 70C and 70D are graphs of ACPR and PAE, respectively, for the power amplifier of module 770 for high power, low frequency operation corresponding to three types of transmit lines. Table 7 summarizes some of the data from fig. 70C and 70D.

TABLE 7 FOM area Power, Low frequency

The data in tables 6 and 7 indicate that the emission lines with NiPdAu surface treatment plating including 0.1um thick nickel have the best FOM for the emission lines tested. The data of table 6 indicate that the average FOM of the emission lines with NiPdAu surface treatment plating including 0.1um thick nickel is 0.35 better than the average FOM of the equivalent emission lines with NiAu plating and 2.42 better than the average FOM of the equivalent emission lines with NiPdAu plating including 6um nickel thickness. The data in table 7 indicate that the average FOM for the emission lines with NiPdAu surface treatment plating including 0.1um thick nickel is 2.27 better than the average FOM for the equivalent emission lines with NiAu plating and 1.34 better than the average FOM for the equivalent emission lines with NiPdAu plating including 6um nickel thickness.

Table 8 summarizes the high power static collector current I of module 770 with the three types of transmission lines tested_QCCThe data of (1). The data indicates that the modules containing each type of transmission line have DC-like performance.

Surface treatment coating	n＝	Average IQCC (mA)	Standard deviation (mA)
				NiAu(5.5um Ni)	469	95.60	5.46
NiPdAu(6um Ni)	492	94.84	5.21
				NiPdAu(0.1um)	451	96.15	5.26

TABLE 8 DC Performance

Table 9 summarizes the data for the high power, high frequency gain of the power amplifiers in module 770 for the three types of transmit lines tested. The data in table 9 indicate that the power amplifiers in the module with the transmit line comprising NiPdAu surface treatment plating (with 0.1um thick nickel) have the lowest insertion loss because these power amplifiers have the highest average gain.

Surface treatment coating	n＝	Average gain	Delta gain
				NiAu(5.5um Ni)	469	28.65	---
NiPdAu(6um Ni)	492	28.47	-0.18
				NiPdAu(0.1um)	451	28.77	0.12

TABLE 9 gain/insertion loss

H. Example Components coupled by RF Transmit lines

Fig. 71 is a schematic block diagram of two Radio Frequency (RF) components coupled to each other via transmission line 757 of fig. 67A. Fig. 72A-72F are schematic block diagrams of various components that may be electrically coupled to each other via the transmission line 757 of fig. 67A. The illustrated components may be coupled to a substrate 772 that includes any combination of the features of the substrates described herein, for example, as described in connection with fig. 69. As one example, the substrate 772 may have a surface treatment coating. Alternatively, or in addition, the various components may be included in a mobile device (e.g., mobile device 788 described with reference to fig. 73).

As shown in fig. 71, a transmission line 757 may electrically couple the first RF component 782 to the second RF component 783. The first RF component 782 may include any suitable circuit elements configured to transmit RF signals, receive RF signals, process RF signals, condition RF signals, and the like, or any combination thereof. Similarly, the second RF component 783 may include any suitable circuit elements configured to transmit RF signals, receive RF signals, process RF signals, condition RF signals, and the like, or any combination thereof. Non-limiting examples of RF components include power amplifiers, RF switches, filters, and antennas.

As illustrated in fig. 72A and 72B, the power amplifier 779 may have an output electrically coupled to the transmission line 757 included on the substrate 772. For example, the output of the power amplifier 779 may be wire bonded to the transmit line 757. In the implementation shown in fig. 72A, the transmit line 757 is configured to transmit the output of the power amplifier 779 to the RF switch 784. The RF switch 784 may be any suitable switch configured to pass RF signals when turned on and block RF signals when turned off. In the implementation shown in fig. 72B, the transmit line 757 is configured to transmit the output of the power amplifier 779 to the filter 786. Filter 786 may be any suitable filter configured to filter the RF signal. For example, filter 786 may be a low pass filter, a band pass filter, or a high pass filter.

As illustrated in fig. 72C and 72D, the RF switch 784 may have an output electrically coupled to a transmit line 757 included on the substrate 772. For example, the output of the RF switch 784 may be wire bonded to the transmit line 757. In the implementation shown in fig. 72C, transmit line 757 is configured to transmit the output of RF switch 784 to antenna 787. In the implementation shown in fig. 72D, transmit line 757 is configured to transmit the output of RF switch 784 to filter 786.

As illustrated in fig. 72E and 72F, the filter 786 may have an output electrically coupled to a transmission line 757 included on a substrate 772. For example, the output of filter 786 may be wire bonded to transmit line 757. In the implementation shown in fig. 72E, transmit line 757 is configured to transmit the output of filter 786 to RF switch 784. In the implementation shown in fig. 72F, transmit line 757 is configured to transmit the output of filter 786 to antenna 787.

I. Mobile device

Any of the systems, methods, and apparatuses described herein may be implemented in a variety of electronic devices, such as mobile devices (which may also be referred to as wireless devices). FIG. 73 is a schematic block diagram of an example mobile device 788 that includes the transmit line of FIG. 67A. Examples of mobile device 788 include, but are not limited to, cellular telephones (for example, smart phones), laptop computers, tablet computers, Personal Digital Assistants (PDAs), electronic book readers, and portable digital media players. For example, the mobile device 788 may be a multi-band and/or multi-mode device (e.g., a multi-band/multi-mode mobile phone) configured to communicate using, for example, Global System for Mobile (GSM), Code Division Multiple Access (CDMA), 3G, 4G, and/or Long Term Evolution (LTE).

In a particular embodiment, the mobile device 788 may include one or more of: switching component 789, transceiver component 791, antenna 787, power amplifier 792, control component 793, computer readable medium 794, processor 796, battery 797, and supply control 798. Any of the transmit lines 757 described herein may be implemented in a variety of locations in the mobile device 788. For example, as illustrated in fig. 73, the transmit line 757 may electrically connect the output of the power amplifier 792 to the switching component 789 and/or electrically connect the switching component 789 to the antenna 787.

Transceiver component 791 may generate RF signals for transmission via antenna 787. Further, transceiver component 791 may receive incoming RF signals from antenna 787.

It should be understood that various functionalities associated with the transmission and reception of RF signals may be realized by one or more components collectively represented as transceiver 791 in fig. 73. For example, a single component may be configured to provide both transmit and receive functionality. In another example, the transmit and receive functionality may be provided by separate components.

Similarly, it should be understood that various antenna functionality associated with the transmission and reception of RF signals may be realized by one or more components collectively represented in fig. 73 as antenna 787. For example, a single antenna may be configured to provide both transmit and receive functionality. In another example, transmit and receive functionality may be provided by separate antennas. In yet another example, different frequency bands associated with mobile device 788 may be provided with different antennas.

In fig. 73, one or more output signals from transceiver 791 are depicted as being provided to antenna 787 via one or more transmit paths. In the example shown, different transmit paths may represent output paths associated with different frequency bands and/or different power outputs. For example, the two example power amplifiers 792 shown may represent amplification associated with different power output configurations (e.g., low power output and high power output) and/or amplification associated with different frequency bands.

In fig. 73, one or more detected signals from an antenna 787 are depicted as being provided to a transceiver 791 via one or more receive paths, each of which may benefit from the transmit line 757 of the present disclosure as shown and described herein. In the example shown, different receive paths may represent paths associated with different frequency bands. For example, the four example paths shown may represent quad-band capabilities that some mobile devices 788 are capable of.

To facilitate switching between receive and transmit paths, switching component 789 may be configured to electrically connect antenna 787 to a selected transmit or receive path. Accordingly, the switching component 789 may provide a number of switching functionalities associated with operation of the mobile device 788. In a particular embodiment, the switching component 789 may include a number of switches configured to provide functionality associated with, for example, switching between different frequency bands, switching between different power modes, switching between transmit and receive modes, or some combination thereof. The switching component 789 may also be configured to provide additional functionality including filtering of the signal. For example, switching component 789 may include one or more duplexers.

The mobile device 788 may include one or more power amplifiers 792. The RF power amplifier may be used to boost the power of RF signals having relatively low power. Thereafter, the boosted RF signal may be used for a variety of purposes, including driving an antenna of the transmitter. The power amplifier 792 may be included in an electronic device, such as a mobile phone, to amplify the RF signal for transmission. For example, in a mobile phone having an architecture for communicating under 3G and/or 4G communication standards, a power amplifier may be used to amplify RF signals. Managing amplification of RF signals may be desirable because the desired transmit power level may depend on how far away the user is from the base station and/or the mobile environment. The power amplifier may also be used to help adjust the power level of the RF signal over time in order to prevent transmission signal interference during the assigned reception time slots. The power amplifier module may include one or more power amplifiers.

FIG. 73 shows that in a particular embodiment, a control component 793 can be provided, and such component can include circuitry configured to provide various control functionality associated with operation of the switching component 789, the power amplifier 792, the supply control 798, and/or other operating components.

In a particular embodiment, the processor 796 may be configured to facilitate implementation of the various functionalities described herein. Computer program instructions associated with the operation of any of the components described herein may be stored in a computer readable memory 794 that may direct the processor 796 such that the instructions stored in the computer readable memory produce an article of manufacture including instructions that implement various operating features of the mobile device, module, etc., described herein.

The illustrated mobile device 788 also includes a supply control block 798 that may be used to provide a power supply to one or more power amplifiers 792. For example, the supply control block 798 may include a DC/DC converter. However, in a particular embodiment, the supply control block 798 may include other blocks, such as, for example, an envelope tracker configured to vary a supply voltage provided to the power amplifier 792 based on an envelope of an RF signal to be amplified.

The supply control block 798 may be electrically connected to a battery 797, and the supply control block 798 may be configured to vary the voltage provided to the power amplifier 792 based on the output voltage of the DC/DC converter. Battery 797 may be any suitable battery for use in mobile device 788, including, for example, a lithium ion battery. With the transmit line 757 for the transmit path including a diffusion barrier layer made of a material, such as nickel, and having a thickness less than the skin depth of the material at frequencies in the RF range, power consumption of the battery 797 may be reduced and/or signal quality may be improved, thereby improving performance of the mobile device 788.

J. Applications of

Some of the embodiments described above in this section have provided examples along with modules and/or electronic devices, such as mobile phones, that include power amplifiers. However, the principles and advantages of the embodiments may be applied to any other system or apparatus requiring high performance RF transmit lines.

Systems implementing one or more aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, portions of consumer electronics, electronic test equipment, and the like. More specifically, an electronic device configured to implement one or more aspects of the present disclosure may include, but is not limited to, an RF transmitting device, any portable device with a power amplifier, a mobile phone (for example, a smart phone), a telephone, a base station, a femto cell, a radar, a device configured to communicate according to a wireless fidelity and/or bluetooth standard, a television, a computer monitor, a computer, a handheld computer, a tablet computer, a laptop computer, a Personal Digital Assistant (PDA), a microwave, a refrigerator, an automobile, a stereo, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi-function peripheral device, Wrist watches, clocks, etc. Portions of the consumer electronic product may include multi-chip modules (including RF transmission lines), power amplifier modules, integrated circuits (including RF transmission lines), substrates (including RF transmission lines), and the like, or any combination thereof. Further, other examples of electronic devices may also include, but are not limited to, memory chips, memory modules, circuits for optical networks or other communication networks, and disk drive circuits. Further, the electronic device may contain unfinished products.

While various embodiments of the present disclosure and related features, aspects, and characteristics have been described in this section, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible so as to be within the scope of the present disclosure. For example, the invention herein is not limited to the materials or systems described, and may be further combined, integrated, assembled, or joined together, individually or otherwise, with any other number of relevant, desired, or suitable aspects of the invention as described throughout this disclosure, to even further improve the performance of integrated circuits, power amplifiers, power amplifier modules, and devices in which they are used.

XI tantalum nitride terminated through-wafer vias

Apparatus and methods for tantalum nitride terminated through-wafer vias are described herein. In a particular embodiment, a tantalum nitride (TaN) stop layer is formed on a first or front side of a gallium arsenide (GaAs) wafer, and a gold conductive layer is formed over the TaN stop layer. Thereafter, through-wafer vias are etched into the second or backside of the GaAs wafer so as to extend through the GaAs wafer and the first or inner portion of the TaN stop layer to reach the gold conductive layer. In a particular embodiment, the through-wafer via is electroplated with a nickel vanadium (NiV) barrier layer, a gold seed layer, and a copper layer. During through-wafer via formation, a second or outer portion of the TaN stop layer is maintained and configured to surround the interface between the gold conductive layer and the copper layer so as to inhibit diffusion of copper into the GaAs wafer.

TaN-terminated through-wafer vias can provide improved metal adhesion and reduced copper migration relative to schemes using silicon nitride terminations and sputtered barrier layers. Furthermore, in particular implementations, the use of a TaN stop layer to terminate the through-wafer via may permit the location or positioning of the through-wafer via to be moved without changing fabrication or lithography masks associated with transistor structures formed on the front side of the GaAs wafer. Configuring the through-wafer vias to be movable without changing photolithographic masks associated with the transistors may increase design flexibility and/or reduce time and costs associated with progressive adjustment or factory inspection of finished products of integrated circuit designs including the through-wafer vias. In view of the present disclosure, one of ordinary skill in the relevant art will readily appreciate that these aspects of the present disclosure may be combined with other aspects disclosed herein to further improve the performance of power amplifier modules and devices in which power amplifier modules are used.

Continuing now to next reference to figure 74A, a schematic plan view of a wafer 799 is shown, in accordance with one embodiment of certain aspects of the present invention. Wafer 799 includes a plurality of through wafer vias 802 and has been mounted to a carrier substrate or board 801.

Wafer 799 may be a gallium arsenide (GaAs) wafer that may include electronic circuits, such as transistor, resistor, and/or diode structures, formed thereon. In a particular implementation, an electronic circuit is configured to operate as a power amplifier circuit.

Wafer 799 further includes through-wafer vias 802 that may be used to provide electrical connections between opposite sides of wafer 799. In a particular implementation, the through-wafer vias 802 are used to electrically power electronic circuitry formed on the first or front side of the wafer 799 with ground or a power low supply voltage provided using conductors disposed on the second or back side of the wafer 799.

To assist in forming through-wafer via 802, wafer 799 may be configured to have a relatively small thickness, such as a thickness of less than about 200 μm. The carrier plate 801 can be used to help form through-wafer vias 802 on the wafer 799 by preventing damage or other damage to the wafer 799 during processing.

Although fig. 74A shows wafer 799 as including less than 100 through-wafer vias for clarity, wafer 799 typically includes more through-wafer vias, such as 100,000 or more than 100,000 through-wafer vias.

Fig. 74B is an enlarged plan view of a portion of the portion of wafer 799 of fig. 74A. The illustrated through-wafer via 802 defines a cavity in the wafer 799, and the cavity includes a first end and a second end. In a particular implementation, the wafer 799 is etched using an anisotropic etching process, which may result in the first end and the second end of the cavity of the through wafer via having different sizes.

In one embodiment, the first end of the cavity has a width W₁And length L₁And the second end of the cavity has a width W₂And length L₂And W is₁In the range of about 15 μm to about 60 μm, L₁In the range of about 15 μm to about 60 μm, W₂In the range of about 50 μm to about 70 μm, and L₂In the range of between about 60 μm to about 90 μm.

Although fig. 74A and 74B are illustrated for the case where through-wafer via 802 is substantially rectangular in shape when wafer 799 is viewed from above, through-wafer via 802 may be shaped in other ways, including, for example, a circular shape, an oval shape, a trapezoidal shape, and/or a square shape.

Fig. 75A-75I are schematic cross-sections illustrating the fabrication process of a wafer according to one embodiment of the present invention for forming through-wafer vias.

Fig. 75A illustrates the formation of a passivation layer 804 over a first or front side of a substrate 803, which may be a gallium arsenide (GaAs) substrate in a particular embodiment. The front side of the substrate 803 may include electronic circuitry, such as power amplifier circuitry, formed thereon. A passivation layer 804 may be formed over the front side of the substrate 803 to help passivate the substrate 803 and/or encapsulate electronic circuitry. In one embodiment, the passivation layer 804 is a silicon nitride (SiN) layer. The passivation layer 804 may have any suitable thickness, such as a thickness of about 190 nm.

Fig. 75B illustrates a photoresist layer 806 being formed and patterned over the passivation layer 804, and the passivation layer 804 being patterned using the photoresist layer 806. The photoresist layer 806 may be formed using any suitable technique, including deposition of photoresist using spin coating and subsequent patterning of the photoresist using photolithography.

The passivation layer 804 may be etched using any suitable process, including, for example, a Chemical Vapor (CV) etch. As shown in fig. 75B, the etch of passivation layer 804 may extend below the edges of photoresist layer 806, which may aid in the subsequent removal or stripping of photoresist layer 806. In one embodiment, the process to etch the passivation layer 804 is configured to incompletely etch the photoresist layer 806 by at least about 3 μm.

Fig. 75C illustrates the formation of a tantalum nitride (TaN) stop layer 807 using the photoresist layer 806 as a mask. The TaN stop layer 807 may be formed using any suitable process, such as a sputtering process. As will be described further below, a TaN stop layer 807 may be used to terminate through-wafer vias formed through the substrate 803. In one embodiment, the TaN stop layer 807 has a thickness in the range of about 50nm to about 100 nm.

Certain semiconductor processes utilize TaN to form thin film resistors in electronic circuits disposed on the front side of the substrate 803. In such processes, the TaN stop layer 807 may be formed by using a TaN thin film resistor layer, thereby reducing several steps and/or costs of the fabrication process of the wafer.

Fig. 75D illustrates the removal of the photoresist layer 806 and the formation of a conductive layer 809 over the TaN stop layer 807. The photoresist layer 806 may be removed using any suitable process, such as a plasma ashing process using reactive species, such as oxygen (O) and/or fluorine (F1).

In a particular implementation, conductive layer 809 is a gold layer configured to operate as a metallization layer for electronic circuitry formed on the front side of substrate 803. As shown in fig. 75D, a portion of the conductive layer 809 has been formed over the TaN stop layer 807. The conductive layer 809 may have improved adhesion to the TaN stop layer 807 relative to schemes using a silicon nitride stop layer.

As will be described in further detail below, through-wafer vias may be formed in the substrate 803 to electrically connect a portion of the conductive layer 809 formed over the TaN stop layer 807 to backside conductive structures formed on a second or backside of the substrate 803. The backside conductive structure may comprise a copper layer, and the TaN stop layer 807 may reduce or inhibit copper migration into the substrate 803.

Although the conductive layer 809 is illustrated as being continuous over the portion of the substrate 803 shown in fig. 75D, the conductive layer 809 is typically patterned over the substrate 803. The conductive layer 809 can be patterned using any suitable patterning process, such as a photoresist process.

FIG. 75E illustrates the attachment or bonding of the carrier plate 801 to the front side of the substrate 803 using the adhesive 808, and the formation and patterning of a photoresist layer 811 on the backside of the substrate 803. An adhesive 808 may be used to bond the substrate 803 to the carrier plate 801. The binder can be, for example, any suitable polymer or wax.

In a particular implementation, the carrier plate 801 is a sapphire substrate having a diameter greater than the diameter of the substrate 803. The carrier plate 801 may resist damage to the substrate 803 during processing and may be removed later. Additionally, the carrier plate 801 can be resistant to chemicals and/or environments associated with processing of the substrate 803.

Fig. 75F illustrates the formation of a through-wafer via 802 into a substrate 803 from the backside of the substrate 803. Through-wafer via 802 may be formed by using, for example, a plasma etch process. The through-wafer via 802 may extend through the substrate 803 and through an inner portion of the TaN stop layer 807 to reach the conductive layer 809. In one embodiment, the height of through-wafer via 802 is in a range from about 80 μm to about 200 μm.

Fig. 75G illustrates the removal of the photoresist layer 811 and the formation of the barrier layer 812 over the through-wafer via 802. The photoresist layer 811 can be removed using any suitable process, such as the process described earlier with respect to fig. 75D. The barrier layer 812 may serve to reduce copper diffusion of a subsequently deposited copper layer into the substrate 803. In a particular implementation, barrier layer 812 is a nickel vanadium (NiV) layer. The barrier layer 812 can be formed using any suitable process, such as a sputtering process. Although the barrier layer 812 may reduce copper diffusion of a subsequently deposited copper layer, some copper may still migrate through the barrier layer 812 for a variety of reasons, such as imperfect step coverage of the barrier layer 812.

Fig. 75H illustrates the formation of a seed layer 813 over the barrier layer 812, and the formation of a copper layer 814 over the seed layer 813. Seed layer 813 can be formed using a variety of processes, such as by exposing substrate 803 to a solution containing metal ions. Seed layer 813 can comprise any suitable metal, such as gold. A copper layer 814 has been formed over the seed layer 813. The copper layer 814 may be formed over the seed layer 813 using any suitable process, including, for example, electrochemical plating.

As illustrated in fig. 75H, the outer portion of the termination layer 807 has been preserved during processing and is configured to surround the interface between the conductive layer 809 and the copper layer 814 in order to terminate the through-wafer via 802. The TaN stop layer 807 can reduce copper migration by passivating portions of the substrate 803 near the through wafer via 802 and inhibiting copper that migrates through the barrier layer 812 from reaching the substrate 803. In one embodiment, the portion of the TaN stop layer 807 surrounding the interface between the conductive layer 809 and the copper layer 814 has a width of at least about 10 μm.

Copper layer 814 and conductive layer 809 are electrically connected to each other using through-wafer vias 802. In a particular implementation, the front side of the substrate 803 includes a transistor formed thereon, and the through-wafer via 802 is used to electrically connect the transistor to a conductive ground plane formed by the copper layer 814 and/or dissipate heat generated by the transistor. For example, the front side of substrate 803 may include a power amplifier circuit formed thereon, and the emitter of a bipolar transistor associated with the power amplifier circuit may be electrically connected to a conductive ground plane formed by copper layer 814 using through-wafer via 802.

FIG. 75I illustrates the removal or debonding of the carrier plate 801 from the substrate 803. The carrier plate 801 can be removed from the substrate 803 in a variety of ways including, for example, heating the adhesive 808 to reduce the bond strength and using mechanical force. The substrate 803 can be cleaned after removal of the carrier plate 801 by, for example, using a plasma etch and/or using a cleaning liquid, such as acetone, to cause the adhesive 808 to be removed as desired.

Although the fabrication process shown in fig. 75A-75I is illustrated as ending with a debonding process, the illustrated wafer may undergo further processing. For example, the wafer may undergo singulation to form dies from the wafer. In one embodiment, the wafer is configured to include power amplifier circuitry and is singulated to form a power amplifier die.

The above detailed description of embodiments is not intended to be exhaustive or to limit the invention to the precise form disclosed above. Although a particular manufacturing process has been described above for illustrative purposes, various modifications may be made within the scope of the invention, as those skilled in the relevant art will recognize. For example, various omissions, substitutions and/or changes in the manufacturing processes described herein may be made without departing from the scope of these aspects of the disclosure.

Thus, while various embodiments of the present disclosure and related features, aspects, and characteristics have been described in this section, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible so as to be within the scope of the present disclosure. For example, the invention herein is not limited to the materials or systems described, and may be further combined, integrated, assembled, or joined together, individually or otherwise, with any other number of relevant, desired, or suitable aspects of the invention as described throughout this disclosure, to even further improve the performance of integrated circuits, power amplifiers, power amplifier modules, and devices in which they are used.

XII via density and placement in radio frequency shielding applications

Aspects of the invention discussed in this section relate to determining the location and/or density of vias and resulting RF isolation structures forming part of the RF isolation structures of a packaged module. From electromagnetic interference (EMI) data, locations can be identified where via density can be increased and/or decreased without significantly degrading EMI performance of the RF isolation structure. In a particular embodiment, one or more vias may be added to and/or removed from a selected region of a packaged module based on EMI data. As indicated above, these aspects of the invention may be combined with other aspects of the invention to further improve the performance of the power amplifier module and the device in which the power amplifier module is used.

The vias may form part of an electrical connection between the top and bottom conductive layers of the RF isolation structure. It may be desirable to have a strong ground connection, for example, from one of the conductive layers to the RF isolation structure. The strength of the RF isolation structure may be based on the strength of the ground connection. More vias may provide a stronger ground connection. In previous designs, as many vias as possible were included in order to provide a strong ground connection to a particular RF isolation structure. However, the vias consume significant die area and increase the cost of the packaged module.

In this section of the disclosure, it should be recognized that via placement can be determined based on electromagnetic interference (EMI) data, such as EMI detection data and/or near field scan data. Particular features related to isolation associated with the RF signal are also identified in the present invention. One or more features described herein relate to selectively placing vias such that an RF isolation structure provides desired RF isolation without consuming too much die area. For example, EMI data from a particular environment may be obtained, and via placement may be determined based on this data.

As generally described, aspects of the invention in this section relate to determining the location and/or density of vias forming part of an RF isolation structure. From the simulation and/or EMI data, the location of "hot spots" and/or "non-radiating areas" of the packaged module can be determined. A "hot spot" may be a region of a packaged module that emits a relatively high amount of electromagnetic radiation and/or a region of a packaged module that receives a relatively high amount of external electromagnetic radiation. The "non-radiating areas" may be areas of the packaged module that emit relatively low amounts of electromagnetic radiation and/or areas of the packaged module that receive relatively low amounts of external electromagnetic radiation. Based on the location of the hot spots and/or non-radiating areas, the density of vias forming portions of the RF isolation structures may be adjusted in selected areas of the packaged module without significantly degrading the EMI performance of the RF isolation structures. In a particular embodiment, one or more vias may be added to and/or removed from a selected region of a packaged module. For example, the via may be removed around the non-radiative region. As another example, vias may be added around hot spots. Alternatively or additionally, the sensitivity of the position of the packaged module to external radiation may be determined. Based on the sensitivity data, the location and/or density of the vias can be adjusted.

By adjusting the location and/or density of the vias, the RF isolation structures may consume less area on the substrate. Thus, the packaged module may be smaller, less expensive, consume less power, or any combination thereof. Tailoring via location and/or density to specific RF isolation needs can reduce the total number of vias without significantly degrading EMI performance. This may allow fewer vias to be used, which may reduce the overall cost of the substrate including the vias. These cost savings can be important in manufacturing when large numbers of packaged modules are manufactured.

Various examples of systems, apparatus, device structures, materials, and/or methods related to the fabrication of packaged modules having Radio Frequency (RF) circuitry and wire bond-based Electromagnetic (EM) isolation structures are described herein in this section. Although described in the context of RF circuitry, one or more features described herein may also be used in packaging applications involving non-RF components. Similarly, one or more features described herein may also be used in packaging applications without EM isolation functionality. It should also be understood that one or more features described herein may be applied to isolation structures that do not include wire bonds.

Referring now next to fig. 76A, a top plan view of an illustrative packaged module 816 is shown. The packaged module 816 may include one or more circuit elements. In a number of embodiments, the one or more circuit elements include RF circuit elements. Packaged module 816 can include an RF isolation structure that includes a plurality of vias. The packaged module 816 may be a packaged integrated circuit. The illustrated packaged module 816 includes a Radio Frequency (RF) isolation structure 818 and RF components including a high-band portion 819 and a low-band portion 821. Although not illustrated in fig. 76A for clarity, packaged module 816 may include numerous other structures.

The RF isolation structure 818 may act as a faraday cage. The RF isolation structure 818 may include conductive features surrounding at least one RF component. In a particular implementation, the conductive feature may include a plurality of wire bonds 832 in combination with vias, the plurality of wire bonds configured to provide RF isolation. More details of the plurality of wire bonds 832 will be provided later, for example, with reference to fig. 87A and 87B. In some other implementations, the conductive features may include other structures, such as solid metal cans.

The illustrated packaged module 816 is a packaged power amplifier Integrated Circuit (IC) in which the high-band portion 819 includes high-band power amplifier circuitry and the low-band portion 821 includes low-band power amplifier circuitry. A power amplifier may be used to boost the amplitude of the relatively weak RF signal. Thereafter, the boosted RF signal may be used for a variety of purposes including, for example, driving an antenna, a switch, a mixer, a filter, etc., or any combination thereof in an RF system. In certain electronic systems, such as multi-band systems, different power amplifier configurations may be used to amplify RF signals at different frequencies. In the illustrated configuration, the packaged module 816 includes high-band power amplifier circuitry for amplifying relatively high-frequency RF signals and low-band power amplifier circuitry for amplifying relatively low-frequency RF signals.

Although packaged module 816 illustrates one example of a packaged IC that may be used herein, the methods and apparatus described herein may be implemented in connection with a variety of other isolation structures.

FIG. 76B shows a cross section of the packaged module 816 along line A-A of FIG. 76A. The illustrated cross-section shows a side view of the RF isolation structure 818. As illustrated, the packaged module 816 includes a system board 826, a printed circuit board 825, wire bonds 832, an overmold structure 833, and a conductive layer 834 formed over the overmold structure 833. System board 826 may include a substrate system board substrate 822 and an electrical reference plane 831, which may be a ground plane. The printed circuit board may be a laminate substrate. The printed circuit board 825 may include input-output (I/O) pads (e.g., ground contact pad 829), a plurality of vias 823, and one or more rails (tracetrack) 824. A plurality of vias 823 and one or more rails 824 can electrically connect ground contact pads 829 to wire bond pads 828, thereby electrically connecting reference plane 831 to wire bonds 832. In the orientation shown in fig. 76B, wire bonds 832 may be disposed over printed circuit board 825. The overmolded structure 833 may encapsulate the wire bonds 832. More details regarding the over-mold structure 833 will be provided later, for example, with reference to fig. 89 and 90. Wire bonds 832 may be electrically connected to conductive layer 834.

As illustrated, the RF isolation structure 818 includes a ground plane 831, a ground contact pad 829, a rail 824, a plurality of vias 823, wire bonds 832, and a conductive layer 834. For example, the plurality of vias 823 may provide RF isolation from RF signals generated by RF circuitry within the RF isolation structure 818 and/or external to the RF isolation structure 818. The vias 823 may be spaced apart by a distance such that most of the power of the RF signal is blocked by the vias 823. The placement of the vias 823 may be determined according to one or more features described herein.

While the illustrative cross-section of fig. 76B shows a two-layer via 823, it is understood that one or more features described herein may be applied to RF isolation structures that include any suitable number of layers of vias 823. For example, in other embodiments, there may be a layer of vias 823. As another example, in particular implementations, there may be three or more layers of vias 823. In embodiments having two or more layers of vias 823, the vias 823 may be disposed in the same placement or in different layers in different placements. Although the plurality of vias 823 are illustrated as being the same size, it is understood that two or more vias may have different sizes.

Fig. 77 shows a process 836 that may be implemented to fabricate a packaged module 816, such as a packaged module having and/or fabricated with one or more features as described herein. FIG. 77 shows various portions and/or stages of various operations associated with process 836 of FIG. 77.

In block 837 of fig. 77, a package substrate and a portion to be mounted on the package substrate may be provided. Such portions may include, for example, one or more Surface Mount Technology (SMT) components and one or more singulated dies having Integrated Circuits (ICs). Fig. 78A and 78B show that in some embodiments, the package substrate may include a laminate panel 858. Fig. 78A shows the front side of an example laminate panel 858; and fig. 78B shows the back side of an example laminate panel 858. The laminate panel 858 can include a plurality of individual module substrates 827 arranged in a group (sometimes referred to as an array) 859. Although four separate molding sections are shown in fig. 78A, 78B, 90 and 94, any of the features described in the present application may be applied to other suitable arrangements, such as a single array mold cap without breaks.

Fig. 79A, 79B, 79C show top, side, and bottom views, respectively, of an example configuration of an individual module substrate 827. For illustrative purposes, the boundary 863 may define the area occupied by the module substrate 827 on the panel 858, fig. 78A and 78B. Within boundary 863, module substrate 827 may include a top or front surface 862 and a bottom or back surface 869. An example mounting area 864 sized to receive a die (not shown) is shown on the front surface 862. A plurality of example contact pads 866 are arranged around the die-receiving area or die pad 864 so as to allow for bond wire bonding to be formed between the die and the bottom contact pad 871 arranged on the back surface 869. Although not shown, the electrical connection between the wire bond contact pads 866 and the contact pads 871 of the module may be configured in a number of ways. Also within the boundary 863 are two sets of example contact pads 867 configured to allow installation of, for example, a passive SMT device (not shown). The contact pads may be electrically connected to contact pads of the module and/or some of the ground contact pads 829 disposed on the back surface 869. A plurality of wire bond pads 828 configured to allow formation of a plurality of EM isolation wire bonds (not shown) are also within the boundary 863. The wire bond pads 828 may be electrically connected to an electrical reference plane (e.g., ground plane) 831. Such connections between the wire bond pads 828 and the ground plane 831 (depicted as dotted lines 874) may be accomplished in a number of ways. For example, as shown in fig. 76B, the plurality of vias 823 and/or one or more rails 824 can form at least a portion of an electrical connection between the wire bond pad 828 and the ground plane 873. The vias 823 and/or rails 824 (fig. 76B) can form part of an RF isolation structure 818 (fig. 76A) that surrounds the RF circuitry in the module. In some embodiments, the ground planes 831, 873 may or may not be connected to the ground contact pads 829 disposed on the back surface 869.

FIG. 80 shows an example fabricated wafer 876 that includes a plurality of functional dies 877 waiting to be cut (or sometimes referred to as singulated) into individual dies. This cutting of the die 877 can be accomplished in several ways. Fig. 81 schematically depicts an individual die 877 in which a plurality of metalized contact pads 878 may be provided. Such contact pads can be configured to allow for the formation of bond wire bonds between die 877 and contact pads 866 (e.g., fig. 79A) of the module substrate.

In block 838 of fig. 77, solder paste may be applied on the module substrate to allow for the mounting of one or more SMT devices. Fig. 82A and 82B show an example configuration 879 in which solder paste 881 is provided on each of contact pads 867 on a front or top surface of a module substrate 827. In some implementations, the solder paste 881 can be applied by an SMT stencil printer in a desired amount to a desired location on a panel (e.g., 858 in fig. 78A).

In block 839 of fig. 77, one or more SMT devices may be positioned over the solder contacts with solder paste. Fig. 83A and 83B show an example configuration 882 in which an example SMT device 883 is positioned on solder paste 881 provided on each of contact pads 867. In some embodiments, the SMT device 883 may be positioned at a desired location on the panel by an automated machine fed with the SMT device from a tape reel.

In block 841 of fig. 77, a reflow operation may be performed to melt the solder paste to solder one or more SMT devices to their respective contact pads. In some implementations, the solder paste 881 may be selected and a reflow operation may be performed at a first temperature to melt the solder paste 881 to thereby allow the desired solder contact to be formed between the contact pad 867 and the SMT device 883.

In block 842 of fig. 77, the solder residue from the reflow operation of block 841 may be removed.

In block 843 of fig. 77, an adhesive may be coated on one or more selected regions on the module substrate 827 to allow one or more dies to be mounted. Fig. 84A and 84B show an example configuration 884 in which an adhesive 886 is coated in the die mounting area 864. In some implementations, the adhesive 886 can be applied to desired locations on the panel (e.g., 858 in fig. 78A) in desired amounts by techniques such as screen printing.

In block 844 of fig. 77, one or more dies may be positioned on a selected area with an adhesive coated thereon. Fig. 85A and 85B show an example configuration 887 in which a die 877 is positioned on a die mount area 864 via an adhesive 886. In some implementations, the die 877 can be positioned on a die mount on a panel for throughput by an automated machine fed with die from a tape of die wound on a reel.

In block 846 of fig. 77, the adhesive between the die and the die mount may be cured. Preferably, this curing operation may be performed at one or more temperatures lower than the reflow operation described above for mounting one or more SMT devices on their respective contact pads. This configuration allows the solder connections of the SMT device to remain intact during the curing operation.

In block 847 of fig. 77, adhesive residue from the mounting operations of blocks 843 and 844 may be removed.

In block 848 of fig. 77, electrical connections (e.g., wire bonds) may be formed between the mounted die and corresponding contact pads on the module substrate 827. Fig. 86A and 86B show an example configuration 888 in which a number of wire bonds 889 are formed between a contact pad 878 of a die 877 and a contact pad 866 of a module substrate 827. Such wire bonds may provide electrical connections for signals and/or power to and from one or more circuits of die 877. In some embodiments, the aforementioned formation of wire bonds may be accomplished by an automated wire bonding machine.

In block 849 of fig. 77, a plurality of RF shield wire bonds may be formed around selected regions on the module substrate 827. Fig. 87A and 87B show an example configuration 891 in which a plurality of RF shield wire bonds 832 are formed on wire bond pads 828. The wire bond pads 828 are schematically depicted as being electrically connected (dotted lines 874) with one or more reference planes, such as ground plane 873. In some embodiments, such a ground plane may be disposed within the module substrate 827. The aforementioned electrical connection between the RF shield wire bond 832 and the ground plane 873 may result in interconnected RF shield structures at the sides and bottom side of the region defined by the RF shield wire bond 832. The electrical connection between the RF shield wire bond 832 and the ground plane 873 can include vias 823 and/or one or more rails 824, for example, as described with reference to fig. 76B. As described herein, a conductive layer may be formed over this region and connected to an upper portion of the RF shield wire bond 832 to thereby form an RF isolation structure 818 (fig. 76A) having a volume of RF shielding.

In the example configuration 891 of fig. 87A and 87B, the RF shield wire bonds 832 are shown forming a perimeter around the region in which the die 877 and SMT device 883 are located. Other perimeter configurations are also possible. For example, a perimeter may be formed with RF wire bonding around the die, around one or more of the SMT devices, or any combination thereof. In some implementations, a perimeter based on RF wire bonding may be formed around any circuit, device, component, or region where RF isolation is desirable. For purposes of illustration, it should be understood that RF isolation may include preventing RF signals or noise from entering or leaving a given shielded region. Thus, for purposes of illustration, it is further understood that the terms isolation and shielding may be used interchangeably as desired. For example, RF components being shielded may include situations in which some or substantially all PF signals in an RF signal from another source are blocked from reaching the RF components. As another example, RF components being isolated may include situations where some or substantially all of the PF signal (e.g., noise or actively generated signals) is blocked from reaching another device. It should be understood that each of the terms masking and isolating can include any one or both of the foregoing functionalities unless the context indicates otherwise.

In the example configuration 891 of fig. 87A and 87B, the RF shield wire bonds 832 are shown having asymmetric side profiles configured to facilitate controlled deformation during a molding process as described herein. Additional details regarding such wire bonds may be found, for example, in PCT publication No. WO2010/014103 entitled semiconductor package with integrated interference shielding and method of manufacturing the same (semiconductor package and semiconductor package with integrated interference shielding). In some embodiments, other shapes of RF shield wire bonds may also be utilized. For example, symmetrical arcuate wire bonds, as generally described in U.S. patent No. 8,071,431 entitled "overmolded semiconductor package with wire bond cage for EMI shielding" (over metal d e s e m onductor pacukegiew with wire bond cage for RF shielding wire bonds) may be used instead of or in combination with the shown asymmetrical wire bonds as RF shielding wire bonds. In some embodiments, the RF shield wire bond need not form a loop shape and have both ends on the surface of the module substrate. For example, wire extensions with one end on the surface of the module substrate and the other end positioned above the surface (for connection to an upper conductive layer) may also be utilized.

In the example configuration 891 of fig. 87A and 87B, the RF shield wire bonds 832 are shown having a similar height that is generally higher than the height of the die attach wire bonds 889. This configuration allows the die bond wire bond 889 to be encapsulated by a molding compound as described herein and isolated from the upper conductive layer to be formed after the molding process.

In block 851 of fig. 77, an overmold may be formed over the SMT components, die, and RF shield wire bonds. Fig. 88 shows an example configuration 893 that can facilitate the formation of such an overmold. Template lid 894 is shown positioned over module substrate 827 such that a lower surface 896 of template lid 894 and an upper surface 862 of module substrate 827 define a volume 897 in which molding compound can be introduced.

In some implementations, the template cover 894 may be positioned such that its lower surface 896 engages and pushes down on the upper portion of the RF shield wire bonds 832. This configuration allows any height variations of the RF shield wire bonds 832 to be removed so that the upper portions of the lower surface 896 of the contact template cover 894 are at approximately the same height. When the molding compound is introduced and the overmolded structure is formed, the foregoing techniques maintain the upper portion of the encapsulated RF shield wire bond 832 at or near the resulting upper surface of the overmolded structure.

In the example molding configuration 893 of fig. 88, molding compound may be introduced from one or more sides of the molding volume 897, as indicated by arrows 898. In some implementations, this introduction of molding compound can be performed under heated and vacuum conditions to facilitate easier flow of the heated molding compound into the volume 897.

Fig. 89 shows an example configuration 899 in which molding compound has been introduced into volume 897 (as described with reference to fig. 88) and the molding lid is removed to create an overmolded structure 833 that encapsulates various module elements (e.g., dies, die-bond wire bonds, and SMT devices). The RF shield wire bonds are also shown as being substantially encapsulated by the overmolded structure 833. The upper portion of the RF shield wire bond is shown at or near the upper surface 902 of the over-mold structure 833.

Fig. 90 shows an example panel 903 having an overmolded structure 833 formed over a plurality of array segments. The overmolded structure for each array segment may be formed as described herein with reference to fig. 88 and 89. The resulting overmolded structure 833 is shown to define a common upper surface 902 for a plurality of modules covering a given array segment.

The molding process described herein with reference to fig. 88, 89, and 90 can produce a configuration in which the upper portion of the encapsulated RF shield wire is joined at or near the upper surface of the overmolded structure. This configuration may or may not result in the RF shield wire bond forming a reliable electrical connection with the upper conductor layer to be formed thereon.

In block 852 of fig. 77, a thin top portion or layer of the overmolded structure may be removed to better expose an upper portion of the RF shield wire bond. Fig. 91 shows an example configuration 904 in which such removal has been performed. In the example, an upper portion of the overmold structure 833 is shown removed to create a new upper surface 906 that is lower than the original upper surface 902 (pursuant to the molding process). This material removal is shown to better expose the upper portion 907 of the RF shield wire bond 832.

The aforementioned material removal from the upper portion of the overmolded structure 833 can be accomplished in several ways. Fig. 92A shows an example configuration 908 in which such material removal is accomplished by sandblasting. In the example, the lighter shaded portions are where material has been removed to create a new upper surface 906 and a better exposed upper portion 907 of the RF shield wire bond. The darker shaded portion is where material is not removed so that the original upper surface 902 remains.

In the example shown in fig. 92A, a modular structure corresponding to an underlying module substrate 827 (depicted with dot block 863) is readily shown. Such modules would be separated after the conductive layer is formed over the newly formed upper surface 906.

In block 853 of fig. 77, the newly exposed upper surface resulting from the removal of material may be cleaned.

In block 854 of fig. 77, a conductive layer can be formed on the newly exposed upper surface of the overmolded structure such that the conductive layer is in electrical contact with the upper portion of the RF shield wire bond. This conductive layer can be formed by several different techniques, including methods such as spraying or printing. Fig. 92B illustrates one method for forming a conductive layer 834 (fig. 93) in accordance with aspects of the present invention. Here, after the entire top surface of the arrangement 908 has been reduced to a height 906 by sandblasting or other ablation methods, a nozzle 909 sprays a conductive coating 910 onto the top of the arrangement. The conductive paint 910 may be a conductive metallic paint formulated to achieve the intended aspects of the invention. Further details regarding this are found in U.S. patent application nos. 13/893,605, 13/893,614, and 13/904,566, as incorporated herein above.

Fig. 93 shows an example configuration 911 in which a conductive layer 834 has been formed over the upper surface 906 of the over-mold structure 833. As described herein, the upper surface 906 preferably exposes the upper portion 907 of the RF shield wire bond 832. Thus, the formed conductive layer 834 forms an improved contact with the upper portion 907 of the RF shield wire bond 832.

As described with reference to fig. 87A and 87B, the RF shield wire bonds 832 and the ground plane 873 may create interconnected RF isolation structures at the sides and bottom side of the region defined by the RF shield wire bonds 832. With the upper conductive layer 834 in electrical contact with the RF shield wire bond 832, the upper side over the region is now also shielded, thereby creating a shielded volume.

Fig. 94 shows an example panel 913 that has been sprayed with a conductive paint to create a conductive layer 834 that covers multiple array segments. As described with reference to fig. 90, each array segment includes a plurality of modules that are to be separated to form a finished packaged module.

In block 856 of fig. 77, the modules in the array segments having a common conductive layer (e.g., a layer of conductive paint) may be singulated into individual packaged modules. This module singulation can be achieved in several ways, including sawing techniques.

FIG. 95 shows an example configuration 916 in which modular sections 827 described herein have been singulated into separated modules 917. The overmold is shown, in part, to include sidewalls 919; and the module substrate portion is shown to include sidewalls 918. Collectively, sidewalls 919 and 918 are shown as defining sidewalls 921 of separated modules 917. The upper portion of the separated module 917 remains covered by the conductive layer 834. As described herein with reference to fig. 79A, 79B, and 79C, the lower surface 869 of the separated module 917 includes contact pads 871, 829 to facilitate electrical connection between the module 917 and a circuit board (e.g., a phone board).

FIGS. 96A, 96B, and 96C show front (also referred to herein as top), back (also referred to herein as bottom) and perspective views of the singulated module 917. As described herein, such a module includes an RF shielding structure encapsulated within an overmolded structure; and in some embodiments, the overall dimensions of module 917 are not necessarily larger than a module without RF shielding functionality. Thus, a module with integrated RF shielding functionality may advantageously result in a more compactly assembled circuit board, since no external RF shielding structure is required. Furthermore, the packaged modular form allows for easier handling of the modules during handling and assembly processes.

In block 857 of FIG. 77, the singulated modules may be tested for appropriate functionality. As discussed above, the modular form allows this test to be performed more easily. Furthermore, the internal RF shielding functionality of the module allows this test to be performed without an external RF shielding device.

Fig. 97 shows that in some embodiments, one or more of the modules included in a circuit board (e.g., a wireless telephone board) can be configured with one or more packaging features as described herein. Non-limiting examples of modules that may benefit from such packaging features include, but are not limited to, a controller module, an application processor module, an audio module, a display interface module, a memory module, a digital baseband processor module, a GPS module, an accelerometer module, a power management module, a transceiver module, a switching module, and a Power Amplifier (PA) module.

Figure 98A shows a process 923 that may be implemented to assemble a packaged module having one or more features as described herein on a circuit board. In block 924, a packaged module may be provided. In some embodiments, the packaged modules may represent the modules described with reference to fig. 97. In block 926, the packaged module may be mounted on a circuit board (e.g., a phone board). Fig. 98B schematically depicts the resulting circuit board 928 with the module 816 mounted thereon. While one module is illustrated as being mounted on the circuit board 928, it should be understood that one or more other modules may also be mounted thereon. The circuit board 928 may also include other features, such as a plurality of connections 930, to facilitate operation of the various modules mounted thereon.

In block 927 of fig. 98A, a circuit board with a module mounted thereon may be mounted in a wireless device. Fig. 98C schematically depicts a wireless device 931 (e.g., a cellular phone) having a circuit board 928 (e.g., a phone board). The circuit board 928 is shown to include a module 929 having one or more features as described herein. The wireless device is shown to further include other components, such as an antenna 932, a user interface 933, and a power supply 934.

Figure 98D schematically depicts a wireless device 931 with a packaged module 816, such as a chip or module. The wireless device 931 illustrated in figure 98D may include one or more features shown in figure 98C, some of which have been omitted from figure 98D for illustrative purposes. In some embodiments, packaged module 816 may include any of the modules described herein. As illustrated, the packaged module 816 includes RF components 938 and RF isolation structures 818 formed around the RF components 938 in order to provide RF isolation properties. The RF isolation structure 818 may be disposed around the perimeter of the packaged module 816 or around RF components 938 on other suitable regions of the packaged module 816. The RF isolation structure 818 may provide one or more RF isolation functionalities, such as isolating the RF component 938 from RF influence from another component 939 in the electronic wireless device 931 (arrow 936), isolating the RF component 938 from an external RF source external to the wireless device 931 (arrow 937), and/or preventing electromagnetic radiation from the RF signal and/or noise from the RF component 938 from reaching another component 939 in the wireless device 931 and/or an external RF source external to the electronic wireless device 931 (not shown) (arrows 941 and 942). RF component 938 may include one or more circuit elements configured to transmit and/or receive RF signals. Non-limiting examples of RF components include power amplifiers, voltage controlled oscillators, filters, switches, and the like. For example, in the embodiment illustrated in fig. 76A, the RF components may include a high-band portion 819 and/or a low-band portion 821.

While one RF component 938 is shown in fig. 98D, it is understood that two or more RF components may be included within the RF isolation volume created by the RF isolation structure 818. According to some embodiments, the packaged module 816 may include two or more RF components each having a dedicated RF isolation structure.

Fig. 99A is a flow diagram of an illustrative process 943 of determining via placement. Any combination of the features of process 943 or any of the other processes described herein may be embodied in a non-transitory computer readable medium and stored in memory. When executed, the non-transitory computer-readable medium may cause some or all portions of process 943 or other processes to be performed. It should be understood that any of the methods discussed herein may include more or fewer operations, and the operations may be performed in any order as desired.

Process 943 can determine via placement around the periphery of the packaged module. The via may be part of an RF isolation structure that forms an RF isolation volume around one or more RF components. Vias may be formed in one or more layers of the substrate. In some embodiments, the vias may be formed as part of a printed circuit board, for example, as shown in fig. 76B. Having a higher via density in selected defined regions around the perimeter of the packaged module can provide stronger ground connections and/or stronger RF isolation in the selected regions. Conversely, reducing the via density in selected regions may reduce die size and overall cost of the packaged module. Process 943 can determine where vias can be removed to save die area and/or where adding vias can improve RF isolation.

The process 943 may include obtaining electromagnetic interference (EMI) data at block 944, identifying regions associated with relatively high EMI and/or relatively low EMI at block 946, and determining updated via placements at block 947. At block 948, this process may be iterated until the EMI specification is met. The discussion process 943 will now be discussed with reference to the example EMI distribution profiles illustrated in fig. 100A and 100B, the relationship between via density and back radiated power shown in 101, and the via placement illustrated in 102A and 102B.

At block 944, EMI data may be obtained for the initial via placement. In some embodiments, electromagnetic scanning/probing may be performed in the initial via placement to obtain EMI data. For example, near field scanning may be performed. The EMI data may be associated with an RF application. According to a particular embodiment, the EMI data may correspond to two or more operating modes of the packaged module. For example, EMI data may correspond to a high-band mode of operation and a low-band mode of operation in which a packaged module operates in a lower frequency band than in the high-band mode of operation. Different RF isolation considerations may apply to different operating frequency bands. For example, at higher frequencies, the RF signal may have a smaller wavelength. Thus, it may be desirable to bring the vias closer together near the high-band portion of the packaged module. As another example, EMI data may correspond to a low power mode of operation and a high power mode of operation. According to a particular implementation, the initial via placement may correspond to an RF component that does not have any vias that provide RF shielding. Alternatively, the initial via placement may correspond to any other placement of the at least one via disposed around the RF assembly. In a particular implementation, the initial placement may correspond to the maximum number of vias that may be included in a packaged module of a particular size.

Example EMI data is reflected in the EMI profiles shown in figures 100A and 100B. The EMI profiles of fig. 100A and 100B correspond to the via placements shown in fig. 102A and 102B, respectively. The EMI data reflected in diagram 100A may correspond to an initial via placement or via placements after one or more iterations of determining updated via placements. The EMI data reflected in diagram 100B may correspond to updated via placements determined based on the EMI distribution profile shown in diagram 100A.

Fig. 100A shows an example of an EMI distribution profile corresponding to a plurality of vias disposed around a perimeter of a packaged module of RF components. More specifically, the EMI distribution profile shown in figure 100A corresponds to the via placement shown in figure 102A. The EMI profile graphically illustrates EMI associated with a portion of the surface of the packaged module. In the graph 100A, the regions correspond to squares that may be identified by columns numbered left-to-right along the top side of the EMI distribution profile in the graph 100A and rows with letters along the left side of the EMI distribution profile in the graph 100A. Shading of the EMI profile indicates EMI values associated with corresponding regions of the packaged module. More specifically, the legend of graph 100C indicates corresponding EMI values in dBm, which may represent a power ratio in decibels of a measured EMI referenced to milliwatts. It is understood that lower EMI values are numbers represented with higher negative values. For example, an EMI value of-14 dBm is higher than an EMI value of-24 dBm. The shading of the EMI distribution profiles in fig. 100A and 100B corresponds to the EMI values in dBm in the legend of fig. 100C.

Each area of the EMI profile may correspond to a defined surface area of the packaged module and/or its printed circuit board. The defined surface area may include zero, one, two, or more through holes. Each of the regions including the at least one via may have approximately the same width in a dimension that is substantially parallel to an outer edge of the packaged module. In a particular implementation, each region may have about the same area. In other implementations, two or more regions may have different areas. It should be understood that the regions may be smaller or larger than illustrated. Any particular region may be associated with one or more EMI values. For example, region B1 in graph 100A is associated with multiple EMI values and region F1 is associated with a single EMI value.

Referring back to fig. 99A, at block 946, zones associated with relatively high and/or relatively low EMI may be identified. For example, the zone of the packaged module associated with the highest EMI value may be identified. As another example, one or more zones of a packaged module associated with EMI values above a predefined threshold may be identified. Alternatively or additionally, one or more zones of the packaged module associated with EMI values below a predefined threshold may be identified. In yet another example, the zone with the lowest EMI value may be identified.

Areas of a packaged module associated with relatively high EMI may benefit from stronger RF isolation compared to other areas of the packaged module. In some implementations, the region of the packaged module associated with relatively high EMI may be a region for which the hot spots and/or RF isolation structures provide less RF isolation than other regions of the packaged module. Such zones may provide less RF isolation than defined in product specifications and/or than desired levels of EMI. According to some embodiments, hot spots may occur at or near the region of the packaged module that generates signals with high power levels, such as the output of a Power Amplifier (PA). In contrast, for a Low Noise Amplifier (LNA), hot spots may occur at or near the input of the LNA. Alternatively or additionally, hot spots may occur at or near regions of a packaged module with a high activity factor, such as near an oscillator (e.g., a voltage controlled oscillator) and/or an LNA.

The region of the packaged module associated with relatively low EMI may provide a sufficient level of RF isolation with a relatively low via density. In some implementations, the region of the packaged module associated with relatively low EMI may be a non-radiating region and/or a region for which the RF isolation structure provides more RF isolation than other regions of the packaged module. Such zones may provide more RF isolation than defined in product specifications and/or than is desired for EMI. According to some embodiments, the non-radiating region may occur at or near a region of the packaged module that does not generate signals or generates signals having a low power level. Alternatively or additionally, the non-radiating region may occur at or near a region of the packaged module having a low activity factor. As another example, for a power amplifier module, the RF input and DC path may be less sensitive to EMI radiation than an Output Matching Network (OMN).

The EMI profile of fig. 100A indicates that regions B1 and C1 are associated with relatively high EMI and regions a8, B8, C8, D8, E8, and F8 are associated with relatively low EMI. In particular, the EMI value associated with region B1 is approximately-14 dBm. In certain applications, such EMI values can be problematic. Accordingly, it may be desirable to adjust the via density of the packaged module to improve EMI. Via density may be adjusted by changing the number, location, size, or any combination thereof in the updated via placement as compared to the initial via placement.

An RF isolation structure including a plurality of vias may be grounded through a connection to a ground plane (e.g., through an electrical connection to a lower conductive layer below an RF component configured as a ground plane). While the ground plane ideally has zero parasitic inductance, in reality, the ground plane has non-zero parasitic inductance of zero. Adding additional vias may reduce the inductance of the ground plane. Conversely, reducing the number of vias may increase the inductance of the ground plane. The higher inductance associated with the ground plane may result in a less stable ground plane that may affect signals generated by RF components isolated by the RF isolation structure. For example, when the ground plane is unstable, the RF isolation structure may function similar to an antenna. This may cause the RF isolation structure to amplify the radiation rather than providing RF isolation. This effect may occur at locations corresponding to relatively high EMI packaged modules (e.g., locations corresponding to packaged modules of regions B1 and C1 in the EMI profile shown in fig. 100A).

Fig. 101 illustrates a relationship among via density and reverse radiation power. When the via surface area density is lower than d1, the RF isolation structures may float due to the weak ground connection. The weak ground connection may cause portions of the packaged module to be associated with relatively high EMI, for example, as shown by regions B1 and C1 of the EMI profile of fig. 100A. The density d1 may represent a lower threshold below which the RF isolation structure functions similarly to a weak ground. The curve illustrated in fig. 101 has a low back radiation power and thus a relatively high radiation associated with a via surface area density lower than the density d 1. This may cause the RF isolation structure to act as an antenna. Therefore, it may be desirable to increase the surface area density below the density d1 in order to increase the back radiation power (reduce the radiated power). Density d2 may represent an upper threshold above which increased via density may not significantly improve RF isolation. Above density d2, the curve illustrated in fig. 101 flattens out. When the via surface area density is higher than the density d2, the advantage of increasing the via density may not provide a significant increase in the back radiated power and thus the RF isolation of the RF isolation structure. Thus, it may be desirable for the via surface area density to be between density d1 and density d2 in fig. 101. This may, for example, reduce die area and/or reduce manufacturing costs.

Referring back to fig. 99A again, at block 947, an updated via placement may be determined. In the updated via placement, via density in regions associated with high EMI may be increased compared to the initial placement. Alternatively or additionally, in the updated via placement, via density in regions associated with low EMI may be reduced compared to the initial placement. According to a particular embodiment, the via density in the updated placement may be determined such that the via density is above a lower threshold (below which the RF isolation structure acts as a weak ground) and below an upper threshold (above which increased via density may not significantly improve RF isolation). For example, the via density in the updated placement may be between density d1 and density d2 in fig. 101.

In the updated via placement, the number of vias, the location of the vias, the size of the vias, or any combination thereof may be adjusted as compared to the initial via placement. For example, vias may be moved away from regions associated with relatively low EMI toward regions of relatively high EMI. As another example, vias may be added to and/or removed from areas associated with relatively high EMI. In yet another example, the size of one or more vias may be increased in areas associated with relatively high EMI and/or the size of one or more vias may be decreased in areas associated with relatively low EMI.

For illustrative purposes, reference will be made to providing more detail to the addition of vias to selected areas along the periphery of the substrate. FIG. 102A shows a top plan view of a substrate with placement of vias 823 arranged around the perimeter. As shown in fig. 102A, the vias 823 may be aligned around the perimeter of the substrate. The vias 823 illustrated in fig. 102A may be included in the same layer of the substrate. The placement of the vias 823 shown in fig. 102A may correspond to the EMI distribution profile shown in fig. 100A. FIG. 102B shows another top plan view of the updated placed substrate with vias 823 and 823' arranged around the perimeter. The placement of the vias 823 and 823' shown in fig. 102B may correspond to the EMI distribution profile shown in fig. 100B. The placement of vias 823 and 823' in figure 102B may be the last via placement used in the fabricated packaged module, according to some embodiments.

In the updated placement shown in FIG. 102B, two additional vias 823' are added in the region of the substrate corresponding to regions B1 and C1, as compared to the placement of vias 823 shown in FIG. 102A. The EMI profile of fig. 100B shows that the two additional vias 823' improve the EMI associated with the corresponding regions in the EMI profile. For example, the EMI profile of fig. 100B indicates that the EMI of region C1 is improved by about 10dBm compared to the EMI profile of fig. 100A without the two additional vias 823'. The EMI profile of fig. 100B shows that the two additional vias 823' improve EMI associated with other adjacent regions in the EMI profile. For example, the EMI profile of fig. 100B indicates that the EMI of region a1 is improved by about 4dBm and the EMI of region a4 is improved by about 7dBm compared to the EMI profile of fig. 100A without the two additional vias 823'.

Referring back to fig. 99A, at block 948, the process may be iterated any suitable number of times until the EMI specification is met. More specifically, EMI data may be obtained, regions associated with relatively high and/or relatively low EMI may be identified and updated via placements may be determined. Thus, in particular embodiments, process 943 can be an iterative process. For example, the EMI profile of fig. 100A and the via placements shown in 102A may correspond to iterations of the process 943 between an initial via placement and a final via placement used in production. According to a particular embodiment, at block 948, the process 943 may be iterated for different operating modes such that EMI specifications are satisfied for the different operating modes. Different operating modes may be associated with different frequency bands and/or different power modes, for example. In some embodiments, at block 948, the process 943 may be iterated for the vias 823 of different layers.

By performing process 943, via placement can be improved such that EMI associated with the packaged module meets specifications without using too many vias. Thus, the process 943 can produce a packaged module having vias configured to provide RF isolation with efficient utilization of die area.

Fig. 99B is a flow diagram of an illustrative process 949 of determining via placement. Process 949 may be substantially the same as process 943, except for the fact that in process 949, block 946 replaces process 943 with block 951. Thus, the process 949 may include any combination of features described earlier with reference to obtaining EMI data at block 944, determining updated via placements at block 947, and iterating the process at block 948. The process 949 may include obtaining EMI data at block 944, determining the sensitivity of the zone to external radiation at block 951, and determining updated via placement at block 947. At block 948, the process 949 may be iterated until EMI specifications are met. It should be understood that processes 943 and 949 may be performed together, serially, in parallel, or any combination thereof, depending on the particular embodiment. Thus, via placement may be based on the relative levels of EMI associated with the regions of the packaged module and/or the sensitivity of the regions of the packaged module to external radiation.

At block 951, the principles and advantages described in connection with regions of packaged modules associated with relatively low and/or relatively high EMI may be applied to regions of packaged modules that are relatively sensitive and/or relatively insensitive to external radiation. For example, sensitivity data may be obtained and regions that are relatively more sensitive to electromagnetic radiation and/or regions that are relatively less sensitive to electromagnetic radiation may be identified. In some embodiments, the sensitivity data may include EMI data, such as the EMI profile shown in figure 100A and/or data derived from such EMI data. Regions of packaged modules that are sensitive to external radiation may be processed similarly to regions of packaged modules associated with relatively high EMI. For example, at block 951, the via density in these regions may be increased at block 951. Alternatively or additionally, regions of packaged modules that are not sensitive to external radiation may be processed similar to regions of packaged modules associated with relatively low EMI. The region sensitive to external radiation may include, for example, an Output Matching Network (OMN) region of the power amplifier module and/or the output of the VCO. In contrast, regions that are not sensitive to external radiation may include, for example, input regions and/or DC paths.

A packaged module in accordance with one or more features described herein may include a particular via placement. For example, a plurality of vias may be disposed around the RF components such that there is a higher density in a first area of the packaged module than in a second area of the packaged module, wherein the first area is associated with higher electromagnetic interference than the second area. For example, vias 823 and 823' in FIG. 102B are included in region 952 corresponding to regions B1 and C1 of the illustrated EMI distribution profile. The region 952 has a higher density than the region 953 corresponding to regions B8 and C8 of the illustrated EMI profile. Regions 952 and 953 are provided for illustrative purposes, and it is understood that other regions and/or region sizes may be implemented in conjunction with one or more features described herein.

Different via densities can be achieved in a variety of ways. For example, as illustrated in fig. 102B, region 952 includes more vias than region 953. When vias of the plurality of vias are about the same size, vias in the same layer of the substrate that are spaced closer together have a higher via density. For example, vias 823 and 823' are spaced closer together in region 952 than via 823 is in region 953. As another example, different via densities may be achieved by using vias of different sizes.

As illustrated in fig. 102B, region 952 is disposed along a periphery of the packaged module and region 953 is also disposed along the periphery of the packaged module. Regions 952 and 953 have about the same width in a dimension that is substantially parallel to the outer edge of the packaged module. As illustrated in fig. 102B, the region 952 has about the same area as the region 953. In a particular embodiment, the first region may have a via density at least as large as any region along a periphery of the packaged module having an area at least as large as an area of the first region. Alternatively or additionally, the second region may have a density of vias that is no greater than a density of any region along a periphery of the packaged module having an area that is at least as large as an area of the second region.

The vias 823 and 823' disposed along the periphery of the packaged module may be spaced closer together in the hot spot than in the low-emissivity region. Such via spacing may be in one or more layers of the substrate. For example, in a single layer of the substrate, the vias 823 and 823' disposed along the periphery of the packaged module may be spaced closer together in the hot spot than in the low-emissivity region. As another example, the vias may be spaced closer together in the hot spot than along the periphery of the packaged module in the low-e region in each of the two or more layers of the substrate. Referring to FIG. 102B, the illustrated vias 823 and 823' are spaced closer together in region 952 than in region 953. The vias 823 and 823' may be aligned along the periphery of the packaged module, for example, as shown in fig. 102A and 102B.

In a packaged module, a first region and a second region having a lower via density than the first region may each include at least one via. The first region and the second region having a lower via density than the first region may each include at least two vias.

One or more RF components isolated by the RF isolation structure may emit more radiation to the first region than to the second region. For example, the RF assembly may emit more radiation to region 952 than to region 953.

The first region may correspond to a hot spot of the packaged module and the second region may correspond to a low-emissivity region of the packaged module. For example, region 952 may be adjacent to a power amplifier output or an output of a different RF component that generates a high power signal. As another example, region 952 may be adjacent to a voltage controlled oscillator output or an output of a different RF component with a high activity factor. In contrast, the second region may be adjacent to a region of a packaged module having a low activity factor, a region of a packaged module that does not generate signals, a region of a packaged module in which low power signals propagate, and the like, or any combination thereof.

Alternatively or additionally, the first region may be exposed to more external radiation than the second region. For example, a hot spot adjacent to a component may be adjacent to region 952.

The via placement described herein may be included in an RF isolation structure of a packaged module that includes one or more conductive features that form at least a portion of an electrical connection between a plurality of vias and a conductive layer over an RF component. As one example, the one or more conductive features may include wire bonds (e.g., wire bond 832 illustrated in fig. 76B). Alternatively, the one or more conductive features may include a metal can surrounding the RF components.

In a particular embodiment, the RF components within the RF isolation volume formed by the RF isolation structure include a power amplifier. For example, the via placement illustrated in fig. 102B may correspond to the packaged module illustrated in fig. 76A and 76B. Region 952 may be adjacent to the power amplifier output. More specifically, the region 952 may be adjacent to the output of a power amplifier in the high-band portion 819 of the packaged module 816 of fig. 76A.

Some of the above-described embodiments have provided examples in connection with packaged modules and/or electronic devices that include RF components, such as power amplifiers. However, the principles and advantages of these embodiments may be used in any other system or device where shielding and/or isolation is desired.

Systems implementing one or more aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, portions of consumer electronics, electronic test equipment, and the like. More specifically, an electronic device configured to implement one or more aspects of the present disclosure may include, but is not limited to, an RF transmitting device, an RF receiving device, an RF transceiver, any portable device with RF components (e.g., power amplifiers), a mobile phone (e.g., a smart phone), a telephone, a base station, a femto cell, a radar, a device configured to communicate according to the wireless fidelity and/or bluetooth standards, a television, a computer monitor, a computer, a handheld computer, a tablet computer, a laptop computer, a Personal Digital Assistant (PDA), a microwave, a refrigerator, an automobile, a stereo, a DVD player, a CD player, a VCR, an MP3 player, a radio device, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a camera, a microphone, copiers, facsimile machines, scanners, multifunction peripherals, wrist watches, clocks, and the like. Portions of the consumer electronics product may include a multi-chip module (including an RF isolation structure), a power amplifier module, an integrated circuit (including an RF isolation structure), a substrate (including vias that may be used to form portions of the RF isolation structure), and the like, or any combination thereof. Further, other examples of electronic devices may also include, but are not limited to, memory chips, memory modules, circuits for optical networks or other communication networks, and disk drive circuits. Further, the electronic device may contain unfinished products.

The teachings of the invention provided herein may be applied to other systems and not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

While various embodiments of the present disclosure and related features, aspects, and characteristics have been described in this section, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible so as to be within the scope of the present disclosure. For example, the invention herein is not limited to the materials or systems described, and may be further combined, integrated, assembled, or joined together, individually or otherwise, with any other number of relevant, desired, or suitable aspects of the invention as described throughout this disclosure, to even further improve the performance of integrated circuits, power amplifiers, power amplifier modules, and devices in which they are used.

Semiconductor package with integrated interference shield

This section of the invention relates to an integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on top of the package molding compound. The wirebond spring has a defined shape that causes a spring effect to provide a contact electrical connection between the top of the wirebond spring and the conductive layer. The wire bond springs may be positioned anywhere in the package around some or all of the devices included in the module package to form a complete EMI shield around the devices. And as such, may be worth repeating, those skilled in the relevant art(s) of the present disclosure will readily appreciate that these particular aspects of the present disclosure, as discussed in this section, may be combined with any or all of the other aspects of the present disclosure to further improve the performance of the power amplifier module and the devices in which it is used.

In many modern applications, including cellular telephone handsets, Personal Digital Assistants (PDAs), media players, and other portable devices using Radio Frequency (RF) components, the size (length, width, and thickness) and weight of the finished product can often be critical design parameters. For example, particularly for cellular telephone handsets, there is a continuing effort toward smaller and lighter devices that provide increased functionality and features. Thus, the size and weight of the individual components used in these devices may also be important. As discussed above, conventional approaches for improving electromagnetic interference shielding of RF devices involve placing grounded metal cans over the individual RF devices to be shielded, which adds size, weight, and cost to the design and thus may be undesirable in many applications.

Aspects and embodiments relate to methods and apparatus to provide interference shielding integrated into individual devices or modules with minimal increase in size and/or weight of the devices or modules during a packaging process. As used herein, the term "EMI shield" is used to refer to both electromagnetic interference and radio frequency interference shielding. In one embodiment, the integrated EMI shield may be formed using a wire bonding manufacturing process as discussed further below, and thus, may be manufactured using existing tools and assembled on a common processing line with conventional wire bonding to provide electrical connections to the electronic devices in the module. This approach may provide high design flexibility as well as an easier and less expensive method by which to manufacture EMI shields. Additionally, the integrated "wire-bond cage" shielding according to aspects of the present invention provides a way to achieve inter-module/intra-module isolation and low package profile (not yet achieved by conventional prior art). As discussed below, wire bond cages may be formed using "wire bond spring" connectors having specific and well-controlled designs and shapes to provide robust and practical EMI shielding for various packaging and process conditions.

It is to be understood that the embodiments of the methods and apparatus discussed herein are not limited in application to the details of construction and the arrangement of components set forth in the following description or illustrated in the following drawings. The methods and apparatus are capable of implementation in other embodiments and of being practiced or of being carried out in various ways. Examples of specific implementations are provided herein for illustrative purposes only and are not intended to be limiting. In particular, acts, elements and features discussed in connection with any one or more embodiments are not intended to be excluded from a similar role in any other embodiments. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. Any reference to an embodiment or element or act of the systems and methods herein referred to in the singular may also encompass embodiments comprising a plurality of these elements, and any reference to any embodiment or element or act herein in the plural may also encompass embodiments comprising only a single element. References in the singular or plural form are not intended to limit the presently disclosed systems or methods, components, acts or elements thereof. The use of "including," "comprising," "having," "containing," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. References to "or" may be construed as inclusive such that any term described using "or" may indicate any of a single, more than one, and all of the described terms. Any reference to front and back, left and right, top and bottom, and upper and lower portions is intended to facilitate description, not to limit the present systems and methods or components thereof to any one positional or spatial orientation.

Referring now to fig. 103, one example of a method of packaging an electronic device or module incorporating integrated EMI shielding is illustrated, in accordance with aspects of the present invention. Aspects and embodiments of the method are discussed below with continued reference to fig. 103.

A first step 954 includes preparing the substrate for incorporation into an electronic module. This step 954 may include forming metallizations on the substrate that can be used to interconnect various components of the electronic module, and at least some of the metallizations may be part of an integrated EMI shield, as discussed further below. In step 956, the electronic module may be assembled according to methods and techniques as may be known to those of skill in the art. This step 956 may include actions such as: one or more dies are mounted to a substrate, forming any necessary internal or external connections or connections, including deposition of metallization layers and/or dielectric layers, and the like. Thus, it should be appreciated that while the module assembly is illustrated in fig. 103 as a single step 956, it may comprise several steps that may be performed simultaneously, at different times, and/or in different locations. Further, it is understood that step 954 may be considered part of step 956.

An example of such a module is illustrated in figure 104. Module 962 includes one or more dies 963 mounted to a substrate 964. Some examples of module 962 include, but are not limited to, power amplifiers, transceivers, linear devices, filters, and other devices that may require or benefit from EMI shielding. As discussed above, EMI shielding is generally desirable for RF devices, and thus, at least one of the dies 963 can be an RF device and the module 962 can be an RF module; however, it should be understood that the invention is not so limited and die 963 may include any type of digital or analog device or component. In one example, the die 963 is mounted to the substrate 964 using wire bonds 966 connected to bond pads 967, as illustrated in fig. 104. Alternatively, the die 963 may be mounted to the substrate 964 using a flip-chip bonding method or any other suitable technique known to those skilled in the art.

According to one embodiment, the integrated EMI shield may be incorporated into the module 962 by constructing a wire-bond cage around the edges of the substrate 964 during the packaging process. A wire bonding process similar to the conventional process used to form the wire bonds 966 and using the same equipment may be implemented to construct a wire bond spring, as discussed below. A plurality of these wire bond springs may be placed around the die 963 on the substrate 964 and connected to a ground plane in the package (as discussed further below) to provide a wire bond spring cage that forms an integrated EMI shield. To form an integrated shield in a molding module, manufacturing difficulties exist in finding ways to connect a ground plane in a substrate to a top conductive shield layer. Embodiments of methods of forming an integrated shield using wire bond spring connectors provide a robust manufacturing process that addresses this difficulty, as discussed further below.

Referring again to fig. 103, as discussed above, step 954 may include forming metallization on the substrate 964 that will be part of the integrated EMI shield. Referring to fig. 105, these metallizations can include wire bond pads 968, a ground plane 969, and vias 971 connecting the wire bond pads to the ground plane. Wire bond springs 972 may then be connected to wire bond pads 968 (step 957), as discussed further below. It should be appreciated that while in the example illustrated in fig. 105, two discrete wire bond pads 968 and associated through holes 971 are provided for each wire bond spring 972, the invention is not limited thereto and many other configurations are contemplated. For example, as illustrated in fig. 106A and 106B, the individual wire bond pads 968 of fig. 105 may be replaced with metallization traces or rings 973 that may at least partially surround the die 963. In this example, one or more vias 971 (fig. 106A) may be provided at points along the traces 973 to couple the traces, and thus the wirebond springs 972, to the ground plane 969. Moreover, in one example, the trace 973 may be continuous between two or more wirebond springs 972, and thus, each wirebond spring need not have a respective associated through-hole 971. Additionally, although in fig. 105, wirebond spring 972 is illustrated as two connection points (at wirebond pad 968) coupled to ground plane 969 through vias 971, this need not be the case, and one of the ends of the wirebond spring can be left floating (i.e., not electrically coupled to the ground plane).

According to one embodiment, the method of forming the integrated EMI shield includes a transfer molding process to encapsulate the die 963 in a molding compound 974 (step 958, fig. 103). As discussed further below, during the transfer molding process, the substrate 964 is placed in a lower mold sleeve, an upper mold sleeve is lowered onto the lower mold sleeve to seal a cavity around the device, and molding compound 974 is flowed into the cavity to encapsulate the die 963 on the substrate. Transfer molding processes are well known to those skilled in the art.

Still referring to fig. 103 and 105, after the transfer molding process (step 958), an ablation process (step 959) may be used to expose the tops of the wirebond springs 972 through the molding compound 974. The ablation process may include, for example, a laser ablation process that grinds and/or polishes the molding compound 974 to remove the layer molding compound and expose the tops of the wirebond springs 972. In one example, the ablation process can remove a layer of molding compound that is less than about 40 microns thick. In another example, the ablation process may remove a layer molding compound that is about 10 microns thick. After the top of the wire bond springs 972 have been exposed, a thin conductive coating or layer 975 may be formed on top of the molding compound 974 (step 961) to contact the exposed top of the wire bond springs 972. A conductive layer 975 may be deposited on top of the molding compound 974 using any of a variety of techniques, such as by printing, deposition, sputtering, and so forth. In one example, the conductive layer 975 comprises a metal-filled epoxy (e.g., silver-filled epoxy) sprayed on top of the molding compound 974, as discussed above in section XII with respect to fig. 92B. The conductive layer 975 contacts and thus electrically connects the exposed tops of the wire bond springs 972.

As discussed herein above, in one embodiment, module 962 includes a ground plane 969 disposed along a bottom surface of substrate 964 (as shown in fig. 105) and connected to wire bond springs 972 by vias 971. An electrical connection is made between the conductive layer and the ground plane 969 by contact between the top of wire bond spring 972 and conductive layer 975, thus completing EMI shielding in module 962. The wirebond springs 972 provide a flexible (as they may be located anywhere suitable on the substrate) and fully integrated connection between the ground plane 969 in the substrate 964 and the top conductive shield layer 975. In one embodiment, the wirebond springs 972 have a defined shape (as discussed further below) that is controlled to create a spring effect that facilitates forming a reliable electrical connection between the wirebond springs and the conductive layer 975. Thus, one or more of the dies 963 can be substantially enclosed in a ground EMI shield formed by the conductive layer 975, the wire bond springs 972 (and their associated metallization such as vias 971 and bond pads 968), and the ground plane 969. Unlike the bulky metal cans of conventional EMI shielding solutions, this integrated EMI shielding according to embodiments of the invention may add minimal size and weight to the module 962.

According to one embodiment of the present invention, the wire bond spring 972 has a particular shape and height that is sufficiently controlled and substantially different from conventional wire bonds 966. As may be known to those skilled in the art, conventional wire bonds 966 are formed using a wire bonding machine by: one end of the bond wire is connected to die 963 and movement of the wire bonding machine is controlled to draw the bond wire away from the die to form a loop, as illustrated in fig. 104 and 105, and then the other end of the bond wire is connected to a pad on the substrate. The wire bond spring 972 according to embodiments of the present invention may be formed using similar techniques, but the wire loop is processed into a unique shape that provides the desired spring effect and other properties of the wire bond spring discussed below by manipulating the x-axis and y-axis motions of the wire bonding machine.

Referring to fig. 107, one embodiment of a wire bond spring 972 in accordance with aspects of the present invention is illustrated. The wire bond spring 972 includes: a ball bond 976 providing a first connection point between the wire bond spring and the substrate 964; and a wire loop 977 extending from the ball bond to a second connection point 983 on the substrate. Referring to fig. 107 and 108, the process of forming the wire bond spring 972 (step 957) may begin with a first step 978 of forming a ball bond 976. This step can include placing a metal ball on a wirebond pad 968 (see fig. 105) on the substrate 964 (step 979) and bonding the ball to the wirebond pad (step 981) to form a ball bond 976. The wire bond springs may be formed using any of a variety of metals, including gold (as is commonly used for conventional wire bonding) and copper. In one example where the wire bond springs are made of gold, the wire bond pads 968 may similarly be gold or gold plated, and the ball bonds 976 are ultrasonically bonded to the substrate 964. A similar thermosonic process can be used to form copper ball bonds 976 on gold, copper or tin plated wire bond pads 968.

According to one embodiment, the wire loop 977 is formed by: the wire is pulled from the ball joint 976, shaped by manipulating the x-axis and y-axis motions of the wire bonding machine (step 982), and finally the tail end of the wire loop is bonded to the wire bond pad 968 (step 983). In one embodiment, the wire loop 977 is shaped to have the shape illustrated in fig. 107 or a shape similar thereto. As further shown in fig. 108, step 978 may include sub-step 979 to place a metal ball 976 on a pad 968 and sub-step 981 in which the ball 976 is bonded to the pad 968.

Referring to fig. 109, one embodiment of a wirebond spring 972 bonded to a wirebond pad 968 (or trace 973) provided on a substrate 964 as discussed above is illustrated. In one embodiment, the wire bond spring 972 includes a recurved zone 986 near the ball joint 976. The wire extends from the recurved partition 986 up to the peak 987 of the wire bond spring 972. The convex region 988 extends between the reverse curve partition 986 and the peak 987. The wire bond spring 972 further includes an upper region 989 proximate the peak 987 and a downwardly sloped tail region 991 extending between the upper region 989 and the second connection point 983. In one example, the upper region 989 is substantially planar so as to provide a large contact area with the upper conductive layer 975 (see fig. 106A), thereby facilitating a good electrical connection with the conductive layer. The recurved zone 986 serves to make the wirebond spring 972 more resilient than conventional wirebonds, contributing to the spring effect of the wirebond spring and the ability of the wirebond spring to withstand the pressure applied by the mold sleeve and molding compound and preserving its shape during the transfer molding process, as discussed further below. In one example, the peak 987 of the wirebond spring is positioned substantially above the recurved zone 986 (as indicated by the dotted line 992), which can further contribute to the spring force of the wirebond spring 972, as discussed below.

As known to those skilled in the art and discussed above, during the transfer molding process, the device is placed in a lower mold sleeve, an upper mold sleeve is lowered onto the lower mold sleeve to seal the cavity surrounding the device, and molding compound 974 is flowed into the cavity, fig. 105 and 106A. The height of the wirebond springs 972, measured from wirebond pads 968 to apex 987, can be made slightly higher than the expected or designed thickness of the molding compound 974. During the transfer molding process (step 958, fig. 103), the wire bond springs 972 are compressed by lowering the upper mold chase 993, as illustrated in fig. 110. In one example, the upper die sleeve 993 first contacts the peaks 987 of the wire engaging springs 972 because the peaks are the highest points of the wire engaging springs. Due to the spring constant of the wire engaging springs 972 provided by the location of the recurved partition 986 and the peaks 987 generally above the recurved partition, the wire engaging springs remain in contact with the surface of the upper die sleeve 993 as illustrated in fig. 110. This spring effect provided by the shape of the wirebond springs 972 enables robust manufacturing of the integrated EMI shield because by causing the tops of the wirebond springs to remain in contact with the surface of the mold sleeve, only a thin layer of molding compound can cover the tops of the wirebond springs so that the tops of the wirebond springs can be easily and reliably exposed after the ablation process (step 959). In one example, the wirebond springs 972 have a large spring range in the vertical direction and are able to withstand variations in finished height due to variations in molding compound thickness, substrate thickness, and warpage that can occur during the transfer molding process. The height of the wire bonding spring may be selected to be sufficiently high so that the wire bonding spring is compressed as the upper die sleeve 993 is lowered, but not so high that the lowered upper die sleeve crushes the wire bonding spring. Thus, the wire bond springs should not be so high that the amount of deformation required to accommodate the lowered upper die sleeve 993 exceeds the spring capacity of the wire bond springs. Similarly, if the wire bond springs are not sufficiently high, the tops of the wire bond springs may not contact or be sufficiently close to the upper surface of the molding compound after the transfer molding process, and thus may not be exposed by the ablation process (step 959, fig. 103), or may not exhibit sufficient elastic deformation (spring effect) to keep the tops of the wire bond springs in contact with the upper surface of the molding compound. In one example, the height of the wire bond springs 972 is about 90 microns higher than the designed thickness of the molding compound. It should be appreciated, however, that the wirebond springs can have different heights depending on a number of factors, such as, for example, the metal, mold material, and other like factors used to form the wirebond springs.

According to one embodiment, the shape of wire bond springs 972 are optimized to provide large contact areas with conductive layer 975 (fig. 105 and 106A), thereby facilitating good electrical connection with conductive layer 975. As discussed above, in one example, the upper region 989 (fig. 109 and 110) of the wire bond spring 972 is substantially planar. Thus, the upper region 989 may provide a large planar area (length) of contact with the mold sleeve (or surface of the molding compound) when compressed by the upper mold sleeve 993. This is the area that will be exposed at the top of the package by the ablation step (step 959) and in contact with the conductive layer 975 to make an electrical connection with the conductive layer 975 and complete EMI shielding.

Referring now to fig. 111, an image of one example of a wire bond spring incorporated in a device package is illustrated. As illustrated in fig. 111, the upper regions 989 of the wirebond springs form a large planar area on top of the molding compound 974 and in contact with the conductive layer 975. A plan view of the wirebond spring of fig. 111 prior to coating the conductive layer 975 is illustrated in fig. 112. Referring to fig. 112, a long length 994 of exposed wire corresponding primarily, but not necessarily completely, to the upper region 989 and peak 987 of the wirebond spring can be seen on top of the molding compound 974. Fabricated and simulated examples of packages have been formed that include wire bond springs having an average exposed length 994 of about 400 microns and a minimum exposed length of about 962 microns. These examples illustrate an improvement of about 10 times the exposed length of the wire compared to a conventional wire bond loop (966 in fig. 106A). This increased contact area provides a robust and low resistance electrical connection to the integrated EMI shield. Furthermore, if materials other than gold (e.g., to reduce cost) are used for the wire bond spring, such as copper, large contact areas may be particularly important because copper has a lower electrical conductivity than gold. In addition, since solder is not used to make the connection between the exposed area of the wirebond spring and the conductive layer 975 (the connection is made only by contact between the two conductors), the larger the contact area, the more reliable the connection can be.

In addition to providing a spring effect and large contact areas to facilitate a good and robust electrical connection with conductive layer 975, the shape of wirebond springs 972 also provides a spring force during the transfer molding process. Applicants have experimentally determined that it is important that the wirebond springs remain vertical during the transfer molding process so that the upper region is at or near the top of the molding compound and can be easily exposed with minimal ablation. Testing and simulation have demonstrated that wire bond loops shaped in a conventional manner fold and collapse during the transfer molding process because their shape provides little or no stability. Thus, the circuit may move in any direction under pressure from the upper die sleeve 993 (fig. 110) and flow the molding compound. In contrast, the shape of the wire bond spring 972 controls its movement to compress (elastically deform) primarily in the vertical direction (y-direction in fig. 105), producing the spring effect discussed above. In one example, the wire bond spring is rigid in the in-plane direction (i.e., the x-z direction in fig. 105) and has good resistance to mold flow and wire sweep defects, which can be a major concern for very high loops.

In summary, effective, low cost, and robust integrated EMI shielding can be provided in any transfer-molded module using only: a ground plane, which is usually already present in the module substrate; a thin layer of conductive material deposited on top of the molding compound; and a plurality of wirebond springs as discussed herein to connect the conductive layer to the ground plane, thereby forming a complete shield for some or all of the devices in the module. Wire bond springs can be placed anywhere in the package with optional redundant connections ensuring contact to conductive layer 975 meets all electrical needs, allowing for a very flexible EMI shielding design that can be easily modified to accommodate different module layouts and devices. Similarly, as discussed above with reference to fig. 106A and 106B, the vias 971 connecting the wire bond pads 968 (or traces 973) to the ground plane need not coincide with each pad or with a particular location on the ground plane, allowing for flexible pad 968 and via 971 placement in the module. The number of wire bond springs needed to provide adequate EMI shielding depends on the frequency of operation of the device to be shielded and the level of shielding required. For example, the wire density (i.e., the spacing between immediately adjacent wirebond springs 972 in any given direction) can increase with increasing signal frequency. In one example, a wire spacing of about λ/20 (where λ is the wavelength of the signal to be shielded) may be used. It should be appreciated that the wire spacing need not be uniform, so long as the minimum spacing to achieve the desired shielding at a given frequency is maintained. The example of a wire-bonded spring EMI cage has been tested and found to provide approximately 20dB shielding, which is currently sufficient for most RF handheld device applications. Thus, the wirebond springs discussed herein can be used to provide a fully integrated EMI shield that is highly flexible and adds minimal cost, weight, and/or size to the module. The wirebond springs can be processed using conventional processing techniques that are low cost, robust, and do not require any procurement of additional or specialized assembly equipment.

Having thus described several aspects of the above embodiments in this section, it is to be appreciated various alternatives, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the scope of the invention. Accordingly, the foregoing is by way of example only, and the scope of the invention should be determined from appropriate interpretation of the appended claims and equivalents thereof.

Statement and discussion of XIV

While various embodiments of the present disclosure and related features, aspects, and characteristics have been described throughout the present disclosure, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible so as to be within the scope of any corresponding invention that will be described herein. For example, the present invention is not limited to the materials, process techniques, devices, or systems described above. And further, the invention may be combined, integrated, assembled, or linked together, individually or otherwise, with any other number of relevant, selected, or suitable aspects of the invention, as described throughout this disclosure, in various desired combinations, to even further improve the performance of integrated circuits, power amplifiers, power amplifier modules, and devices in which they are used.

Headings are provided in the specification for convenience only and do not necessarily affect the scope or meaning of the claims appended hereto.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; i.e., in the sense of "including, but not limited to". The word "coupled" as generally used herein refers to two or more elements that may be connected directly or by way of one or more intermediate elements. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application, unless the context of the present disclosure would indicate a particular section of the implementation contemplated thereby. Words in the above embodiments that use the singular or plural number may also include the plural or singular number, respectively, where the context permits. Reference to the word "or" in a list of two or more items encompasses all of the following interpretations of the word including: any one of the items in the list, all of the items in the list, and any combination of the items in the list.

The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks or steps thereof are presented in a given order, alternative embodiments may perform routines having steps, or use systems having blocks, in a different order, and some processes, blocks or steps may be deleted, moved, added, subdivided, combined and/or modified. Each of these processes, blocks or steps may be implemented in a number of different ways. Further, while processes, blocks, or steps are sometimes shown as being performed in series, these processes, blocks, or steps may instead be performed in parallel, or may be performed at different times.

The teachings of the invention provided herein may be applied to other systems and not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

And further, while the invention has been described in detail with reference to certain preferred embodiments, it is to be understood that the invention is not limited to the precise embodiments described. Rather, in view of the present disclosure which describes the current best mode for practicing the disclosure, many modifications and variations will present themselves to those skilled in the art without departing from the scope and spirit of this disclosure. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes, modifications and variations coming within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims (29)

1. A power amplifier module, comprising:

a power amplifier comprising a gallium arsenide (GaAs) bipolar transistor having a collector, an emitter, and a base adjoining the collector, the collector having at least about 3 x 10 at a junction with the base¹⁶cm^-3The collector further having at least a first grading in which the doping concentration increases in a direction away from the base; and

an RF transmit line driven by the power amplifier, the RF transmit line comprising a conductive layer and a surface treatment plating on the conductive layer, the surface treatment plating comprising a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer comprising nickel and having a thickness of less than about the skin depth of nickel at 0.9 GHz.

2. The power amplifier module of claim 1 further comprising an output matching network having: a first termination circuit configured to match a fundamental frequency of an output of the power amplifier; and a second termination circuit configured to terminate at a phase of a harmonic of the output of the power amplifier, the first termination circuit including at least a portion of the RF transmit line.

3. The power amplifier module of claim 1 wherein the power amplifier is included on a power amplifier die having a tantalum nitride terminated through-wafer via.

4. The power amplifier module of claim 3, wherein the power amplifier die further comprises: a GaAs substrate; a gold layer disposed on a first side of the GaAs substrate; and a copper layer disposed on a second side of the GaAs substrate opposite the first side, the tantalum nitride terminated through-wafer via configured to electrically connect the gold layer to the copper layer.

5. The power amplifier module of claim 4 wherein the power amplifier die further comprises a tantalum nitride termination region configured to surround at least a portion of an interface between the copper layer and the gold layer so as to inhibit diffusion of copper from the copper layer into the GaAs substrate.

6. The power amplifier module of claim 1 wherein the GaAs bipolar transistor is a heterojunction bipolar transistor, HBT, included on a power amplifier die, the power amplifier die further including a resistor formed from at least one HBT layer.

7. The power amplifier module of claim 1, further comprising: a wire bond in contact with the gold layer of the RF transmission line; at least one edge adjacent to the wire bond; and at least one sidewall adjacent to the at least one edge, the at least one sidewall being free of the diffusion barrier layer of the RF transmission line, the palladium layer of the RF transmission line, and the gold layer of the RF transmission line.

8. The power amplifier module of claim 1, further comprising:

a dual mode control interface having a front end core configured to provide a serial interface;

a voltage input/output (VIO) pin configured to receive a VIO signal that determines whether an operating mode of the front-end core is set to one of an active state and an inactive state, the dual-mode control interface configured to provide a general purpose input/output (GPIO) interface when the front-end core is set to the inactive state;

a combinational logic block configured to provide an enable signal and a mode signal to the enable level shifter and the mode level shifter, respectively; and

a power-on reset configured to select the enable signal and the mode signal to be provided to the enable level shifter and the mode level shifter, respectively, based on the VIO signal.

9. The power amplifier module of claim 1 further comprising an RF isolation structure including wire bonds disposed along a periphery of the power amplifier module.

10. A power amplifier module, comprising:

a power amplifier configured to receive an RF input signal and generate an amplified RF output signal, the power amplifier comprising a GaAs bipolar transistor having a collector, an emitter, and a base adjoining the collector, the collector having at least about 3 x 10 at a junction with the base¹⁶cm^-3The collector further having at least a first grading in which the doping concentration increases in a direction away from the base; and

an output matching network, comprising: a first termination circuit configured to match an impedance of a fundamental frequency of the amplified RF output signal; and a second termination circuit separate from the first termination circuit, the second termination circuit configured to terminate with a phase corresponding to a harmonic frequency of the amplified RF output signal.

11. The power amplifier module of claim 10 wherein the power amplifier drives an RF transmit line having a diffusion barrier layer comprising nickel and having a thickness of less than about 0.5 μ ι η.

12. The power amplifier module of claim 11 wherein a wire bond electrically connects an output of the power amplifier to the RF transmit line, the wire bond included in the first termination circuit.

13. The power amplifier module of claim 11, further comprising a dual mode control interface configured to provide both a Radio Frequency Front End (RFFE) serial interface and a tri-mode general purpose input/output (GPIO) interface on a single die.

14. The power amplifier module of claim 11 further comprising an RF isolation structure including wire bonds disposed along a periphery of the power amplifier module.

15. A power amplifier module, comprising:

a power amplifier configured to receive an RF input signal and generate an amplified RF signal;

an RF transmit line configured to propagate the amplified RF signal, the RF transmit line comprising: a gold layer configured to receive the amplified RF signal; a palladium layer proximate the gold layer; and a diffusion barrier layer proximate to the palladium layer; and a conductive layer proximate to the diffusion barrier layer, the diffusion barrier layer comprising nickel and having a thickness less than about a skin depth of nickel at 0.45 GHz;

A first termination circuit configured to match an impedance of a fundamental frequency of the amplified RF signal, the first termination circuit including at least a portion of the RF transmit line; and

a second termination circuit separate from the first termination circuit, the second termination circuit configured to terminate in a phase corresponding to a harmonic frequency of the amplified RF signal, the power amplifier electrically coupled to the first termination circuit by way of at least one wire bond and the power amplifier electrically coupled to the second termination circuit by way of a different number of wire bonds than the first termination circuit.

16. The power amplifier module of claim 15 wherein the power amplifier comprises a GaAs bipolar transistor having a collector, an emitter, and a base adjoining the collector, the collector having at least about 3 x 10 at a junction with the base¹⁶cm^-3The collector further having at least a first grading in which the doping concentration increases in a direction away from the base.

17. The power amplifier module of claim 15, further comprising a dual mode control interface configured to provide both a Radio Frequency Front End (RFFE) serial interface and a general purpose input/output (GPIO) interface on a single die.

18. The power amplifier module of claim 15 further comprising an RF isolation structure including wire bonds disposed along a periphery of the power amplifier module.

19. A power amplifier module, comprising:

a substrate configured to receive a plurality of components, the substrate including an RF transmission line thereon, the RF transmission line including an electrically conductive layer and a surface treatment plating on the electrically conductive layer, the surface treatment plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness less than a skin depth of nickel at a frequency of about 0.45 GHz;

a first die coupled to the substrate, the first die including a power amplifier having an output electrically connected to the gold layer of the RF transmission line, the first die further including passive components; and

a second die coupled to the substrate, the second die including bias generation circuitry configured to generate a bias signal based at least in part on an indicator of a property of the passive component of the first die.

20. The power amplifier module of claim 19 further comprising an output matching network having: a first termination circuit configured to match a fundamental frequency of the output of the power amplifier; and a second termination circuit configured to terminate at a phase of a harmonic of the output of the power amplifier, the first termination circuit including at least a portion of the RF transmit line.

21. The power amplifier module of claim 19 wherein the first die has tantalum nitride terminated through-wafer vias.

22. The power amplifier module of claim 19 wherein the first die includes HBT devices and resistors formed from at least one HBT layer.

23. The power amplifier module of claim 19, further comprising an RF isolation structure including a plurality of vias in the substrate disposed around the power amplifier and wire bonds disposed along a periphery of the power amplifier module, the plurality of vias having a higher density in a first region of the power amplifier module than a second region of the power amplifier module, the first region associated with higher electromagnetic interference than the second region.

24. A power amplifier module, comprising:

a substrate configured to receive a plurality of components, the substrate having a surface treatment plating comprising a layer of gold, a palladium layer proximate the layer of gold, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer comprising nickel and having a thickness less than about a skin depth of nickel at 0.45 GHz;

A power amplifier die including a power amplifier and at least one tantalum nitride terminated through-wafer via, the power amplifier configured to receive an RF input signal and generate an amplified RF signal; and

a termination circuit configured to terminate with a phase of a harmonic of the amplified RF signal, the termination circuit including at least one wire bond configured to electrically couple an output of the power amplifier to the gold layer of the surface treatment plating.

25. The power amplifier module of claim 24 wherein the power amplifier die comprises: a passive component on a die; a first lead electrically connected to the on-die passive component; and a second lead configured to receive the amplified RF signal.

26. The power amplifier module of claim 25 wherein a first portion of the surface treatment plating is electrically connected to the first lead and a second portion of the surface treatment plating is electrically connected to the second lead to thereby conduct current from the first portion of the surface treatment plating.

27. The power amplifier module of claim 24 wherein the power amplifier die includes a heterojunction bipolar transistor and a resistor including a layer of heterojunction bipolar material.

28. The power amplifier module of claim 24 wherein the power amplifier comprises a GaAs bipolar transistor having a collector, an emitter, and a base adjoining the collector, the collector having at least about 3 x 10 at a junction with the base¹⁶cm^-3The collector further having at least a first grading in which the doping concentration increases in a direction away from the base.

29. The power amplifier module of claim 24, further comprising:

a dual mode control interface having a front end core configured to provide a serial interface;

a voltage input/output (VIO) pin configured to receive a VIO signal that determines whether an operating mode of the front-end core is set to one of an active state and an inactive state, the dual-mode control interface configured to provide a general purpose input/output (GPIO) interface when the front-end core is set to the inactive state;

a combinational logic block configured to provide an enable signal and a mode signal to the enable level shifter and the mode level shifter, respectively; and

a power-on reset configured to select the enable signal and the mode signal to be provided to the enable level shifter and the mode level shifter, respectively, based on the VIO signal.