HK1204507B - Semiconductor device - Google Patents

Description

Semiconductor device with a plurality of semiconductor chips

The present application is a divisional application of the chinese invention patent application, the title of the original application is "semiconductor device", the application number of the original application is 201010222675.2, and the date of the application of the original application is 6/30/2010.

Cross Reference to Related Applications

This application is based on and claims the benefit of priority from japanese patent application No.2009-166975, filed on 7/15/2009, the entire disclosure of which is incorporated herein by reference.

Technical Field

The present invention relates to a semiconductor device including a wiring board and an Integrated Circuit (IC) chip mounted on the wiring board, and particularly relates to a heat dissipation structure in the semiconductor device.

Background

The heat value of an IC chip such as a liquid crystal driver IC during operation is increasing. In a semiconductor device using a flexible wiring board, an increase in the heat value of an IC chip is particularly remarkable as compared with a semiconductor device using a rigid wiring board. Accordingly, heat dissipation structures in semiconductor devices are becoming increasingly important.

The flexible wiring board has the following structure: a conductor layer such as a wire is formed on the flexible insulating film. For example, the conductor layer is formed by applying a copper foil to a polyimide film as an insulating film. The flexible wiring board has a lower heat capacity and a lower mechanical strength for a thin profile than the rigid wiring board. Therefore, it is often difficult to mount a heavy component such as a heat sink onto the flexible wiring board.

In order to deal with the thermal problem when using a flexible wiring board, japanese unexamined patent application publication nos. 2007-158001 and 2004-111996 disclose a heat dissipation structure of a Tape Carrier Package (TCP), which is a type of semiconductor device using a flexible wiring board. The TCP disclosed in Japanese unexamined patent application publication No.2007-158001(JP 2007-158001A) has the following structure. That is, an IC chip having an electrode for heat dissipation spaced apart from an electrode for signal input/output with an external device is mounted on the flexible wiring board. In addition, on the surface of the flexible wiring board, a heat dissipation conductive pattern physically isolated from the signal line pattern is formed. The heat dissipation electrodes of the IC chip and the heat dissipation conductive patterns of the wiring board are connected by conductors (gold bumps, solder, etc.). In this specification, connection by a conductor such as a gold bump or solder is referred to as "conductor connection".

Japanese unexamined patent application publication No. 2004-. However, in JP2004-111996a, no electrode in the IC chip is connected to the heat dissipating conductive pattern. Specifically, JP 2004-. More specifically, fig. 3 and 6 in JP2004-111996a show the following structure: no electrode in the IC chip is in conductor connection with the heat dissipation conductive pattern, and the heat dissipation conductive pattern is formed so as to oppose the entire short-side length of the rectangular IC chip.

Disclosure of Invention

As described above, the semiconductor device disclosed in JP 2007-158001A has a heat dissipation structure in which the heat dissipation conductive pattern formed on the flexible wiring board and the heat dissipation electrode of the IC chip are connected by a conductor having low thermal resistance. The thermal resistance between the IC chip and the heat dissipation conductive pattern is thereby reduced, so that the heat dissipation effect is improved. However, there are many cases where conductor connection cannot be made between the electrodes of the IC chip and the heat dissipation conductive pattern, for example, when terminals having different potentials are irregularly arranged near the IC chip or when electrostatic discharge (ESD) is concerned. For example, when the IC chip is a driver IC for driving a liquid crystal display panel, the driver IC may be damaged by discharge when a human body charged with electricity comes into contact with the liquid crystal display panel. Because the heat dissipating conductive pattern generally has a large surface area for enhancing heat dissipation, the conductor connection between the heat dissipating conductive pattern and the IC chip increases the likelihood of damage to the IC chip caused by ESD.

On the other hand, as described above, the heat dissipation structure disclosed in JP2004-111996A is a structure in which no conductor connection is made between the electrodes of the IC chip and the heat dissipation conductive pattern. Specifically, fig. 3 and 6 in JP 2004-: the heat dissipation conductive pattern is electrically insulated from the chip electrode, and the heat dissipation conductive pattern is formed to be opposite to the entire length of one side of the rectangular chip. This structure has an advantage in that the IC chip can be reliably prevented from being damaged by ESD, and is therefore effective in the case where conductor connection cannot be made between the electrodes of the IC chip and the heat dissipation conductive pattern.

However, it is considered to be practically difficult to adopt a structure in which the electrodes of the IC chip are in physical contact with the heat dissipation conductive pattern without contact between the electrodes of the IC chip and the heat dissipation conductive pattern (fig. 6 in JP2004-111996A), which is one of the heat dissipation structures disclosed in JP 2004-111996A. This is particularly difficult in flip chip packages (face-down packages) in which an IC chip is mounted with the surface of the wiring board on which the functionalized circuits and electrodes are formed facing the wiring board. In order to ensure stable connection, a large number of electrode pads are generally arranged in the peripheral portion of the IC chip, which requires downsizing, and it is generally difficult to make physical contact between the heat dissipation conductive pattern and the IC chip by avoiding contact with the electrodes.

On the other hand, with respect to the structure in the structure (JP2004-111996A) in which the IC chip and the heat dissipating conductive pattern are physically separated, which is another heat dissipating structure disclosed in JP2004-111996A, the length at the interface where the rectangular IC chip and the heat dissipating conductive pattern are placed opposite to each other is as short as the length of the short side of the IC chip. Therefore, heat conduction from the IC chip to the heat dissipation conductive pattern is insufficient, which raises the temperature of the IC chip and thus causes an increase in temperature gradient in the vicinity of the IC chip.

As described above, the heat dissipation structures disclosed in JP 2007-158001A and JP2004-111996A have a problem in that heat conduction from the IC chip to the heat dissipation conductive pattern is insufficient when conductor connection cannot be made between the electrodes of the IC chip and the heat dissipation conductive pattern.

An exemplary aspect of the present invention is a semiconductor device including a wiring board having a conductive pattern formed on at least one main surface, and an IC chip mounted on the wiring board. The IC chip includes a plurality of electrodes for conductor connection with the wiring board.

The conductive pattern includes a lead pattern and a heat dissipation pattern. The lead pattern is connected to at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically separated from each of the chip and the lead pattern, and has a surface area greater than that of the lead pattern.

In addition, the lead line pattern and the heat dissipation pattern are placed to be opposed to each other with a gap therebetween, and opposed portions in the lead line pattern and the heat dissipation pattern respectively have mutually intersecting shapes (interdigitated shapes), and are arranged such that the respective mutually intersecting shapes mesh with each other with a gap therebetween.

According to the exemplary aspects of the present invention described above, heat can be efficiently released from the IC chip by the conductive lead pattern that is conductor-connected to the electrode formation conductors of the IC chip. In addition, since the lead line pattern and the heat dissipation pattern are arranged in such a manner that they are engaged with each other in a shape in which they cross each other with a gap therebetween, it is possible to make the total extension of the gap sufficiently long and reduce the thermal resistance between the lead line pattern and the heat dissipation pattern. Therefore, the thermal resistance from the IC chip to the heat dissipation pattern can be reduced, thereby enhancing the heat dissipation effect. In addition, it is easy to make the total extension of the longitudinal length of the gap longer than the length of the short side of the IC chip.

According to the exemplary aspects of the present invention described above, even when conductor connection is not possible between the electrodes of the IC chip and the heat dissipation pattern, it is possible to reduce the thermal resistance between the IC chip and the heat dissipation conductive pattern and enhance the heat dissipation effect.

Drawings

The above and other exemplary aspects, advantages, and features will become more apparent from the following description of certain exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 is a plan view schematically showing the structure of a semiconductor device according to a first exemplary embodiment of the present invention;

fig. 2 is a plan view schematically showing an example of an electrode layout of an IC chip included in the semiconductor apparatus shown in fig. 1;

fig. 3 is an enlarged plan view showing the vicinity of a lead pattern and a heat dissipation pattern included in the semiconductor device shown in fig. 1;

FIG. 4 is a schematic cross-sectional view taken along line A-A in FIG. 3;

fig. 5A and 5B are a plan view and a temperature distribution diagram of the semiconductor device for describing a heat dissipation effect of the semiconductor device shown in fig. 1;

fig. 5C and 5D are a plan view and a temperature distribution diagram of the semiconductor device according to the comparative example;

fig. 6 is a view showing an alternative example of the lead line pattern and the heat dissipation pattern;

fig. 7A to 7D are views showing alternative examples of the lead wire pattern and the heat dissipation pattern;

fig. 8A to 8E are views showing alternative examples of the lead line pattern and the heat dissipation pattern;

fig. 9A and 9B are views showing alternative examples of the lead line pattern and the heat dissipation pattern;

fig. 10A and 10B are views showing alternative examples of the lead line pattern and the heat dissipation pattern;

fig. 11A and 11B are views showing alternative examples of the lead wire pattern and the heat dissipation pattern;

fig. 12 is a plan view schematically showing the structure of a semiconductor device according to a second exemplary embodiment of the present invention; and

fig. 13 is an enlarged plan view showing the vicinity of the lead pattern and the heat dissipation pattern included in the semiconductor device shown in fig. 12.

Detailed Description

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that in the drawings, structural elements having substantially the same function and structure are denoted by the same reference numerals, and repeated explanation of these structural elements is omitted.

First exemplary embodiment

The semiconductor device according to this exemplary embodiment is a Tape Carrier Package (TCP), and particularly, a TCP incorporating a driver IC for driving a liquid crystal display panel. Fig. 1 is a schematic plan view of a TCP 1 according to an exemplary embodiment. The TCP 1 includes a flexible wiring board 10 and an IC chip 11. The wiring board 10 has the following structure: the conductive pattern is formed of a copper foil or the like on a flexible insulating film such as a polyimide film. The conductive pattern includes an input signal line pattern 12, an output signal line pattern 13, a lead line pattern 14, and a heat dissipation pattern 15. Note that a plurality of conveying holes (pockets) 100 made at regular intervals along both ends of the flexible wiring board 10 are used to carry and position the carrier tape before the TCP 1 is cut.

The IC chip 11 is a flip chip mounted on the main surface of the flexible wiring board 10 on which the conductive pattern is formed. The IC chip 11 has a plurality of first electrodes 111 for outputting and inputting power, display data, control signals, and the like from and to an external device (e.g., a display controller on the input side, a liquid crystal display panel on the output side, and the like), and a plurality of second electrodes 112 that are not normally connected to the external device and are mainly used for ensuring stable connection and heat dissipation.

Fig. 2 is a plan view showing a layout example of the electrodes 111 and 112 formed on the main surface of the IC chip 11. In the example of fig. 2, a plurality of first electrodes 111 are arranged along the long sides of the rectangular main surface of the IC chip 11, and a plurality of second electrodes 112 are arranged along the short sides of the main surface of the IC chip 11. Each of the plurality of first electrodes 111 is bonded to the input signal line pattern 12 or the output signal line pattern 13 through a conductor bump (Au bump, solder bump, or the like). In addition, each of the plurality of second electrodes 112 is bonded to the lead pattern 14 through a conductor bump. Note that this arrangement is merely an example, and the second electrodes 112 need not be arranged only along the short sides, but may be arranged along the long sides or along the two sides.

Referring back to fig. 1, the input signal line pattern 12 and the output signal line pattern 13 are used to input and output power, display data, control signals, and the like between the IC chip 11 and an external device (e.g., a display controller on the input side, a liquid crystal display panel on the output side, and the like). Although not shown in fig. 1, the input signal line pattern 12 includes a plurality of minute input lines, and the output signal line pattern 13 includes a plurality of minute output lines.

The lead line pattern 14 is in conductor connection with at least one of the first electrode 111 and the second electrode 112. The heat dissipation pattern 15 is physically separated from each of the IC chip 11, the signal line patterns 12 and 13, and the lead line pattern 14, and has a larger surface area than the lead line pattern 14. In addition, the lead line pattern 14 and the heat dissipation pattern 15 are disposed opposite to each other with a gap therebetween. Respective portions of the lead line pattern 14 and the heat dissipation pattern 15 which are opposed to each other have mutually intersecting shapes, and they are engaged with each other in the respective mutually intersecting shapes with a gap therebetween. In other words, the boundary lines of the opposing portions in the lead line pattern 14 and the heat dissipation pattern 15 have shapes that intersect each other. The shape of the boundary line may also be regarded as a wave, zigzag, serpentine or star-like shape.

Fig. 3 is an enlarged plan view showing the vicinity of the lead pattern 14 and the heat dissipation pattern 15 located on the right side of the IC chip 11 shown in fig. 1. In the example of fig. 3, the lead line pattern 14 is constituted by five lead lines 141 to 145 separated from each other. Fig. 4 is a schematic cross-sectional view taken along line a-a in fig. 3. In fig. 4, the sealing resin is not shown. As shown in fig. 4, a wire 145 is formed on the flexible insulating film 101 and bonded to the electrode 112 through the conductor bump 113. The other leads 141 to 144 are also bonded to the IC chip 11 through the conductor bumps 113 in the same manner as the lead 145.

In addition, as shown in fig. 3, the leads 141 to 145 are arranged so as to be radiated from the short sides of the IC chip 11. The radial ends of the leads 141 to 145 correspond to the convex portions of the lead pattern 14. In addition, the heat dissipation pattern 15 is arranged to surround the ends of the leads 141 to 145 with a gap 16 therebetween. In other words, the leads 141 to 145 are arranged inside the heat dissipation pattern 15. Specifically, the convex portions 151 to 156 of the heat dissipation pattern 15 extend between the respective lead lines 141 to 145, between the chip 11 and the line 141, and between the chip 11 and the line 145.

In this way, the opposing portions in the lead line pattern 14 (lead lines 141 to 145) and the heat dissipation pattern 15 are designed with an interdigitated structure and are arranged to engage with each other with the gap 16 therebetween, thereby increasing the length of the opposing portions in the pattern 14 and the pattern 15 (i.e., the length of the boundary line or the length of the gap 16). Since the gap 16 as an insulating film has a lower thermal conductivity than the pattern 14 and the pattern 15 made of a conductor such as copper or aluminum, the thermal resistance at the boundary between the pattern 14 and the pattern 15 is caused to increase. However, by making the total extension of the longitudinal length of the gap 16 sufficiently long, the thermal resistance between the lead line pattern 14 and the heat dissipation pattern 15 can be reduced. Note that it is easy to make the total extension of the longitudinal length of the gap 16 longer than the length of the short side of the IC chip 11. Therefore, when conductor connection is not possible between the IC chip 11 and the heat dissipation pattern 15, a higher heat dissipation effect can be expected in the heat dissipation structure according to the exemplary embodiment, as compared with the heat dissipation structure disclosed in JP 2004-.

Hereinafter, with reference to fig. 5A to 5D, a heat dissipation effect by the layout of the lead line pattern 14 and the heat dissipation pattern 15 described in the exemplary embodiment is described. Fig. 5A is a plan view in which isotherms L1 through L8 are added to the layout of the patterns 14 and 15 shown in fig. 3. Fig. 5B is a graph showing a temperature distribution along the X-axis of fig. 5A. On the other hand, fig. 5C is a plan view relating to the comparative example in the case where the boundary line between the patterns 14 and 15 does not have the shape of intersecting with each other. Fig. 5D is a graph showing a temperature distribution along the X-axis in fig. 5C. It should be noted that the structure shown in fig. 5C is designed by the inventor of the present invention for comparison with TCP 1, and therefore this is not a known structure.

As is apparent from the comparison results between fig. 5B and 5D, according to the exemplary embodiment, heat is effectively released from the IC chip 11 to the heat dissipation pattern 15, so that the temperature of the IC chip 11 falls and the temperature of the heat dissipation pattern 15 rises. Thereby, as shown in fig. 5B, the temperature gradient along the boundary P1 of the IC chip 11 becomes less steep.

Since the temperature gradient in the vicinity of the IC chip 11 as a heat source is steep in fig. 5C and 5D, lowering the temperature gradient leads to effective heat dissipation. As shown in fig. 1 and 3, by forming the lead line pattern 14 so as to radially spread from the IC chip 11, the heat dissipation effect can be improved. This is because the radial line layout is along the diffusion direction of the thermal current. By placing the lead line patterns 14 radially in the direction of thermal current diffusion in close proximity to the IC chip 11, the temperature gradient near the IC chip 11 becomes less steep (as shown in fig. 5A and 5B), so that efficient heat dissipation can be performed.

In addition, by using the radial lead line patterns 14, the total area of the lead line patterns 14 can be small. Therefore, the radial lead pattern 14 is particularly effective when attention is paid to breakdown of the IC chip 11 due to ESD.

According to the exemplary embodiment, even when the conductor connection of the heat dissipation pattern 15 and the IC chip 11 is not available for ESD countermeasures, restrictions on the electrode layout of the IC chip 11, or the like, it is possible to reduce the thermal resistance between the IC chip 11 and the heat dissipation pattern 15 and increase the heat dissipation effect. In addition, by making the total extension of the gap 16 sufficiently long, a heat dissipation effect equivalent to that when conductor connection is made between the IC chip 11 and the heat dissipation pattern 15 can be obtained.

Note that the shape of the lead line pattern 14 shown in fig. 1, 3, and 5 is merely an example. For example, when electrical connection is possible, the lead line pattern 14 may have an integrated conductive pattern in which the lead lines 141 to 145 are connected at the central portion 146, as shown in fig. 6.

Alternative examples of the lead line pattern 14 are shown in fig. 7A to 7D and fig. 8A to 8E. Fig. 7A to 7D show alternative examples of the lead line pattern 14 having radial lead lines 141 to 145. Fig. 7A is an example in which each of the leads 141 to 145 shown in fig. 3 is branched to thereby additionally increase the boundary length. Fig. 7B is an example in which each of the lead wires 141 to 145 is widened toward their ends. Fig. 7C and 7D are examples in which the end portion of each of the leads 141 to 145 is wider than the root portion and each has a wavy edge to thereby further increase the boundary length.

Fig. 8A to 8D show alternative examples of the lead line pattern 14 having the non-radial lead lines 141 to 145. Although the non-radial lead line pattern 14 may not be more advantageous than the radial pattern in terms of thermal current diffusion characteristics, it is effective when it is difficult to adopt the radial lead line pattern 14 due to layout restrictions.

In addition, the heat dissipation pattern 15 may be electrically suspended or provided with a certain potential. For example, the heat dissipation pattern 15 may be grounded. In the heat dissipation structure according to the exemplary embodiment, the lead line pattern 14 and the heat dissipation pattern 15 are physically separated from each other. Therefore, when a given potential is supplied to the heat dissipation pattern 15, the heat dissipation structure is also applicable.

In addition, the electrode 112 for heat dissipation may be connected to a power supply potential, a ground potential, or the like within the IC chip 11. Stated differently, the lead line pattern 14 (the lead lines 141 to 145) may be electrically connected to an external device through the internal line of the IC chip 11. In the heat dissipation structure according to the exemplary embodiment, the respective leads 141 to 145 of the lead pattern 14 and the heat dissipation pattern 15 are physically separated from each other, respectively. Therefore, when a given potential is supplied to the respective leads 141 to 145 of the lead pattern 14, a heat dissipation structure is also applicable.

Although the case where the heat dissipation pattern 15 is one island pattern is described above, the heat dissipation pattern 15 may be divided into a plurality of island patterns.

One feature of the heat dissipation structure according to the exemplary embodiment is that the boundary line between the lead wire pattern 14 and the heat dissipation pattern 15 has an interdigitated shape (including a corrugated shape, a zigzag shape, a serpentine shape, or a star-like shape). This layout is generally applicable to a portion in which the lead line pattern 14 and the heat dissipation pattern 15 are arranged in close proximity to each other.

Specifically, it is more preferable that the boundary line (L22) between the lead pattern 14 and the heat dissipation pattern 15, which are opposed to each other with a gap therebetween, have a shape intersecting each other as shown in fig. 9B, as compared with the case where the boundary line (L21) between the pattern 14 and the pattern 15 is a straight line as shown in fig. 9A. In addition, when the lead line pattern 14 includes a plurality of micro-lines (fig. 10A), it is preferable to vary the length of each micro-line and form a comb shape such that a boundary line (L22) between the pattern 14 and the pattern 15 has a shape intersecting each other (fig. 10B). In addition, when both the lead line pattern 14 and the heat dissipation pattern 15 include a plurality of micro-lines, it is preferable to make the respective patterns have a comb shape and mesh with each other with a gap therebetween so that a boundary line (L22) between the patterns 14 and 15 has a shape intersecting each other (fig. 11B).

Second exemplary embodiment

In this exemplary embodiment, application of the conductor pattern layout shown in fig. 9B, 10B, and 11B is described. Fig. 12 is a schematic plan view of TCP 2 according to an exemplary embodiment. In the example of fig. 12, dummy lines (dummy lead lines) are formed in the region 21, and the signal input/output patterns 13 and 14 are not formed in the region 21. It is generally performed in a semiconductor device such as a TCP using a flexible wiring board to form a dummy line in a margin portion. The dummy lines also contribute to heat dissipation of the IC chip 11.

In addition, in the example of fig. 12, a folding line 24 is formed in the region 21. The folding line 24 is connected in a folding manner between two electrodes 112, which are not connected to an external device, among the electrodes of the IC chip 11. For example, fold line 24 is provided for power. When fold line 24 is present, the dashed line is interrupted by fold line 24. In this exemplary embodiment, the layouts of the conductive patterns shown in fig. 9 to 11 are used to improve the thermal conductivity between the divided dummy lines and the folding lines 24.

Fig. 13 is an enlarged plan view showing the vicinity of the folding line 24 provided in the area 21. The folding line 24 is not connected to an external device, and is in conductor connection with the electrode 112 of the IC chip 11. Thus, the folding lines 24 correspond to the lead line patterns 14. In addition, the dummy lines 25 are physically separated from each of the IC chip 11, the signal line patterns 12 and 13, and the folding lines 24 (corresponding to the lead line patterns 14), and the dummy lines 25 have a surface area larger than that of the folding lines 24. Accordingly, the dummy lines 25 correspond to the heat dissipation patterns 15. The dummy lines 26 are connected to dummy electrodes of the IC chip 11 through conductor bumps to ensure stable connection with the flexible wiring board 10. Note that the dummy lines 26 do not have to be in conductor connection with the electrodes of the IC chip 11.

As shown in fig. 13, the opposing portions of the folding line 24 (corresponding to the lead line pattern 14) and the dummy line 25 (corresponding to the heat dissipation pattern 15) have shapes intersecting each other and engage with each other with a gap therebetween, thereby reducing the thermal resistance. Also, it is preferable that the boundary line between the imaginary line 26 on the IC chip 11 side and the folding line 24 also have a mutually intersecting shape. Thereby, the thermal resistance from the IC chip 11 to the dummy line 25 can be reduced.

In the first and second exemplary embodiments of the present invention, the structure in which the lead pattern is in conductor connection with the electrode 112 is described, the electrode 112 is separated from the electrode 111 without being connected to an external device, and the electrode 111 is connected to the external device and mainly used for the purpose of ensuring stable connection and heat dissipation. However, at least one of the input signal line pattern 12 and the output signal line pattern 13 connected to the electrode 111 connected to the external device may be disposed opposite to the heat dissipation pattern 15 with a gap therebetween. In other words, at least one of the input signal line pattern 12 and the output signal line pattern 13 may also function as a wiring pattern.

As described above, in the TCP 1 and the TCP 2, the lead line pattern 14 and the heat dissipation pattern 15 are arranged to engage with each other with a gap therebetween, and thus the thermal resistance can be reduced without making electrical connection between the lead line pattern 14 and the heat dissipation pattern 15. Therefore, the input signal pattern 12 and the output signal line pattern 13, which should avoid electrical connection with the heat dissipation pattern 15, may be used as the lead line pattern 14. In this way, since the signal line patterns 12 and 13 and the like connected to the external device can be used as the lead line patterns 14, the heat dissipation structure having the lead line patterns 14 and the heat dissipation pattern 15 has an advantage in that restrictions on the layout are less.

In addition, in a semiconductor device using a flexible wiring board, particularly in a TCP having a structure in which a conductive layer formed on an insulating film is a single layer and an IC chip is flip-chip mounted on the same main surface as the conductive layer, the heat dissipation structure of the semiconductor device described in the above first and second exemplary embodiments of the present invention is particularly effective. The package is referred to as a Chip On Film (COF). In the COF, it is not necessary to form a hole in a portion of the insulating film opposed to the IC chip, and it is not necessary to use a flying wire. A COF in which a conductive layer is formed only on a main surface of a film and an IC chip is mounted on the main surface is a general packaging type for compatibility with a fine pitch structure and capable of reducing the manufacturing cost of TCP and ensuring flexibility. On the other hand, in the TCP having such a structure, strict layout restrictions are imposed on the conductive pattern, and the IC chip temperature is likely to rise. However, by using the heat dissipation structure described in the first and second exemplary embodiments, the heat dissipation effect can be enhanced when conductor connection is made between the IC chip 11 and the heat dissipation pattern 15.

However, the heat dissipation structure of the semiconductor device described in the first and second exemplary embodiments can also be applied to a semiconductor device using a flexible wiring board different from the TCP. In addition, the wiring layer (conductive layer) of the flexible wiring board may have a multi-layer structure. In addition, conductive layers may be formed simultaneously on both main surfaces of the flexible wiring board. Further, mounting the IC chip 11 into the flexible wiring board 10 is not limited to the flip-chip mounting described above. For example, it is applicable to Tape Automated Bonding (TAB) mounting. In addition, the heat dissipation structure can also be applied to a semiconductor device using a rigid wiring board, not limited to a flexible wiring board.

One of ordinary skill in the art may combine the first and second exemplary embodiments as desired.

While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that various modifications of the invention can be practiced without departing from the spirit and scope of the appended claims, and that the invention is not limited to the examples described above.

In addition, the scope of the claims is not limited by the above-described exemplary embodiments.

Further, it is noted that, applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution.

Claims (7)

1. A semiconductor device, comprising:

a semiconductor chip, the semiconductor chip being substantially rectangular in shape, having: a front side; a first side extending in a first direction; and a plurality of bump electrodes formed on the front surface and extending along the first side; and

a wiring substrate having: a major surface; and a plurality of wirings formed on the main surface of the wiring substrate; the semiconductor chip is mounted on the wiring substrate such that the front surface of the semiconductor chip faces the main surface of the wiring substrate in a plan view, the wiring substrate having a second side that is disposed outside the semiconductor chip and extends substantially parallel to the first side of the semiconductor chip,

wherein the plurality of wirings include a first lead-out pattern, a second lead-out pattern, and signal wirings,

wherein the plurality of bump electrodes include: a first bump electrode; second bump electrodes disposed at both sides of the first bump electrodes; and a third bump electrode formed on the first substrate,

wherein one end portion of the first lead-out pattern is electrically connected to the first bump electrode,

wherein one end portion of the signal wiring is electrically connected to the third bump electrode, and the other end portion of the signal wiring extends toward the second side of the wiring substrate,

wherein the second extraction pattern has a first portion extending in the first direction in which the first portion has a width greater than a width of a second portion and a second portion extending from the first portion toward the second bump electrode,

wherein the second portion of the second lead-out pattern is electrically connected with the second bump electrode to thereby surround the first lead-out pattern in a plan view,

wherein the first extraction pattern includes a plurality of micro-lines extending in a second direction perpendicular to the first direction,

wherein each of the second portions of the second extraction patterns includes micro-lines extending in the second direction, and

wherein the other end portion of the first lead-out pattern is terminated near the first portion of the second lead-out pattern, compared with the first edge of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,

wherein the second bump electrode is a power supply bump electrode, and

wherein the second lead out pattern is electrically connected to the second bump electrode.

3. The semiconductor device according to claim 1, further comprising:

a heat dissipation pattern formed on the main surface of the wiring substrate,

wherein the heat dissipation pattern is arranged near the first portion of the second lead-out pattern on a side opposite to the first lead-out pattern in a plan view.

4. The semiconductor device according to claim 3, wherein the first and second semiconductor layers are stacked,

wherein the heat dissipation pattern includes a dummy pattern that is not electrically connected to the semiconductor chip.

5. The semiconductor device according to claim 4, wherein the first and second semiconductor layers are stacked,

wherein the semiconductor chip does not overlap the heat dissipation pattern in a plan view.

6. The semiconductor device according to claim 3, wherein the first and second semiconductor layers are stacked,

wherein a length of each of the signal wirings is greater than a length of each of the first lead-out patterns in the second direction in a plan view.

7. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,

wherein the wiring substrate includes a tape substrate including an insulating film.