HK1204161B - Process-compensated hbt power amplifier bias circuits and methods - Google Patents

Description

Process compensated HBT power amplifier bias circuit and method

RELATED APPLICATIONS

The present disclosure claims priority from provisional application No. us 61/659,701 entitled "PROCESS-COMPENSATED HBT POWER amplifier biasing circuit AND method" filed on day 14/6/2012 AND provisional application No. us 61/659,834 entitled "RF POWER amplifier having a SEMICONDUCTOR resistor" filed on day 14/6/2012, the disclosure of which is expressly incorporated herein in its entirety by reference.

Technical Field

The present disclosure relates generally to power amplifiers. More particularly, the present disclosure relates to Heterojunction Bipolar Transistor (HBT) power amplifier bias circuits.

Background

A power amplifier is typically an active element that can amplify an input signal to produce an output signal that is significantly larger than the input signal. There are many types of power amplifiers and there are many ways to manufacture power amplifiers. For example, some power amplifiers may be fabricated using Heterojunction Bipolar Transistors (HBTs).

In some such configurations, the diode stack bias configuration exhibits sensitivity to device β (beta), which can result in significant quiescent current variations of the amplifier.

Disclosure of Invention

According to some embodiments, the present disclosure relates to a system for biasing a power amplifier. The system may include a first die including a power amplifier circuit and a passive component having an electrical property that depends on one or more states of the first die. Further, the system may include a second die including a bias signal generation circuit configured to generate a bias signal based at least in part on a measurement (measurement) of an electrical property of a passive component of the first die.

In some cases, the first die comprises a Heterojunction Bipolar Transistor (HBT) die and the second die comprises a silicon die. Further, the passive component may include a resistor formed from a portion of the HBT die. Further, the electrical property of the passive component may include an electrical resistance.

In some embodiments, the one or more states may include process variations of the HBT die.

Further, in some cases, the bias signal generation circuit includes a V-I circuit configured to provide a reference current to the resistor. The reference current may have a value that depends on the resistance of the resistor. Further, in some cases, the V-I circuit provides the reference current based on a PTAT reference voltage that is substantially independent of one or more states of the first die. Further, in some cases, the V-I circuit is further configured to generate the bias signal based on a reference current sunk by the resistor.

Certain embodiments described herein relate to power amplifier modules. The power amplifier module may include a package substrate configured to house a plurality of components, and further, the power amplifier module may include a first die mounted on the package substrate. The first die may include a power amplifier circuit and a passive component having an electrical property that depends on one or more states of the first die. Further, the power amplifier may include a second die mounted on the packaging substrate and interconnected with the first die. The second die may include a bias signal generation circuit configured to generate a bias signal based at least in part on a measurement of an electrical property of a passive component of the first die.

In some examples, the first die comprises a III-V semiconductor die mounted on the packaging substrate. Further, the first die may include an HBT having a selected layer over a subcollector layer. The first die may also include a semiconductor resistor having a resistive layer disposed laterally with respect to and electrically isolated from the selected layer. The resistive layer and the selected layer may be formed of substantially the same material. Further, the passive component may include the semiconductor resistor.

In some embodiments, the selected layer comprises a base layer. Further, in some cases, the selected layer comprises a sub-collector layer. The semiconductor resistor may further include electrical contact pads disposed on the resistive layer to produce a resistance value of the semiconductor resistor. In some examples, the semiconductor resistor is connected to circuitry located outside the first die. Further, the semiconductor resistor may be configured to be sensitive to a change in one or more states associated with the selected layer of the HBT.

Additional embodiments described herein relate to wireless devices. The wireless device may include a transceiver configured to process RF signals. Further, the wireless device may include an antenna in communication with the transceiver, the antenna configured to facilitate transmission of the amplified RF signal. Further, the wireless device may include a power amplifier disposed on the first die and connected to the transceiver, and the power amplifier is configured to generate the amplified RF signal. The first die may include a passive component having an electrical property that depends on one or more states of the first die. Further, the wireless device may include a bias circuit disposed on the second die and interconnected to the power amplifier. The bias circuit may be configured to generate a bias signal for the power amplifier based at least in part on a measurement of an electrical property of a passive component of the first die.

Some embodiments described herein relate to semiconductor die. The semiconductor die may include a substrate configured to accommodate a plurality of components. Further, the semiconductor die may include a Heterojunction Bipolar Transistor (HBT) disposed on the substrate. The HBT may comprise a base formed of a base material. Further, the semiconductor die may include a resistor disposed on the substrate and formed from the base material. In some embodiments, the resistivity of the base material is dependent on at least one state of the HBT. Further, the semiconductor die may include electrical contacts formed on the resistor such that the resistance between the electrical contacts substantially follows the at least one state of the HBT.

According to some embodiments, the present disclosure relates to III-V semiconductor die. The III-V semiconductor die may include a substrate and an HBT formed on the substrate. Further, the HBT may include selected layers over the subcollector layer. Further, the III-V semiconductor die may include a semiconductor resistor disposed over the substrate. The semiconductor resistor may include a resistive layer disposed laterally with respect to and electrically isolated from the selected layers. The resistive layer and the selected layer may be formed of substantially the same material.

In some cases, the substrate comprises GaAs. Further, the selected layer may include an emitter layer. Further, the selected layer may include a base layer. In some cases, the selected layer may comprise an ion implanted base layer.

In some embodiments, the semiconductor resistor is connected to the HBT. Further, the semiconductor resistor may be configured to provide a ballast resistance for the HBT. In some cases, the semiconductor resistor is connected to circuitry located outside of the die. Further, the semiconductor resistor may be configured to be sensitive to a change in one or more states associated with the selected layer of the HBT.

For some cases, the semiconductor resistor further includes electrical contact pads disposed on the resistive layer to produce a resistance value of the semiconductor resistor. In some examples, the selected layer and the resistive layer are formed during the same processing step. Further, in some cases, the layer structure underlying the selected layer and the resistive layer is substantially the same. Further, in some embodiments, the die is substantially free of thin film resistors.

Some embodiments described herein relate to III-V semiconductor die that may include a substrate and a stack structure formed on the substrate. The stack structure may include selected layers. Further, the III-V semiconductor die may include a semiconductor resistor disposed over the substrate. The semiconductor resistor may include a resistive layer disposed laterally with respect to and electrically isolated from the stack structure. Further, the resistive layer and the selected layer may be formed of substantially the same material.

In some embodiments, the III-V semiconductor die further includes electrical contact pads disposed on the resistive layer and configured for external connection of the semiconductor resistor. Further, the stack structure may include an HBT. In some cases, the selected layer includes a base layer. Further, in some cases, the selected layer comprises a sub-collector layer.

Certain embodiments described herein relate to power amplifier modules. The power amplifier module may include a package substrate configured to house a plurality of components. Further, the power amplifier module may include a III-V semiconductor die mounted on the packaging substrate. In some cases, the die includes an HBT having a selected layer over a subcollector layer. The die may also include a semiconductor resistor having a resistive layer disposed laterally with respect to and electrically isolated from the selected layer. Further, the resistive layer and the selected layer may be formed of substantially the same material.

Some embodiments described herein relate to wireless devices. The wireless device may include a transceiver configured to process RF signals. Further, the wireless device may include an antenna in communication with the transceiver, the antenna configured to facilitate transmission of the amplified RF signal. Further, the wireless device may include a power amplifier disposed on the III-V semiconductor die and connected to the transceiver, and the power amplifier is configured to generate the amplified RF signal. The die may also include an HBT having a selected layer above the subcollector layer. Further, the die may include a semiconductor resistor having a resistive layer disposed laterally with respect to and electrically isolated from the selected layer. Further, the resistive layer and the selected layer may be formed of substantially the same material.

Drawings

Throughout the drawings, reference numerals are repeatedly used to indicate correspondence between the referred elements. The drawings are provided to illustrate embodiments of the inventive subject matter described herein and not to limit the scope thereof.

Fig. 1 illustrates an embodiment of a Radio Frequency (RF) configuration including an Integrated Circuit (IC) formed on a semiconductor die.

Fig. 2 illustrates an embodiment of an RF configuration in which the IC and die-related components of fig. 1 are formed on a first semiconductor die and the bias circuit of fig. 1 is formed on a second semiconductor die.

Fig. 3 illustrates another embodiment of the RF configuration shown in fig. 2.

Figure 4 illustrates an embodiment of a linear HBT PA die with a standard "diode stack" bias configuration.

Figure 5 illustrates another embodiment of an RF configuration in which an HBT PA die includes a resistor whose resistance Rb is process dependent.

Figure 6 shows an example graph of 1/Rb values for HBT die formed on different wafers (W2 through W10).

Figure 7 shows an example graph of β values for the same HBT die formed on an example wafer W2-W10.

Figure 8 shows an example plot of reference resistance (Rref) versus operating temperature for different power output settings (in dBM) of an HBT PA.

Fig. 9 illustrates an embodiment of a V-I circuit that can generate a compensated control signal.

FIG. 10 shows an example plot of measured output voltage from the V-I circuit versus temperature for different Vbatt settings (2.9V, 3.4V, 3.9V, 4.4V).

Fig. 11A and 11B show example graphs of quiescent current versus temperature for the first and second stages of an uncompensated PA example.

Fig. 12A and 12B show example graphs of quiescent current versus temperature for the first and second stages of a compensated PA example.

FIG. 13 shows an example plot of calculated gain (dB) versus power output (dBm) at three example temperatures (-20 deg.C, 25 deg.C, 85 deg.C).

Fig. 14 shows an exemplary plot of gain versus power output for different combinations of the varying parameters described with reference to fig. 12.

Fig. 15 illustrates an embodiment of a semiconductor die having an Integrated Circuit (IC).

Figure 16 shows an embodiment of an HBT having a stack of layers formed on a semiconductor substrate (e.g., semi-insulating GaAs).

Figures 17A-17G illustrate an embodiment of a semiconductor resistor that may be formed using the various layers associated with the exemplary HBT of figure 16. Fig. 17A1-17G-1 are electrical schematic diagrams of the semiconductor resistor of fig. 17A-17G, respectively.

Fig. 18A and 18B illustrate an embodiment of a semiconductor resistor that may have a thickness "t" that is substantially the same as the thickness of selected layers of the stack, and lateral dimensions "d 1" and "d 2".

Fig. 18C shows that the embodiment of the semiconductor resistor described with reference to fig. 18A and 18B can be represented as a resistor having a resistance "R".

Fig. 19 illustrates an embodiment of a semiconductor resistor formed on a die and having one or more features described herein that may be coupled to a stacked device, such as a transistor (e.g., HBT), on the same die.

Figures 20A-20C illustrate embodiments of configurations of the semiconductor resistor and stack device combination of figure 19.

Fig. 21 illustrates an embodiment when a semiconductor resistor is formed on a die.

Fig. 22A and 22B illustrate an embodiment of a module that may include a package of a bias die and PA having one or more of the features described herein.

Fig. 23 illustrates an embodiment of a wireless device having one or more of the advantageous features described herein.

Detailed Description

The headings, if any, are provided herein for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

Fig. 1 shows a Radio Frequency (RF) configuration 100 that includes an Integrated Circuit (IC)104 formed on a semiconductor die 102. Operation of at least a portion of IC 104 may be facilitated by bias circuit 110 located outside die 102. In some implementations as described herein, a die 102 may include a die-related component 106, the die-related component 106 having one or more operating parameters that depend on one or more conditions associated with the die 102. Non-limiting examples of such die-related components will be described herein in greater detail.

As further shown in fig. 1, the die-related component 106 can be coupled to the bias circuit 110 such that the bias circuit 110 can operate based at least in part on a state of the die-related component 106. Because such states of die-related components 106 represent states of die 102, operating bias circuits in the foregoing manner may allow IC 104 to operate in an improved manner. Various examples of such die-related operations will be described herein in greater detail.

Fig. 2 illustrates that in some implementations, the IC 102 and die-related components 106 of fig. 1 can be formed on a first semiconductor die 102 and the bias circuit 110 (of fig. 1) can be formed on a second semiconductor die 120. Examples of the kinds of the first and second dies 102, 120 will be described herein in more detail.

Fig. 3 shows an example of the two separate die 102, 120 of fig. 2. The first die 102 may be a die 130 based on a Heterojunction Bipolar Transistor (HBT) process technology. As further shown in fig. 3, an IC formed on such a die may include a Power Amplifier (PA) circuit 104. As further shown in fig. 3, the process-related components may include a component 106.

Fig. 3 further illustrates that the second die 120 may be a silicon process technology based die 140. Bias circuit 110 is shown formed on such a die. Although various examples are described herein in the context of HBTs and silicon die, it should be understood that one or more features of the present disclosure may also be applied to other combinations of die types. It should also be understood that although described in the context of PA operation and biasing of such a PA, one or more features of the present disclosure may also be applied to other types of ICs and control of such ICs.

In the context of HBT-based PA die and bias circuits on separate silicon die, the standard "diode stack" bias configuration used in many linear HBT power amplifier designs typically exhibits sensitivity to device β, resulting in significant variations in the quiescent current of the amplifier.

In some cases, more complex circuit designs may be applied to the diode stack biasing approach (apuach), which generally increases circuit area and current drain.

Fig. 4 shows an exemplary linear HBT PA die 10 with the aforementioned standard "diode stack" bias configuration. For illustrative purposes, the example PA die 10 is shown to include two stages 12a, 12 b. It is understood that the number of stages may be more or less than 2. The first stage 12a is shown receiving RF signals to be amplified from the RFIN node 14 through an input matching circuit 16. The output of the first stage 12a is shown as being passed to the second stage 12b through an interstage circuit 18, the interstage circuit 18 providing matching and harmonic termination. The output of second stage 12b is shown as being passed to RFOUT node 22 through output matching and harmonic termination circuit 20.

In the example shown in fig. 4, each PA stage is shown receiving a DC bias current from a CMOS bias circuit (not shown) through input 24. the bias current is shown being provided to a 2xVbe diode mirror with a diode stack to generate a bias signal the design topology thus demonstrates sensitivity to process β, which can result in increased component-to-component variations in quiescent current, affecting gain, efficiency, and linearity.

In some implementations, the present disclosure relates to a PA configuration that utilizes passive devices on an amplifier die to effectively sense die-related parameters (such as β) and compensate for associated effects (such as variations in quiescent current) to improve performance and/or reduce component-to-component variations in products.

In some implementations of the present disclosure, such a discrete reference resistor may be replaced by an integrated resistor on the HBT die.

In some embodiments, the aforementioned base resistor (Rb) type may be configured to generate a high temperature coefficient that may be compensated for by a bias generation circuit in the silicon control die such that the voltage applied across the reference resistor increases with ambient temperature the resulting reference current provided to the amplifier may be substantially constant over a selected range of ambient temperatures and substantially follow HBT process β.

Fig. 5 shows an example configuration 100 in which HBT PA die 130 includes resistor 106, the resistance Rb of resistor 106 being process dependent. Such a resistor may be used as a reference resistance for generating the bias signals for the two example PA stages 104a, 104 b. It should be understood that one or more features associated with the reference resistance and the generation of a bias signal based on such reference resistance may be applied to PA configurations having a greater or lesser number of stages.

In the example configuration 100, one end of the reference resistor 106 is shown connected to the V-I circuit 144; and the other end is shown connected to ground. V-I circuit 144 is depicted on silicon die 140 and is shown to cause current sources 146a, 146b to provide bias signals for first and second stages 104a, 104 b. As described herein, such bias signals may be compensated for variations in one or more states of HBT PA die 130. An example of how the V-I circuit 144 may be configured and operated in conjunction with a Proportional To Absolute Temperature (PTAT) voltage reference 142 and a reference resistor 106 is described in more detail herein.

6-8 show how measurements (measurements) of the resistance (Rref, and also referred to as Rb) associated with the reference resistor 106 can detect β parameter and temperature variations FIG. 6 shows a graph of the 1/Rb values of HBT die formed on different wafers (W2 through W10 FIG. 7 shows a graph of the β values of the same HBT die formed on example wafers W2 through W10 multiple observations can be made one can see in FIG. 7 that there can be die-to-die variations in the β parameter in a given wafer, between different wafers there can also be significant variations in the β parameter similarly one can see in FIG. 6 that there can be significant die-to-die and wafer-to-wafer variations in 1/Rb.

One can also see in figures 6 and 7, empirically, that the wafer-to-wafer value of 1/Rb correlates with the β value, for example, a drop in the average β value for wafers W2 through W5 corresponds to a rise in the average 1/Rb value (hump) for the same wafer.

While not wishing or intending to be bound by any particular theory, some theories associated with the base resistance Rb and β parameters may be considered_bshThe sheet resistance R_bshAnd then can be represented as

R_bsh＝1/(qμ_pN_Aw_b) (1)

Where q is the charge of the carrier, μ_nIs N type carrier mobility, N_AIs the net impurity concentration, and w_bIs the base layer thickness for AlGaAs and Si, the β parameter can be expressed as the DC current gain

Wherein N is_EAnd N_BIs the emitter and base doping concentration, w_EAnd w_BIs the emitter and base thickness, and Δ Ev is the effective valence band barrier height. In some cases, the DC current gain of InGaP may be expressed as

β＝(v_nB/w_b)τ(N_b) (2B)

Which can be processed to indicate

Thus, for variations in the base (which is where most of the variations of Rb and β occur for HBTs), the beta parameter β and the base resistance Rb may respond substantially the same or in a similar manner so that the ratio of these two parameters may be approximately constant.

Figure 8 shows a plot of reference resistance (Rref) versus operating temperature for different power output settings (in dBM) of an HBT PA. One can see that the relationship between Rref and temperature is approximately linear.

As described with reference to fig. 5-8, the base resistance of a PA die (e.g., HBT PA die) may vary with temperature and/or base layer parameters. In some implementations, such a resistance can be used as a reference resistance to generate a control signal (e.g., a bias signal) that compensates for one or more variations associated with temperature and/or base layer parameters. Fig. 9 shows an example V-I circuit 144 that can generate such a compensated control signal.

An example V-I circuit 144 is shown formed on the silicon die 140 and may be configured to receive a Proportional To Absolute Temperature (PTAT) signal (e.g., approximately 0.6V) from a PTAT source 142. Typically (generally) such signals, independent of temperature and process parameters of the HBTPA die, can be provided to the base resistor (106 in fig. 5). For example, the current provided to base resistor 106 may vary depending on the value of base resistance (Rb). In the example shown, a 0.6PTAT voltage provided to an example Rb value of 6k Ω results in a current of approximately 100 μ A being drawn. This current may be used to generate an output voltage from the V-I circuit to generate a reference current Iref to be provided to a PA circuit formed on the HBT die. Such a reference current (Iref) provided to the HBT die is compensated for one or more effects related to the HBT die sensed by base resistor 106.

FIG. 10 shows a plot of measured output voltage from the V-I circuit versus temperature for different Vbatt settings (2.9V, 3.4V, 3.9V, 4.4V). Similar to the substantially linear relationship between reference resistance and temperature, the V-I output voltage is also substantially proportional to the base temperature of the HBT PA die.

To simulate the performance of a power amplifier in different states, the following parameters vary between a nominal value, a high value, and a low value, β parameter, the turn-on voltage Vbe, Ft parameter, resistance, and capacitance the "uncompensated" design of fig. 11A and 11B corresponds to the example configuration of fig. 4, and the "compensated" design of fig. 12A and 12B corresponds to the example configuration of fig. 5.

Fig. 11A and 11B show graphs of quiescent current versus temperature for the first and second stages of the uncompensated PA examples described herein. Different graphs correspond to different combinations of varying parameters. In each of the first and second level simulations, the quiescent current varied by approximately +/-50%.

Fig. 12A and 12B show graphs of quiescent current versus temperature for the first and second stages of the compensated PA examples described herein. Different graphs correspond to different combinations of varying parameters. For the first stage, the quiescent current varies by about +/-10%. For the second stage, the quiescent current varies by about +/-7%. One can see that for these two stages, the relative amount of change in quiescent current in the compensated configuration is much less than that of the uncompensated configuration.

Fig. 13 and 14 show examples of improvements in gain characteristics that can be provided by reduced variation in quiescent current. FIG. 13 shows plots of calculated gain (dB) versus power output (dBm) at three example temperatures (-20 deg.C, 25 deg.C, 85 deg.C). For each temperature, the middle curve corresponds to the nominal configuration; the upper curve corresponds to quiescent current at positive 10% and the lower curve corresponds to quiescent current at negative 10%. It should be noted that 10% is the worst case variation of the compensated configuration described with reference to fig. 12. One can see that the variation of the quiescent current +/-10% is approximately constant with temperature; resulting in good compression performance characteristics.

Fig. 14 shows a plot of gain versus power output for different combinations of the varying parameters described with reference to fig. 12. One can see that all compensated gain curves are ideally contained in a window of 28dB +/-3 dB.

In some implementations, a base resistor having one or more features as described herein can be a semiconductor resistor formed on a III-V semiconductor die (e.g., an HBT die). Additional details regarding such resistors are described herein with reference to fig. 15-21.

Fig. 15 schematically illustrates a semiconductor die 102 having an Integrated Circuit (IC) 104. In some embodiments, such an IC may include one or more semiconductor resistors 106. Examples of such semiconductor resistors are described herein in more detail.

In some implementations, some or all of the thin film (e.g., TaN) resistors associated with the semiconductor die and the IC thereon may be replaced with semiconductor resistors. In some implementations, such semiconductor resistors can be fabricated from one or more actual layers forming a layer stack device such as a Heterojunction Bipolar Transistor (HBT). Such a resistor can be fabricated without additional process steps when the HBT is fabricated. Because multiple such resistors can be fabricated from different layers of the stack (e.g., emitter layer, base layer, and ion implanted base layer of the HBT), flexibility in resistance values and reduction in die size is possible.

Figure 16 shows an example of HBT500 having a stack of layers formed on a semiconductor substrate 510 (e.g., semi-insulating GaAs). As described herein by way of example, different layers of such a stack may be used as semiconductor resistors. It should be understood that although such examples are described in the context of HBT structures, semiconductor resistors may also be formed based on layers associated with other types of stacked devices. Further, although various examples of layer materials are described in the context of the layer materials shown in fig. 16, it should be understood that other materials may also be used.

As shown in fig. 16, a sub-collector layer 512 (e.g., n + GaAs) may be formed over a substrate 510. Collector layer 514 (e.g., n-GaAs) can be formed over subcollector layer 512. Base layer 516 (e.g., p + GaAs) can be formed over collector layer 514. An emitter layer 518 (e.g., n-InGaP) may be formed over the base layer 516. An emitter cap layer 520 (e.g., n-GaAs) may be formed over the emitter layer 518. A bottom contact layer 522 (e.g., n + GaAs) may be formed over emitter cap layer 520. A top contact layer 524 (e.g., InGaAs) may be formed over the bottom contact layer 522.

As further shown in fig. 16, a collector contact 526 may be formed on the subcollector layer 512. A base contact 528 may be formed on the base layer 516. Emitter contact 530 may be formed on top contact layer 524.

Figures 17A-17G illustrate examples of semiconductor resistors that can be formed using the various layers associated with the exemplary HBT500 of figure 16. Fig. 17A1-17G 1 are electrical schematic diagrams of the semiconductor resistor of fig. 17A-17G, respectively. The resistance of the semiconductor resistors on fig. 17A-17G may be based on the contact resistance of the metal-semiconductor interface and the resistance of one or more semiconductor regions. In some implementations, the resistance of the semiconductor resistor can be based on a contact resistance of the metal-semiconductor interface and a resistance of the two or more semiconductor regions.

In the example shown in figure 17A, semiconductor resistor 106 formed on die 102 can include isolated resistive region 612 formed during the step of forming subcollector 512 of HBT 500. Such resistive regions may be formed of n + GaAs, for example, and isolated from HBT500 and other portions of die 102 by isolation features 640 and 642. Electrical contacts 652 may be formed on resistive region 612 so that semiconductor resistor 106 may be used in a circuit.

In some implementations, resistive region 612 may be masked during formation of other upper layers of HBT 500. Upon completion of HBT500, the mask over resistive region 612 may be removed. Electrical contacts 652 for the resistive region 612 may then be formed during the formation of other contacts (e.g., 526, 528, and 530).

Fig. 17A-1 is an electrical schematic diagram of the semiconductor resistor 106 of fig. 17A. As shown in FIG. 17A-1, the resistance between two electrical contacts 652 may be determined by the resistance with resistive region 612 and the metal-semiconductor interface R_C ^AAnother contact resistance of (a) a metal-semiconductor interface R connected in series_C ^AThe contact resistance of (1) was simulated. The contact resistance of the metal-semiconductor interface Rc may be equal to exp (C(Nd)) in proportion ofIs the barrier height (which depends on the work function of the contact metal) and Nd is the doping concentration of the semiconductor material near the contact metal. The contact resistances in fig. 17A-1-17G-1 are different from each other when the semiconductor layers near the electrical contacts have different doping concentrations. The different contact resistances in FIGS. 17A-1-17G-1 may be implemented for semiconductor resistors 106 having selected resistance valuesAnd making a contribution.

In the example shown in fig. 17B, semiconductor resistor 106 formed on die 102 can include an isolated resistive region 614 formed during the step of forming collector 514 of HBT 500. Such resistive regions may be formed of, for example, n-GaAs and isolated from HBT500 and other portions of die 102 by isolation features 640, 642. Electrical contacts 654 may be formed on the resistive regions 614 so that the semiconductor resistor 106 may be used in an electrical circuit.

In some implementations, resistive region 614 may be masked during formation of other upper layers of HBT 500. Upon completion of HBT500, the mask over resistive region 614 may be removed. Electrical contacts 654 for resistive regions 614 may then be formed during the formation of other contacts (e.g., 526, 528, and 530).

Fig. 17B-1 is an electrical schematic diagram of the semiconductor resistor 106 of fig. 17B. The schematic diagram of fig. 17B-1 has a different contact resistance value than the schematic diagram of fig. 17A-1. In addition, the schematic of FIG. 17B-1 also includes the resistance of resistive region 614 in parallel with the resistance of resistive region 612. As shown in fig. 17B-2, the resistance between two electrical contacts 654 may be established by a parallel resistance in series with resistive region 612 and resistive region 614 and further in series with metal-semiconductor interface R_C ^BAnother contact resistance of the series connection of the metal-semiconductor interfaces R_C ^BThe contact resistance of (1) was simulated.

In the example shown in fig. 17C, semiconductor resistor 106 formed on die 102 can include isolated resistive regions 616 formed during the step of forming base 516 of HBT 500. Such resistive regions may be formed of, for example, p + GaAs and isolated from HBT500 and other portions of die 102 by isolation features 640, 642. Electrical contacts 656 may be formed on resistive region 616 so that semiconductor resistor 106 may be used in a circuit.

In some implementations, resistive region 616 may be masked during formation of other upper layers of HBT 500. Upon completion of HBT500, the mask over resistive region 616 may be removed. Electrical contacts 656 for the resistive regions 616 may then be formed during the formation of other contacts (e.g., 526, 528, and 530).

Fig. 17C-1 is an electrical schematic diagram of the semiconductor resistor 106 of fig. 17C. The schematic diagram of fig. 17C-1 has a different contact resistance value from the schematic diagrams of fig. 17A-1 and 17B-1. The schematic of fig. 17C-1 includes a diode at the PN junction between resistive region 614 and resistive region 616. One of these diodes should be reverse biased. Accordingly, the resistance of resistive regions 612 and 614 should not significantly contribute to the resistance between electrical contacts 656. Thus, the resistance between electrical contacts 656 may be established by the resistance in series with resistive region 616, and further with metal-semiconductor interface R_C ^CAnother contact resistance of the series connection of the metal-semiconductor interfaces R_C ^CThe contact resistance of (a) is similar.

In the example shown in figure 17D, semiconductor resistor 106 formed on die 102 can include isolated resistive region 618 formed during the step of forming emitter 518 of HBT 500. Such resistive regions may be formed of, for example, n-InGaP and isolated from HBT500 and other portions of die 102. Electrical contacts 658 may be formed over resistive region 618 so that semiconductor resistor 106 may be used in a circuit.

In some implementations, resistive region 618 may be masked during formation of other upper layers of HBT 500. Upon completion of HBT500, the mask over resistive region 618 may be removed. Electrical contacts 658 for resistive region 618 may then be formed during the formation of other contacts (e.g., 526, 528, and 530).

Fig. 17D-1 is an electrical schematic diagram of the semiconductor resistor 106 of fig. 17D. The schematic of fig. 17D-1 includes a diode at the PN junction between resistive segment 618 and resistive segment 616. One of these diodes should be reverse biased. Accordingly, the resistance of resistive regions 612, 614, and 616 should not significantly contribute to the resistance between electrical contacts 658. Thus, the resistance between electrical contacts 658 may be determined by the resistance with resistive region 618 and metal-semiconductor interface R_C ^DAnother contact resistance of the series connection of the metal-semiconductor interfaces R_C ^DThe contact resistance of (a) is similar.

In the example shown in fig. 17E, semiconductor resistor 106 formed on die 102 can include isolated resistive region 620 formed during the step of forming emitter cap 520 of HBT 500. Such resistive regions may be formed of, for example, n-GaAs and isolated from HBT500 and other portions of die 102. Electrical contacts 660 may be formed on resistive region 620 so that semiconductor resistor 106 may be used in a circuit.

In some implementations, resistive region 620 may be masked during formation of other upper layers of HBT 500. Upon completion of HBT500, the mask over resistive region 620 may be removed. Electrical contacts 660 for resistive region 620 may then be formed during the formation of other contacts (e.g., 526, 528, and 530).

Fig. 17E-1 is an electrical schematic diagram of the semiconductor resistor 106 of fig. 17E. The schematic diagram of fig. 17E-1 is similar to the schematic diagram of fig. 17D-1, except that the resistance of resistive region 620 is included in parallel with the resistance of resistive region 618 and the contact resistance of the metal-semiconductor interface is different. The resistance between electrical contacts 660 may be established by the parallel resistance with resistive regions 618 and 620 and further with metal-semiconductor interface R_C ^EAnother contact resistance of the series connection of the metal-semiconductor interfaces R_C ^EThe contact resistance of (a) is similar.

In the example shown in figure 17F, semiconductor resistor 106 formed on die 102 can include isolated resistive regions 622 formed during the step of forming bottom contact layer 522 of HBT 500. Such resistive regions may be formed of, for example, n + GaAs and isolated from HBT500 and other portions of die 102. Electrical contacts 662 may be formed on the resistive region 622 such that the semiconductor resistor 106 may be used in a circuit.

In some implementations, resistive region 622 can be masked during the formation of one or more other upper layers of HBT 500. Upon completion of HBT500, the mask over resistive region 622 may be removed. Electrical contacts 662 for resistive region 622 may then be formed during the formation of other contacts (e.g., 526, 528, and 530).

Fig. 17F-1 is an electrical schematic diagram of the semiconductor resistor 106 of fig. 17F. The schematic diagram of fig. 17F-1 is similar to the schematic diagram of fig. 17E-1, except that the resistance of resistive region 622 is included in parallel with the resistance of resistive regions 618 and 620 and the contact resistance of the metal-semiconductor interface is different. The resistance between contacts 662 may be in series with the parallel resistance of resistive regions 618, 620, and 622, and further with metal-semiconductor interface R_C ^FAnother contact resistance of the series connection of the metal-semiconductor interfaces R_C ^FThe contact resistance of (a) is similar.

In the example shown in fig. 17G, semiconductor resistor 106 formed on die 102 can include isolated resistive region 624 formed during the step of forming top contact layer 524 of HBT 500. Such resistive regions may be formed of InGaAs, for example, and isolated from HBT500 and other portions of die 102. Electrical contacts 664 may be formed on resistive region 624 so that semiconductor resistor 106 may be used in a circuit.

In some implementations, resistive region 624 may be masked during the formation of one or more of any other upper layers of HBT 500. Upon completion of HBT500, the mask over resistive region 624 may be removed. The electrical contacts 664 for the resistive region 624 may then be formed during the formation of other contacts (e.g., 526, 528, and 530).

Fig. 17G-1 is an electrical schematic diagram of the semiconductor resistor 106 of fig. 17G. The schematic diagram of fig. 17G-1 is similar to the schematic diagram of fig. 17F-1, except that the resistance of resistive region 624 is included in parallel with the resistance of resistive regions 618, 620, and 622, and the contact resistance of the metal-semiconductor interface is different. The resistance between electrical contacts 664 may be in series with the parallel resistance of resistive regions 618, 620, 622, and 624, and further with metal-semiconductor interface R_C ^GAnother contact resistance of the series connection of the metal-semiconductor interfaces R_C ^GThe contact resistance of (a) is similar.

In the example configuration of figures 17A-17G, the resistive region of the top layer of resistor 106 may represent a corresponding layer in the stack of HBT 500. Thus, for example, the resistive region 614 corresponds to the collector 514. Similarly, resistive region 616 corresponds to base 516. The resistance of one or more resistive regions in the resistor 106 may contribute to the overall resistance of the resistor 106. In some cases, the resistance of two or more resistive regions in the resistor 106 may contribute to the overall resistance of the resistor 106. As discussed above, in some implementations, the lower layers may have a relatively small contribution to the resistance of the semiconductor resistor 106 compared to the contribution from one or more upper layers that include electrical contacts. In some cases, the resistance of the top layer of resistor 106 may be correlated with a measurement of a characteristic of a corresponding layer of HBT 500.

The example configurations of fig. 17A-17G show that a selected one of some or all of the layers in the stacked device may be used to form a semiconductor resistor. Such a concept is schematically depicted in fig. 18A, where die 102 is shown as including a stacked device having multiple layers. The selected layer 704 is among such multiple layers; and there may be additional layers above (collectively depicted as 706) and/or additional layers below (collectively depicted as 702). To form the resistive regions 754 corresponding to the selected layer 704, one or more layers collectively depicted as 752 may be formed during the formation of the corresponding lower portion 702 (if present). The desired resistive region 754 may then be formed during the formation of the selected layer 704. If it is desired to form the upper portion 706 of the stack 700, the resistive region 754 may be masked during such a formation step. When such steps are completed, the mask may be removed to allow for the formation of electrical contacts 760. The resulting resistive region 754 with contacts 760 then forms the semiconductor resistor 106.

In some embodiments, as shown in fig. 18A and 18B, the resistive region 754 may have a thickness "t" that is substantially the same as the thickness of the selected layer 704 of the stack 700, and lateral dimensions "d 1" and "d 2". Such dimensions may be selected to produce characteristics of the resistor 106 such as a desired resistance and footprint size. Furthermore, as already described, the resistance of the resistor 106 may in some cases primarily come from the layer with the electrical contacts. Thus, in some cases, the thickness "t" of the top layer of the resistor 106 may be related to the resistance of the resistor 106.

Fig. 18C shows that the semiconductor resistor 106 described with reference to fig. 18A and 18B may be represented as a resistor having a resistance "R". Examples of how such resistors may be used in different applications are described in more detail herein.

Fig. 19 illustrates that, in some embodiments, a semiconductor resistor 106 formed on a die and having one or more features described herein can be coupled with a stacked device, such as a transistor 700 (e.g., HBT), on the same die. 20A-20C illustrate an example of the configuration of FIG. 19. In the illustrated example, semiconductor resistor 106 is shown providing a ballast resistance for the base of HBT 700 (fig. 20A), for the emitter of HBT 700 (fig. 19B in the context of an example NPN configuration), and for the collector of HBT 700 (fig. 19C). Additional details regarding SEMICONDUCTOR ballasting can be found in U.S. patent No. 5,378,922 entitled "hbt WITH SEMICONDUCTOR ballasting (hbt WITH SEMICONDUCTOR ballasting)", the entire contents of which are expressly incorporated by reference and should be considered part of the specification of the present application.

In some embodiments, a resistor 106 having one or more features as described herein may be coupled to the transistor 700 for purposes other than ballasting. In some embodiments, such resistors may be used in circuits having transistors; and not necessarily directly to the transistor.

In some embodiments, a resistor having one or more features as described herein may be implemented on a die and connected to another circuit located outside the die. For example, fig. 21 shows an example in which the semiconductor resistor 106 is formed on the die 102. One terminal (760a) of resistor 106 is shown configured for electrical connection to a location outside die 102, and the other terminal (760b) is shown within die 102. The die 102 may include an integrated circuit (e.g., a power amplifier circuit) having one or more transistors 700; and such circuitry may be controlled from external circuitry (e.g., via terminals 770). For example, a bias circuit located outside die 102 may be such an external circuit. Such a bias circuit may be connected to the resistor 106 and the transistor 700 to allow the transistor to be operated based on parameters obtained from the resistor 106. Because the resistor 106 may be formed of substantially the same material as the layers of the transistor 700, such parameters associated with the resistor 106 may follow the state common to both the transistor 700 and the resistor.

In some implementations, the fabrication of a semiconductor resistor having one or more features as described herein may be achieved without additional processing steps or with very little modification to process steps when compared to the fabrication of one or more stack structures on a given die. Although various examples are described herein in the context of HBTs, it should be understood that similar resistor structures and fabrication methods may be applied to other configurations. For example, additional layers for fabricating devices including the HBT and one or more other transistor structures may be formed. Examples of such devices include, but are not limited to, the examples described in U.S. patent No. 6,906,359 entitled "BIFET with increased linearity AND MANUFACTURABILITY comprising FET (BIFET INCLUDING A FETHAVING INCREASED LINEARITY AND MANUFACTURABILITY)" AND PCT publication No. WO 2012/061632 entitled "apparatus AND method related to STRUCTURES HAVING HBTs AND FETs (DEVICES AND methods related to HAVING HBTs AND FETs)" both of which are expressly incorporated herein by reference in their entirety AND should be considered part of the specification of this application.

In some embodiments, one or more features of the present disclosure may be implemented in a III-V semiconductor die. In some embodiments, such III-V semiconductor die may comprise GaAs based die. Transistors and/or other stack structures formed on such GaAs based die may or may not include HBTs.

As described herein, a number of advantageous features may be provided by semiconductor resistors. Other advantages may include desirable characteristics that provide different values of the temperature parameter of resistance (TCR), for example, by selecting materials associated with the resistor layers. In another example, because of such a range of possible resistance values (e.g., sheet resistance of about 8Ohms/sq (e.g., subcollector) to about 1,000Ohms/sq (e.g., implanted base layer)), the size of the resistor may be optimized or configured in a desired manner. In yet another example, the RF roll-off of a resistor may be selected and/or tuned according to which resistor is selected (e.g., by modifying how the third terminal on the device is biased).

In some embodiments, a PA and bias die having one or more of the features described herein may be implemented in a packaged module. Examples of such modules are shown in fig. 22A (top view) and 22B (side view). The module 300 is shown to include a package substrate 320. Such a package substrate may be configured to house a plurality of components, and may include, for example, a laminate substrate. The components mounted on the package substrate 320 may include one or more die. In the example shown, a PA die (e.g., HBT PA die 130) and a bias die (e.g., silicon bias die 140) are shown mounted on the packaging substrate 320. PA die 130 may include PA circuit 104 and base resistor 106 as described herein; and bias die 140 may include V-I circuit 144 as also described herein. The dies 130, 140 may be electrically connected to other portions of the module and to each other by connections such as bond wires 349. Such connect-wire bonds may be formed between contact pads 337 formed on the die and contact pads 324 formed on package substrate 320. In some embodiments, one or more Surface Mount Devices (SMDs) 343 may be mounted on the package substrate 320 to facilitate various functions of the module 300.

In some embodiments, RF shielding features such as shielding bond wire 351 may be provided to facilitate RF shielding of one or more components (e.g., die 130, die 140, and/or SMD 343). Such RF shielding may inhibit RF signals or noise from passing through areas outside of such components and modules 300. In the context of shield-bond wire 351, such bond wire may be formed on contact pad 326 such that shield-bond wire 351 generally forms a perimeter around a desired area (e.g., near the perimeter of module 300). The size and spacing of such shield-wire bonds may be selected to provide desired RF shielding properties.

In some embodiments, a three-dimensional RF shielding structure may be provided as follows. As shown in fig. 22B, shield-wire bond 351 may be electrically connected to ground plane 330 below the surface of package substrate 320. Such a connection between shield-bond wire 351 and ground plane 330 may be facilitated by contact pad 326 and connection feature 331 (e.g., a via). Over shield-bond wire 351, a conductive layer (e.g., a conductive paint layer) 371 may be provided such that conductive layer 371 is electrically connected to an upper portion of shield-bond wire 351. Accordingly, the conductive layer 371, shield-bond wire 351 and ground plane 330 may form a three-dimensional RF-shield structure.

In some embodiments, the space between the package substrate 320 and the conductive layer 371 may be filled with a molded plastic structure 359. Such a molded structure may provide a number of desirable functions, including protecting the components and wire bonds from external elements, and making it easier to hold the packaged module 300.

In some implementations, a device and/or circuitry having one or more of the features described herein may be included in an RF device, such as a wireless device. Such devices and/or circuits may be implemented directly in a wireless device, in a modular fashion as described herein, or in some combination thereof. In some embodiments, such wireless devices may include, for example, cellular telephones, smart phones, handheld wireless devices with or without telephone functionality, wireless tablets, and the like.

Fig. 23 schematically depicts an example wireless device 400 having one or more of the advantageous features described herein. In the context of biasing of PAs as described herein, a PA die 130 having one or more PAs may be part of the module 300. Such a module may also include bias die 140 having one or more features as described herein. In some embodiments, such PA modules may facilitate, for example, multi-band operation of wireless device 400.

The PAs in module 300 may receive their respective RF signals from transceiver 414 and process the received signals, and transceiver 414 may be configured and operated in a known manner to generate RF signals to be amplified and transmitted. A transceiver 414 is shown interacting with the baseband subsystem 410, the baseband subsystem 410 configured to provide conversion between data and/or voice signals appropriate for a user and RF signals appropriate for the transceiver 414. The transceiver 414 is also shown connected to a power management component 406, the power management component 406 configured to manage power for operation of the wireless device. Such power management may also control the operation of the baseband subsystem 410 and the module 300.

The baseband subsystem 410 is shown connected to the user interface 402 to facilitate various inputs and outputs of voice and/or data provided to and received from a user. The baseband subsystem 410 may also be coupled to a memory 404, the memory 404 configured to store data and/or instructions to facilitate operation of the wireless device and/or to provide storage of information for a user.

In the example wireless device 400, the outputs of the PAs of the module 300 may be matched by matching networks and routed through their respective duplexers 420 and band selection switches 422 to the antenna 424. In some embodiments, each duplexer may allow simultaneous transmit and receive operations with a common antenna (e.g., antenna 424). In fig. 16, the received signal is shown as being routed to an "Rx" path (not shown), which may include, for example, a Low Noise Amplifier (LNA).

A number of other wireless device configurations may utilize one or more of the features described herein. For example, the wireless device need not be a multi-band device. In another example, the wireless device may include additional antennas, such as diversity antennas, and additional connection features, such as Wi-Fi, bluetooth, and GPS.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is to be interpreted in the meaning of "including, but not limited to". As generally used herein, the term "coupled" refers to two or more elements that may be connected directly or through one or more intermediate elements. Moreover, as used in this application, the words "herein," "above," "below," and words of similar import shall refer to this application as a whole and not to any particular portions of this application. Words in the above detailed description using the singular or plural number may also include the plural or singular number, respectively, as the context permits. The word "or" when referring to a list of two or more items covers all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a number of different ways. Further, while processes or blocks are sometimes shown as being performed in series, these processes or blocks may alternatively be performed in parallel, or may be performed at different times.

The teachings of the invention provided herein may be applied to other systems, not necessarily the systems described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the present disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

Claims (16)

1. A system for biasing a power amplifier, the system comprising:

a first die including a power amplifier circuit and a resistor configured to sense an β parameter of the power amplifier, the β parameter being dependent on a characteristic of the first die, an

A second die including a bias signal generating circuit,

the bias signal generation circuit is configured to generate a bias signal based at least in part on a measurement of an β parameter sensed by the resistor of the first die.

2. The system of claim 1, wherein the first die comprises a heterojunction bipolar transistor die and the second die comprises a silicon die.

3. The system of claim 2, wherein the resistor is formed from a portion of a heterojunction bipolar transistor die.

4. The system of claim 3, wherein the resistor is formed from a base material of a heterojunction bipolar transistor die.

5. The system of claim 1, wherein the resistor has a resistance value approximately proportional to a temperature of the first die.

6. The system of claim 3, wherein the bias signal generating circuit comprises a V-I circuit configured to provide a reference current to the resistor, the reference current having a value that depends on a resistance of the resistor.

7. The system of claim 6, wherein the V-I circuit provides the reference current based on a PTAT reference voltage, the PTAT reference voltage independent of one or more states of the first die.

8. The system of claim 6, wherein the V-I circuit is further configured to generate the bias signal based on a reference current sunk by the resistor.

9. A power amplifier module comprising:

a package substrate configured to accommodate a plurality of components;

a first die mounted on the packaging substrate, the first die including a power amplifier circuit and a resistor configured to sense an β parameter of the power amplifier, the β parameter being dependent on a characteristic of the first die, and

a second die mounted on the packaging substrate and interconnected with the first die, the second die including a bias signal generation circuit configured to generate a bias signal based at least in part on a measurement of an β parameter sensed by the resistor of the first die.

10. The power amplifier module of claim 9 wherein the first die comprises a III-V semiconductor die mounted on the packaging substrate, the first die comprising a heterojunction bipolar transistor having a selected layer above a subcollector layer, the resistor being a semiconductor resistor and having a resistive layer disposed laterally with respect to and electrically isolated from the selected layer, the resistive layer and the selected layer being formed of substantially the same material.

11. The power amplifier module of claim 10 wherein the selected layer comprises a base layer.

12. The power amplifier module of claim 10 wherein the selected layers comprise sub-collector layers.

13. The power amplifier module of claim 10 wherein the semiconductor resistor further comprises electrical contact pads disposed on the resistive layer to produce a resistance value of the semiconductor resistor.

14. The power amplifier module of claim 10 wherein the semiconductor resistor is connected to circuitry located outside the first die.

15. The power amplifier module of claim 10 wherein the semiconductor resistor is configured to be sensitive to changes in one or more states associated with the selected layer of the heterojunction bipolar transistor.

16. A wireless device, comprising:

a transceiver configured to process a radio frequency signal;

an antenna in communication with the transceiver, the antenna configured to facilitate transmission of an amplified radio frequency signal;

a power amplifier disposed on a first die and connected to the transceiver and configured to generate the amplified radio frequency signal, the first die including a resistor configured to sense an β parameter of the power amplifier, the β parameter being dependent on a characteristic of the first die, and

a bias circuit disposed on the second die and interconnected to the power amplifier, the bias circuit configured to generate a bias signal for the power amplifier based at least in part on a measurement of the β parameter sensed by the resistor of the first die.