HK1201991B - Integrated circuit stack with low profile contacts - Google Patents

Abstract

The present invention relates to an integrated circuit stack with low profile contacts. An integrated circuit system includes first and second device wafers, each having lateral sides along which a plurality of T-contacts are disposed. The first and second device wafers are stacked together and the lateral sides of the first and second device wafers are aligned such that each one of the plurality of T-contacts of the first device wafer is coupled to a corresponding one of the plurality of T-contacts of the second device wafer. A plurality of solder balls are attached to the lateral sides and are coupled to the plurality of T-contacts. A circuit board includes a recess with a plurality of contacts disposed along lateral sides within the recess. The first and second device wafers are attached to the circuit board such that each one of the plurality of solder balls provide a lateral coupling between the first and second device wafers and the circuit board.

Description

Integrated circuit stack with low profile contacts

Technical Field

The present invention relates generally to semiconductor processing. More specifically, examples of the invention relate to semiconductor processing of stacked integrated circuit systems.

Background

As integrated circuit technology continues to advance, there is a continuing effort to increase performance and density, improve form factor, and reduce cost. Implementation of stacked three-dimensional integrated circuits has been one approach that designers sometimes use to achieve these benefits. Advances in wafer bonding with extremely precise alignment make it possible to fabricate stacked chips on a wafer level. Possible applications may include logic chip bonding to memory, image sensors, and others. This provides the advantages of a smaller form factor, higher performance, and lower cost.

A key challenge in implementing stacked three-dimensional complementary metal oxide semiconductor ("CMOS") image sensors that are becoming ever smaller and faster relates to keeping the overall package height as short as possible because of the continuing trend toward smaller profile devices. For example, as new models are released, smart phones and tablet computers continue to become thinner and lighter, thus requiring the image sensor module to be shorter in order to fit in the thinner smart phones and tablet computers. In addition, stacking of integrated circuits, which has led to continual efforts to increase performance and density and improve form factor, has introduced challenges in dealing with dissipation of heat generated by the stacked integrated circuit dies.

Disclosure of Invention

One embodiment of the present invention provides an integrated circuit system, comprising: a first device wafer having a lateral side, the first device wafer further including a plurality of T-shaped contacts disposed along the lateral side of the first device wafer; a second device wafer having a lateral side, the second device wafer further including a plurality of T-shaped contacts disposed along the lateral side of the second device wafer, wherein the first and second device wafers are stacked together with the lateral side of the first device wafer aligned with the lateral side of the second device wafer such that each of the plurality of T-shaped contacts of the first device wafer is coupled to a corresponding one of the plurality of T-shaped contacts of the second device wafer; a plurality of solder balls attached to the lateral sides of the first and second dies and coupled to the plurality of T-shaped contacts of the first and second device dies; and a circuit board having a recess defined on a surface thereof, the circuit board including a plurality of contacts disposed within the recess along a lateral side, wherein the first and second device wafers are attached to the circuit board within the recess such that each of the plurality of solder balls provides lateral coupling between each of the plurality of T-shaped contacts of the first and second device wafers and the plurality of contacts disposed within the recess of the circuit board along a lateral side.

Another embodiment of the present invention provides an imaging system, including: an image sensor wafer having a lateral side, the image sensor wafer further including a plurality of T-shaped contacts disposed along the lateral side of the image sensor wafer, wherein the image sensor wafer includes a pixel array having a plurality of image sensor pixels; an image sensor processor wafer having a lateral side, the image sensor processor wafer further including a plurality of T-shaped contacts disposed along the lateral side of the image sensor processor wafer, wherein the image sensor and the image sensor processor wafer are stacked together with the lateral side of the image sensor wafer aligned with the lateral side of the image sensor processor wafer, such that each of the plurality of T-shaped contacts of the image sensor wafer is coupled to a corresponding one of the plurality of T-shaped contacts of the image sensor processor wafer, wherein the image sensor processor wafer includes control circuitry coupled to the pixel array to control operation of the pixel array and readout circuitry coupled to the pixel array to readout image data from the plurality of image sensor pixels; a plurality of solder balls attached to the lateral sides of the image processor and image sensor processor wafer and coupled to the plurality of T-shaped contacts of the image sensor and image sensor processor wafer; and a circuit board having a recess defined on a surface thereof, the circuit board including a plurality of contacts disposed within the recess along a lateral side, wherein the image sensor and image sensor processor wafer is attached to the circuit board within the recess such that each of the plurality of solder balls provides lateral coupling between each of the plurality of T-shaped contacts of the image sensor and image sensor processor wafer and the plurality of contacts disposed within the recess of the circuit board along the lateral side.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Figure 1A is a cross-sectional view illustrating an example of first and second device wafers stacked and bonded together in an exemplary imaging system prior to separation according to the teachings of this disclosure.

Figure 1B is a bottom view illustrating an example of first and second device wafers stacked and bonded together in an exemplary imaging system prior to singulation according to the teachings of this disclosure.

Figure 2A is a cross-sectional view illustrating another example of first and second device wafers stacked and bonded together in an exemplary imaging system prior to separation according to the teachings of this disclosure.

Figure 2B is a bottom view illustrating another example of first and second device wafers stacked and bonded together in an exemplary imaging system prior to singulation according to the teachings of the present disclosure.

Figure 3A is a side view illustrating an example of an example imaging system including an integrated circuit system to be attached within an example recess in a circuit board, according to the teachings of this disclosure.

Figure 3B is a side view illustrating an example of an example imaging system including an integrated circuit system that has been attached within an example recess in a circuit board, according to the teachings of this disclosure.

Figure 4 is a diagram illustrating one example of an imaging system including a pixel array having image sensor pixels included in an integrated circuit system attached within an example recess in a circuit board, according to the teachings of this disclosure.

Corresponding reference characters indicate corresponding parts throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments of the present invention. Additionally, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

Detailed Description

As will be shown, methods and apparatus for an image sensing integrated circuit stack with low profile contacts are disclosed. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one embodiment," "an embodiment," "one example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. Thus, the appearances of the phrases such as "in one embodiment" or "in one example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The following is a detailed description of terms and elements used in the description of examples of the invention, with reference to the accompanying drawings.

As will be shown, an imaging system including an integrated circuit stack with low profile contacts according to the teachings of the present invention reduces the overall thickness of the camera module by moving the die electrical connections from the bottom of the integrated circuit stack to lateral sides of the integrated circuit stack. By moving the die electrical connections to the lateral sides, the thickness of the camera module is reduced because any additional thickness required for the solder balls to be on the bottom of the integrated circuit stack is moved to the lateral sides of the integrated circuit stack. Additionally, this allows the chip surface on the bottom of the device wafer of the integrated circuit stack to be coated with a thermally conductive interface material (such as a metal coating and/or a thermally conductive epoxy) and placed adjacent to a metal heat spreader, which can provide additional heat dissipation, according to the teachings of this disclosure.

To illustrate, FIG. 1A is a cross-sectional view illustrating an example of an integrated circuit stack 100A and an integrated circuit stack 100B prior to separation during fabrication according to the teachings of this disclosure. Specifically, in the example depicted in fig. 1A, two device wafers are stacked face-to-face with their top metal interconnects connected together. FIG. 1A also shows that the integrated circuit stack 100A includes a lens stack 106A stacked with a second device wafer 104A, and the integrated circuit stack 100B includes a lens stack 106B stacked with a second device wafer 104B. In the example, the integrated circuit stacks 100A and 100B are included in an imaging system such that the second device wafers 104A and 104B thus include image sensor chips. In the example, the first device wafers 102A and 102B may include memory chips, processor chips, Application Specific Integrated Circuit (ASIC) chips, and the like. The combined stacked wafers are then separated into different integrated circuit stacks 100A and 100B by sawing at the die saw lines 120 as shown.

In other examples, it should be appreciated that the stacked first and second device dies may include a variety of combinations, such as, but not limited to: a memory chip stacked on top of the image sensor; a memory chip stacked on top of the processor chip; a processor chip stacked on top of the image sensor; chips manufactured by different manufacturing processes; smaller chips stacked with a higher individual yield than one larger chip; or stacked chips that save integrated circuit system real estate, increase speed, and/or reduce power.

In the particular example depicted in fig. 1A, the integrated stack 100A includes a first device wafer 102A stacked face-to-face with a second device wafer 104A, and the integrated stack 100B includes a first device wafer 102B stacked face-to-face with a second device wafer 104B. In the illustrated example, the front side 126A of the first device wafer 102A and the front side 128A of the second device wafer 104A are stacked face-to-face at the bonding interface between the first device wafer 102A and the second device wafer 104A such that an image sensor included in the second device wafer 104A is illuminated through the back side 130A of the second device wafer 104A via the lens stack 106A. The front side 126B of the first device wafer 102B and the front side 128B of the second device wafer 104B are stacked face-to-face at the bonding interface between the first device wafer 102B and the second device wafer 104B such that an image sensor included in the second device wafer 104B is illuminated through the back side 130B of the second device wafer 104B via the lens stack 106B. In other examples (not shown), it should be understood that the backsides of the device wafers may be bonded together in an integrated circuit stack, or the front side of one of the device wafers may be bonded to the backsides of the other device wafers in an integrated circuit stack, in accordance with the teachings of this disclosure.

As shown in the illustrated example, the first device wafers 102A and 102B have substantially the same scribe line dimensions as the second device wafers 104A and 104B, such that lateral side 122A of the first device wafer 102A is aligned with lateral side 123A of the second device wafer 104A and lateral side 122B of the first device wafer 102B is aligned with lateral side 123B of the second device wafer 104B. Thus, the T-shaped contact 112A along the lateral side 122A of the first device wafer 102A is coupled to the T-shaped contact 114A along the lateral side 123A of the second device wafer 104B, as shown. Similarly, the T-shaped contact 112B along the lateral side 122B of the first device wafer 102B is coupled to the T-shaped contact 114B along the lateral side 123B of the second device wafer 104B, as shown. In addition, the metal interconnects 116A proximate the front side 126A of the first device wafer 102A are coupled to the metal interconnects 118A proximate the front side 128A of the second device wafer 104A through a bonding interface between the first device wafer 102A and the second device wafer 104A. Similarly, the metal interconnects 116B proximate to the front side 126B of the first device wafer 102B are coupled to the metal interconnects 118B proximate to the front side 128B of the second device wafer 104B by a bonding interface between the first device wafer 102B and the second device wafer 104B.

In the example depicted in fig. 1A, solder masks 108A and 108B are shown deposited over portions of the backsides 124A and 124B of the first device wafers 102A and 102B, leaving openings exposing a "V" shaped region 132 between the integration stacks 100A and 100B that exposes a plurality of T-shaped contacts 112A, 112B, 114A and 114B disposed along the lateral sides 122A, 122B, 123A and 123B of the first device wafers 102A, 102B and the second device wafers 104A and 104B. Solder balls, shown as 110A and 110B, may then be deposited in the "V" shaped region 132 to provide electrical coupling to a plurality of T-shaped contacts 112A, 112B, 114A and 114B along the lateral sides 122A, 122B, 123A and 123B of the first device wafer 102A, 102B and the second device wafers 104A and 104B, as shown. In the example, when the integrated circuit stacks 100A and 100B are separated by sawing the die along the die saw lines 120 as shown, the solder balls are then separated into two halves, as illustrated with solder balls 110A and 110B. After separation, it should be appreciated that the solder balls 110A and 110B may be heated and reshaped as needed, and in one example, only a small number of solder balls 110A and 110B are needed so that the solder balls 110A and 110B may be very large, in accordance with the teachings of the present invention.

Figure 1B is a bottom view illustrating an example of a plurality of device wafers stacked and bonded together in an integrated circuit stack 100A, 100B, 100C, and 100D prior to sawing in accordance with the teachings of the present invention. In one example, the integrated circuit stacks 100A, 100B, 100C, and 100D in fig. 1B are substantially similar to the integrated circuit stacks 100A and 100B in fig. 1A, in accordance with the teachings of this disclosure. In the depicted illustration, solder balls 110 are coupled to a plurality of T-shaped contacts arranged along lateral sides of a plurality of device wafers exposed in "V" shaped regions between integrated circuit stacks 100A, 100B, 100C, and 100D. Fig. 1B also shows the separation of integrated circuit stacks 100A, 100B, 100C and 100D into individual stacks by sawing along die saw lines 120A and 120B that pass through solder balls 110, according to the teachings of the present invention. After separation, it should be appreciated that the solder balls 110 may be heated and reshaped as desired.

Figure 2A is a cross-sectional view illustrating another example of first and second device wafers stacked prior to separation and bonded together in integrated circuit stacks 200A and 200B during fabrication according to the teachings of this disclosure. It should be noted that the integrated circuit stacks 200A and 200B of fig. 2A share many similarities with the integrated circuit stacks 100A and 100B of fig. 1A and that similarly-named and numbered elements mentioned below are coupled and function similarly as described above.

For example, similar to fig. 1A, the integrated stack 200A of fig. 2A includes a first device wafer 202A stacked face-to-face with a second device wafer 204A, and the integrated stack 200B includes a first device wafer 202B stacked face-to-face with a second device wafer 204B. In the illustrated example, the front side 226A of the first device wafer 202A and the front side 228A of the second device wafer 204A are stacked face-to-face at the bonding interface between the first device wafer 202A and the second device wafer 204A such that an image sensor included in the second device wafer 204A is illuminated through the back side 230A of the second device wafer 204A via the lens stack 206A. The front side 226B of the first device wafer 202B and the front side 228B of the second device wafer 204B are stacked face-to-face at the bonding interface between the first device wafer 202B and the second device wafer 204B such that the image sensors contained in the second device wafer 204B are illuminated through the back side 230B of the second device wafer 204B via the lens stack 206B. One difference between the integrated circuit stacks 200A and 200B of fig. 2A and the integrated circuit stacks 100A and 100B of fig. 1A is that, in the integrated circuit stacks 200A and 200B of fig. 2A, the first device wafers 202A and 202B are intermediate carriers or interposed dies disposed between the second device wafers 204A and 204B and the second dies 234A and 234B, respectively, as shown. In the illustrated example, it should be appreciated that the second dies 234A and 234B are separate wafers and on different planes, as shown.

As shown in the example of fig. 2A, the first device wafers 202A and 202B have substantially the same scribe line dimensions as the second device wafers 204A and 204B, such that lateral side 222A of the first device wafer 202A is aligned with lateral side 223A of the second device wafer 204A, and lateral side 222B of the first device wafer 202B is aligned with lateral side 223B of the second device wafer 204B. Thus, the T-shaped contact 212A along the lateral side 222A of the first device wafer 202A is coupled to the T-shaped contact 214A along the lateral side 223A of the second device wafer 204B, as shown. Similarly, the T-shaped contact 212B along the lateral side 222B of the first device wafer 202B is coupled to the T-shaped contact 214B along the lateral side 223B of the second device wafer 204B, as shown. In addition, the metal interconnects 216A proximate the front side 226A of the first device wafer 202A are coupled to the metal interconnects 218A proximate the front side 228A of the second device wafer 204A through a bonding interface between the first device wafer 202A and the second device wafer 204A.

In the example depicted in FIG. 2A, the T-shaped contacts 212A extend along the lateral side 222A to the back side 224A of the first device wafer 202A to provide electrical coupling to the second die 234A. In the example depicted in fig. 2A, the metal interconnects 216B proximate the backside 224B of the first device wafer 202B are coupled to the metal interconnects 218B proximate the frontside 228B of the second device wafer 204B by Through Silicon Vias (TSVs) 250 that pass through the bonding interface between the first device wafer 202B and the second device wafer 204B. In addition, the example shown in FIG. 2A shows the metal interconnects 216B being further coupled to the second die 234B by solder balls 252 to provide electrical coupling to the second die 234B.

In another example, it should be noted that the electrical coupling from both the first die 234A and the second die 234B to their respective stacked wafers may be provided entirely by T-shaped contacts (e.g., similar to T-shaped contacts 212A) rather than a combination of T-shaped contacts and TSVs and solder balls as illustrated in the example of fig. 2A. Similarly, in yet another example, it should be appreciated that electrical coupling from both the first die 234A and the second die 234B to their respective stacked wafers may be provided entirely by TSVs and solder balls (e.g., similar to TSVs 250 and solder balls 252) rather than T-contacts and combinations of TSVs and solder balls as illustrated in the example of fig. 2A. The combined stacked wafer and die are then separated into different integrated circuit stacks 200A and 200B by sawing at die saw lines 220 as shown.

In the example depicted in fig. 2A, solder masks 208A and 208B are shown deposited over portions of the backsides 224A and 224B of the first device wafers 202A and 202B, leaving an opening exposing a "V" shaped region 232 between the integration stacks 200A and 200B, which exposes a plurality of T-shaped contacts 212A, 212B, 214A, and 214B disposed along the lateral sides 222A, 222B, 223A, and 223B of the first device wafers 202A, 202B and the second device wafers 204A and 204B. Solder balls, shown as 210A and 210B, may then be deposited in the "V" shaped region 232 to provide electrical coupling to the plurality of T-shaped contacts 212A, 212B, 214A and 214B along the lateral sides 222A, 222B, 223A and 223B of the first device wafer 202A, 202B and the second device wafers 204A and 204B, as shown. In the example, when the integrated circuit stacks 200A and 200B are separated by sawing the die along the die saw lines 220 as shown, the solder balls are then separated into two halves, as illustrated with solder balls 210A and 210B. After separation, it should be appreciated that solder balls 210A and 210B may be heated and reshaped as needed in accordance with the teachings of the present invention.

Figure 2B is a bottom view illustrating another example of a plurality of device wafers stacked and bonded together in an integrated circuit stack 200A, 200B, 200C, and 200D prior to sawing in accordance with the teachings of the present invention. It should be appreciated that the integrated circuit stacks 200A, 200B, 200C, and 200D in fig. 2B are substantially similar to the integrated circuit stacks 200A and 200B in fig. 2A, in accordance with the teachings of the present disclosure. Figure 2B also shows the bottom of second integrated circuit dies 234A, 234B, 234C and 234D attached to the interposed dies of the integrated circuit stacks 200A, 200B, 200C and 200D in one example. In the depicted illustration, solder balls 210 are coupled to a plurality of T-shaped contacts arranged along lateral sides of a plurality of device wafers exposed in "V" shaped regions between integrated circuit stacks 200A, 200B, 200C, and 200D. In the example of FIG. 2B, the solder balls 210 are also coupled to the second die 234A of the integrated circuit stack 200A through the T-shaped contacts 212, as shown. In the integrated circuit stacks 200B, 200C, and 200D, it should be appreciated that the second dies 234B, 234C, and 234D may be coupled to their respective interposed dies of the integrated circuit stacks 200B, 200C, and 200D by solder balls and/or by TSVs, respectively, similar to the integrated circuit stack 200B as shown in fig. 2A. Figure 2B also shows the separation of the integrated circuit stacks 200A, 200B, 200C, and 200D into individual stacks by sawing along die saw lines 220A and 220B that pass through the solder balls 210, according to the teachings of the present disclosure. After separation, it will be appreciated that the solder ball 210 may be heated and reshaped as desired.

Figure 3A is a side view illustrating an example of an exemplary imaging system 350 including an integrated circuit stack 300 having low-profile contacts to be attached to a circuit board 336 according to the teachings of this disclosure. In one example, it should be appreciated that the example integrated circuit stack 300 shares many similarities with the example integrated circuit stacks 100A and 100B of fig. 1A and that similarly named and numbered elements mentioned below are coupled and function similarly as described above. As shown in the depicted example, the integrated circuit stack 300 includes a first device wafer 302, a second device wafer 304, and a lens stack 306 stacked together, as shown. According to the teachings of the present invention, solder balls 310 are attached to lateral sides 322 and are coupled to a plurality of T-shaped contacts included in integrated circuit stack 300 that are arranged along lateral sides 322.

As shown in fig. 3A, the example circuit board 336 includes a recess 338 defined on a surface thereof. In the example, circuit board 336 is a copper clad circuit board and includes a plurality of contacts 352 disposed along lateral sides within recesses 338 defined in circuit board 336. In the depicted example, a thermally conductive interface material 340 (e.g., a metal and/or a thermally conductive epoxy) is coated on the surface of the recess 338 to which the integrated circuit stack 300 is attached to provide high heat transfer between the integrated circuit stack 300 and the circuit board 336. In another example, it should be appreciated that thermally conductive interface material 340 may be coated onto a surface of integrated circuit stack 300 within recess 338 that makes contact with circuit board 336.

Figure 3B is a side view illustrating an example of an exemplary imaging system 350 including an integrated circuit stack 300 having low-profile contacts that have been attached to a circuit board 336 according to the teachings of this disclosure. In the example, it should be appreciated that the integrated circuit stack 300 and circuit board 336 of fig. 3B are substantially similar to the integrated circuit stack 300 and circuit board 336 discussed above with respect to fig. 3A and that similarly named and numbered elements mentioned below are coupled and function similarly as described above.

As shown in the example depicted in fig. 3B, an integrated circuit stack 300 including a first device wafer 302, a second device wafer 304, and a lens stack 306 is attached to a circuit board 336 within a recess 338 such that each of a plurality of solder balls 310 provides lateral coupling between each of a plurality of T-shaped contacts of the first and second device wafers 302, 304 and a plurality of contacts disposed along lateral sides within the recess 338 of the circuit board 336, in accordance with the teachings of the present invention. Additionally, fig. 3B shows that a thermally conductive interface material 340 is thermally coupled between the first and second device wafers 302, 304 and the inside surface of the circuit board 336 to which the integrated circuits of the recess 338 are attached. In one example, circuit board 336 further includes a heat sink thermally coupled to an inside surface of recess 338 of circuit board 336 to provide additional heat dissipation from integrated circuit stack 300 through circuit board 336 in accordance with the teachings of the present invention.

It should be appreciated that where each of the plurality of solder balls 310 provides lateral coupling between each of the plurality of T-shaped contacts of the first device wafer 302 and the second device wafer 304 and a plurality of contacts disposed along the lateral sides within the recess 338 of the circuit board 336, the overall thickness of the camera module including the imaging system 350 is reduced as the die electrical connection is moved from the bottom to the lateral sides 322 of the integrated circuit stack 300. Thus, according to the teachings of this disclosure, the overall height of the camera module including the imaging system 350 is shorter, which enables electronic devices utilizing camera modules including the imaging system 350 to be thinner. Furthermore, it should be appreciated that in accordance with the teachings of the present invention, the thermally conductive interface material 340 may now provide improved thermal coupling between the first and second device wafers 302, 304 and the circuit board 336 to provide improved heat dissipation in the event that the plurality of solder balls 310 are moved from the bottom to the lateral sides 322 of the integrated circuit stack 300.

Figure 4 is a diagram illustrating one example of an imaging system 400 including an example pixel array 442 having a plurality of image sensor pixels included in an example integrated circuit system including an integrated circuit stack having low-profile contacts, according to the teachings of this disclosure. As shown in the depicted example, the imaging system 400 includes a pixel array 442 coupled to control circuitry 448 and readout circuitry 444 (which is coupled to functional logic 446).

In one example, pixel array 442 is a two-dimensional (2D) array of image sensor pixels (e.g., pixels P1, P2.., Pn). In one example, pixel array 442 is included in an integrated circuit system included in an integrated circuit stack having low-profile contacts (e.g., the integrated circuit stack examples discussed above in fig. 1A, 1B, 2A, 2B, 3A, and 3B). As illustrated, each pixel is arranged into a row (e.g., rows R1-Ry) and a column (e.g., columns C1-Cx) to acquire image data of a person, place, object, etc., which can then be used to render a 2D image of the person, place, object, etc.

In one example, after each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 444 and then transferred to functional logic 446. In various examples, readout circuitry 444 may include amplification circuitry, analog-to-digital (ADC) conversion circuitry, or others. Function logic 446 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry 444 may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels simultaneously.

In one example, the control circuitry 448 is coupled to the pixel array 442 to control an operating characteristic of the pixel array 442. For example, the control circuit 448 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within pixel array 442 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row of pixels, each column of pixels, or each group of pixels is sequentially enabled during successive acquisition windows.

The above description of illustrated examples of the invention, including what is described in the summary, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications can be made without departing from the broader spirit and scope of the invention. Indeed, it should be understood that specific example voltages, currents, frequencies, power range values, times, etc., are provided for purposes of explanation and that other values may also be employed in other embodiments and examples in accordance with the teachings of this disclosure.

These modifications can be made to the examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (20)

1. An integrated circuit system, comprising:

a first device wafer having a lateral side, the first device wafer further including a plurality of T-shaped contacts disposed along the lateral side of the first device wafer;

a second device wafer having a lateral side, the second device wafer further including a plurality of T-shaped contacts disposed along the lateral side of the second device wafer, wherein the first and second device wafers are stacked together with the lateral side of the first device wafer aligned with the lateral side of the second device wafer such that each of the plurality of T-shaped contacts of the first device wafer is coupled to a corresponding one of the plurality of T-shaped contacts of the second device wafer;

a plurality of solder balls attached to the lateral sides of the first and second device wafers and coupled to the plurality of T-shaped contacts of the first and second device wafers;

a circuit board having a recess defined on a surface thereof, the circuit board including a plurality of contacts disposed within the recess along a lateral side, wherein the first and second device wafers are attached to the circuit board within the recess such that each of the plurality of solder balls provides lateral coupling between each of the plurality of T-shaped contacts of the first and second device wafers and the plurality of contacts disposed within the recess of the circuit board along a lateral side; and

a thermally conductive interface material thermally coupled to an inside surface of the circuit board to which the first and second device dies are attached.

2. The integrated circuit system of claim 1, wherein the first and second device wafers each include a front side and a back side such that one of the front side and back side of the first device wafer is attached to one of the front side and back side of the second device wafer at a bonding interface between the first and second device wafers.

3. The integrated circuit system of claim 2, wherein the front side of the first device wafer is attached to the front side of the second device wafer.

4. The integrated circuit system of claim 1, wherein the each of the first and second device wafers further comprises metal interconnects, wherein the metal interconnects of the first device wafer are coupled to the metal interconnects of the second device wafer through a bonding interface between the first and second device wafers.

5. The integrated circuit system of claim 4, further comprising one or more Through Silicon Vias (TSVs) through which the metal interconnect of the first device wafer is coupled to the metal interconnect of the second device wafer through the bonding interface between the first and second device wafers.

6. The integrated circuit system of claim 1, wherein one of the first and second device wafers comprises an image sensor chip and the other of the first and second device wafers comprises a memory chip.

7. The integrated circuit system of claim 1, wherein one of the first and second device wafers comprises an image sensor chip and the other of the first and second device wafers comprises a processor chip.

8. The integrated circuit system of claim 1, wherein one of the first and second device wafers comprises an image sensor chip and the other of the first and second device wafers comprises an Application Specific Integrated Circuit (ASIC) chip.

9. The integrated circuit system of claim 1, further comprising a lens stack attached to the first and second device wafers opposite the circuit board.

10. The integrated circuit system of claim 1, wherein one of the first and second device wafers comprises a memory chip and the other of the first and second device wafers comprises a processor chip.

11. The integrated circuit system of claim 1, wherein the circuit board further includes a heat sink thermally coupled to the inside surface of the circuit board to which the first and second device dies are attached by the thermally conductive interface material.

12. The integrated circuit system of claim 1, wherein the circuit board comprises a copper clad circuit board.

13. An imaging system, comprising:

an image sensor wafer having a lateral side, the image sensor wafer further including a plurality of T-shaped contacts disposed along the lateral side of the image sensor wafer, wherein the image sensor wafer includes a pixel array having a plurality of image sensor pixels;

an image sensor processor wafer having a lateral side, the image sensor processor wafer further including a plurality of T-shaped contacts disposed along the lateral side of the image sensor processor wafer, wherein the image sensor and image sensor processor wafers are stacked together with the lateral side of the image sensor wafer aligned with the lateral side of the image sensor processor wafer, such that each of the plurality of T-shaped contacts of the image sensor wafer is coupled to a corresponding one of the plurality of T-shaped contacts of the image sensor processor wafer, wherein the image sensor processor wafer includes control circuitry coupled to the pixel array to control operation of the pixel array and readout circuitry coupled to the pixel array to readout image data from the plurality of image sensor pixels;

a plurality of solder balls attached to the lateral sides of the image sensor and image sensor processor wafer and coupled to the plurality of T-contact circuit boards of the image sensor and image sensor processor wafer having recesses defined on surfaces thereof, the circuit board including a plurality of contacts disposed within the recesses along lateral sides, wherein the image sensor and image sensor processor wafer is attached to the circuit board within the recesses such that each of the plurality of solder balls provides lateral coupling between each of the plurality of T-contacts of the image sensor and image sensor processor wafer and the plurality of contacts disposed within the recesses of the circuit board along the lateral sides; and

a thermally conductive interface material thermally coupled to an inside surface of the recess of the circuit board to which the image sensor and image sensor processor die are attached.

14. The imaging system of claim 13, further comprising functional logic included in the image sensor processor wafer and coupled to the readout circuitry to store the image data read out from the plurality of image sensor pixels.

15. The imaging system of claim 13, wherein a front side of the image sensor wafer is attached to a front side of the image sensor processor wafer at a bonding interface between the image sensor wafer and the image sensor processor wafer.

16. The imaging system of claim 13, wherein each of the image sensor wafer and the image sensor processor wafer further includes metal interconnects, wherein the metal interconnects of the image sensor wafer are coupled to the metal interconnects of the image sensor processor wafer through a bonding interface between the image sensor wafer and the image sensor processor wafer.

17. The imaging system of claim 16, further comprising one or more Through Silicon Vias (TSVs) through which the metal interconnects of the image sensor wafer are coupled to the metal interconnects of the image sensor processor wafer through the bonding interface between the image sensor wafer and the image sensor processor wafer.

18. The imaging system of claim 13, further comprising a lens stack attached to a backside of the image sensor wafer such that the pixel array is adapted to be illuminated through the lens stack and through the backside of the image sensor wafer, and wherein a front side of the image sensor wafer is attached to the image sensor processor wafer at a bonding interface between the image sensor wafer and image sensor processor wafer.

19. The imaging system of claim 13, wherein the circuit board further includes a heat sink thermally coupled to the inside surface of the recess of the circuit board to which the image sensor and image sensor processor die are thermally attached by the thermally conductive interface material.

20. The imaging system of claim 13, wherein the circuit board comprises a copper clad circuit board.