HK1201985B - Semiconductor device and interconnect substrate - Google Patents

Description

Semiconductor device and interconnection substrate

Cross reference to related applications

The disclosure of Japanese patent application No.2013-081064, filed 2013, 4, 9, including the description, drawings, and abstract, is incorporated herein by reference in its entirety.

Technical Field

The present invention relates to a semiconductor device and an interconnect substrate, and particularly to a technique effective when applied to a semiconductor device capable of high-speed communication.

Background

In recent years, the communication speed in network communication has been further increased, and a signal transmission speed exceeding 10Gbps has been commonly used in network devices. Therefore, signal reflection by parasitic capacitance of an interface buffer (I/O device) of a communication semiconductor device (LSI: large scale integrated circuit) mounted on the network apparatus deteriorates signal quality, which causes a serious problem. It is believed that this phenomenon can be attributed to the fact that the admittance of the parasitic capacitance increases with increasing operating frequency of the I/O device, which significantly lowers the input/output impedance of the I/O device, causing an impedance mismatch between the I/O device and the signal transmission line. For example, it is assumed that an I/O device having a parasitic capacitance on an output side and an I/O device having a parasitic capacitance on an input side are connected with a signal transmission line having a characteristic impedance of 50 Ω. In this case, even when each of the input impedance of the I/O device on the input side and the output impedance of the I/O device on the output side is theoretically defined at 50 Ω, the admittance of the parasitic capacitance of the I/O device on the input side and the output side increases as the frequency of the transmission signal increases, which decreases the input impedance of the I/O device on the input side and the output impedance of the I/O device on the output side. For example, when the parasitic capacitance of the I/O devices on the input side and the output side is 1pF, the input/output impedance of each I/O device is about 45 Ω at 1.25GHz, about 25 Ω at 3.2GHz (corresponding to 6.4 Gbps), and about 14 Ω at 5.0GHz (corresponding to 10 Gbps). Lowering the input/output impedance of the I/O device causes significant impedance mismatch between the signal transmission line and the I/O device, thereby severely distorting the signal waveform.

In order to mitigate the effect of the parasitic capacitance of the I/O device, a technique is currently known in which an impedance matching circuit is formed on a semiconductor chip in which the I/O device is formed, or an inductor (L), a capacitor (C), and a resistor (R) are buried in an interconnect substrate of a semiconductor substrate (package substrate) for mounting the semiconductor chip, thereby compensating for impedance mismatch. Further, as a related art, a related art of reducing waveform distortion caused by impedance mismatch is disclosed in, for example, japanese patent publication nos. 2006-. Japanese unexamined patent application publication No.2006-49645 discloses a configuration in which a plurality of through holes (vias) for ground interconnection are provided around a signal via in a printed substrate. Japanese unexamined patent application publication No.2012-209340 discloses a configuration of a signal transmission line formed to include through via holes (through holes) for connecting an outer layer pattern and an inner layer pattern of a multilayer substrate, wherein buried via holes (via holes) are provided at positions adjacent to the through via holes with an insulator interposed therebetween. Disclosure of Invention

However, the above-described method of forming an impedance matching circuit on a semiconductor device has a problem of increasing the area of a semiconductor chip. In particular, when signals in multiple channels are used, this can significantly increase chip area and is impractical because matching circuits are necessary for each I/O device of each channel. Further, burying inductors, capacitors, and the like in the interconnection substrate of the semiconductor package has a problem that the manufacturing of the interconnection substrate is difficult, thereby increasing the cost.

Before filing the present application, the present inventors have studied to form an impedance matching circuit in an interconnect substrate of a semiconductor package by using a via hole in the interconnect substrate. Specifically, a through via (through via) forming a parasitic capacitance as an impedance matching circuit is provided to a signal transmission line connected to an I/O device on the interconnection substrate at a position spaced from the I/O terminal end by λ/4 of the signal frequency. In this configuration, a signal input to the I/O device is reflected by the parasitic capacitance of the I/O device terminal, and the reflected wave is reflected again by the parasitic capacitance of the via hole and returns with a displacement of λ/2, in consideration of the phase of the I/O device terminal. Therefore, the reflected wave reflected by the parasitic capacitance of the I/O terminal and the reflected wave reflected by the parasitic capacitance of the via hole cancel each other to improve the signal characteristics (e.g., return loss characteristics) of the signal in the signal transmission line.

When the above-described technique is applied to a semiconductor device using a multi-channel signal, since a via hole as an impedance matching circuit is formed for each signal transmission line of each channel, a wide area is required for an interconnection substrate to form a plurality of via holes. In particular, in the case of a differential signal line pair, since it is necessary to provide a via hole connected to a ground potential so as to surround a via hole as an impedance matching circuit connected to a differential signal line in order to propagate a differential signal from an upper layer to a lower layer, a wider area is required on an interconnection substrate. However, in a semiconductor device such as SiP (system in package) in which a plurality of semiconductor chips are packaged in one semiconductor package, since the interconnection density and the via density of a package substrate are high, it is easy to secure a sufficient area for forming the through-hole. For example, in a SiP in which a plurality of semiconductor chips are mounted, interconnects, through holes, and vias (via) for electrically connecting the semiconductor chips to each other are densely formed in a region between one semiconductor chip and another semiconductor chip connected thereto (for example, in a central region of an interconnect substrate). On the other hand, interconnects, through holes, and vias (e.g., interconnects, vias, and the like for electrically connecting I/O devices on the semiconductor chip and external bumps) for connecting the semiconductor chip and the external terminals (external bumps) are densely formed to the outer periphery of the semiconductor chip in the package substrate, i.e., in a narrow area from one end of the semiconductor chip to one end of the package substrate. When vias as impedance matching circuits are provided in signal transmission lines for connecting the I/O devices and external bumps, since they must be formed in the above-described narrow area, it becomes more difficult to secure an area for forming the vias when the number of I/O devices increases. In particular, when most of the I/O devices transmit signals in the same frequency band, it is difficult to perform the arrangement of interconnections (wiring) because the through holes are densely formed at positions at the same distance from the I/O terminal ends (for example, positions spaced at λ/4 of the signal frequency). Therefore, it is necessary to provide a countermeasure against an increase in manufacturing cost due to, for example, an increase in the size of the package substrate. The techniques of japanese unexamined patent application publication nos. 2006-049645 and 2012-209340 are suitable for controlling the parasitic capacitance (impedance) of the via holes included in the signal transmission line, but the via holes in the signal transmission line cannot be surely processed to improve the signal characteristics, and no particular consideration is given to ensuring the area for disposing a plurality of via holes.

Means for solving these subjects will be described below. Other subject matter and novel features will become apparent from the description and drawings.

An outline of typical ones of these embodiments disclosed in the present invention will be briefly described below.

According to one aspect of the present invention, a semiconductor device has a semiconductor chip and an interconnect substrate in which the semiconductor chip is mounted. The interconnection substrate has: a first main surface in which a plurality of first electrodes are electrically connected to the semiconductor chip; a second major surface opposite the first major surface; and an interconnect region interposed between the first major surface and the second major surface. The first electrode includes a plurality of first signal electrodes and second signal electrodes arranged in sequence for receiving a signal supply at a predetermined frequency. The first signal electrode and the second signal electrode are arranged dispersedly in the arrangement thereof. The interconnection region has: a core substrate; a plurality of interconnection layers formed on both surfaces of the core substrate, respectively; and a plurality of first via holes penetrating the core substrate for forming impedance matching capacitances. The interconnection region further has a plurality of first vias passing through an interconnection layer formed to the core substrate on the first main surface side for forming impedance matching capacitances. The interconnect region further includes a plurality of first signal interconnects connected to corresponding first signal electrodes and a plurality of second signal interconnects connected to corresponding second signal electrodes.

The first via is connected to the first signal interconnect at a location spaced apart from the first signal electrode by a first interconnect length, and the first via is connected to the second signal interconnect at a location spaced apart from the second signal electrode by a second interconnect length substantially equal to the first interconnect length.

The advantageous effects obtained by the exemplary embodiments of the embodiments disclosed in the present application will be briefly described below.

According to this aspect of the present invention, the semiconductor device can suppress the manufacturing cost while achieving good signal transmission characteristics.

Drawings

Fig. 1 is an overall cross-sectional schematic view of an electronic circuit in which a semiconductor device according to one embodiment of the present invention is mounted;

FIG. 2 is a detailed overall cross-sectional schematic view of a semiconductor device;

fig. 3 is a schematic diagram illustrating a connection relationship between a semiconductor device and another semiconductor device;

fig. 4 is a schematic diagram illustrating a matching circuit formed in a package substrate of a semiconductor device;

fig. 5A is a graph showing a signal characteristic when the matching circuit CT1 is set to the transmission line SNT 1;

fig. 5B is a graph showing signal characteristics when the matching circuits CT1 and CT2 are provided to the transmission line SNT 1;

fig. 6 is a schematic diagram illustrating a matching circuit formed as a package substrate;

fig. 7A shows an example of a first shape of a land (land) connected to a through hole for forming a matching circuit;

fig. 7B shows an example of a second shape of a land connected to a through-hole for forming a matching circuit;

fig. 7C shows an example of a third shape of a land connected to a through-hole for forming a matching circuit;

fig. 8A shows an example of a first shape of a land for forming a via of a matching circuit;

fig. 8B shows an example of a second shape of a land for forming a via of a matching circuit;

fig. 8C shows an example of a third shape of a land for forming a via of a matching circuit; and

fig. 8D shows an example of a fourth shape of a land for forming a via of a matching circuit;

fig. 9 is a plan view of the semiconductor device;

fig. 10 is a schematic cross-sectional view of a package substrate in which through-holes and vias are formed as matching circuits;

fig. 11A shows a first connection example of an interconnect to a via for forming a matching circuit;

fig. 11B shows a second connection example of the interconnect to the via for forming the matching circuit; and

fig. 11C shows a third connection example of the interconnect to the via for forming the matching circuit;

fig. 12 is a diagram illustrating the interconnect layers: a plan view of layer 2;

fig. 13 is a diagram illustrating the interconnect layers: a plan view of layer 4;

fig. 14 is a diagram illustrating the interconnect layers: a plan view of layer 5;

fig. 15 is a diagram illustrating the interconnect layers: a plan view of layer 6;

fig. 16 is a diagram illustrating the interconnect layers: a plan view of layer 7;

fig. 17 is a diagram illustrating an interconnect layer: a plan view of layer 8;

fig. 18 is a diagram illustrating an interconnect layer: a plan view of layer 9;

fig. 19 is an enlarged view for the matching circuit CT 1;

fig. 20 is an enlarged view for the matching circuit CR 1;

fig. 21 is a diagram illustrating an interconnect layer: a plan view of the interconnect pattern of layer 2;

fig. 22 is a diagram illustrating the interconnect layers: a plan view of the interconnect pattern of layer 4 and layer 5;

fig. 23A is a diagram illustrating transmission characteristics of the differential signal line SNDR in the common mode in the case where the matching circuit CR1 in the first stage is formed with vias and the matching circuit CR2 in the second stage is formed with vias;

fig. 23B is a diagram illustrating transmission characteristics of the differential signal line SNDR in the differential mode in the case where the matching circuit CR1 in the first stage is formed with vias and the matching circuit CR2 in the second stage is formed with vias;

fig. 24A is a diagram illustrating transmission characteristics of the differential signal line SNDT in the common mode in the case where the matching circuit CT1 in the first stage is formed with a via and the matching circuit CT2 in the second stage is formed with a via;

fig. 24B is a diagram illustrating transmission characteristics of the differential signal line SNDT in the differential mode in the case where the matching circuit CT1 in the first stage is formed with a via and the matching circuit CT2 in the second stage is formed with a via;

fig. 25 is a flowchart showing an outline of a manufacturing process of the semiconductor device; and

fig. 26 is a schematic diagram illustrating an outline of a manufacturing process of a package substrate.

Detailed Description

(1) Summary of the embodiments

First, an outline of exemplary embodiments disclosed in the present application will be explained. Each bracketed reference numeral in the drawings referred to in the summary description of the exemplary embodiments is merely an exemplary illustration of a member or component included in the concept of a constituent element to which a bracket is attached.

[1] (semiconductor device having a package substrate in which through holes and vias as matching circuits are each arranged within a predetermined range from a semiconductor chip)

A semiconductor device according to an exemplary embodiment of the present invention has a semiconductor chip (2) and an interconnect substrate (1) on which the semiconductor chip is mounted. An interconnect substrate (1) comprises: a first main surface (1 a) on which a plurality of first electrodes (10) electrically connected to the semiconductor chip are formed; a second main surface (1 b) opposite to the first main surface (1 a); and an interconnection zone interposed between the first main surface (1 a) and the second main surface (1 b). The first electrode includes a plurality of first signal electrodes (10 _ Rx) and a second signal electrode (10 _ Tx) for receiving a signal supply at a predetermined frequency. The first signal and second signal electrodes are arranged dispersedly in the arrangement thereof. The interconnection region has: a core substrate (21) on which a plurality of interconnection layers (20, 22) are formed on both surfaces of the core substrate (21), respectively; and a plurality of first via holes (CR 1) passing through the core substrate for forming impedance matching capacitances. Also, the interconnection region has a plurality of first vias (CT 1) for forming impedance matching capacitances, the first vias (CT 1) passing through an interconnection layer formed to the core substrate on the first main surface side. Also, the interconnect region includes a plurality of first signal interconnects (SNR 1 to SNRm) connected to the corresponding first signal electrodes and a plurality of second signal interconnects (SNT 1 to SNTn) connected to the corresponding second signal electrodes. The first via is connected with the first signal interconnect at a position spaced apart from the first signal electrode by a first interconnect length (LR 1), and the first via is connected with the second signal interconnect at a position spaced apart from a second interconnect length (LT 1 ≈ LR 1) substantially equal to the first interconnect length.

With the above configuration, in the interconnect structure, a plurality of through holes and vias for impedance matching capacitance (hereinafter referred to as matching circuits) are formed in different layers in the interconnect region. More matching circuits can be formed at higher density than in the case where the matching circuits are formed only with the via holes. Also, since the via and the via as the matching circuit are formed in different layers, the interconnects respectively connected to them can be easily wired, thereby reducing the interconnect density. Also, the first via as the matching circuit can be formed by the same manufacturing process as that for the normal via. Therefore, according to the semiconductor device of the present invention, good signal transmission characteristics can be realized while suppressing the manufacturing cost of the interconnect substrate (package substrate).

[2] (matching circuit of multilevel connection)

In the semiconductor device described in the above paragraph (1), the interconnect region further includes a plurality of second vias (CT 2) for forming impedance matching capacitances through the core substrate, and a plurality of second vias (CR 2) through an interconnect layer formed as the core substrate on the second main surface side. The second via is connected with the second signal interconnect at a position spaced apart from the second signal electrode by a third interconnect length (LR 2) longer than the first interconnect layer, and the second via is connected with the first signal interconnect at a position spaced apart from the first signal electrode by a fourth interconnect length (LT 2 ≈ LR 2) substantially equal to the third interconnect length.

According to the above configuration, the plurality of matching circuits are formed to the first signal interconnection connected to the first signal electrode. In the same manner, a plurality of matching circuits are formed to the second signal interconnection connected to the second signal electrode. Therefore, signal characteristics can be improved in a wider frequency region. Also, by forming the matching circuit in the second stage connected to the first signal interconnect with the via and forming the matching circuit in the second stage connected to the second signal interconnect with the via, the matching circuit can be formed at a higher density and the interconnect density can be reduced.

[3] (the correction circuit in the first stage is formed at a position near λ/4.)

In the semiconductor device described in the above paragraph (2), the first interconnection length is a length of 1/4 corresponding to an electromagnetic wavelength (λ a, λ c) corresponding to a first frequency (fa, fc) in a signal band required for the signal transmission line.

According to the above configuration, it is possible to further reduce distortion of the signal waveform of the reflected signal reflected by the first signal interconnection terminal (second signal interconnection terminal) on the first signal electrode side (on the second signal electrode side).

[4] (the correction circuit in the second stage is formed at a position near 3 λ/4.)

In the semiconductor device described in paragraph (2) or (3), the third interconnection length is a length of 3/4 corresponding to an electromagnetic wavelength (λ b, λ d) that coincides with a second frequency (fb, fd) different from the first frequency in a signal band required for the signal transmission line.

Between the case where the matching circuit is provided at a position 1/4 apart by an electromagnetic wavelength coinciding with the second frequency and the case where the matching circuit is provided at a position 3/4 apart by an electromagnetic wavelength from the first signal electrode (second signal electrode), the phase of the reflected signal reflected at the matching circuit and returned to the first signal electrode (second signal electrode) is equivalent to pi (180 degrees). Therefore, the desired effect by providing the matching circuit at the position of 3/4 of the electromagnetic wavelength is the same as that in the case of providing the matching circuit at the position of 1/4 of the electromagnetic wavelength. According to the semiconductor device of the present invention, since the matching circuit (e.g., the first via) in the first stage and the matching circuit (the second via) in the second stage are formed at the spaced-apart positions, the area where the matching circuit is formed in the second stage can be easily secured, and the density of the matching circuit can be increased and the density of the interconnect can be further reduced. This is effective particularly in the case where a value applied to the first frequency is close to that of the second frequency, and it is difficult to set both the matching circuits in the first stage and the second stage at a position 1/4 of the electromagnetic wavelength.

[5] (the correction circuit in the first stage is formed at a position near 3 λ/4)

In the semiconductor device described in paragraph (2), the first interconnection length is a length of 3/4 corresponding to an electromagnetic wavelength (λ a, λ c) that coincides with the first frequency (fa, fc) in the signal band required for the signal transmission line.

As described above, when the matching circuit is provided at the position of 3/4 electromagnetic wavelength, since the effect is the same as when the circuit is provided at the position of 1/4 electromagnetic wavelength, the distortion of the signal waveform can be further reduced in the same manner as in entry 3.

[6] (via and via do not overlap)

In the semiconductor device in any one of items 2 to 5, the first via and the first via do not overlap in a plan view.

According to this configuration, interference between the first signal interconnect and the second signal interconnect by decoupling of the first via and the first via can be suppressed, thereby contributing to achievement of good signal transmission characteristics.

[7] (differential interconnect pair)

In the semiconductor device described in any one of items 2 to 6, the first signal interconnect is a first differential interconnect pair (SNDR) in which two interconnects are formed in parallel, and the second signal interconnect is a second differential interconnect pair (SNDT) in which two interconnects are formed in parallel.

[8]（Tx，Rx）

In the semiconductor device described in any one of items 1 to 7, one of the first signal electrode and the second signal electrode is a receiving electrode for inputting a signal to the semiconductor chip, and the other of them is a transmitting electrode for outputting a signal from the semiconductor chip.

[9] (shape of through-hole; difference in diameter of upper/lower stage: FIG. 7B)

In the semiconductor device described in any one of the paragraphs (1) to (8), a diameter of an uppermost land and a diameter of a lowermost land connected to the first through-hole are different in a cross-sectional view.

According to the above configuration, for example, by increasing the diameter of the land adjacent to the layer on the side where the interconnection density is low and decreasing the diameter of the land adjacent to the layer on the side where the interconnection density is high, it is possible to reduce coupling between the first via and the interconnections of the upper and lower layers adjacent thereto.

[10] (shape of through-hole; multiple soldering lands; FIG. 7C)

In the semiconductor device described in any one of items 1 to 8, the plurality of lands are connected to the first via hole in the vertical direction in the cross-sectional view.

According to the above configuration, since the number of lands forming parasitic capacitance is increased, the land diameter of each land for obtaining a desired capacitance value can be reduced, and the density of matching circuits can be increased and the interconnection density can be further reduced.

[11] (shape of passage: difference in diameter of upper/lower stage: FIGS. 8B and 8D)

In the semiconductor device described in any one of items 1 to 10, a diameter of an uppermost land connected to the first via is different from a diameter of a lowermost land connected to the first via in a cross-sectional view.

According to the above configuration, for example, by increasing the diameter of the land adjacent to the layer on the side where the interconnection density is lower and decreasing the diameter of the land adjacent to the layer on the side where the interconnection density is higher, the coupling between the first via and the interconnections of the upper and lower layers adjacent thereto can be reduced.

[12] (shape of vias: multiple pads: FIG. 8C, FIG. 8D)

In the semiconductor device described in any one of items 1 to 10, the plurality of lands are connected to the first via in a vertical direction in the cross-sectional view.

According to the above configuration, since the number of lands forming parasitic capacitance is increased, the land diameter of each land for obtaining a desired capacitance value can be reduced, and the density of matching circuits can be increased and the interconnection density can be further reduced.

[13] (Via interconnection: connection to the same interconnection layer; combination of FIGS. 11A to 11C)

In the semiconductor device described in any one of items 1 to 12, a part of the plurality of first vias is connected to the second signal interconnect with one pad (fig. 11B and 11C), and the remaining part is connected to the second signal interconnect with a plurality of pads (fig. 11A).

According to the above configuration, since a plurality of interconnects to be connected to the respective first vias can be dispersed in a plurality of interconnect layers, the interconnect density can be further reduced.

[14] (first pathway > second pathway)

In the semiconductor device described in any one of items 2 to 13, the land diameter of the first via is made larger than the land diameter of the second via.

The level of the reflected signal reflected at the first signal interconnection (second signal interconnection) on the first signal electrode side (on the second signal electrode side) decreases as the distance from the first signal electrode (second signal electrode) becomes larger. Therefore, when the matching circuit in the second stage is formed at a position spaced farther from the first signal electrode (second signal electrode) than the matching circuit in the first stage, even when the capacitance value is made smaller than that in the first stage, the effect of canceling the reflected wave reflected at the first signal interconnection terminal (second signal interconnection terminal) can be sufficiently obtained. Therefore, without reducing the effect of suppressing distortion of the signal waveform of the reflected wave by reducing the capacitance value of the matching circuit in the second stage as compared with the matching circuit in the first stage in the semiconductor device of the present invention, it is possible to improve the density of the matching circuit and further reduce the interconnection density.

[15] (the first path is larger than the usual path)

In the semiconductor device described in any one of items 1 to 14, the diameter of the land of the first via is made larger than the diameter of the land of the via for connecting the adjacent interconnect layers.

According to the above configuration, since the parasitic capacitance of the first path is larger than that of the normal path, the function as the matching circuit is easily realized.

[16] (interface buffer)

In the semiconductor device described in any one of items 1 to 15, the semiconductor chip has a plurality of interface buffers (Tx 1 to Txn and Rx1 to Rxm) respectively connected to the first signal terminal and the second signal terminal correspondingly.

According to the above configuration, due to the configurations of the entries 1 to 15, the signal characteristics of the interface buffer can be improved.

[17] (external terminal: BGA)

The semiconductor device shown in any one of items 1 to 16 further has a plurality of external terminals (8). The second main surface has a plurality of second electrodes (11) electrically connected to corresponding external terminals. The first signal interconnect forms a transmission line electrically connecting the first signal electrode and the corresponding second electrode, and the second signal interconnect forms a transmission line electrically connecting the second signal electrode and the corresponding second electrode.

According to the above configuration, the signal transmission characteristics of the transmission line from the semiconductor chip to the external terminal in the interconnect substrate can be improved.

[18] (interconnection substrate)

An interconnect substrate (1) according to an exemplary embodiment of the present invention has: a first main surface (1 a) on which a plurality of first electrodes (10) for electrical connection with a semiconductor chip (2) are provided; a second main surface (1 b) opposite to the first main surface; and an interconnect region interposed between the first major surface and the second major surface. The first electrode includes a plurality of first signal electrodes (10 _ Rx) and second signal electrodes (10 _ Tx) arranged in sequence for receiving a signal supply at a predetermined frequency. The first signal electrode and the second signal electrode are arranged dispersedly in the arrangement thereof. The interconnect region includes: a core substrate (21); a plurality of interconnection layers (20, 22) formed on both surfaces of the core substrate, respectively; and a plurality of first via holes (CR 1) passing through the core substrate for forming impedance matching capacitances. The interconnection region further includes a plurality of first vias (CT 1) passing through an interconnection layer (20) formed to the core substrate on the first main surface side and a plurality of first signal interconnections (SNR 1) connected to the corresponding first signal electrodes, and a plurality of second interconnections (SNT 1) connected to the corresponding second signal electrodes. The first via is connected to the first signal interconnect at a location spaced apart from the first signal electrode by a first interconnect length (LR 1), and the first via is connected to the second signal interconnect at a location spaced apart from the second signal electrode by a second interconnect length (LT 1) substantially equal to the first interconnect length.

The above configuration can provide an interconnect substrate capable of providing good signal transmission characteristics while suppressing the manufacturing cost in the same manner as described in the paragraph (1).

[19] (multiple matching circuits for one signal interconnect)

In the interconnect substrate described in item 18, the interconnect region further includes a plurality of second vias (CT 2) passing through the core substrate for forming impedance matching capacitances and a plurality of second vias (CR 2) passing through an interconnect layer formed to the core substrate on the side of the second main surface (22). The second via is connected to the second signal interconnect at a location spaced apart from the second signal electrode by a third interconnect length (LR 2) that is longer than the first interconnect length, and the second via is connected to the second signal interconnect at a location spaced apart from the first signal electrode by a fourth interconnect length (LT 2) that is substantially equal to the third interconnect length.

In the same manner as described in item 2, the above configuration can improve signal characteristics in a wider frequency band, and can increase the density of matching circuits and further reduce the interconnection density.

[20] (semiconductor device having a package substrate in which a through hole and a via as a matching circuit are formed to be mixed together)

A semiconductor device (10) according to an exemplary embodiment of the present invention has a semiconductor chip (2) and an interconnect substrate (1) on which the semiconductor chip is mounted. The interconnection substrate has: a first main surface (1 a) which is electrically connected to the semiconductor chip and in which a plurality of signal electrodes for receiving a signal supply at a predetermined frequency are formed; a second main surface (1 b) opposite to the first main surface; and an interconnect region interposed between the first major surface and the second major surface. The interconnect region includes: a core substrate (21); a plurality of interconnection layers (20, 22) formed on both surfaces of the core substrate, respectively; a plurality of signal interconnects (SNR 1 to SNRm, SNT1 to SNTn) formed in the interconnect layer and extending from the signal electrodes; and a plurality of impedance matching circuits connected to the signal interconnects at positions spaced apart from the signal electrodes by a predetermined interconnect length (LR 1 ≈ LT 1). A part of the plurality of impedance matching circuits is formed by a plurality of vias (CR 1) passing through the core substrate, and the remaining part thereof is formed by a plurality of vias (CT 1) passing through an interconnect layer (20) formed as the core substrate on the first main surface side.

According to the above configuration, since the through-hole and the via as the impedance matching circuit are formed in different layers, more impedance matching circuits can be formed on the interconnect substrate than the case where the impedance matching circuit is formed only through the through-hole.

[21] (the correction circuit in the first stage is formed at a position near λ/4.)

In the interconnect substrate of the item 19, the first interconnect length corresponds to 1/4 of electromagnetic wavelengths (λ a, λ c) that coincide with the first frequencies (fa, fc) in the signal band required for the signal transmission line.

The above configuration can further reduce distortion of a signal waveform of a reflected signal by reflection at the first signal interconnection terminal (second signal interconnection terminal) on the first signal electrode side (on the second signal electrode side).

[22] (the correction circuit in the first stage is formed at a position near λ/4, and the correction circuit in the second stage is formed at a position near 3 λ/4)

In the interconnect substrate described in the item 21, the third interconnect length corresponds to 3/4 of an electromagnetic wavelength (λ b, λ d) that coincides with a second frequency (fb, fd) different from the first frequency in a signal band required for the signal transmission line.

According to the above configuration, since the matching circuit (e.g., the first via) in the first stage and the matching circuit (the second via) in the second stage are formed at positions different from each other, an area for forming the matching circuit in the second stage can be easily secured, and the density of the matching circuit can be increased and the interconnection density can be further reduced. This is effective particularly in the case where the value of the first frequency is close to the value of the second frequency, and it is difficult to set both the matching circuits in the first stage and the second stage at the position of 1/4 of the electromagnetic wavelength.

2. Explanation of the description form, basic terms and applications in the present application

In the present application, preferred embodiments are described, divided into sections for convenience, if necessary. However, unless otherwise indicated, they are not independent of each other, but rather are each part of an example, a detail of a part, a part of another or an entire modified example. Moreover, description of the same parts will not be repeated in general. Moreover, unless otherwise stated or except where the theoretical limitation to a specific number and clearly contradictory context, individual constituent elements in the embodiments are not necessary.

Moreover, in the present application, when referring to "a semiconductor device" or "a semiconductor integrated circuit device", it mainly refers to various transistors (active devices) themselves; or those in which a resistor, a capacitor, or the like is integrated together with the transistor as a main component on a semiconductor chip or the like (e.g., a single crystalline silicon substrate); packaged semiconductor chips, etc. Typical examples of the various transistors include, for example, MISFETs (metal insulator semiconductor field effect transistors) typified by MOSFETs (metal oxide semiconductor field effect transistors). A typical configuration of an integrated circuit includes, for example, a CMIS (complementary metal oxide semiconductor) type integrated circuit typified by a CMOS (complementary metal oxide semiconductor) type integrated circuit including N-channel type MISFETs and P-channel type MISFETs in combination.

Similarly, in the description of the embodiments, when it is described that "X includes a" for a material, a composition, or the like, unless otherwise specified and clearly contradicted by context, a case where an element other than a is included as one of the main constituent elements is not excluded. For example, when referring to an ingredient, this means "X includes a as a main ingredient". For example, when referring to "silicon material", it is needless to say that not only pure silicon is limited, but also a material including a multicomponent alloy including silicon as a main component, such as SiGe alloy, and further including other additives and the like.

Similarly, while the preferred embodiments illustrate shapes, positions, characteristics, etc., it is not to be borne in mind, and are not to be strictly limited to such shapes, positions, characteristics, etc., unless otherwise indicated and clearly contradicted by context.

Also, when a particular value, amount, etc., is referred to, the value can be greater or less than the particular value unless otherwise indicated or limited theoretically to the particular value and clearly contradicted by context.

"wafer" generally refers to a single crystal silicon wafer on which semiconductor integrated circuit devices (as well as semiconductor devices and electronic devices) are mounted. Needless to say, the wafers also include epitaxial wafers, and composite wafers including insulating substrates such as an SOI substrate and LDC glass.

"solder" is typically a low melting temperature (about less than 250 ℃) metallic material that includes tin as one of the major components. The solder includes "lead-containing solder" containing lead and "lead-free solder" containing no lead. In the present invention, as an example, the solder bump is formed of a lead-free solder.

3. Detailed description of the embodiments

Embodiments of the present invention will be described in further detail. In the respective drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in general. Also, in the drawings, in the case where the hatching makes the drawings complicated or in the case where the distinction from the blank portion becomes clear, the hatching may be omitted sometimes even in the sectional view. In connection therewith, even in the case where the hole in the plan view is closed, the outline at the background may sometimes be omitted in a clear case in view of the description or the like. Moreover, shading may sometimes be applied to a portion of a non-cross-sectional view to clearly show that the portion is not a blank portion.

Fig. 1 is an overall cross-sectional schematic view of an electronic circuit having a semiconductor device according to a first embodiment of the present invention mounted thereon.

The electronic circuit 200 shown in fig. 1 is, for example, a circuit module on a network device such as a router for high-speed communication of a communication device installed in a base station of a mobile phone or for providing a communication function to a network device. In the electronic circuit 200, a plurality of semiconductor devices and various electronic components electrically mounted on a mounting substrate (printed substrate) 6 such as a motherboard, for example, are connected through an interconnection pattern formed in the mounting substrate 6 and portions that transmit/receive various signals to/from each other, thereby providing a desired function. Fig. 1 typically illustrates a semiconductor device 100 as a plurality of parts forming an electronic circuit 200, and another semiconductor device 101.

The semiconductor device 100 and the other semiconductor device 101 are electrically connected with the mounting substrate 6 and transmit/receive signals therebetween. Although not particularly limited, the semiconductor device 100 has, for example, a storage device (memory) for storing data. Also, another semiconductor device 101 is, for example, a memory controller that accesses a memory in the semiconductor device.

As shown in fig. 1, the semiconductor device 100 includes two semiconductor chips 2 and 3, a plurality of external terminals 8 formed of solder bumps (solder balls), and a package substrate (interconnect substrate, interposer) 1 on which the semiconductor chips 2 and 3 are mounted. The semiconductor device 100 is, for example, an SIP sealed by an FCBGA (flip chip ball grid array) type package, in which solder bumps forming the bump electrodes 7 and 13 are applied to the semiconductor chips 2 and 3 and face-down bonded to the package substrate 1. In order to simplify the drawing, the number of bump electrodes of the semiconductor device 100 shown in the drawing is smaller than the actual number. The actual bump pitch of the solder bumps (bump electrodes 7, 13) on the semiconductor chip side is, for example, about 100 μm, and the actual bump pitch of the solder bumps (external terminals 8) on the mounting substrate 6 side is, for example, about 1 mm. The material of the solder bump preferably includes, for example, a silver-added tin type lead-free solder to which 1.5% by weight of silver (melting point; about 221 c) is added. In addition to the above examples, various lead-free solders can also be applied. Also, if conditions permit, although lead type solders may also be used, lead-free solders are preferably used in consideration of the environment.

Fig. 2 shows a detailed overall cross-sectional schematic of the semiconductor device 100.

As shown in fig. 2, the package substrate 1 has a first main surface 1a formed with a plurality of first electrodes 10 electrically connected to the semiconductor chips 2 and 3 with bump electrodes 7 and 13, and a second main surface 1b opposite to the first main surface 1a and formed with a plurality of second electrodes 11 electrically connected to the external terminals 8, and an interconnection region interposed between the first main surface 1a and the second main surface 1 b. The package substrate 1 is, for example, a build-up substrate (build down substrate). The interconnect region includes a core substrate 21 and a plurality of interconnect layers (hereinafter also referred to as build-up layers) formed on both surfaces of the core substrate 21, respectively. The core substrate 21 is, for example, a glass epoxy substrate having two interconnect layers, i.e., layer 5 and layer 6. In the build-up layers 20 and 22, insulating films (resins) and interconnect layers (conductors) are alternately laminated. For example, build-up layer 20 formed to core substrate 21 on the first main surface 1a side has four interconnect layers including layer 1, layer 2, layer 3, and layer 4, and build-up layer 22 formed to core substrate 21 on the second main surface 1b side has four interconnect layers including layer 7, layer 8, layer 9, and layer 10. As the metal material for the interconnect pattern formed in the interconnect layer, i.e., layers 1 to 10, copper (Cu), aluminum (Al), or the like may be used.

The semiconductor chip 3 is, for example, a memory IC. The semiconductor chip 2 is, for example, a logic IC that can access the semiconductor chip 3 in accordance with an access requested from the outside. The semiconductor chip 2 writes data to the semiconductor chip 3 or reads data from the semiconductor chip 3 in accordance with reading from another semiconductor device 101. The semiconductor chip 2 includes, for example, a SerDes circuit that converts serial data and parallel data into each other, and performs serial communication at 12.5GHz with respect to the semiconductor device 101 and parallel communication at 1.2GHz with respect to the semiconductor chip 3, for example, using the SerDes circuit.

Fig. 3 is a schematic diagram illustrating a connection relationship between the semiconductor device 100 and another semiconductor device 101.

As shown in fig. 3, the semiconductor chip 2 has a plurality of I/O devices (interface buffers) as input/output circuits that transmit/receive signals (data) with respect to another semiconductor device 101. Specifically, the semiconductor chip 2 has reception I/O devices Rx1 to Rxm (m is an integer of 2 or more) and transmission I/O devices Tx1 to Txn (n is an integer of 2 or more). In the same manner, another semiconductor device 101 has a plurality of transmission I/O devices XTx1 through XTxm and reception I/O devices XRx1 through XRxn.

The transmission I/O devices Tx1 to Txn of the semiconductor device 100 are connected to the corresponding I/O devices XRx1 to XRxn of the other semiconductor device 101, respectively, using the external terminal 8 of the semiconductor device 100, the signal lines SNT1 to SNTn, and the external terminal 9 of the other semiconductor device 101. In the same manner, the reception I/O devices Rx1 to Rxm of the semiconductor device 100 are connected to the corresponding I/O devices XTx1 to XTxm of the other semiconductor device 101, respectively, using the external terminal 8 of the semiconductor device 100, the signal lines SNR1 to SNRm, and the external terminal 9 of the other semiconductor device 101.

High-speed serial communication between the semiconductor device 100 and another semiconductor device 101 is performed by LVDS (low voltage differential signaling), for example, in which signal lines SNT1 to SNTn and SNRs 1 to SNRm form a plurality of differential signal line pairs. For example, the signal lines SNT1 and SNT2 form a differential signal line SNDT for high-speed serial communication, and the signal lines SNR1 and SNR2 form a differential signal line SNDR. In the present embodiment, reference numerals SNR1 to SNRm, SNTR1 to SNTRn, SRDT and SNDR denote not only signal lines but also transmission lines from input/output terminals of an I/O device of the semiconductor device 100 to input/output terminals of an I/O device of the other semiconductor device 101.

For example, when data is transferred from the semiconductor chip 2 to the other semiconductor device 101, signals transmitted from the transmission I/O devices Tx1 to Txn of the semiconductor chip 2 are supplied to the I/O devices XRx1 to XRxn of the other semiconductor device 101 through the signal lines SNT1 to SNTn. In the same manner, when the semiconductor chip 2 receives data from the other semiconductor device 101, signals transmitted from the I/O devices XTx1 to XTxm of the other semiconductor device 101 are supplied to the reception I/O devices Rx1 to Rxm of the semiconductor chip 2 through the signal lines SNR1 to SNRm.

The signal lines SNT1 to SNTn and SNRs 1 to SNRm are adjusted so that each of them has a characteristic impedance of 50 Ω, and in accordance therewith, the transmitting I/O devices Tx1 to Txn and the receiving I/O devices Rx1 to Rxm of the semiconductor chip 2 are each terminated by a resistor R0 (= 50 Ω). However, a parasitic capacitance CT0 exists at the output terminal of each of the transmitting I/O devices Tx1 to Txn, and a parasitic capacitance CR0 exists at the input terminal of the receiving I/O devices Rx1 to Rxm. Therefore, as described above, since the admittance of the respective parasitic capacitances CT0 and CR0 increases more as the frequency of the signals supplied to the signal lines SNT1 to SNTn and SNR1 to SNRm increases, the impedance mismatch increases between the I/O devices Tx1 to Txn (Rx 1 to Rxm) and the signal lines SNT1 to SNTn (SNR 1 to SNRm), which tends to cause signal reflection. Therefore, in the semiconductor device 100 according to the present embodiment, a matching circuit for impedance matching is formed in the package substrate 1.

Fig. 4 is a diagram illustrating a matching circuit formed in the package substrate 6 of the semiconductor device 100.

In the package substrate 6, capacitances are provided as impedance circuits for impedance matching to the signal lines SPT1 to SPTn connecting the bump electrodes 7 and the corresponding external terminals 8, the bump electrodes 7 being connected to the output terminals of the transmission I/O devices Tx1 to Txn formed in the semiconductor chip 2, respectively.

Specifically, in the package substrate 6, the capacitances CT1 are formed at positions spaced apart from the output terminals of the transmission I/O devices Tx1 to Txn (e.g., the first signal electrodes 10 connected to the output terminals of the transmission I/O devices Tx1 to Txn) by the interconnection length LT1 on the signal lines SPT1 to SPTn to which the output terminals of the transmission I/O devices Tx1 to Txn are connected, respectively. The interconnection length LT1 is a length of 1/4 corresponding to an electromagnetic wavelength λ a that coincides with the first frequency fa in the signal band required for the transmission lines SNT1 to SNTn. For example, at fa =30GHz, λ a/4 is about 1 mm. According to such a configuration, in the transmission line SNT1, the folding back distance when a signal at the frequency fa is output from the output terminal of the I/O device Tx1, reflected at the capacitance CT1, and returned again to the output terminal of the I/O device Tx1 is, for example, λ a/2 (= 2 × λ a/4). Therefore, in terms of phase, since the signal output from the output terminal of the I/O device Tx1 returns to the output terminal of the I/O device Tx1 in a state of displacement of pi (180 degrees), the reflected wave reflected by the parasitic capacitance CT0 at the output terminal of the I/O device Tx1 and the reflected wave reflected by the capacitance CR1 cancel each other, and distortion of the signal waveform in the transmission line SNT1 can be reduced. The length of 1/4 corresponding to the electromagnetic wavelength λ a is not limited to the exact interconnect length λ a/4, but more or less error may be allowed with respect to the exact interconnect length λ a/4. For example, a length within a tolerance of ± 20% with respect to λ a/4 is allowed. In fact, since the I/O device is not a simple capacitor or resistor but has a structure in which they are synthesized together, even when the length is set to exactly the accurate interconnection length "λ/4", the optimum characteristics are sometimes not obtained. In this case, the optimum arrangement of the capacitance CT1 can be established in consideration of the simulation result and the actual measurement value. Therefore, the optimum arrangement of the capacitance CT1 is sometimes in the range of, for example, λ/8 to λ/4.

Also, capacitors CT2 as matching circuits are each formed at a position separated from the output terminals of the transmitting I/O devices Tx1 to Txn by an interconnect length LT 2. The interconnection length LT2 is a length of 3/4 of the electromagnetic wavelength λ b corresponding to coincide with the predetermined frequency fb in the signal band required for the transmission line SNT 1. According to such a configuration, for example, in the transmission line SNT1, the folding back distance at which the signal at the frequency fb output from the output end of the I/O device Tx1 is reflected by the capacitance CT2 and returned again to the output end of the I/O device Tx1 is 3 λ b/2 (= 2 × 3 λ b/4). Therefore, in the same manner as the case where the capacitor CT1 is disposed at a position separated from the output terminal of the I/O device Tx1 by 1/4 of the electromagnetic wavelength, the reflected wave of the signal output from the output terminal of the I/O device Tx1 returns to the output terminal of the I/O device Tx1 in a state of being shifted by pi in phase. Therefore, the reflected wave reflected by the parasitic capacitance CT0 and the reflected wave reflected by the capacitance CT2 at the output end of the I/O device Tx1 cancel each other, and the distortion of the signal waveform in the transmission line SNT1 can be further reduced. The length corresponding to 3/4 for the electromagnetic wavelength λ b is not limited to exactly equal the interconnect length 3 λ b/4, but more or less error is allowed with respect to the exact interconnect length 3 λ b/4 in the same manner as the interconnect length λ a/4 described above. For example, a length within a range of ± 20% of the error with respect to λ b/4 is allowed.

In the package substrate 6, in the same manner as the transmission side, capacitances as matching circuits are provided to the signal lines SPR1 to SPRn connecting the bump electrodes 7 and the corresponding external terminals 8, the bump electrodes 7 being connected to the reception I/O devices Rx1 to Rxm formed in the semiconductor chip 2, respectively.

Specifically, on the signal lines SPR1 to SPRm connected to the input terminals of the reception I/O devices Rx1 to Rxm, capacitances CR1 are formed at positions spaced apart from the input terminals of the I/O devices Rx1 to Rxm (for example, the first signal electrodes 10 connected to the input terminals of the I/O devices Rx1 to Rxm) by an interconnection length LR1, respectively. The interconnect length LR1 is a length of 1/4 corresponding to an electromagnetic wavelength λ c that coincides with a predetermined frequency fc in the signal band required for the transmission line SNR 1. Therefore, distortion of the signal waveform in the transmission line SNR1 can be reduced in the same manner as the transmission line SNT 1. Also, the capacitors CR2 are each formed at a position spaced apart from the input terminals of the receiving I/O devices Rx1 through Rxn by an interconnect length LR 2. The interconnect length LR is a length of 3/4 corresponding to an electromagnetic wavelength λ d that coincides with the predetermined frequency fd in the signal band required for transmission line SNR 1. According to the above configuration, distortion of the signal waveform in the transmission line SNR1 can be further reduced in the same manner as the transmission line SNT 1.

In the present embodiment, it is assumed that the same frequency band (12.5 Gbps) is required on both the transmission side and the reception side of the semiconductor device 100 for the frequency, and fa = fc (λ a = λ c) and fb = fd (λ b = λ d) are also satisfied. Thus, the interconnect length LR1 and the interconnect length LT1 are substantially equal, and the interconnect length LR2 and the interconnect length LT2 are substantially equal. Substantially equal lengths are meant to be not only exactly equal lengths, but also to include the case where a predetermined error (e.g., about ± 20%) exists. Also, in the following description, reference symbol CT1 represents not only a capacitance but also a matching circuit formed by the capacitance. The same applies to the reference signs CT2, CR1 and CR 2.

Fig. 5A illustrates signal characteristics in the case where the matching circuit CT1 is provided on the signal line SPT1, and fig. 5B illustrates signal characteristics in the case where the matching circuits CT1 and CT2 are provided in the signal line SPT 1. Suppose that: CT1=0.25pF and CT2=0.05 pF.

In fig. 5A and 5B, reference numeral 300 shows the return loss of the transmission line SNT1 when the matching circuits CT1 and CT2 are not provided. Reference numeral 301 shows the return loss when the matching circuit CT1 is disposed at a position spaced apart from the output end of the I/O device Tx1 by an interconnection length LT1 corresponding to 1/4 of an electromagnetic wavelength that coincides with the signal frequency f1 (= 12 GHz). Reference numeral 302 shows a return loss when the matching circuit CT1 is disposed at a position spaced apart from the output terminal of the I/O device Tx1 by an interconnection length LT1 and the matching circuit CT2 is disposed at a position spaced apart from the interconnection length LT2, the interconnection length LT1 corresponding to 1/4 of an electromagnetic wavelength coinciding with the signal frequency f1 (= 12 GHz), and the interconnection length LT2 corresponding to 3/4 of an electromagnetic wavelength coinciding with the signal frequency f2 (= 8 GHz).

As indicated by reference numeral 300, when the matching circuits CT1 and CT2 are not provided, the return loss increases as the frequency increases. On the other hand, as shown by reference numeral 301, when the matching circuit CT1 is disposed at a position spaced apart from the output terminal of the I/O device Tx1 by the interconnect length LT1, the bottom of the characteristic appears at a position near 12 GHz. Also, as shown by reference numeral 302, when the matching circuit CT2 is disposed at a position spaced apart from the output terminal of the I/O Tx1 by the interconnect length LT2 in addition to the capacitance CT1, the bottom as a characteristic of return loss appears at a position near 8GHz in addition to a position near 12 GHz. By forming the bottom portion of the plurality of characteristics, return loss can be suppressed in a wide range of band. Since CT1> CT2, although the bottom of the characteristic in the vicinity of 8GHz is smaller than that of the characteristic in the vicinity of 12GHz, the return loss can be more reduced by further adding the matching circuit CT 2. Although not shown, when the capacitances CR1 and CR2 are provided in the reception signal line SPR1 of the semiconductor chip 2, the signal characteristics are shown to be similar to the tendency of fig. 5A and 5B.

Specific configurations of the matching circuits CT1 and CT2 (CR 1 and CR 2) will be explained.

In the semiconductor device 100 according to the present embodiment, the capacitances CT1 and CT2 (CR 1 and CR 2) as matching circuits are obtained by the parasitic capacitances of the through holes or vias in the package substrate 1. The through hole is a through hole passing through the core substrate 21, and the via is a through hole passing through an insulating layer for electrically connecting between adjacent interconnect layers in the build-up layers 20 and 22.

Fig. 6 is a schematic diagram illustrating the matching circuits CT1 and CT2 (CR 1 and CR 2) formed in the package substrate 1. As shown in the drawing, Through Holes (TH) or vias (Via) are each formed at a position spaced apart from input terminals (output terminals) of the I/O devices of the semiconductor chip 2 by a predetermined interconnection length (LT 1, LT2, LR1, and LR 2). The capacitances CT1, CT2, CR1, CR2 are obtained by using the parasitic capacitance of the via or via.

For the capacitances CT1, CT2, CR1, and CR2, parasitic capacitances formed mainly between the lands connected to the vias or vias and the levels formed around them (the same interconnect layer and the upper and lower interconnect layers) are used. Therefore, the capacitance values of the respective matching circuits (capacitances) CT1, CT2, CR1, and CR2 are obtained mainly by adjusting the magnitude of the stage diameter. For example, the land diameter of a via forming a capacitance as a matching circuit is made larger than that of a usual via (a via for electrically connecting adjacent interconnect layers, respectively). For example, when the diameter of a general via is 90 to 100 μm, the diameter of the via as a matching circuit has a larger size. The land diameter of the via hole forming the capacitance as the matching circuit is made equal to or alternatively larger than the land diameter of the usual via hole (via holes penetrating the core substrate for electrically connecting the interconnects formed in the upper and lower interconnect layers, respectively).

Fig. 7 and 8 illustrate examples of land shapes connected to through holes or vias for forming matching circuits.

Fig. 7A shows a first example of the shape of a land connected to a through-hole forming a matching circuit, fig. 7B shows a second example of the shape of a land connected to a through-hole forming a matching circuit, and fig. 7C shows a third example of the shape of a land connected to a through-hole forming a matching circuit.

In the first example of the shape shown in fig. 7A, the diameters of the upper and lower lands connected to the through hole are made equal in the cross-sectional view of the package substrate 1.

In the second example of the shape shown in fig. 7B, the diameters of the upper and lower lands connected to the through-hole are made different in the sectional view of the package substrate 1. Therefore, it is possible to reduce coupling between the via and the interconnect in the upper and lower layers adjacent to each other by increasing the diameter of the land adjacent to the layer on the side where the interconnect density is lower, and by decreasing the diameter of the land adjacent to the layer on the side where the interconnect density is higher. For example, when the interconnection density is higher on the upper layer side than on the lower layer side of the via hole, as shown in fig. 7B, the diameter of the land for the upper layer is preferably formed larger than the diameter of the land for the lower layer.

In a third example of the shape shown in fig. 7C, in the cross-sectional view of the package substrate 1, a plurality of lands are connected in the vertical direction of the through-hole. This shape example is suitable for the case where the interconnect layer is formed inside in addition to both surfaces of the core substrate 21. Fig. 7C illustrates a case where two lands are formed in the through hole between the uppermost land and the lowermost land. According to this configuration, the magnitude of parasitic capacitance formed between the lands and the ground plane (ground plane) therearound can be controlled depending on the number of lands. Therefore, the land diameter of each land for obtaining a desired capacitance value can be reduced by increasing the number of stages of the land, and the area of a region for forming a via hole as a matching circuit can be made small. As shown in fig. 7B, the diameters of the uppermost and lowermost two lands are different.

Fig. 8A shows a first example of the shape of a land forming a via of a matching circuit, fig. 8B shows a second example of the shape of a land connected to a via forming a matching circuit, fig. 8C shows a third example of the shape of a land connected to a via forming a matching circuit, and fig. 8D shows a fourth example of the shape of a land connected to a via forming a matching circuit.

In the first example of the shape shown in fig. 8A, the diameters of the upper and lower lands of the connection passage are made the same in the cross-sectional view of the package substrate 1.

In the second example of the shape shown in fig. 8B, the diameters of the upper and lower lands connected to the via are made different in the cross-sectional view of the package substrate 1. According to the above configuration, as in the case of the above-described via, coupling between the via and the interconnect in the upper and lower layers adjacent to each other can be reduced. For example, when the interconnection density on the lower layer side of the via is higher than the interconnection density on the upper layer side of the via, as shown in fig. 8B, the diameter of the upper layer land may be formed larger than the diameter of the lower layer land.

In a third example of the shape shown in fig. 8C, in the cross-sectional view of the package substrate 1, a plurality of lands are connected in the vertical direction of the via. Fig. 8C shows a case where one land is formed between the uppermost land and the lowermost land. According to the above configuration, the magnitude of parasitic capacitance formed between the lands and the surrounding horizontal plane is controlled by the number of lands in the same manner as in the above-described through-holes. Therefore, the area of the region for forming the via as the matching circuit can be further reduced by increasing the number of lands.

In a fourth example of the shape shown in fig. 8D, a plurality of lands are connected in the vertical direction of the via and the diameters of the two uppermost and lowermost lands are made different in the cross-sectional view of the package substrate 1. According to the above configuration, it is possible to further reduce the area of the region for forming the via as the matching circuit while reducing the coupling between the via and the interconnect in the upper and lower layers adjacent to each other.

Fig. 9 shows a plan view of the semiconductor device 100. In the semiconductor device 100 as shown in fig. 9, a semiconductor chip 2 and another semiconductor chip 3 are juxtaposed on a package substrate 1. A set of interconnects for connecting the semiconductor chip 2 and the other semiconductor chip 3 is mainly formed in the interconnect region of the region B of the package substrate 1. A set of interconnections connected to the external terminals 8 for connecting the semiconductor chip 2 and the semiconductor device 101 is mainly formed in the interconnection region including the region a ranging from the substrate end P of the package substrate 1 to the chip end Y of the semiconductor chip. In the semiconductor device 100, through holes and vias as matching circuits CT1, CT2, CR1, and CR2 are formed, for example, in a region a on the package substrate 1.

Fig. 10 shows a schematic cross-sectional view of a package substrate 1 in which through-holes and vias are formed as matching circuits. Fig. 10 typically shows the signal line SPT1 forming the differential signal line SNDT and the matching circuits CT1 and CT2 connected to them, and the signal line SPR1 forming the differential signal line SNDR and the matching circuits CR1 and CR2 connected to them. Other signal lines forming the differential signal line and a matching circuit connected thereto, a via connected to ground potential, a through hole connected to ground potential, and the like are not shown for simplifying the explanation.

As shown in fig. 10, the matching circuit CR1 in the first stage of the signal line SPR1 on the reception side of the semiconductor chip 2 is formed by a via between the interconnect layers, i.e., between the layers 5 and 6, and the matching circuit CR2 in the second stage is formed by a via between the interconnect layers, i.e., between the layers 7 and 9. Also, the matching circuit CT1 in the first stage of the signal line SPT1 on the transmission side of the semiconductor chip 2 is formed by a via between the interconnect layers, i.e., between the layers 2 and 4, and the matching circuit CT2 in the second stage is formed by a via between the interconnect layers, i.e., between the layers 5 and 6. In the signal line SPR1, the interconnection length from the output terminal (first signal electrode 10_ Rx 1) of the semiconductor chip 2 to the via (CR 1) in the first stage is LR1, and the interconnection length from the output electrode (pad) of the I/O device connected to the output terminal (bump electrode 7) of the semiconductor chip 2 to the via (CR 2) in the second stage is LR 2. In the signal line SNR2, the interconnection length from the output terminal (second signal electrode 10_ Tx 1) of the semiconductor chip 2 to the via (CT 1) in the first stage is LT1, and the interconnection length from the output terminal of the semiconductor chip 2 to the via (CT 2) in the second stage is LT 2. Interconnect length LR1 ≈ LT1 and interconnect length LR2 ≈ LT 2.

As shown in fig. 10, matching circuits formed by vias (CR 1) and by vias (CT 1) are provided in the first stage to be mixed together as matching circuits. According to the above configuration, since the matching circuits in the first stage can be formed so as to be stacked in the vertical direction in the cross section of the package substrate 1, the number of matching circuits formed on the same plane can be reduced as compared with the usual case where all matching circuits are formed in the first stage through vias, thereby forming the matching circuits at higher density. In particular, as in the present embodiment, when the interconnect length LR1 and the interconnect length LT1 are substantially equal, since the matching circuits CR1 and CT1 in the first stage are densely formed at the same position in the region a on the package substrate 1, as described above, when the matching circuits of the through-holes and the matching circuits of the vias are provided to be mixed together, more matching circuits can be formed at higher density in the region a. Also, since the matching circuits are formed in different layers of the interconnection region of the package substrate 1, the interconnections connected to the corresponding matching circuits can be easily wired, thereby reducing interconnection density. For example, signal interconnections after passing through the matching circuit CT1 formed by vias may be routed in the build-up layer 20 on the upper side of the core substrate 21, and signal interconnections after passing through the matching circuit CT2 formed by vias may be routed in the build-up layer 22 on the lower side of the core substrate 21. That is, since the signal interconnections SPT1 to SPTn and SPR1 to SPRm on the package substrate 1, which form the differential signal lines SNDR and SNDT, can be wired respectively in the upper and lower interconnection layers of the core substrate 21, the density of interconnections formed in one interconnection layer can be reduced, which can suppress mutual interference between interconnections.

In the same manner, matching circuits formed by the via (CT 2) and the via (CR 2) are provided mixed together as matching circuits in the second stage. With the above configuration, the matching circuits in the second stage can be formed at high density in the same manner as the matching circuits in the first stage, and the interconnection density can be reduced. In particular, as in the present embodiment, in the case where the interconnect length LR2 and the interconnect length LT2 are substantially equal, when the matching circuit of the via and the matching circuit of the via are mixed together, more matching circuits can be formed at higher density in the region a on the package substrate 1 in the same manner as the matching circuits in the first stage.

Fig. 11A to 11C show connection examples of interconnections to a via as a matching circuit. Fig. 11A shows a first connection example of the interconnect to the via forming the matching circuit, fig. 11B shows a second connection example of the interconnect to the via forming the matching circuit, and fig. 11C shows a third connection example of the interconnect to the via forming the matching circuit.

In the first connection example shown in fig. 11A, in the cross-sectional view of the package substrate, the interconnects are connected to the vias using a plurality of lands. Fig. 11A shows a case where an interconnect is connected to the uppermost land to be connected to a via and another interconnect is connected to the lowermost land to be connected to a via in the same manner as a general connection method of a via and an interconnect.

In the second connection example shown in fig. 11B, and in the third connection example shown in fig. 11C, in the cross-sectional view of the package substrate 1, the interconnects are connected to the vias with a single land. Fig. 11B shows a case in which two interconnects are connected to the uppermost lands connected to the vias, and fig. 11C shows a case in which two interconnects are connected to the intermediate lands in the third-stage lands connected to the vias.

In any of the connection methods in fig. 11A to 11C, the via may function as a matching circuit. Also, the connection methods of fig. 11A to 11C may be combined. For example, among the vias forming the plurality of matching circuits CT1, a part of the vias are connected to the interconnect with one pad as shown in fig. 11B and 11C, and the remaining part of the vias are connected to the interconnect with a plurality of pads as shown in fig. 11A. According to the above configuration, it is possible to easily route the interconnect connected to the via forming the matching circuit CT1 to further increase the density of the matching circuit and to reduce the interconnect density.

Also, as shown in fig. 10, the via forming the matching circuit CT1 and the via forming the matching circuit CR1 are preferably provided so as not to overlap in plan view. In the same manner, the through hole forming the matching circuit CT2 and the via forming the matching circuit CR2 are preferably arranged so as not to overlap in plan view. This can suppress interference of signals between the through hole and the via with the stage.

Fig. 12 to 18 show plan views of the corresponding interconnect layers corresponding to fig. 10.

Fig. 12 shows the interconnect layers: plan view of layer 2, fig. 13 shows the interconnect layers: plan view of layer 4, fig. 14 shows the interconnect layers: plan view of layer 5, fig. 15 shows the interconnect layers: plan view of layer 6, fig. 16 shows the interconnect layers: plan view of layer 7, fig. 17 shows the interconnect layers: a plan view of layer 8, and fig. 18 shows the interconnect layers: plan view of layer 9.

As shown in fig. 12 and 13, in the signal lines SPT1 and SPT2 that form the differential signal line SNDT on the transmission side of the semiconductor chip 2, the matching circuit CT1 provided in the first stage is each formed by passing through a via between interconnect layers, i.e., between layers 2 and 4.

Fig. 19 is an enlarged view of the matching circuit CT 1. As shown in fig. 19, the two signal lines SPT1 and SPT2 forming the differential signal line SNDT are connected to a matching circuit formed by vias. Also, a plurality of ground paths 16 connected to the ground potential are provided so as to surround each of the paths of the matching circuit CT1 forming the differential signal line SNDT. Therefore, the differential signals supplied to the two signal lines SNT1 and SNT2 can propagate in the vertical direction of the package substrate 1 (vertical direction in the cross-sectional view).

As shown in fig. 14 and 15, in the signal lines SPR1 and SPR2 forming the differential signal line SNDR on the reception side of the semiconductor chip 2, the matching circuits CR1 provided in the first stage are each formed by a via passing through the interconnection layer, i.e., between the layers 5 and 6.

Fig. 20 shows an enlarged view of the matching circuit CRT 1. As shown in fig. 20, two signal lines SPR1 and SPR2 forming the differential signal line SNDR are connected to circuits CR1 each formed of a through hole TH. Also, as shown in fig. 20, a plurality of vias 15 connected to the ground potential are provided so as to surround the respective vias of the matching circuit CR1 that forms the differential signal line SNDR. Therefore, the differential signals supplied to the two signal lines SNR1 and SNR2 can propagate in the vertical direction of the package substrate 1 (vertical direction in the cross-sectional view).

Also, as shown in fig. 14 and 15, in the differential signal line SNDT on the transmission side of the semiconductor chip 2, the matching circuit CT2 provided in the second stage is formed by a via hole passing through the interconnect layer, i.e., between the layers 5 and 6. In the same manner as the above-described matching circuit CR1, a plurality of vias 15 connected to the ground potential are provided so as to surround the respective vias of the matching circuit CT2 that forms the differential signal line SNDT.

As shown in fig. 16 to 18, in the differential signal lines SNDR on the reception side of the semiconductor chip 2, the matching circuits CR2 provided in the second stage are each formed by a via passing through the interconnect layer, i.e., between the layers 7 and 9. The vias connecting the lands formed in layer 7, the lands formed in layer 8, and the lands formed in layer 9 are shown in the shape of vias forming matching circuit CR 2. Also, in the same manner as the above-described matching circuit CT1, a plurality of ground paths 16 connected to the ground potential are provided so as to surround the respective paths of the matching circuit CR1 that forms the differential signal line SNDR.

The diameter of the lands connected to the vias forming the matching circuit CR2 in the second stage is made smaller than the diameter of the lands connected to the vias forming the matching circuit CT1 in the first stage. The above relationship is determined by considering that the level of a signal reflected by the parasitic capacitances CT0, CR0 at the input/output ends of the I/O devices Tx1, Rx1, etc. decreases as it goes away from the input/output ends of the I/O devices Tx1, Rx1, etc. That is, when the capacitance value of the matching circuit in the second stage formed at a position farther from the I/O device Tx1, Rx1, etc. than the matching circuit in the first stage is smaller than the capacitance value of the matching circuit in the first stage, an effect of sufficiently canceling the reflected wave reflected at the input/output end of the I/O device Tx1, Rx1, etc. can be obtained. Therefore, as described above, by lowering the capacitance value of the matching circuit CR2 in the second stage more than the capacitance value of the matching circuit CT1 in the first stage, the area of the region for forming the matching circuit CR2 in the second stage can be reduced. Therefore, without reducing the effect of suppressing the distortion of the signal waveform caused by the reflected wave, the density of the matching circuit can be increased and the interconnection density can be further reduced.

Further, as shown in fig. 17 and 18, in the interconnect layer directly above the openings 31 of the second electrodes 11 connected to the respective external terminals 8, that is, in the layer 8, a mesh-like metal material 30 that absorbs electromagnetic waves is formed. Since this can reduce the discontinuity of the impedance at the second electrode 11 in contact with the external terminal 8 (solder bump), the signal transmission characteristics of the differential signal lines SNDR and SNDT can be further improved.

Fig. 21 and 22 show one example of the arrangement of through holes and vias as matching circuits on the package substrate 11. In the same manner as in fig. 10, this example shows a case where the matching circuit CR1 in the first stage of the signal line SNR1 is formed by a via between layers 5 and 6, the matching circuit CR2 in the second stage is formed by a via between layers 7 and 9, the matching circuit CT1 in the first stage of the signal line SNT1 is formed by a via between layers 2 and 4, and the matching circuit CT2 in the second stage is formed by a via between layers 5 and 6.

Fig. 21 is a plan view illustrating one example of an interconnection pattern in the interconnection layer, i.e., layer 2, and fig. 22 is a plan view illustrating one example of an interconnection pattern in the interconnection layer, i.e., layers 4 and 5.

As shown in fig. 21, a plurality of first electrodes 10 are formed in a region directly below the semiconductor chip 2 of the package substrate 1. Among the plurality of first electrodes 10, first signal electrodes 10_ Rx connected to output terminals of the transmission I/O devices Tx of the semiconductor chip 2 and second signal electrodes 10_ Tx connected to input terminals of the reception I/O devices Rx of the semiconductor chip 2 are sequentially arranged. For example, as shown in fig. 21, the two first signal electrodes 10_ Rx forming the differential pair are juxtaposed in the x direction, and in the same manner, the two signal electrodes 10_ Tx forming the differential pair are juxtaposed in the x direction. Then, the differential pairs of the first signal electrodes 10_ Rx and the differential pairs of the second signal electrodes 10_ Tx are alternately arranged in each group or two groups in the y-direction. The arrangement of the first signal electrodes 10_ Tx and the arrangement of the second signal electrodes 10_ Rx are not limited to the case shown in fig. 21 as long as they are sequentially arranged in whole or in part.

The plurality of first signal electrodes 10_ Rx are arranged as described above, and the vias as the matching circuits CR1 are each formed at a position spaced apart from the corresponding first signal electrode 10_ Rx by the interconnect length LR 1. The matching circuit CR1 is thus densely formed in the region S shown in fig. 21 and 22.

Also, the plurality of second signal electrodes 10_ Tx are disposed as described above, and each of the vias as the matching circuit CT1 is formed at a position spaced apart from each of the second signal electrodes 10_ Tx by the interconnection length LT 1. Therefore, the matching circuit CR1 is densely formed in the region U shown in fig. 22. In fig. 22, the interconnect length LR1 is made shorter than the interconnect length LT1 within the error range (within 20%) of the precise interconnect length (λ/4) so that the via and the via do not overlap in a plan view.

From fig. 21 and 22, it can be understood that more matching circuits are formed at higher density in the area a on the face of the package substrate 1. Also, it is understood that the interconnect components connected to the matching circuits are dispersed in a plurality of interconnect layers.

Fig. 23A and 23B show the transmission characteristics of the differential signal line SNDR in the case where the matching circuit CR1 in the first stage is formed of a via and the matching circuit CR2 in the second stage is formed of a via. By extracting model parameters from the interconnect patterns in fig. 12 to 18. And using the model parameters, a simulation is performed using a three-dimensional electromagnetic field simulator to obtain a characteristic curve.

Fig. 23A shows the characteristics of the return loss of the signal frequency in the common mode, and fig. 23B shows the characteristics of the return loss of the signal frequency in the differential mode. Reference numeral 400 represents a required specific value of return loss in the common mode of the transmission line at 12.5GHz, and reference numeral 401 represents return loss of the differential signal line SNDR in the common mode when the matching circuits CR1 and CR2 are not provided, and reference numeral 403 represents return loss of the differential signal line SNDR in the common mode in the case where the matching circuits CR1 and CR2 are provided. Also, reference numeral 410 represents a desired specific value of the return loss in the differential mode of the transmission line at 12.5GHz, and reference numeral 411 represents the return loss of the I/O device Rx in the differential mode. Reference numeral 412 represents the return loss of the differential signal line SNDR in the differential mode in the case where the matching circuits CR1 and CR2 are provided, and reference numeral 413 represents the return loss of the differential signal line SNDR in the differential mode in the case where the matching circuits CR1 and CR2 are provided.

As can be understood from fig. 23A and 23B, good signal transmission characteristics can be achieved in a wide frequency band by providing the matching circuits CR1 and CR2 of the differential signal line SNDR.

Fig. 24A and 24B show transmission characteristics of the differential signal line SNDT when the matching circuit CT1 in the first stage is formed of a via and the matching circuit CT2 in the second stage is formed of a via, respectively. In the same manner as in fig. 23A and 23B, the characteristic curve was obtained by simulation by a three-dimensional electromagnetic field simulator using the extracted model parameters.

Fig. 24A shows the return loss of a signal frequency in the common mode, and fig. 24B shows the return loss of a signal frequency in the differential mode. Reference numeral 500 represents a desired specific value of return loss in the common mode of the transmission line at 12.5GHz, and reference numeral 501 represents return loss of the I/O device Tx in the common mode. Reference numeral 502 represents return loss of the differential signal line SNDT in the common mode when the matching circuits CT1 and CT2 are provided. Also, reference numeral 510 represents a desired specific value of the return loss in the differential mode of the transmission line at 12.5GHz, and reference numeral 511 represents the return loss of the I/O device Tx in the differential mode. Reference numeral 512 represents the return loss of the reference signal line SNDT in the differential mode when the matching circuits CT1 and CT2 are set.

As can be understood from fig. 24A and 24B, good signal transmission characteristics can be achieved in a wide frequency band by the matching circuits CT1 and CT2 that provide the differential signal line SNDT.

A method of manufacturing the semiconductor device 100 will be explained. The semiconductor device 100 is assembled, for example, by the following sequence.

Fig. 25 is a flowchart showing an outline of the manufacturing process of the semiconductor device 100.

Although the following example specifically illustrated refers to a process including introducing an underfill resin after flip-chip bonding as one example, it is apparent that the process may include mounting an underfill resin before flip-chip bonding, and then performing flip-chip bonding.

As shown in fig. 25, the semiconductor chips 2 and 3 having bumps are first provided (S101). For example, in the solder bump forming step proceeding to step S101, a plurality of electrode pads (UBM or the like) are first provided to the device surface of the wafer in which the predetermined circuit pattern is formed and on which the solder bumps forming the bump electrodes 7 are formed. Subsequently, the wafer is divided into individual chips through a wafer probe test step, a bump height inspection step, and a wafer dicing step. Thus, the semiconductor chips 2 and 3 having bumps are obtained.

Then, the package substrate 1 is prepared (S102). In the step of manufacturing the interconnect substrate before step 102, the package substrate 1 is obtained by a manufacturing method of sequentially stacking substrates formed of an upper layer and a lower layer and opening a via hole or a via hole on each stacked body to ensure electrical connection. The method of manufacturing the package substrate 1 is specifically described later.

Subsequently, the package substrate 1 and the semiconductor chips 2 and 3 are electrically connected by a chip bonding step (flip-chip bonding step) (S103). Specifically, in the die bonding step, the electrode pads of the semiconductor chips 2 and 3 and the corresponding first electrodes (first signal electrodes 10_ Rx, second signal electrodes 10_ Tx, etc.) on the corresponding package substrate 1 are connected with the bump electrodes 7 by, for example, reflow processing at a temperature of about 240 ℃ to 260 ℃.

Subsequently, the underfill resin material 12 is injected between the first main surface (upper surface) 1a of the package substrate 1 and the device surface of the semiconductor chip 2, and a curing process is applied (S104). Subsequently, the upper surface of the package substrate 1 and the semiconductor chips 2 and 3 are sealed and encapsulated by a sealing resin material (epoxy resin) (S105). Subsequently, the external solder bump is bonded as the external terminal 8 to the second electrode 11 of the second main surface (lower surface) 1b of the package substrate (S106). Subsequently, the semiconductor device 100 packaged by the above steps is subjected to a marking step of marking the upper surface of the sealing body and the like, and is then subjected to a package test (S107), and the semiconductor device 100 passed through the package test step is packaged and shipped after the appearance inspection (S108).

Fig. 26 shows an outline of a manufacturing process of the package substrate 1.

As shown in fig. 26, a core substrate 21 in which a copper wiring pre-cured sheet is bonded to both sides of a copper wiring board on which an interconnection pattern is formed is prepared (S201). The through hole is bored through the core substrate 21 (S202). In this step, vias forming the matching circuits (CR 1, CT2, etc.) are formed in the same manner as normal vias. Subsequently, plating (electroless plating or electrolytic plating) is applied to the through hole (S203). Subsequently, build-up layers 20 and 22 are formed. After the holes are first filled with resin, an interlayer insulating film is formed on both surfaces (S204). Subsequently, a via is formed by laser fabrication (S205). In this step, the paths forming the matching circuits (CR 2, CT1, etc.) are formed in the same manner as the normal paths. Also, electroless copper plating is applied to the entire surface at a thickness level of several μm (S206). Subsequently, the dry resist film is patterned into an interconnection pattern by using a photomask, and electrolytic copper plating is applied, for example, in the opening portion at a thickness level of 10 μm (S207). Subsequently, the resist is removed and the plated copper is slightly etched to form an interconnect (S208). Subsequently, steps S204 to S208 are repeated, thereby forming build-up layers. After a desired number of interconnect layers are formed in the build-up layer, a solder resist layer is formed as a surface protective film (S209). Subsequently, the first electrode 10 and the second electrode (solder ball pad) 11 are opened as connection portions (pads) to the semiconductor chip 2 and the package substrate 1 (S210). Finally, a surface treatment is applied to the opening portion to complete the package substrate (S211).

As described above, the through holes and vias as the matching circuits can be formed in the same manner as in the case of forming the usual through holes and vias in the package substrate 1, and no other steps are added.

As described above, according to the semiconductor device 100 and the package substrate 1 of the present invention, it is possible to suppress the manufacturing cost of the package substrate while achieving good signal transmission characteristics.

Although the invention proposed by the present inventors has been specifically explained based on the preferred embodiments, it is apparent that the invention is not limited to the above-described embodiments, but can be variously modified within the scope not departing from the gist of the invention.

For example, although an embodiment has been described in which the matching circuit CR1 (CT 1) in the first stage is formed at the position of the interconnect length λ a/4, the present invention is not limited to this embodiment, but the same effect can be obtained by forming the matching circuit CR1 (CT 1) in the first stage at the position of the interconnect length 3 λ a/4. Further, although an embodiment has been described in which the matching circuit CR2 (CT 2) in the second stage is formed at the position of the interconnect length 3 λ a/4, the present invention is not limited to this embodiment, but the same effect can be obtained by forming the matching circuit CR2 (CT 2) in the second stage at the position of the interconnect length λ b/4. For example, in a case where the electromagnetic wavelengths λ a and λ b (signal frequencies fa and fb) of the signal intended to reduce the reflected wave are distant from each other, the matching circuit in the first stage may be formed at the position of λ a/4, and the matching circuit in the second stage may be formed at the position of λ b/4. Alternatively, the matching circuit in the first stage may be formed at a position of 3 λ a/4, and the matching circuit in the second stage may be formed at a position of 3 λ b/4. Also, for a combination of the arrangement of the matching circuits CT2 and CR2, the following pattern can be considered. For example, the combination includes a first pattern in which the matching circuit CT2 is disposed at the position of the interconnection length 3 λ b/4 and the matching circuit CR2 is disposed at the position of the interconnection length 3 λ b/4, and a second pattern in which the matching circuit CT1 is disposed at the position of the interconnection length λ b/4 and the matching circuit CR2 is disposed at the position of the interconnection length λ b/4. The combination further includes a third pattern in which the matching circuit CT2 is disposed at the position of the interconnect length 3 λ b/4 and the matching circuit CR2 is disposed at the position of the interconnect length λ b/4, and a fourth pattern in which the matching circuit CT2 is disposed at the position of the interconnect length λ b/4 and the matching circuit CR2 is disposed at the position of the interconnect length 3 λ b/4. This also applies to the matching circuits CR1 and CT 1. The pattern forming the matching circuit may be variously changed depending on, for example, electromagnetic wavelengths λ a and λ b (signal frequencies fa and fb) intended to reduce reflected waves, a margin of an area on the package substrate 1, and the like. For example, when the matching circuits are intended to be densely arranged in a narrow area, the second pattern may be employed. When the matching circuits are intended to be disposed so as to be dispersed on the interconnect substrate, the third pattern or the fourth pattern may be employed.

This embodiment shows one example of using a via hole for a matching circuit in the first stage of the reception signal line SNDR and using a via hole for a matching circuit in the second stage, using a via hole for a matching circuit in the first stage of the transmission signal line SNDT and using a via hole for a matching circuit in the second stage. However, the present invention is not limited to this configuration. For example, the via may function as a matching circuit in a first stage of the reception signal line SNDR and the via may function as a matching circuit in a second stage, and the via may function as a matching circuit in a first stage of the transmission signal line SNDT and the via may function as a matching circuit in a second stage. Also, in the case where the semiconductor device 100 has only the transmission I/O device, it may be arranged that, among the plurality of transmission signal lines connected thereto, for a part of the signal lines, vias are used as the matching circuit in the first stage and vias are used as the matching circuit in the second stage, and for the other part of the signal lines, vias are used as the matching circuit in the first stage and vias are used as the matching circuit in the second stage, or vice versa. This also applies to the case where the semiconductor device 100 has only a reception I/O device.

Although this embodiment shows the signal lines in which the matching circuits are formed on the package substrate 1 in two stages, the present invention is not limited to such an example, and the number of stages may be changed according to a required specification. For example, the matching circuit may be provided in one stage or three or more stages. Also for matching circuits of three stages or more, the matching circuits can be set with reference to λ/4 or 3 λ/4 in the same manner as in the first stage and the second stage.

Although this embodiment describes an example in which the matching circuit CR1 or the like is formed on the package substrate 1 for impedance matching of the signal line connecting the bump electrode 7 and the external terminal 8 in the signal line connecting the semiconductor device 100 and the other semiconductor device 101, the present invention is not limited to this embodiment. For example, for impedance matching of a signal line connecting the bump electrode 7 of the semiconductor chip 2 and the bump electrode 13 of the semiconductor chip 3, a matching circuit may be formed by a through hole or a via on the package substrate 1 in which the signal line is formed.

Claims (20)

1. A semiconductor device comprising a semiconductor chip and an interconnect substrate having the semiconductor chip mounted on the interconnect substrate,

wherein the interconnect substrate comprises:

a first main surface formed with a plurality of first electrodes electrically connected to the semiconductor chip;

a second major surface opposite the first major surface; and

an interconnect region interposed between the first major surface and the second major surface,

wherein the first electrode includes a plurality of first and second signal electrodes arranged in sequence for receiving a supply of signals each at a predetermined frequency, and

wherein the first signal electrode and the second signal electrode are dispersedly disposed in the arrangement thereof, and

wherein the interconnect region comprises:

a core substrate;

a plurality of interconnection layers formed on both surfaces of the core substrate, respectively;

a plurality of first vias for forming impedance matching capacitances, the first vias passing through the core substrate;

a plurality of first vias for forming impedance matching capacitances, the first vias passing through the interconnect layer formed to the core substrate on the first main surface side;

a plurality of first signal interconnects connected to corresponding ones of the first signal electrodes; and

a plurality of second signal interconnects connected to the corresponding second signal electrodes,

wherein each first via is connected with the first signal interconnect at a position spaced apart from the first signal electrode by a first interconnect length, and

wherein the first via is connected to the second signal interconnect at a location spaced apart from the second signal electrode by a second interconnect length that is equal to the first interconnect length.

2. The semiconductor device as set forth in claim 1,

wherein the interconnect region further comprises:

a plurality of second vias for forming impedance matching capacitances, the second vias passing through the core substrate; and

a plurality of second vias for forming impedance matching capacitances, the second vias passing through the interconnect layer formed to the core substrate on the second main surface side,

wherein each second via is connected with the second signal interconnection at a position spaced apart from the second signal electrode by a third interconnection length, the third interconnection length being longer than the first interconnection length, an

Wherein each second via is connected to the first signal interconnect at a location spaced apart from the first signal electrode by a fourth interconnect length that is equal to the third interconnect length.

3. The semiconductor device according to claim 2, wherein

The first interconnect length is a length corresponding to 1/4 times the electromagnetic wavelength of the first frequency in the signal band required according to the transmission line of the signal.

4. A semiconductor device according to claim 3, wherein

The third interconnect length is a length corresponding to 3/4 of an electromagnetic wavelength of a second frequency in a signal band required according to a transmission line of the signal, the second frequency being different from the first frequency.

5. The semiconductor device according to claim 2, wherein

The first interconnect length is a length corresponding to 3/4 times the electromagnetic wavelength of the first frequency in the signal band required according to the transmission line of the signal.

6. The semiconductor device according to claim 2, wherein

The first via and the first via do not overlap in a plan view.

7. The semiconductor device according to claim 2, wherein

The first signal interconnect is a first differential interconnect pair formed by two parallel interconnects, and the second signal interconnect is a second differential interconnect pair formed by two parallel interconnects.

8. The semiconductor device according to claim 2, wherein

One of the first signal electrode and the second signal electrode is a receiving electrode for inputting a signal to the semiconductor chip, and the other of the first signal electrode and the second signal electrode is a transmitting electrode for outputting a signal from the semiconductor chip.

9. The semiconductor device according to claim 2, wherein

In a cross-sectional view, a diameter of an uppermost land and a diameter of a lowermost land connected to the first through-hole are different.

10. The semiconductor device according to claim 2, wherein

The first through-hole is connected to the plurality of lands in a vertical direction in a cross-sectional view.

11. The semiconductor device according to claim 2, wherein

In a cross-sectional view, a diameter of an uppermost land and a diameter of a lowermost land connected to the first via are different.

12. The semiconductor device according to claim 2, wherein

A plurality of lands are connected to the first via in a vertical direction in a cross-sectional view.

13. The semiconductor device according to claim 2, wherein

A portion of the plurality of first vias is connected to the second signal interconnect with one pad, and a remaining portion of the plurality of first vias is connected to the second signal interconnect with a plurality of pads.

14. The semiconductor device according to claim 2, wherein

The diameter of the land for the first via is larger than the diameter of the land for the second via.

15. The semiconductor device according to claim 2, wherein

The first via has a land diameter larger than a land diameter of an adjacent via for connecting adjacent interconnect layers to each other.

16. The semiconductor device according to claim 2, wherein

The semiconductor chip has a plurality of interface buffers connected to the first signal terminal and the second signal terminal respectively in correspondence.

17. The semiconductor device of claim 16, further comprising:

a plurality of external terminals, each of which is provided with a plurality of external terminals,

wherein the second main surface includes a plurality of second electrodes electrically connected to the corresponding external terminals,

wherein the first signal interconnect forms a transmission line electrically connecting the first signal electrode and the corresponding second electrode, and

wherein the second signal interconnect forms a transmission line electrically connecting the second signal electrode and the corresponding second electrode.

18. An interconnect substrate comprising:

a first main surface formed with a plurality of first electrodes for electrical connection with a semiconductor chip;

a second major surface opposite the first major surface; and

an interconnect region interposed between the first major surface and the second major surface,

wherein the first electrode includes a plurality of first signal electrodes and second signal electrodes arranged in sequence for receiving a supply of a signal at a predetermined frequency,

wherein the first signal electrode and the second signal electrode are disposed dispersedly in the arrangement thereof,

wherein the interconnect region comprises:

a core substrate;

a plurality of interconnection layers formed on both surfaces of the core substrate, respectively;

a plurality of first vias for forming impedance matching capacitances, the first vias passing through the core substrate;

a plurality of first vias for forming impedance matching capacitances, the first vias passing through the interconnect layer formed to the core substrate on the first main surface side;

a plurality of first signal interconnects connected to corresponding first signal electrodes; and is

Wherein a plurality of second signal interconnects are connected to corresponding second signal electrodes,

wherein each first via is connected to the first signal interconnect at a location spaced apart from the first signal electrode by a first interconnect length, an

Wherein the first via is connected to the second signal interconnect at a location spaced apart from the second signal electrode by a second interconnect length that is equal to the first interconnect length.

19. An interconnection substrate according to claim 18,

wherein the interconnect region further comprises:

a plurality of second vias for forming impedance matching capacitances, the second vias passing through the core substrate; and

a plurality of second vias for forming impedance matching capacitances, the second vias passing through the interconnect layer formed to the core substrate on the second main surface side,

wherein each second via is connected to the second signal interconnect at a location spaced apart from the second signal electrode by a third interconnect length, the third interconnect length being longer than the first interconnect length, an

Wherein each second via is connected to the second signal interconnect at a location spaced apart from the first signal electrode by a fourth interconnect length that is equal to the third interconnect length.

20. A semiconductor device, comprising:

a semiconductor chip; and

an interconnect substrate having the semiconductor chip mounted thereon,

wherein the interconnect substrate comprises:

a first main surface electrically connected with the semiconductor chip and formed with a plurality of signal electrodes supplied with signals at a predetermined frequency;

a second major surface opposite the first major surface; and

an interconnect region interposed between the first major surface and the second major surface,

wherein the interconnect region comprises:

a core substrate;

a plurality of interconnection layers formed on both surfaces of the core substrate, respectively;

a plurality of signal interconnects formed in the interconnect layer and extending from the signal electrodes; and

a plurality of impedance matching circuits each connected to the signal interconnect at a position spaced apart from the signal electrode by a predetermined interconnect length,

wherein a part of the plurality of impedance matching circuits is formed by a plurality of through holes passing through the core substrate, and the remaining part of the plurality of impedance matching circuits is formed by a plurality of vias passing through the interconnect layer formed to the core substrate on the first main surface side, and wherein each of the plurality of through holes does not overlap with each of the plurality of vias in a plan view.