HK1201101B - Method of manufacturing semiconductor device and semiconductor device - Google Patents

Description

Method for manufacturing semiconductor device and semiconductor device

Cross Reference to Related Applications

The disclosure of japanese patent application No. 2013-061089, filed 2013, month 3 and 22, is hereby incorporated by reference in its entirety, including the specification, drawings and abstract.

Technical Field

The present invention relates to a manufacturing technique of a semiconductor device and a semiconductor device, and for example, to an effective technique suitable for a semiconductor device obtained by mounting a semiconductor chip on a wiring board via bump electrodes.

Background

Japanese patent laid-open No. 2008-80396 (patent document 1) describes a solder paste composition for precoating solder on the surface of an electrode, the solder paste composition containing solder powder or a solder material of a precipitation type and a flux.

Japanese patent laid-open No. 5 (1993) -308184 (patent document 2) describes a solder-coated circuit board having a solder layer on its land, the solder layer having a thickness required for soldering a component lead. The pad has the following structure: which is locally increased in width in the pad length direction and has a solder bump portion on the resulting wide-width portion, whose solder layer is thicker than that of the other portion.

WO2009/034628 (patent document 3) describes a solder-precoated substrate having a connection conductor pattern constituted by a wiring pattern to be a wiring and a connection pad formed continuously from the wiring pattern at a position where a bump provided on an electronic component is to be soldered. The connection pad is formed to have a width dimension larger than that of the wiring pattern.

Japanese patent laid-open No. 2000-77471 (patent document 4) describes a flip chip package substrate having a wiring pattern composed of a wiring pattern and connection pads to which bumps are to be soldered. Further, this document describes a technique of forming the connection pad to have a width dimension larger than that of the wiring pattern.

[ patent document 1] Japanese patent laid-open No. 2008 & 80396

[ patent document 2] Japanese patent laid-open No. Hei 5 (1993) -308184

[ patent document 3] WO2009/034628

[ patent document 4] Japanese patent laid-open No. 2000-

Disclosure of Invention

The BGA (ball grid array) package has the following structure: the semiconductor chip is mounted on the wiring board via bump electrodes formed as connection terminals on the surface of the semiconductor chip.

The wiring substrate of the BGA package requires a region on the surface thereof for arranging a plurality of lead portions to be connected with a plurality of bump electrodes arranged on the semiconductor chip side. In this region, an insulating film formed on a surface of the wiring substrate is partially opened and the lead portion is disposed so as to be exposed from the opened portion of the insulating film.

Such a wiring substrate of BGA has a plurality of lands for connection with external terminals of BGA on its back surface side, and the plurality of lead portions on the front surface side are electrically connected with the plurality of lands on the back surface side respectively by wires.

Therefore, on the surface side of the substrate, wires are drawn from a lead portion for flip-chip bonding (the lead portion is exposed at the opening portion of the insulating film) to the inside or outside of the opening portion of the insulating film, and these wires are drawn to be connected with lands on the back surface side.

When the number of pins increases and the wiring density becomes high as the BGA has a stronger function, it becomes necessary to draw out wiring so as to cross the inner region and the outer region of the opening portion of the insulating film on the surface side of the substrate.

In flip chip bonding, the upper surface of the lead portion is sometimes precoated with solder to stably connect a plurality of bump electrodes of the semiconductor chip to the lead portion of the wiring substrate. During the precoating, the upper surface of the wiring that spans the opening portion of the insulating portion of the wiring substrate and thus has an exposed surface is also precoated with solder.

The inventors of the present invention studied soldering of a flip chip package using a wiring substrate equipped with the above-described wiring across the opening portion, and thereby found the problems described below.

In the step of precoating the upper surfaces of the plurality of lead portions of the wiring substrate with solder before the flip-chip packaging step, when solder is supplied onto the lead portions and solder reflow is performed, the solder may accumulate at any position of the wiring across the opening portion after the reflow. If the height of the accumulated solder is higher than that of the bump electrode of the semiconductor chip, contact (interference) between the accumulated solder and the surface of the semiconductor chip occurs during flip-chip bonding and the semiconductor chip is lifted by the accumulated solder because it prevents the bump electrode of the semiconductor chip from contacting the lead portion of the wiring substrate, which inevitably leads to connection failure (non-connection) between the bump electrode and the lead portion.

It is an object of the embodiments disclosed herein to provide a technique capable of improving connection reliability in flip-chip bonding of a semiconductor device.

Additional objects and novel features will be apparent from the description and drawings herein.

A method of manufacturing a semiconductor device according to an embodiment includes: a step of preparing a wiring substrate including a first surface having a plurality of terminals thereon, the first surface having a first region obtained by opening an insulating film, a second region located inside the first region, and a third region located outside the first region; a step of preparing a semiconductor chip having bump electrodes on a plurality of surface electrodes thereof. Further, the method includes a step of electrically connecting the bump electrodes of the semiconductor chip and the terminals of the wiring substrate by the connection members. The wiring substrate has, in a first region thereof, a terminal and a wiring across the first region and the wiring has a first portion across the first region and a second portion exposed from the second region or the third region and connected to some of the terminals. The terminal of the second portion has a bump electrode thereon and the first portion has a wider portion than the wiring width.

According to the above embodiment, the connection reliability of flip chip bonding of the semiconductor device can be improved.

Drawings

Fig. 1 is a plan view showing an example of a structure of a main surface of a semiconductor chip to be mounted on a semiconductor device of an embodiment;

fig. 2 is a cross-sectional view showing an example of the structure of a semiconductor device of the embodiment;

fig. 3 is a partially enlarged cross-sectional view showing an example of a detailed structure of the semiconductor device shown in fig. 2;

fig. 4 is a partial cross-sectional view showing an example of a connection state of a pillar-shaped bump electrode in the semiconductor device shown in fig. 2;

fig. 5 is a partial plan view showing an example of wiring direction on the upper surface of the wiring substrate to be mounted on the semiconductor device of the embodiment;

fig. 6 is a partially enlarged top view showing an example of the structure of the portion B shown in fig. 5;

fig. 7 is a partially enlarged top view showing an example of the structure of the portion C shown in fig. 5;

fig. 8 includes a flowchart and a cross-sectional view showing an example of a manufacturing process of a semiconductor device of the embodiment;

fig. 9 is a plan view showing an example of a structure of a wiring substrate to be used in the manufacturing shown in fig. 8;

fig. 10 is a cross-sectional view showing an example of the structure of a lead before a solder coat is formed in the manufacture of the wiring substrate shown in fig. 9;

fig. 11 is a cross-sectional view showing an example of the structure of a lead after a solder coat is formed in the manufacture of the wiring substrate shown in fig. 9;

fig. 12 is a cross-sectional view showing an example of a state of solder after reflow processing in manufacturing of the wiring substrate shown in fig. 9;

fig. 13 is an enlarged plan view showing an example of a state of the solder shown in fig. 12;

fig. 14 is a partial plan view showing an example of a state of solder after reflow processing of a wiring substrate to be used in the embodiment;

FIG. 15 is a partial cross-sectional view showing the structure taken along line A-A shown in FIG. 14;

FIG. 16 is a top view showing an example of a structure after application of an underfill material in the fabrication shown in FIG. 8;

fig. 17 is a plan view showing an example of a structure after flip-chip bonding in the manufacture shown in fig. 8;

fig. 18 is a partial top view showing an example of the structure after flip chip bonding shown in fig. 17;

FIG. 19 is a partial cross-sectional view showing the structure taken along line A-A shown in FIG. 18;

fig. 20 is a cross-sectional view showing the structure of a wiring substrate to be used in the manufacture of a semiconductor device of a second modification of the embodiment;

fig. 21 is a cross-sectional view showing a structure after flip-chip bonding in manufacturing of a semiconductor device of a second modification of the embodiment;

fig. 22 is a cross-sectional view showing a structure after application of an underfill material in the manufacture of a semiconductor device of a second modification of the embodiment;

fig. 23 is a cross-sectional view showing a structure after ball mounting in manufacturing of a semiconductor device of a second modification of the embodiment;

fig. 24 is a partial plan view showing a structure of a flip chip bonding portion in the semiconductor device of the comparative example;

fig. 25 is a partial cross-sectional view showing the structure taken along line a-a shown in fig. 24.

Detailed Description

In the following embodiments, descriptions of the same or similar parts are not repeated in principle unless otherwise specifically necessary.

In the following embodiments, the description is divided into a plurality of sections or embodiments, if necessary, for convenience. These parts or embodiments are not independent of each other, but are in a relationship of a modification, detailed description, or supplementary description, which is one of the others, in part or in whole, unless otherwise specifically stated.

In the following embodiments, when referring to the number of elements (including numbers, numerical values, amounts, ranges, etc.), the number is not limited to a specific number, but may be larger or smaller than the specific number unless otherwise specifically stated or it is obvious in principle that the number is limited to the specific number.

Moreover, in the following embodiments, it is needless to say that constituent elements (including constituent steps) are not always necessary unless otherwise specifically stated or it is obvious in principle that they are necessary.

In the following embodiments, the terms "comprising a", "consisting of a", "having a", "containing a", and the like, for any constituent element, do not exclude additional elements unless otherwise specifically stated that the element is limited to the referenced element. Similarly, in the following embodiments, when referring to the shape or positional relationship of constituent elements, the shape or positional relationship substantially similar or analogous thereto is also included unless otherwise specifically stated or is apparently not in principle. This also applies to the above-mentioned values, ranges, etc.

Embodiments will be described in detail below with reference to the accompanying drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by like reference numerals and overlapping description thereof is not repeated. The top view may even be shaded to facilitate understanding of the drawings.

< description of the problem with reference to the drawings >

First, problems of flip chip bonding of semiconductor devices studied by the inventors of the present invention for comparison will be described with reference to some drawings.

Fig. 24 is a partial plan view showing a structure of a flip chip bonding portion in a semiconductor device of a comparative example studied by the inventors of the present invention; and fig. 25 is a partial cross-sectional view showing the structure taken along the line a-a shown in fig. 24.

As shown in fig. 24, the wiring substrate 10 has an insulating film 10b on its upper surface 10a and has a plurality of terminals (lead portions) 10e for performing flip-chip bonding to the semiconductor chip 1 shown in fig. 25 in an opening portion 10c formed on the insulating film 10 b. The terminals have been arranged in two rows and exposed. These terminals 10e each have a surface precoated with solder 11.

On the wiring substrate 10, wires 10d have been led from terminals 10e for flip chip bonding placed at the opening portions 10c of the insulating film 10b to any region inside or outside the opening portions 10c of the insulating film 10b and these wires 10d have been led to bump lands on the back surface side. When the number of pins is increased and the wiring density becomes higher as the semiconductor device has a stronger function, the wiring 10d1 that spans the regions inside and outside the opening portion 10c of the insulating film 10b and surrounds the periphery becomes necessary on the upper surface 10a side of the wiring substrate 10.

The terminal 10e has a corresponding surface precoated with solder 11, but when the wiring 10d1 is formed in the opening portion 10c, this wiring 10d1 is also precoated with solder 11. This means that when solder is supplied onto the wiring 10d or the wiring 10d1 and solder reflow is performed, the solder 11 is formed on the terminal 10e and the wiring 10d1 after the reflow.

At this time, the solder 11 sometimes accumulates at an arbitrary position of the wiring 10d1 across the opening portion 10c and the height of the solder accumulated at this portion (which will be referred to as "solder accumulating portion" hereinafter) becomes high.

Therefore, as shown in part R of fig. 25, during flip chip bonding, when the height of the solder 11 accumulated on the wiring 10d1 exceeds the height of the solder 11 on the terminal 10e (which terminal 10e is originally a pad PD to be connected to the semiconductor chip 1), contact (interference) is generated between the solder 11 formed by accumulation and the surface of the semiconductor chip 1, and the semiconductor chip 1 is lifted by the solder 11 formed by accumulation.

The inventors of the present invention have found that, thereby, the bump electrode (bump electrode 12) of the semiconductor chip 1 does not reach the terminal 10e of the wiring substrate 10, causing a connection failure (no connection) between the bump electrode and the terminal 10 e.

Specifically, when the wiring 10d1 of the opening portion 10c becomes long, the above-described solder reservoir portion is easily formed. This means that, when the wiring 10d1 of the opening portion 10c is long, temperature distribution occurs in the heated wiring 10d1 at the time of reflow, and the solder at the high temperature portion melts first. In this way, a solder pool is formed by accumulating additional solder that is subsequently melted on the previously melted solder.

When the solder accumulating portion and the surface of the semiconductor chip 1 are in contact with each other, the semiconductor chip 1 is mounted obliquely, which tends to cause a package failure of the semiconductor chip 1. Also, when the solder accumulating portion is formed on the wiring 10d1 of the opening portion 10c, voids tend to be formed in the vicinity of the solder accumulating portion when the underfill is filled in the molding step performed after flip-chip bonding, which may have a detrimental effect on the reliability of the semiconductor device.

Note that when the wiring substrate 10 is a through-hole substrate, the wiring density is not easily increased as compared with a build-up type substrate in which the wiring density is increased by forming fine pitch wiring. Thus, in order to increase the wiring density, wirings such as the wiring 10d1 crossing the opening portion 10c are inevitably formed. The use of a through-hole substrate tends to further cause the above-mentioned problems.

A through-hole substrate as referred to herein has a plurality of through-holes or vias penetrating the substrate from the surface to the back surface. Since a build-up layer (wiring layer) cannot be formed thereon unlike a build-up layer substrate, a through-hole substrate is not suitable for a substrate for increasing wiring density. However, the through-hole substrate is inexpensive compared to the build-up substrate because no build-up layer is formed thereon.

Therefore, in the embodiments of the present invention, measures are taken to improve the connection reliability in flip chip bonding of a semiconductor device while using an inexpensive through electrode substrate. The semiconductor device of the embodiment of the present invention and the manufacturing method thereof, which have taken this measure, will be described below.

< Structure of semiconductor device according to embodiment of the present invention >

Fig. 1 is a plan view showing an example of a structure of a main surface of a semiconductor chip to be mounted on a semiconductor device of an embodiment; fig. 2 is a cross-sectional view showing an example of the structure of a semiconductor device of the embodiment; fig. 3 is a partially enlarged cross-sectional view showing an example of a detailed structure of the semiconductor device shown in fig. 2; and fig. 4 is a partial cross-sectional view showing an example of a connection state of a pillar-shaped bump electrode in the semiconductor device shown in fig. 2. Fig. 5 is a partial plan view showing an example of wiring direction on the upper surface of the wiring substrate to be mounted on the semiconductor device of the embodiment; fig. 6 is a partially enlarged plan view showing an example of the structure of the portion B in fig. 5; and fig. 7 is a partially enlarged plan view showing an example of the structure of the portion C in fig. 5.

As shown in fig. 1, the semiconductor chip 1 to be mounted on the semiconductor device of the embodiment of the present invention is square and the semiconductor chip 1 has, in each region on its main surface (first main surface) 1a, a columnar bump electrode PLBMP1 and a columnar bump electrode PLBMP 2. These pillar bump electrodes PLBMP1 and pillar bump electrodes PLBMP2 each include, for example, a pillar portion composed of copper (Cu) and a connection portion made of solder formed on the pillar portion. In this embodiment, the columnar portion has a height of, for example, about 30 μm, and the connection portion has a height (solder height) of about 15 μm. The columnar portion has a cylindrical or cubic shape. In a plan view, the columnar portion having a cylindrical shape has a diameter of about 30 μm to 35 μm, and the side length of the columnar portion having a cubic shape is about 30 μm to 35 μm.

Specifically, in the semiconductor chip 1 of the embodiment of the present invention, as shown in fig. 1, the main surface 1a of the semiconductor chip 1 has been divided into: a region (first region) AR1, a region (second region) AR2 located inside the region AR1, and a region (fourth region) AR4 located inside the region AR 2. The region AR1 has a plurality of stud bump electrodes PLBMP1 therein, and the region AR4 has a plurality of stud bump electrodes PLBMP2 therein. This means that region AR2 is interposed between stud bump electrode PLBMP1 and stud bump electrode PLBMP 2. At this time, the region AR1 has therein pillar bump electrodes PLBMP1 in a plurality of rows (two rows in fig. 1) and the region AR4 has therein pillar bump electrodes PLBMP2 at equal intervals.

In the embodiment of the present invention, the minimum pitch between two adjacent bumps of the stud bump electrodes PLBMP1 disposed in the region AR1 is smaller than the minimum pitch between two adjacent bumps of the stud bump electrodes PLBMP2 disposed in the region AR 4. The minimum pitch between two adjacent bumps of the stud bump electrode PLBMP1 placed in the region AR1 is about 40 μm to 60 μm. Even if the minimum pitch between two adjacent bumps of the pillar bump electrode PLBMP1 is equal to or greater than the minimum pitch between two adjacent bumps of the pillar bump electrode PLBMP2, such a case is not particularly excluded.

Region AR2 has neither stud bump electrode PLBMP1 nor stud bump electrode PLBMP2 therein.

However, the semiconductor chip 1 may have the bump electrodes BMP on the entire main surface 1a thereof.

Next, the configuration of the semiconductor device of the embodiment of the present invention will be described. As shown in fig. 2, the semiconductor device of the present embodiment has a through-hole substrate 2, and this through-hole substrate 2 has a plurality of solder balls SB on its back surface (second surface) 2b (back surface 2b, i.e., the lower surface of through-hole substrate 2). On the other hand, the through-hole substrate 2 has the semiconductor chip 1 on its upper surface (first surface).

At this time, the semiconductor chip 1 is on the upper surface 2a of the through-hole substrate 2 so as to electrically connect the stud bump electrodes PLBMP1 and the stud bump electrodes PLBMP2, which are respectively formed on the plurality of electrode pads (surface electrodes) 1c on the main surface 1a of the semiconductor chip 1, to terminals (not shown) formed on the upper surface 2a of the through-hole substrate 2. The columnar bump electrodes PLBMP1 and PLBMP2 have been electrically connected to the terminals of the through-hole substrate 2 via solders 3(4) as connection members.

The space formed between the semiconductor chip 1 and the via substrate 2 is filled with underfill UF, which is a molding resin. In many cases, the underfill UF is an epoxy-based resin and is used to ensure connection reliability between the semiconductor chip 1 and the via substrate 2.

The back surface (second main surface) 1b of the semiconductor chip 1 is exposed upward through the back surface and this back surface 1b may have a heat radiation member such as a heat sink thereon.

With respect to the semiconductor device of the embodiment of the present invention having the configuration, particularly the internal structure of the through-hole substrate 2 will be described in more detail next. In the embodiment of the present invention, as shown in fig. 3, the through-hole substrate 2 is made of a core layer CRL containing a glass fiber fabric. The through-hole substrate 2 has through-holes TH1, TH2, and TH3 penetrating the through-hole substrate 2 from the upper surface 2a to the lower surface 2 b.

The through-hole substrate 2 has a solder resist (insulating film) 2c on its upper surface 2a and the through-holes TH1, TH2, and TH3 are filled with the solder resist 2 c. As shown in fig. 5, the solder resist 2c has an opening portion (area AR 1), and, in this opening portion, a plurality of terminals (land pattern, pin pattern) TE1 or a plurality of terminals (land pattern, pin pattern) TE2 are exposed.

For example, the through-hole substrate 2 has a plurality of terminals TE1 on the upper surface 2a thereof and some of the terminals TE1 are electrically connected to the through-holes TH1 on the upper surface 2a of the through-hole substrate 2, and some of the other terminals TE1 are similarly electrically connected to the through-holes TH2 on the upper surface of the through-hole substrate 2.

The through-hole substrate 2 also has terminals TE2 on the upper surface 2a thereof, and these terminals TE2 are electrically connected with the through-holes TH3 of the upper surface 2a of the through-hole substrate 2. Further, the through-hole substrate 2 has the semiconductor chip 1 on the upper surface 2a thereof, and the columnar bump electrode PLBMP1 formed on the semiconductor chip 1 is electrically connected to the terminal TE1 formed on the upper surface 2a of the through-hole substrate 2.

Similarly, the columnar bump electrodes PLBMP2 formed on the semiconductor chip 1 are electrically connected to the terminals TE2 formed on the upper surface 2a of the through-hole substrate 2. This means that the through-hole substrate 2 has only one wiring layer on the surface and the back surface of the core layer CRL, and the semiconductor device of the embodiment of the present invention has a structure in which the stud bump electrodes are directly electrically connected to the wiring layer.

As shown in fig. 3, on the other hand, the through-hole substrate 2 further has a solder resist 2c on its back surface 2 b. The solder resist 2c has an opening portion therein from which a plurality of back surface terminals (lands) BTE1 are exposed. These back surface terminals BTE1 are electrically connected to the through holes TH1, TH2 and TH3 on the back surface 2b of the through hole substrate 2. These back surface terminals BTE1 have solder balls SB thereon.

More specifically, in the through-hole substrate 2 of the embodiment of the present invention, the thickness (in consideration of the wiring thickness on the upper surface 2a and the back surface 2 b) that can be caused by the core layer CRL (about 0.4 mm) is about 0.5mm and the through-hole diameter is about 150 μm.

Next, the formation positions of the through holes TH1, TH2, and TH3 in the through hole substrate 2 and the formation positions of the terminals TE1 and TE2 on the upper surface 2a of the through hole substrate 2 of the embodiment of the present invention will be described.

First, in fig. 3, the through-hole substrate 2 has the semiconductor chip 1 thereon and the through-hole substrate 2 is divided into regions as shown below. Specifically, of the regions on the through-hole substrate 2, the outer region having no semiconductor chip 1 thereon is defined as a region (third region) AR 3. The region having the semiconductor chip 1 thereon is divided into the region AR1 of the semiconductor chip 1, the region AR2 of the semiconductor chip 1, and the region AR4 of the semiconductor chip 1 so as to correspond to the division as shown in fig. 1. Thus, the area on the upper surface 2a of the through-hole substrate 2 can be divided into the above-described four areas, as shown in fig. 3.

Here, the area AR3 will be described. The through-hole substrate 2 has a plurality of through-holes TH2 in its area AR 3. This means that, in these regions of the upper surface 2a of the through-hole substrate 2, the region AR3 has a plurality of through-holes TH2 therein, but it is not terminated with both the terminals TE1 and TE 2. Specifically, the through hole TH2 is electrically connected to the terminal TE1, but the terminal TE1 is not formed in the region AR3 having the through hole TH 2.

Next, the area AR1 will be described. In the through-hole substrate 2, the area AR1 has a plurality of terminals TE1 therein. This means that, in these regions of the upper surface 2a of the through-hole substrate 2, the region AR1 has the terminal TE1 therein, but does not have the through-holes TH1, TH2, and TH 3. Specifically, some of the terminals TE1 among the terminals TE1 are electrically connected to the through holes TH1, and some of the terminals TE1 among the remaining terminals TE1 are electrically connected to the through holes TH 2. There are neither through holes TH1 nor through holes TH2 in the area AR1 having the terminal TE1 therein.

The semiconductor chip 1 has a plurality of stud bump electrodes PLBMP1 in the region AR1 and the stud bump electrodes PLBMP1 formed in the region AR1 of the semiconductor chip 1 are directly electrically connected to the terminals TE1 formed in the region AR1 of the via substrate 2.

Next, the area AR2 will be described. The through-hole substrate 2 has a plurality of through-holes TH1 in its area AR 2. This means that, in these regions of the upper surface 2a of the through-hole substrate 2, the region AR2 has a plurality of through-holes TH1 therein, but is not terminated with both the terminals TE1 and TE2 therein. Specifically, the through hole TH1 is electrically connected to the terminal TE1, but the terminal TE1 is not present in the region AR2 having the through hole TH 1. Neither the stud bump electrode PLBMP1 nor the stud bump electrode PLBMP2 is present in the region AR2 of the semiconductor chip 1.

The area AR4 will be described next. The through-hole substrate 2 has a plurality of through-holes TH3 and a plurality of terminals TE2 in its area AR 4. This means that, in these regions of the upper surface 2a of the through-hole substrate 2, the region AR4 has both the plurality of through-holes TH3 and the plurality of terminals TE 2. Specifically, the through hole TH3 is electrically connected to the terminal TE2 and this terminal TE2 is also formed in the area AR4 having the through hole TH 3. The region AR4 of the semiconductor chip 1 has a plurality of stud bump electrodes PLBMP2 therein and the stud bump electrodes PLBMP2 formed in the region AR4 of the semiconductor chip 1 are electrically connected to the terminals TE2 formed in the region AR4 of the via substrate 2.

Next, a gap (interval) between the semiconductor chip 1 and the through-hole substrate 2 will be described with reference to fig. 4. In the present embodiment, as shown in fig. 4, the through-hole substrate 2 has the terminal TE1 thereon and the pillar bump electrode PLBMP1 is mounted on the terminal TE 1. This stud bump electrode PLBMP1 includes, for example, a columnar portion made of copper and a connection portion made of solder formed on the columnar portion. The columnar bump electrode PLBMP1 is located in an opening portion OP formed on a passivation film (surface protective film) PAS made of, for example, a silicon nitride film, and the columnar bump electrode PLBMP1 is located on a pad PD (electrode pad 1c in fig. 2) exposed from the opening portion OP. The pad PD is located on the interlayer insulating film IL.

Even if the pillar bump electrode PLBMP1 having such a configuration is made small, the pillar portion made of copper prevents the gap (interval) T between the semiconductor chip 1 and the via substrate 2 from becoming small. This means that the stud bump electrode PLBMP1 includes a connection portion made of solder and a stud portion (copper) having a melting point higher than that of the connection portion (solder).

When the semiconductor chip 1 is mounted on the through-hole substrate 2 as shown in fig. 2 and the stud bump electrode PLBMP1 of the semiconductor chip 1 is connected to the terminal TE1 of the through-hole substrate 2 by melting the connection portion (solder) of the stud bump electrode PLBMP1 at a high temperature (for example, about 240 ° to 260 °), the bump electrode PLBMP1 is not melted at the high temperature because the melting point of the columnar portion (copper) of the bump electrode PLBMP1 is higher than the melting point of the connection portion (solder).

Thus, as shown in fig. 4, the gap (interval) T between the semiconductor chip 1 and the via substrate 2 does not become smaller than the height of the columnar portion (copper) of the columnar bump electrode PLBMP 1. Therefore, when the pillar bump electrode PLBMP1 shown in fig. 4 is used, even if the size of the pillar bump electrode PLBMP1 itself becomes small, it is possible to suppress deterioration of the filling performance of the underfill or deterioration of the connection reliability between the semiconductor chip 1 and the via substrate 2. Therefore, the semiconductor chip 1 of the embodiment of the present invention uses, for example, as shown in fig. 2 or 3, a stud bump electrode PLBMP1 or a stud bump electrode PLBMP 2.

In the above-described example, the columnar portion of the columnar bump electrode PLBMP1 was made of copper, but any material (metal) having a melting point higher than that of the connection portion can be used without problem. The solder of the connection portion of the stud bump electrode PLBMP1 is preferably a tin-silver (Sn-Ag) -based or tin-silver-copper (Sn-Ag-Cu) -based lead-free solder.

Next, the configuration of the upper surface 2a of the through-hole substrate 2 of the embodiment of the invention will be described with reference to a partial top view of fig. 5 to clearly explain the positional relationship between the through-holes TH1, TH2, and TH3 and the terminals TE1 and TE 2. Fig. 5 shows approximately one quarter of the entire area of the upper surface 2a of the through-hole substrate 2. Fig. 5 shows a region AR1, a region AR2, a region AR3, and a region AR 4.

As shown in fig. 3 and 5, the area AR3 is an area located on the outer periphery of the semiconductor chip 1 in plan view. In other words, the area AR3 is an area that does not overlap with the semiconductor chip 1 in the top view. The region AR1, the region AR2, and the region AR4 are regions located inside the outer periphery of the semiconductor chip 1 in plan view. In other words, the region AR1, the region AR2, and the region AR4 are regions overlapping with the semiconductor chip 1 in a plan view.

In fig. 5, the area AR1 has a plurality of terminals TE1 therein. More specifically, the area AR1 has a plurality of terminals TE1 in two rows. For example, the number of the terminals TE1 disposed in a line near the outer side is larger than the number of the terminals TE1 disposed in a line near the inner side.

The terminals TE1 arranged in a row near the outside of this area are electrically connected to the through holes TH2 formed in the area AR 3. More specifically, the area AR3 has a plurality of through holes TH2 therein and it also has a land LND2 that is in contact with these through holes TH 2. These lands LND2 are electrically connected to terminals TE1 provided in a row near the outside via second wires 2 e.

The terminals TE1 arranged in a row near the inner side of this region are electrically connected to the through holes TH1 formed in the region AR 2. More specifically, the area AR2 has a plurality of through holes TH1 and it also has a land LND1 that is in contact with these through holes TH 1. These lands LND1 are electrically connected to terminals TE1 provided in a row near the inside via first wires 2 d.

The area AR4 has a plurality of through holes TH3 and a plurality of terminals TE2 therein. The terminal TE2 formed in the area AR4 is electrically connected to the through hole TH3 formed in the same area AR 4. More specifically, the area AR4 has a plurality of through holes TH3 and it has a land LND3 that is in contact with the through holes TH 3. These lands LND3 are connected to the terminal TE2 via the third wire 2 f. This means that the terminal TE1 and the terminal TE2 are disposed such that the area AR2 is interposed between the terminal TE1 and the terminal TE 2.

< features of the semiconductor device according to the embodiment of the present invention >

The semiconductor device of the embodiment of the invention has the configuration described above. The features of the device will be described in detail below.

On the through-hole substrate 2 of the semiconductor device of the embodiment of the present invention, the area AR1 (first area) shown in fig. 5 and obtained by opening the solder resist 2c formed on the upper surface 2a shown in fig. 3 has a plurality of terminals TE1 in two rows (i.e., inside and outside this area), and it also has the wiring 2g that crosses this area AR1 and extends to the area AR2 and the area AR 3.

This means that the semiconductor device according to the embodiment of the present invention employs the via substrate 2, and it is difficult for the via substrate 2 to increase the wiring density to meet the increase in the number of pins as compared with a build-up substrate. Measures are thus taken to arrange the wirings 2g so as to increase the wiring density, the wirings 2g crossing the area AR1 and extending to the areas AR2 and AR3, where the area AR1 is an opening area of the solder resist 2 c.

The wiring 2g extending across the area AR1 has, as shown in fig. 6, a first portion 2h extending across the area AR1 and a second portion 2i connected to a part of the terminals TE1 among the plurality of terminals TE1 after the area AR2 (or the area AR 3) is exposed. The first portion 2h has a wide portion 2j, and the wide portion 2j is a portion having a width wider than the width of the wiring 2 g.

The wide-width portion 2j is used to disperse and accumulate the solder to be formed on this wiring 2g during solder precoating. It is used to prevent or suppress the formation of a solder pool portion on the wiring 2 g.

Thus, the wiring 2g placed in the area AR1 preferably has a plurality of wide portions 2 j. By using the wiring having the plurality of wide portions 2j, the number of solder dispersions can be increased, and formation of solder reservoir portions can be suppressed.

Further, as shown in a portion P in fig. 14 described later, when the wiring 2g provided in the area AR1 has a plurality of wide-width portions 2j, the wide-width portions 2j are disposed such that a distance L in the extending direction E of the wiring 2g between two adjacent wide-width portions 2j of the first portion 2h (refer to fig. 6) does not exceed a total length (L1 + L2) in the extending direction F of the terminal TE1 and the wiring 2g of the second portion 2i (refer to fig. 6).

In other words, when the distance L in the extending direction E of the wiring 2g between two adjacent wide-width portions 2j of the first portion 2h exceeds the total length (L1 + L2) in the extending direction F of the terminal TE1 of the second portion 2i and the wiring 2g, another wide-width portion 2j is provided between the two adjacent wide-width portions 2 j.

By making the length of the portion of the wiring 2g, which is composed only of the wiring 2g, set to be exposed in the area AR1 as short as possible, the solder 3 (solder layer, refer to fig. 14) to be formed on this wiring 2g by solder pre-coating is dispersed, and at the same time, the solder 3 is accumulated on each wide-width portion 2 j. Since the solder material has a property of flowing and accumulating on the wide-width portions when melted on the wiring, the solder 3 is dispersed on the wide-width portions 2j and, at the same time, accumulates on the respective wide-width portions 2 j.

This can prevent or suppress the solder reservoir portion from being formed on the wiring 2g exposed in the area AR 1.

Also, as shown in fig. 6, in the area AR1 which is an open area, the first part 2h and the second part 2i are electrically connected to each other under the solder resist 2c of the area AR 2.

Specifically, the wiring 2g has the terminal TE1 of the second portion 2i at one end thereof and has a plurality of wide portions 2j in the first portion 2h of the crossing region AR 1. The wiring 2g (the first portion 2h of the wiring 2g has a plurality of wide portions 2j) crossing the area AR1 enters the inside of the substrate and extends to the area AR2, changes its extending direction toward the area AR1 at the area AR2, is exposed again in the area AR1, and becomes a second portion 2 i. The second portion 2i has a terminal TE 1.

The plurality of first portions 2h of the wiring 2g are provided in the vicinity of the ends of the plurality of terminals TE1 arranged in the area AR1 (refer to part B of fig. 5). This is because as the wiring density increases due to an increase in the number of pins of a semiconductor device or the like, the number of terminals TE1 provided in the area AR1 increases so that the position where the wiring 2g is provided may be near the end where the terminals TE1 are arranged, rather than near the center thereof.

In short, it is preferable that the wiring 2g is provided near the end where the terminals TE1 are arranged because the space near the end is larger than the space near the center where the terminals TE1 are arranged. However, as shown in part C in fig. 5, the wiring 2g crossing the region AR1 may be provided near the center where the terminals TE1 are arranged.

Note that the wiring 2g may be any one of a wiring for a signal, a wiring for GND, and a wiring for a power supply.

Fig. 7 shows an example of a wiring pattern when the wiring 2g is for GND. When the wiring 2g is for GND, the wiring 2g is usually connected to the planar wiring 2k in one or both of the area AR3 and the area AR 2. One end of the wiring 2g shown in fig. 7 is connected to the planar wiring 2k in the area AR3, and in turn, protrudes from the planar wiring 2k, is exposed in the area AR1 to become the second portion 2i, and has the terminal TE1 therein, and the other end thereof is connected to another planar wiring 2k in the area AR 2.

The wiring 2g may have a bent portion 2m at the first portion 2h thereof, as shown in fig. 6, the wiring 2g is bent at the bent portion 2m, and is shown later by a portion Q of fig. 14. However, the formation of the solder accumulation portion on the curved portion 2m due to the excessive accumulation of the solder should be avoided.

When the wiring 2g has the bent portion 2m as shown in fig. 6 at the first portion 2h thereof, the plurality of wide-width portions 2j provided on the first portion 2h require some design in terms of their arrangement. First, a plurality of wide portions 2j are provided in the vicinity of the bent portion 2 m. If there is enough space on both sides of the bent portion 2m, the wide portions 2j are preferably provided on both sides of the bent portion 2m so as to sandwich the bent portion 2m, as shown in portions E and F in fig. 6.

When the plurality of bent portions 2m are formed at different angles, in other words, when the number of bent portions 2m is large and the straight line portion of the wiring 2G is short, a part of the wide-width portion 2j in the wide-width portion 2j is disposed to overlap with the bent portion 2m as shown by a portion G in fig. 6.

Thus, there are spaces on both sides of the bent portion 2m, wide-width portions 2j are placed on both sides of the bent portion 2m so as to sandwich the bent portion therebetween, and when the straight portions of the wires 2g on both sides of the bent portion 2m are short and only a narrow space is left, the wide-width portions 2j are disposed so as to overlap the bent portion 2 m.

By providing the wide-width portions 2j on both sides of the bent portion 2m so as to sandwich the bent portion therebetween or by providing the wide-width portions 2j so that the wide-width portions 2j overlap the bent portion 2m, solder that would otherwise accumulate on the bent portion 2m when it is not done can be dispersed, and at the same time, solder material can accumulate on the respective wide-width portions 2j while being prevented from becoming high.

By the solder precoating, solder (solder layer) 3 is formed on each of the terminal TE1 and the wide-width portion 2j as shown later in fig. 15. After the flip chip bonding, as shown later in fig. 19, the stud bump electrode PLBMP1 (2) (bump electrode) is mounted on the terminal TE1 of the second portion 2i (refer to fig. 6) of the wiring 2g, while the stud bump electrode PLBMP1 (2) is not mounted on the wide-width portion 2j of the first portion 2h, and only the solder 3 is formed on the wide-width portion 2 j.

< method for manufacturing semiconductor device according to embodiment of the present invention >

The semiconductor device of the embodiment of the invention has the configuration as described above. An example of a manufacturing method thereof will be described next with reference to some drawings.

Fig. 8 includes a flowchart and a cross-sectional view showing an example of a manufacturing process of a semiconductor device of the embodiment; fig. 9 is a plan view showing an example of a structure of a wiring substrate to be used in the manufacturing shown in fig. 8; fig. 10 is a cross-sectional view showing an example of the structure of a lead before formation of a solder plating layer in the manufacture of the wiring substrate shown in fig. 9; fig. 11 is a cross-sectional view showing an example of the structure of a lead after formation of a solder plating layer in the manufacture of the wiring substrate shown in fig. 9. Fig. 12 is a cross-sectional view showing an example of a state of solder after reflow processing in manufacturing of the wiring substrate shown in fig. 9; fig. 13 is an enlarged plan view showing an example of a state of the solder shown in fig. 12; fig. 14 is a partial plan view showing an example of a state of solder after reflow processing of a wiring substrate to be used in the embodiment; and FIG. 15 is a partial cross-sectional view showing the structure taken along line A-A shown in FIG. 14. FIG. 16 is a top view showing an example of a structure after application of an underfill material in the fabrication shown in FIG. 8; fig. 17 is a plan view showing an example of a structure after flip-chip bonding in the manufacture shown in fig. 8; fig. 18 is a partial top view showing an example of the structure after flip chip bonding shown in fig. 17; and FIG. 19 is a partial cross-sectional view showing the structure taken along the line A-A shown in FIG. 18.

First, preparation of the substrate shown in step S1 of fig. 8 is performed. In this step, the through-hole substrate 2 of the embodiment of the present invention is prepared. For example, as shown in fig. 5, the through-hole substrate 2 has a plurality of terminals TE1 and TE2 and a plurality of through-holes TH1, TH2 and TH3 on its upper surface 2 a.

The substrate further has an area AR1, wherein the area AR1 is an opening area of the solder resist 2c, and the area AR1 has two rows of terminals TE 1. This area AR1 has wiring 2g that spans area AR1 and extends to areas AR2 and AR 3. Similar to the through-hole substrate 2 of the embodiment of the present invention shown in fig. 5 to 7, the wiring 2g has a first portion 2h crossing the area AR1 and a second portion 2i exposed from the area AR2 and then connected to a part of the terminals TE1 among the plurality of terminals TE 1. The first portion 2h has a wide portion 2j, and the width of the wide portion 2j is wider than the width of the wiring 2 g.

As shown later in a part P of fig. 14, the wiring 2g has a plurality of wide-width portions 2j on the first portion 2h thereof such that a distance L in the extending direction E of the wiring 2g between two adjacent wide-width portions 2j (refer to fig. 6) in the first portion 2h does not exceed a total length (L1 + L2) of the terminal TE1 and the wiring 2g in the extending direction F in the second portion 2i (refer to fig. 6).

Subsequently, the terminals TE1 and TE2 of such a through-hole substrate 2 are subjected to solder precoating to form solders (solder layers) 3 on the terminals TE1 and TE2, respectively, as shown in fig. 9.

In the above-described solder precoating, the solder 3 is formed on the terminal TE1 (TE 2) exposed from the solder resist film 2c of the through-hole substrate 2 as shown in fig. 10 (for example, formed on the terminal TE1 (TE 2) by electrolytic zinc (tin) plating treatment or the like), followed by solder precoating. For example, the terminal TE1 (TE 2) is a copper wiring. In the solder precoating, as shown in fig. 11, an electrolytic zinc plating process or the like is performed to cover the terminal TE1 with the solder 3 (TE 2). Subsequently, as shown in fig. 12, a reflow process is performed to precoat the terminal TE1 with solder 3 (TE 2).

The solder precoating process shown in fig. 10 to 12 is similarly performed on each wide width portion 2 j. This means that, when the solder precoating process is performed, as shown in fig. 14, the plurality of terminals TE1 and the respective wide-width portions 2j are precoated with the solder 3 in the areas AR1, respectively.

In the through-hole substrate 2 of the embodiment of the invention, the wiring 2g exposed in the area AR1 and crossing the area AR1 at this time has a plurality of wide-width portions 2j (for example, the portion P or the portion Q in fig. 14) so that the solder in a fluid state during solder precoating can be dispersed to the respective wide-width portions 2j and the solder can be accumulated on the respective wide-width portions 2 j.

It is preferable that the shapes (length, width, etc. in a plan view) of the wide-width portion 2j and the terminal TE1 in a plan view be substantially equal to each other. As shown in fig. 15, this can form the solder 3 formed by the pre-coating on the wide-width portion 2j and the solder 3 formed by the pre-coating on the terminal TE1 at substantially the same height.

Next, the respective widths of the terminal TE1 and the wiring 2g in the area AR1, in which the area AR1 is an opening area of the solder resist 2c, will be described. As shown in fig. 13, assuming that the width of the wiring 2g exposed from the solder resist film 2c (which is an insulating film) in the area AR1 is W1 and the width of the terminal TE1 is W2, W1 and W2 satisfy the following ranges: w1< W2, and W2= (1.5-3.0) × W1, where W2 is the width of the terminal TE 1. Such definitions W1 and W2 apply equally to the terminal TE 2.

The width and size of the wide-width portion 2j in plan view are preferably equal to those of the terminal TE 1. By making the width and the size of the wide-width portion 2j equal to those of the terminal TE1, the thickness or the size of the solder 3 formed on the terminal TE1 by precoating and the solder 3 formed on the wide-width portion 2j can be substantially equal to each other.

In short, as shown in fig. 15, the solder 3 on the wide-width portion 2j and the solder 3 on the terminal TE1 are made to have the same height.

Next, preparation of the chip shown in step S2 in fig. 8 is performed. As shown in fig. 1 and 2, the semiconductor chip 1 has a plurality of stud bump electrodes PLBMP1 and PLBMP2 on a plurality of electrode pads (surface electrodes) 1c on its main surface 1 a.

These columnar bump electrodes PLBMP1 and PLBMP2 have been already disposed on a semiconductor wafer at a wafer stage before dicing, not shown, and the columnar bump electrodes PLBMP1 and PLBMP2 have solder 4 on top thereof.

Next, the previous resin coating in step S3 shown in fig. 8 is performed. In this step, as shown in fig. 16, underfill UF is applied to the chip mounting region (more specifically, region AR1+ region AR2+ region AR4 shown in fig. 5) of the upper surface 2a of the via substrate 2. Underfill UF is, for example, an epoxy-based resin. Preferably, a fast-curing resin NCP (Non-conductive paste) is used.

Next, flip chip bonding shown in step S4 is performed. As shown in fig. 8, the semiconductor chip 1 is mounted on the upper surface 2a of the through-hole substrate 2 by flip-chip bonding. Specifically, the semiconductor chip 1 is mounted on the through-hole substrate 2 such that the stud bump electrodes PLBMP1 and PLBMP2 formed on the semiconductor chip 1 are in direct contact with the terminals TE1 and TE2 formed on the through-hole substrate 2 shown in fig. 5, followed by heating at a high temperature.

Accordingly, the solder 4 on the stud bump electrodes PLBMP1 and PLBMP2 and the solder 3 on the terminals TE1 and TE2 on the through-hole substrate 2 are melted, and thus the terminals TE1 and TE2 of the through-hole substrate 2 and the copper of the stud bump electrodes PLBMP1 and PLBMP2 are electrically connected to each other via the solder 3(4) serving as a connection member.

In this way, flip chip bonding is performed as shown in fig. 17.

During flip chip bonding, wet underfill UF spreads in the space between the semiconductor chip 1 and the via substrate 2, and the underfill fills the space. When a fast curing resin (non-conductive paste NCP) is used as the underfill UF, the underfill UF is rapidly cured.

In the embodiment of the present invention, even if made small, the pillar bump electrodes PLBMP1 and PLBMP2 capable of ensuring a high height are used for the connection between the semiconductor chip 1 and the via substrate 2 so as not to disturb the diffusion of the wet underfill UF.

After the flip-chip bonding is completed, as shown in fig. 19, each terminal TE1 has a bump electrode (pillar bump electrode PLBMP 1) thereon, but the wide-width portion 2j does not have a bump electrode thereon.

Next, ball mounting shown in step S5 in fig. 8 is performed. In this step, a plurality of solder balls SB are mounted on the back surface (surface on the opposite side of the chip mounting surface) 2b of the through-hole substrate 2. In this manner, the semiconductor device according to the embodiment of the present invention can be manufactured.

According to the embodiment of the present invention, the bump electrodes are mounted on one side (terminal TE 1) of the wiring 2g which crosses the opening area (area AR 1) of the solder resist film 2c of the through-hole substrate 2, and the wide-width portion 2j having no bump electrode thereon is formed on the other side of the wiring, so that the solder 3 can be disposed on the wiring 2g while spreading the solder 3 to the wide-width portion 2j by the reflow process during solder precoating on each terminal TE1, as shown in fig. 14.

In other words, in the wiring 2g exposed in the area AR1, by making the length of the portion constituted only by the wiring 2g as short as possible, the solder 3 formed on the wiring 2g during solder precoating can be dispersed, and at the same time, the solder 3 can be accumulated on the wide-width portion 2 j. The solder 3 is dispersed and accumulated on the wide-width portion 2j of the wiring 2g by utilizing the property that the solder material flows and accumulates on the wide-width portion when melted on the wiring.

This can reduce the difference in height between the solder 3 on each terminal TE1 and the solder 3 on the wide-width portion 2j, as shown in fig. 15.

In other words, it is possible to suppress the formation of a portion (solder accumulation portion) whose height of the solder 11 is high due to the local accumulation of the solder on the wiring 10d1 as shown in fig. 25. This means that in the embodiment of the present invention, as shown in fig. 18 and 19, the solder height on each terminal TE1 and the solder height on the wide-width portion 2j can be made equal to each other.

By making their heights equal to each other, the following problems can be prevented or suppressed from occurring during flip-chip bonding. The problems are as follows: as shown in part R and part S of fig. 25, the semiconductor chip 1 is lifted by the accumulated solder 11 due to contact (interference) between the solder 11 accumulated on the wiring 10d1 and the surface of the semiconductor chip 1, and the bump electrodes 12 of the semiconductor chip 1 cannot reach the solder 11 on the terminals 10 e. Therefore, connection failures of the bump electrodes (in the present embodiment, the columnar bump electrodes PLBMP1 and PLBMP 2) during flip-chip bonding can be reduced.

The embodiment of the invention can also prevent or suppress oblique mounting of the semiconductor chip 1 which would otherwise occur due to contact (interference) between the solder 11 accumulated on the wiring 10d1 and the surface of the semiconductor chip 1 as shown in fig. 25 during flip-chip bonding.

Further, after the flip-chip bonding, when the space between the substrate and the chip is filled with the underfill UF previously coated on the substrate, voids may occur due to the solder 11 accumulated on the wiring 10d1 as shown in fig. 25. In the embodiment of the present invention, on the other hand, the solder 3 has no locally high portion, so that the formation of voids in the underfill UF can be suppressed.

Accordingly, the embodiments of the present invention can improve connection reliability in flip chip bonding of a semiconductor device.

< first modification >

In the above embodiment, each terminal TE1 of the through-hole substrate 2 is precoated when the through-hole substrate 2 is prepared. Alternatively, the semiconductor device may be manufactured using a substrate having the terminal TE1 precoated with solder 3, which has been delivered as the through-hole substrate 2.

In this case, the pre-coating step of the solder 3 can be omitted, so that a semiconductor device can be obtained with improved manufacturing efficiency.

< second modification >

Fig. 20 is a cross-sectional view showing the structure of a wiring substrate to be used in the manufacture of a semiconductor device of a second modification of the embodiment; fig. 21 is a cross-sectional view showing a structure after flip-chip bonding in the manufacture of a semiconductor device of a second modification; fig. 22 is a cross-sectional view showing a structure after application of an underfill in the manufacture of a semiconductor device of the second modification; and fig. 23 is a cross-sectional view showing a structure after ball mounting in manufacturing of a semiconductor device of the second modification.

In the manufacturing method described in the above embodiment, the underfill UF is applied to the via substrate 2 before the flip-chip bonding, and after the application of the underfill UF, the flip-chip bonding is performed. Alternatively, the following semiconductor device manufacturing method may be employed: flip chip bonding is performed, followed by filling underfill UF between the semiconductor chip 1 and the via substrate 2.

Next, manufacturing steps in this case will be described with reference to fig. 20 to 23. First, as shown in fig. 20, a through-hole substrate 2 according to the embodiment of the present invention is prepared. For example, as shown in fig. 5, the through-hole substrate 2 has a plurality of terminals TE1 and TE2, a plurality of through-holes TH1, TH2, and TH3, and the like.

The through-hole substrate also has an area AR1, an area AR1 is an open area on the solder resist 2c and the terminals TE1 are arranged in two rows in the area AR 1. In the area AR1, there is a wiring 2g that spans the area AR1 and extends to the areas AR2 and AR 3. The wiring 2g has a plurality of wide portions 2j (the wide portions 2j have a width wider than the width of the wiring 2 g) in the first portion 2h of the spanning area AR1 thereof, similarly to the wiring 2g of the through-hole substrate 2 in the embodiment shown in fig. 5 to 7 described above. It is to be noted that the wide-width portions 2j are arranged such that, as shown in the portion P of fig. 14, a distance L in the extending direction E of the wiring 2g between two adjacent wide-width portions 2j (refer to fig. 6) in the first portion 2h does not exceed a total length (L1 + L2) in the extending direction F of the terminal TE1 and the wiring 2g (refer to fig. 6) in the second portion 2 i.

Next, as shown in fig. 21, the semiconductor chip 1 is mounted on the through-hole substrate 2. The semiconductor chip 1 mounted in this way has, for example, pillar bump electrodes PLBMP1 and pillar bump electrodes PLBMP2 on its main surface 1 a. Then, the semiconductor chip 1 is mounted on the through-hole substrate 2 so that the bump electrodes PLBMP1 and PLBMP2 formed on the semiconductor chip 1 are brought into direct contact with the terminals TE1 (refer to fig. 5) formed on the through-hole substrate 2. By heating at a high temperature, the solder 4 of the stud bump electrodes PLBMP1 and PLBMP2 and the solder 3 on the terminal TE1 of the via substrate 2 are melted to electrically connect the terminals TE1 and TE2 of the via substrate 2 with the copper of the stud bump electrodes PLBMP1 and PLBMP 2.

Next, as shown in fig. 22, the space between the semiconductor chip 1 and the via substrate 2 is filled with underfill UF. In the present embodiment, since the pillar bump electrodes PLBMP1 and PLBMP2 capable of ensuring the heights even if the sizes thereof are reduced are used for the connection between the semiconductor chip 1 and the via substrate 2, the filling performance of the underfill UF can be ensured.

Next, as shown in fig. 23, the solder ball SB is mounted on the back surface 2b of the through-hole substrate 2. Even if the manufacturing method of the second modification of the embodiment of the present invention is adopted, a semiconductor device having the same level as that of the semiconductor device of the above-described embodiment can be manufactured. Also, advantages similar to those of the above-described embodiment can be obtained.

The present invention made by the inventors is specifically explained based on the embodiments. It is needless to say that the present invention is not limited to or by the above embodiments, but may be changed in various ways without departing from the gist of the present invention.

For example, in the above-described embodiment, a BGA package structure having solder balls SB on the back surface 2b of the through-hole substrate 2 is described as an example of a semiconductor device. The package may be an LGA (land grid array) package without solder balls SB mounted thereon. When the LGA is adopted, the solder ball SB is not mounted, so that the material cost corresponding to the solder ball SB can be saved.

In the above-described embodiment, the through-hole substrate 2 is described as an example of a wiring substrate, but a build-up substrate may be employed as the wiring substrate. The use of the build-up substrate increases the wiring density to realize fine pitch wiring.

In the above-described embodiments, the stud bump electrodes PLBMP1 and PLBMP2 are described as one example of bump electrodes for electrically connecting the semiconductor chip and the wiring substrate. Alternatively, a gold bump or the like may be used as the bump electrode. Further, solder is employed as a member for connecting the bump electrode and the terminal of the wiring substrate, but the connecting member is not limited to solder.

Claims (23)

1. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a wiring substrate having a first surface and a second surface on an opposite side of the first surface, the first surface having a plurality of terminals thereon, the wiring substrate having an insulating film on the first surface, and having a first region obtained by opening the insulating film, a second region located inside the first region in a plan view, and a third region located outside the first region in a plan view on the first surface;

(b) preparing a semiconductor chip having a first main surface and a second main surface on an opposite side of the first main surface, the first main surface having a plurality of electrode pads thereon, and the semiconductor chip having bump electrodes on the electrode pads; and

(c) electrically connecting bump electrodes of the semiconductor chip with terminals of the wiring substrate by connection members to perform flip-chip bonding of the semiconductor chip to the first surface of the wiring substrate,

wherein the wiring substrate has a terminal and a wiring crossing the first region and extending to the second region and the third region in the first region thereof,

wherein the wiring has a first portion crossing the first region and a second portion exposed from the second region or the third region to be connected to a part of the terminals, and

wherein the terminal of the second portion has a bump electrode thereon and the first portion has a wide-width portion wider than a width of the wiring.

2. The method for manufacturing a semiconductor device according to claim 1,

wherein the wiring has a plurality of wide-width portions in the first portion thereof, and the plurality of wide-width portions are disposed such that a distance between any two wide-width portions adjacent to each other in the extending direction of the wiring in the first portion does not exceed a total length of the terminal and the wiring in the second portion in the extending direction.

3. The method for manufacturing a semiconductor device according to claim 1,

wherein the wire has a plurality of wide-width portions and bent portions at a first portion thereof, wherein the wire is bent at the bent portions, and the plurality of wide-width portions are provided so as to sandwich the bent portions between the wide-width portions.

4. The method for manufacturing a semiconductor device according to claim 1,

wherein the wire has a plurality of wide-width portions and a bent portion at a first portion thereof, wherein the wire is bent at the bent portion, and a part of the wide-width portions of the plurality of wide-width portions is disposed to overlap the bent portion.

5. The method for manufacturing a semiconductor device according to claim 1,

wherein bump electrodes are not provided on the wide-width portions in the first portion of the wiring.

6. The method for manufacturing a semiconductor device according to claim 1,

wherein the second region and the third region have a plurality of through holes therein, each of the through holes penetrating the wiring substrate from the first surface to the second surface.

7. The method for manufacturing a semiconductor device according to claim 1,

wherein a first portion and a second portion of the wiring are electrically connected to each other under the insulating film in the second region or the third region.

8. The method for manufacturing a semiconductor device according to claim 1,

wherein each of the wide portions has a solder layer thereon.

9. The method for manufacturing a semiconductor device according to claim 1,

wherein the connecting part is solder.

10. A semiconductor device, comprising:

a semiconductor chip having a first main surface and a second main surface on an opposite side of the first main surface, the first main surface having a plurality of electrode pads thereon, and the semiconductor chip having bump electrodes on the electrode pads;

a wiring substrate having a first surface and a second surface on the opposite side of the first surface, the first surface having a plurality of terminals corresponding to the bump electrodes thereon and having the semiconductor chip mounted thereon, wherein the bump electrodes and the terminals are electrically connected to each other through connection members, respectively; and

a molding resin filled between the semiconductor chip and the wiring substrate;

wherein the wiring substrate has an insulating film on the first surface thereof,

wherein the wiring substrate has, on the first surface thereof, a first region obtained by opening the insulating film, a second region located inside the first region in a plan view, and a third region located outside the first region in a plan view,

wherein the first region has therein a terminal and a wiring that crosses the first region and extends to the second region and the third region,

wherein the wiring has a first portion crossing the first region and a second portion exposed from the second region or the third region to be connected to a part of the terminals, and

wherein the second portion has a bump electrode on a terminal thereof, and the first portion has a wide portion wider than a width of the wiring.

11. The semiconductor device as set forth in claim 10,

wherein the wiring has a plurality of wide-width portions in the first portion thereof, and the wide-width portions are arranged such that a distance between any two of the wide-width portions adjacent to each other in the extending direction of the wiring in the first portion does not exceed a total length of the terminal and the wiring in the second portion in the extending direction.

12. The semiconductor device as set forth in claim 10,

wherein the wire has a plurality of wide-width portions and bent portions at a first portion thereof, wherein the wire is bent at the bent portions, and the plurality of wide-width portions are provided so as to sandwich the bent portions between the wide-width portions.

13. The semiconductor device as set forth in claim 10,

wherein the wiring has a plurality of wide-width portions and a bent portion at a first portion thereof, wherein the wiring is bent at the bent portion, and a part of the wide-width portions among the plurality of wide-width portions is disposed to overlap the bent portion.

14. The semiconductor device as set forth in claim 10,

wherein the second region and the third region have a plurality of through holes therein, each of the through holes penetrating the wiring substrate from the first surface to the second surface.

15. The semiconductor device as set forth in claim 10,

wherein each of the wide portions has a solder layer thereon.

16. The semiconductor device as set forth in claim 10,

wherein the connecting part is solder.

17. A semiconductor device, the semiconductor device comprising:

a semiconductor chip having a first surface and a second surface opposite the first surface, wherein a plurality of electrode pads are disposed over the first surface; and

a wiring board having a first main surface over which a plurality of wirings and an insulating film are formed,

wherein the semiconductor chip is mounted over the first main surface of the wiring board so that the first surface of the semiconductor chip faces the first main surface,

wherein an opening is formed in the insulating film so that a plurality of portions of the first wiring are exposed from the opening,

wherein each of a plurality of portions of the first wiring exposed from the opening is coated with solder, wherein the first wiring has a first portion, a second portion that is an end portion of the first wiring, and a third portion that is located between the first portion and the second portion,

wherein, in a plan view, the first portion and the second portion are exposed from the opening, and the third portion is covered with the insulating film,

wherein a wide-width portion is formed in each of the first portion and the second portion in a plan view, a width of the wide-width portion in a direction perpendicular to an extending direction of each of the plurality of wirings is wider than a width of each of the other portions,

wherein a wide portion of the second portion of the first wiring is electrically connected to the first electrode pad of the semiconductor chip through the first bump electrode and the solder coated on the second portion, and

wherein the wide portion of the first wire is not electrically connected to any of the plurality of electrode pads of the semiconductor chip.

18. The semiconductor device as set forth in claim 17,

wherein the wiring board has a first area, a second area located inside the first area, and a third area located outside the first area in plan view,

wherein the opening is formed in the first region, an

Wherein a third portion of the first wiring is provided in the second region and covered with the insulating film of the second region.

19. The semiconductor device as set forth in claim 18,

wherein the first wiring has a fourth portion,

wherein the first portion is located between the third portion and the fourth portion,

wherein the fourth portion is provided in the third region and covered with the insulating film of the third region.

20. The semiconductor device as set forth in claim 17,

the first wiring is any of a wiring for a signal, a wiring for GND, and a wiring for a power supply.

21. The semiconductor device as set forth in claim 17,

wherein the opening is formed in the insulating film so as to surround the semiconductor chip in a plan view.

22. The semiconductor device as set forth in claim 17,

wherein the first bump electrode is a Cu pillar bump electrode.

23. The semiconductor device according to claim 17, further comprising:

a sealing resin provided between the first surface of the semiconductor chip and the first main surface of the wiring board,

wherein a part of the sealing resin is provided between the wide part of the second portion of the first wiring and a part of the first surface of the semiconductor chip directly above the wide part.