HK1200589A1 - Flash memory system - Google Patents

Abstract

A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

Description

Flash memory system

Cross Reference to Related Applications

This application claims priority to U.S. provisional patent application No. 61/538,540 filed on 23/9/2011 and U.S. patent application No. 13/455,780 filed on 25/4/2012, the contents of both of which are incorporated herein by reference in their entirety.

Technical Field

The present embodiments generally relate to non-volatile memories.

Background

Flash memory is a common type of non-volatile memory that is widely used as mass storage for consumer electronics devices such as digital cameras and portable digital music players). The density of currently available flash memory chips can be as high as several Gigabytes (GB) in size, which is suitable for use in popular USB flash drives because of the small size of one flash memory chip. Another emerging application for flash memory is solid state drives, which are used to replace traditional hard disk drives used in laptop and desktop computers. These applications typically use multi-level cell (MLC) flash memory devices with limited lifetimes. Other types of flash memory, single-level cell (SLC) flash memory devices, are also used in applications for reliable data storage. A disadvantage of SLC flash devices is cost compared to MLC flash devices.

Disclosure of Invention

In a first aspect, a method is provided for programming a multi-bit per cell (MBC) flash memory device configured to store up to N pages of data per physical row, N being an integer greater than 1. The method includes issuing a set of program commands for programming a plurality of pages of data to a subsection of the flash memory device having at least one physical row. The set of programming commands is restricted to addressing a subset of logical page addresses selected from all possible logical page addresses corresponding to each of the at least one physical row. The method also includes programming less than N pages to each of at least one physical row of the flash memory device in response to the subset of logical page addresses in the program command. According to this embodiment, the method further includes accessing a mapping table containing storage mode information for each subsection of the flash memory device prior to issuing the set of programming commands, wherein accessing the mapping table includes selecting the subsection with a partial MBC storage mode in which less than N data pages are stored per physical row.

The method may also include selecting a subset of logical page addresses corresponding to the partial MBC storage mode, and all possible logical page addresses corresponding to each of the at least one physical row include consecutive page addresses beginning with a lower page address and ending with an upper page address. The subset of logical page addresses may include lower page addresses up to an intermediate page address between an upper page address and a lower page address of each of the at least one physical row. Alternatively, the subset of logical page addresses may include only the lower page addresses of each of the at least one physical row.

In another implementation of the first aspect, issuing the set of programming commands includes: repeatedly providing program command packets, each program command packet containing one of the plurality of data pages and one of a subset of logical page addresses; and providing M program command packets for programming M pages of a plurality of data pages to one physical row of the flash memory device, wherein M is an integer value less than N. Optionally, issuing a set of program commands includes repeatedly providing a program command packet for programming one of the plurality of pages of data to one physical row of the flash memory device.

In another embodiment of the first aspect, the method further comprises receiving a host request to program a plurality of pages of data in the partial MBC storage mode prior to issuing the set of programming commands. In yet another embodiment, the method further includes receiving a host request to program a plurality of pages of data in a full MBC storage mode before issuing the set of programming commands, determining that a maximum number of MBC program/erase cycles of a subsection has been reached, and selecting another subsection configured to program the plurality of pages of data in the full MBC storage mode and setting the subsection to a partial MBC storage mode. In this current embodiment, the full MBC storage mode includes a two-bit-per-cell storage mode, while the partial MBC storage mode includes a one-bit-per-cell storage mode.

In a second aspect, a system is provided that includes a memory controller. The memory controller is configured to issue a program command that is restricted to addressing a subset of logical page addresses selected from all possible logical page addresses corresponding to each physical row of the memory device. The memory device includes a multi-bit per cell (MBC) memory device configured to store a maximum of N pages of data per physical row, where N is an integer greater than 1. The memory device is also configured to program less than N pages per physical row in response to a subset of logical page addresses in a program command received from the memory controller. In this embodiment, the memory controller includes a mapping table for storing metadata corresponding to the subdivisions of the memory device, where the mapping table is configured to include storage mode information for each subdivision and address binding information associated with the storage mode for each subdivision.

In this embodiment, the memory controller includes control circuitry for accessing the mapping table and providing the program command in response to metadata of the mapping table. Each program command includes a page of data, address information for selecting a subsection of the memory device and a physical row within the subsection, and a logical page address of the page of data to be programmed in the physical row. In this embodiment, the memory device is configured to store at most N2 pages per physical row, and each of the two pages of each physical row is addressable by an upper page address having a first least significant bit and a lower page address having a second least significant bit different from the first least significant bit. According to further embodiments of the present aspect, the subdivisions of the memory device include a memory block, a sub-block of a memory block, or a physical row of a memory block.

In a third aspect, a method is provided for programming a multi-bit per cell (MBC) flash memory device configured to store up to N bits per cell, where N is an integer greater than 1. The method includes receiving a host request to program a page of data; determining that the data page is to be programmed in a partial MBC storage mode in which fewer than N virtually addressable data pages are stored in each physical row of the flash memory device; accessing a mapping table containing metadata for flash memory devices to select subsections of the MBC flash memory devices configured in a partial MBC storage mode; and issuing at least one program command for programming a page of data to the subsection using a virtual page address limited to a subset of less than N possible virtual page addresses for programming a page to each physical row. In this aspect, N-2, and the possible virtual page addresses include a lower page address and an upper page address, and issuing at least one program command includes repeatedly issuing program commands, each program command including a page of data and a lower page address. Optionally, N >2, and the possible virtual page addresses include a lower page address, an upper page address, and at least one intermediate page address between the lower page address and the upper page address, and issuing at least one program command includes repeatedly issuing program commands, each program command including a page of data, and one of the lower page address and the at least one intermediate page address.

Other aspects and features of particular embodiments of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of such embodiments in conjunction with the accompanying figures.

Drawings

Embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a flash memory device to which the present invention is applicable;

FIG. 2 is a schematic diagram illustrating the organization of one bank of the flash memory device of FIG. 1;

FIG. 3 is a circuit schematic showing a per cell unit (SBC) mapping of a data page to a row of flash memory cells;

figure 4 is a diagram of threshold voltage distributions for SBC data storage;

FIG. 5 is a circuit schematic showing a multi-bit per cell (SBC) mapping of two pages of data to a row of flash memory cells;

FIG. 6 is a diagram of threshold voltage distributions for a two-bit MBC data storage;

FIG. 7 is a circuit schematic showing MBC mapping of three pages of data to a row of flash memory cells;

FIG. 8 is a graph of threshold voltage distributions for a three-bit MBC data storage;

FIG. 9 is a block diagram of a flash memory system according to an embodiment of the present invention;

FIG. 10 is a block diagram of a flash memory system according to another embodiment of the present invention;

FIG. 11 is a table illustrating an exemplary mapping of virtual page addresses to physical rows;

12A and 12B are diagrams of threshold voltage distributions for a two-bit MBC programming sequence;

13A, 13B, and 13C are graphs of threshold voltage distributions for a three-bit MBC programming sequence;

FIG. 14 is a diagram illustrating an example of an SBC programming operation of a two-bit MBC memory device according to an embodiment of the present invention;

FIG. 15 is a diagram illustrating an example of a two-bit MBC programming operation of a three-bit MBC memory device according to an embodiment of the invention;

FIG. 16 is a diagram illustrating an example of an N-bit MBC flash memory controller in which an exemplary mapping table is stored, according to an embodiment of the invention;

FIG. 17 is a flow chart of a method of operating a memory controller to issue a program command to an MBC memory device according to an embodiment of the invention;

FIG. 18 is a flow diagram of a method for operating an MBC memory device in response to a program command received from a memory controller, according to an embodiment of the invention; and

FIG. 19 is a flowchart illustrating a method of detailed exemplary operation of a memory system according to an embodiment of the present invention.

Detailed Description

FIG. 1 depicts a typical flash memory device to which embodiments of the present invention may be applied. Referring to fig. 1, a flash memory device 10 includes an input/output interface circuit, a control circuit, a memory circuit, and a memory array. The input/output interface circuit of the flash memory device 10 includes a ready/busy signal buffer 12, a control signal buffer 14, and a global data buffer 16. In a particular example, the ready/busy signal buffer 12 is an output buffer that drives the ready/busy signal R/B # via a respective pin or port. Control signal buffer 14 is an input buffer that receives flash control signals CE #, CLE, ALE, WE #, RE #, and WP # from respective pins or ports. In the following, a signal name ending with "#" should be understood as an active low signal, wherein an active low signal corresponds to a "0" logic level or, for example, a VSS voltage level. In contrast, an active high logic level signal corresponds to a "1" logic level or a voltage level of, for example, VDD or VCC. The following is a brief description of the aforementioned control signals.

● Command Latch Enable (CLE): the CLE input signal is used to control loading of the operating mode command into the internal command register. When CLE is high, a command is latched into the command register from the I/O port on the rising edge of the WE # signal.

● Address Latch Enable (ALE): the ALE signal is used to control loading of address information into the internal address register. When ALE is high, address information is latched into the address register from the I/O port on the rising edge of the WE # signal.

● chip enable (CE #): the device transitions into a low power standby mode when CE # goes high during the device is in a ready state. When the device is in a busy state (R/B # ═ L), such as during a program or erase or read operation, the CE # signal is ignored and does not enter standby mode even if the CE # input goes high.

● write enable (WE #): the WE # signal is used to control the retrieval of data from the I/O port.

● read enable (RE #): the RE signal controls the serial data output. Data is available after the falling edge of RE #. The internal column address counter is also incremented on this falling edge (address + 1).

● I/O Port (I/O0 to 7): the I/O0 to 7 pins serve as ports for transferring addresses, commands, and input/output data to and from the devices.

● write protection (WP #): the WP # signal is used to protect the device from accidental programming or erasure. When WP # is low, the internal voltage regulator (high voltage generator) is reset. This signal is typically used to protect data during power on/power off sequences when the input signal is inactive.

● ready/busy (R/B #): R/B # is an open drain pin, and the output signal is used to indicate the operating condition of the device. The R/B # signal is in a busy state (R/B # ═ L) during program, erase, and read operations, and will return to a ready state (R/B # ═ H) after the operations are completed.

The global data buffer 16 is a bidirectional buffer that receives write data on corresponding input/output (I/O) pins or ports and provides read data. Flash device 10 is shown with eight such ports I/O0 through I/O7, but may have more or fewer than eight in alternative data width configurations. These I/O ports are also used to receive address and command information.

The control circuitry of flash memory device 10 includes a controller 18, a command register 20, an address register 22, and a status register 24. The controller 18 controls various functions of other circuitry in the flash memory device 10, including, for example, reading, programming, and program verification. Although not shown, the controller 18 may include a command decoder for performing functions in response to received commands. The registers 22, 24 store various types of information received by the flash memory device 10 or to be provided to an external host system (not shown), including, for example, a memory controller (not shown). The registers described are not intended to represent all registers, and may include other registers, such as data registers.

The circuitry primarily controlled by the controller 18 is memory circuitry including row and column pre-decoders 26 and 28, row and column decoders 30 and 32, sense amplifier and page buffer block 34, and high voltage generator 36. The memory cell array 38 of the flash memory device 10 includes a NAND (NAND) cell string connected to a bit line, where each memory cell of the NAND cell string is connected to a word line. More details of the NAND cell string are shown later in figure 3. Row predecoder 26, row decoder 30, and high voltage generator 36 are controlled in a programming operation to drive a selected word line to a high voltage that is effective to change the threshold voltage of the connected memory cell from the default erase threshold voltage to a desired voltage level. Note that high voltages can be used in the storage array 38 to erase memory cells by changing their threshold voltages to a default value. Different combinations of high voltage and high voltage application times may be used to set a particular threshold voltage of a flash memory cell. The combination used to program a particular threshold voltage may be referred to as a programming profile. The page buffer 34 stores a page of data to be programmed to cells connected to a selected word line. Typically, memory cells connected to a bit line are either inhibited from programming or enabled for programming via a selected word line, depending on the logic level to which the bit line is biased or set. The data bits stored in the page buffer are used to bias the bit lines. The memory cell array 38 has any number of banks (banks) that are selected design parameters for a particular flash memory device.

Fig. 2 shows the organization of one bank 40 of the memory cell array 38 of fig. 1. The banks 40 are organized into k blocks, and each block has i pages. k and i are both integer values. Each page corresponds to a row of memory cells coupled to a common word line. The following is a detailed description of the memory cells of the block.

Each block includes NAND memory cell strings having up to i flash memory cells 42 arranged in series and electrically coupled to each other. Thus, word lines WL1 through WLi are coupled to the gates of each flash memory cell in the string of memory cells. A string select device 44 coupled to signal SSL (string select line) selectively connects the memory cell string to a bitline 46, while a ground select device 48 coupled to signal GSL (ground select line) selectively connects the memory cell string to a source line, such as VSS. The string select device 44 and the ground select device 48 are N-channel transistors.

There are j bit lines 46 common to all blocks of the bank 40, and each bit line 46 is coupled to one NAND memory cell string of each of the blocks [1] to [ k ]. The variable j is an integer value. Each word line (WL 1-WLi), SSL and GSL signal is coupled to the same respective transistor device in each NAND memory cell string in the block. As will be understood by those skilled in the art, data stored in flash memory cells along one word line is referred to as a data page.

Coupled to each bit line outside of the memory bank 40 is a page buffer 50 for storing a page of write data to be programmed into a page of flash memory cells. The page buffer 50 corresponds to the sense amplifier and page buffer block 34 shown in fig. 1. Accordingly, the page buffer 50 further includes a sensing circuit for sensing data read out from one page of the flash memory cells. During a program operation, the page buffer performs a program verify operation to ensure that data is properly programmed into the flash memory cells coupled to the selected word line. Programming within a block generally begins at the page corresponding to WL1 and continues continuously to WLi to fill the current block. Alternatively, programming may begin at WLi and continue continuously to WL 1. Programming then continues with WL1 of the new block.

Flash memory 10 may be configured to store data in one of two different ways. Data can be stored in a single-bit-per-cell (SBC) storage mode or a multiple-bit-per-cell (MBC) storage mode. In the SBC storage mode, exactly one bit of information is stored in one cell to represent one of two possible states. In the MBC storage mode, at least two bits are stored in a cell to represent one of four possible states.

FIG. 3 shows the same two NAND cell strings of FIG. 2, with additional comments to help illustrate that the data page is stored in an SLC configuration flash memory device. Each memory cell connected to the same physical word line (i.e., WL1, for example) stores one bit of data of a page of data. Thus, as shown in FIG. 3, the cells connected to physical word line WL1 store the "first page", while the cells connected to the last physical word line WLi store the "ith page".

Figure 4 shows threshold voltage (Vt) distributions for erased memory cells and programmed memory cells in the SBC storage mode. Due to process and voltage supply variations, erased and programmed threshold voltages are distributed within a voltage range. As shown in FIG. 3, erased memory cells have a negative threshold voltage between-3V to-1V, while programmed memory cells have a positive threshold voltage between 1V to 3V. The range depends on the desired threshold voltage of the memory cell. The threshold voltage ranges illustrate possible threshold voltages that may be used in a particular flash memory device, however, those skilled in the art will appreciate that the selection of threshold voltages for erased and programmed memory cells depends on the design and manufacturing process of the flash memory device. Those skilled in the art will appreciate that different flash memory devices have different threshold voltage ranges to suit a particular design or application.

Fig. 5 shows the same circuit as that of fig. 3, except that two bits of data are stored in each memory cell of the flash memory device in a two-bit-per-cell MLC configuration. Thus, each physical word line stores two pages of data. As shown in fig. 5, the physical row addressed by WL1 stores logical first and second pages. The last word line WLi stores page 2i and page 2i-1, where "i" is an integer value.

FIG. 6 illustrates a threshold voltage distribution graph of possible states that may be stored in each memory cell and the corresponding two bit combinations that each state represents.

Fig. 7 shows the same circuit as that of fig. 3, except that three bits of data are stored in each memory cell of the flash memory device in a three-bit-per-cell MLC configuration. Thus, each physical word line stores three pages of data. As shown in fig. 7, the physical row addressed by WL1 stores logical first, second, and third pages. The last word line WLi stores page 3i, page 3i-1 and page 3i-2, where "i" is an integer value. It should be noted that pages 3i, 3i-1 and 3i-2 are general mathematical expressions for representing page numbers of upper, middle and lower pages of each word line, respectively.

FIG. 8 illustrates a threshold voltage distribution diagram of possible states that may be stored in each memory cell, where each state represents a possible three-bit combination.

An advantage of storing data in the MBC storage mode (two or more bits per cell) is at least twice the storage capacity relative to the SBC storage mode when the same number of cells is used. Generally, flash memory manufacturers apply mask options during the manufacturing process to configure flash memory device 10 to perform either SBC-specific algorithms or MBC-specific algorithms, because the flash memory circuitry is controlled differently between SBC and MBC read and program operations.

It is known that flash memory devices have a limited number of erase-program cycles before they are no longer available to reliably store data. For example, the typical nominal erase-program cycle of current SBC flash memories is about 100000 cycles. However, current MBC flash memories have a smaller rating limit of 10000 cycles due to the fact that the cells are subjected to higher stress. The erase-program cycle limits mentioned above are examples only, but it is fully understood that MBC flash memory devices have significantly lower erase-program cycles than SBC configured flash memory devices.

Although MBC flash memory is suitable for most consumer applications, the 10000 cycle program-erase limit may not be sufficient for other applications where data programming and erasing is frequent or where data is mission critical. Therefore, this problem is more critical for commercial applications (e.g., HDD applications) where there are more frequent program-erase cycles. Because HDD applications require higher data integrity than most consumer applications, MBC flash memory is not suitable for use due to its relatively short 10000 cycle life. A dedicated dual mode SBC/MBC flash memory device is proposed, in which the operating mode is set statically or changed dynamically at runtime. Different command sets and/or logic circuits are required for such dual mode devices.

Finally, the cost of SBC flash memory devices currently exceeds that of higher density MBC flash memory devices, as vendors recognize that consumers who require high reliability will pay for higher cost devices. A dedicated dual mode SBC/MBC flash memory device may also cost more than an MBC flash memory device.

It is therefore desirable to provide a low cost flash memory system in which MBC flash memory devices can be used to store data in the SBC storage mode.

In general, at least some example embodiments provide methods and systems for controlling a flash memory device of an MBC configuration to store data in an SBC storage mode or a partial MBC storage mode of less than full MBC storage mode capacity. In a full MBC storage mode, for each physical row of memory cells, pages of data are programmed sequentially from a first page to an Nth page, where N is the total number of pages that can be stored in one physical row. Up to N virtual page addresses per physical row of memory cells are applied to the virtual locations of a specified page in the physical row, as opposed to each page to be programmed. For SBC or partial MBC data storage, the flash controller issues a program command to the MBC storage device using less than a maximum of N virtual page addresses for each physical row. The MBC memory device performs the programming operation continuously until the last received virtual page address of the physical row.

The presently described embodiments may be used in the memory systems shown in fig. 9 and 10.

Fig. 9 illustrates a flash memory system according to an embodiment of the present invention. Referring to fig. 9, a flash memory system 100 is integrated with a host system 102. The flash memory system 100 includes a flash controller 104 in communication with a host system 102 and a plurality of MBC flash memory devices 106-1-106-4. The host system 102 includes a processing device, such as a microcontroller, microprocessor, or computer system (not shown). Flash memory system 100 is configured to include one channel 108, wherein MBC flash memory devices 106-1-106-4 are coupled in parallel to channel 108. Channel 108 includes a set of common buses (not shown) that include data and control lines coupled to all of memory devices 106-1-106-4. Although not shown, each memory device is enabled/disabled using a respective chip select signal provided by the flash controller 104. The flash controller 104 is responsible for issuing commands and data to a selected one of the memory devices 106-1-106-4 via the channel 108 based on the operation of the host system 102. Data read from a selected one of the memory devices 106-1-106-4 is transferred back to the flash controller 104 via the channel 108, which in turn provides the read data to the host system 102. Those skilled in the art will appreciate that the memory system 100 may have more or fewer memory devices coupled to the channel 108.

Flash memory system 100 is commonly referred to as a multi-drop configuration, in which MBC flash memory devices 106-1-106-4 are coupled in parallel with respect to channel 108. The flash controller 104 may have multiple channels, each with flash devices 106-1-106-4 coupled in a multi-drop configuration. Each MBC flash memory device 106-1-106-4 may be a NAND flash memory device having the bank memory organization previously shown in FIG. 2. The flash memory devices 106-1-106-4 may have the same capacity or different capacities.

Fig. 10 shows a flash memory system according to another embodiment of the present invention. Referring to fig. 10, a flash memory system 120 includes a flash memory controller 122 in communication with a host system 124 and a plurality of flash memories connected in series. In this particular example, four MBC flash memory devices 126-1-126-4 are coupled in series. Each of the four flash memory devices 126-1-126-4 has input/output circuitry for facilitating operations between the memory devices. Those skilled in the art will appreciate that memory system 120 may have more or fewer memory devices coupled in series with flash controller 122. Examples of such flash memory devices are described in commonly-owned U.S. patent application serial No. 11/324,023, filed on 30/2005 and 11/496,278, filed on 31/2006, the contents of which are incorporated herein by reference.

According to the present embodiment, the MBC memory device of the system of FIGS. 9 and 10 has an internal controller configured to identify the received page address and determine which particular programming algorithm is required. For example, a page address corresponding to a first page to be programmed to a physical row is programmed using a different algorithm than a second page to be programmed to the physical row. The memory controllers 104 and 122 are configured using an address binding scheme that limits the available virtual address space for programming a page of data to a physical row of memory cells. This address binding scheme is used to program data in SBC mode or partial MBC mode. In the partial MBC storage mode, more than one page of data is stored in a physical row of memory cells, but less than the maximum number of pages that can be stored in a physical row of memory cells. For example, if an MBC memory device can store more than three bits/cell (or more than three pages of data per physical row), the memory controller can be configured to have a first address binding scheme for programming data in the SBC storage mode and a second address binding scheme for programming data in the two-bit/cell MBC storage mode.

In an embodiment, the address binding scheme may be applied to any subsection of a storage array, where the subsection may include a storage block, a sub-block or portion of a storage block, or a physical row. Thus, for increased system flexibility, a combination of different subsections and different address binding schemes may be implemented.

FIG. 11 is a table showing an exemplary mapping of virtual page addresses to physical rows or word lines of a NAND flash memory array for an SBC storage mode in which one bit of data is stored per cell, an MBC storage mode in which two bits of data are stored per cell, and an MBC storage mode in which three bits of data are stored per cell.

In the presently illustrated example, assume that a NAND cell string includes 32 word lines (WL1-WL32), each of which is referred to as a physical row. The second column from the left side of the table shows the virtual address mapping for a one-bit-per-cell data storage mode. Thus, in a one-bit-per-cell storage mode, one page of data (page 1-page 32) is stored in each physical row. Appearing in brackets next to each numbered page is an 8-bit virtual page address with the Least Significant Bit (LSB) at the rightmost bit position. In this example, the first seven bits of each virtual page address are shown as "x" and the LSB is shown as either "0" or "1". Assume in this example that the pages are programmed in sequential order from WL1 to WL32, so the virtual addresses are also ordered sequentially.

In the column labeled "2 bits/cell", 2 pages of data are stored in each physical row. Due to the sequential programming, the first page to be programmed is referred to as the Lower Page (LP), while the second and last page to be programmed is referred to as the Upper Page (UP).

FIG. 12A shows exemplary threshold voltage distributions for possible threshold voltages of a two-bit MBC memory after the lower page is programmed. FIG. 12B shows an exemplary threshold voltage distribution of possible threshold voltages after the upper page is programmed, which takes into account the previously programmed lower page data of FIG. 12A. The arrows in FIG. 12A show that erasing a state 0 cell can change its threshold to state 1 after the lower page is programmed. The arrows in FIG. 12B show where the threshold voltages corresponding to state 0 and state 1 can be changed after upper page programming.

It should be noted that the LSB of the lower page of each physical row is "0", while the LSB of the upper page of each physical row is "1". In alternative embodiments, the LSBs of the upper and lower pages may be different than those shown in the table of FIG. 11. However, the lower page of each physical row will have the same LSBs, while the upper page of each physical row will have the same LSBs.

Referring to FIG. 11, in the column labeled "3 bits/cell", 3 pages of data are stored in each physical row. In this 3-bit per cell MBC storage mode, the lower page is programmed first, then the middle page (IP), and finally the upper page.

FIG. 13A shows exemplary threshold voltage distributions for possible threshold voltages of a three-bit MBC memory after the lower page is programmed. FIG. 13B shows an exemplary threshold voltage distribution of possible threshold voltages after the middle page is programmed, which takes into account the previously programmed lower page data of FIG. 13A. FIG. 13C shows an exemplary threshold voltage distribution of possible threshold voltages after the upper page is programmed, which takes into account the previously programmed lower page data of FIG. 13B.

In an MBC storage mode that stores more than three bits per cell, there may be at least two intermediate pages between the lower page and the upper page. It should be noted that the last two LSBs of the lower page of each physical row are "00", the last two LSBs of the middle page of each physical row are "01", and the last two LSBs of the upper page of each physical row are "10". In an alternative embodiment, the last two LSBs of the lower, middle and upper pages may be different than shown in the table of FIG. 11. However, the lower page of each physical row will have the same last two LSBs, the middle page of each physical row will have the same last two LSBs, and the upper page of each physical row will have the same last two LSBs.

According to an embodiment, an MBC memory device for storing up to N pages per physical row and having a virtual page address scheme as shown in fig. 11 may be controlled to program data into subsections of a storage array in a less than N pages per physical row storage mode. This is accomplished using a memory controller configured to issue program commands using only a subset of the available virtual page addresses that would otherwise be used to address all N pages per physical row. More specifically, the subset of virtual page addresses is limited to the lowest contiguous set of virtual page addresses available per physical line. The number of virtual page addresses of the subset determines the storage mode of the MBC memory device. This is referred to as an address binding scheme for limiting virtual page addresses to only those page addresses for a particular storage mode.

Referring to the table of fig. 11 as an example, a three-bit MBC memory device may store up to N-3 pages of data addressable using N-3 virtual page addresses per physical row. As an example, to store data to a memory block in the SBC storage mode, the memory controller issues a program command for each page of data, with a corresponding virtual page address provided for the lower page of each physical row. As shown in FIG. 13A, after each lower page is programmed to the corresponding physical row, the resulting possible threshold voltages correspond to either state 1 or state 2. In a partial MBC storage mode where two pages are stored in each physical row, the program command issued for each physical row includes the lower page and intermediate page addresses. After the middle page of data is programmed, each physical row will have four possible states as shown in FIG. 13B.

Figure 14 shows an example of an SBC programming operation for a two-bit MBC memory device according to an embodiment of the present invention. Referring to FIG. 14, a two-bit MBC memory device 200 is controlled to store data into memory blocks in the SBC storage mode. The memory device 200 includes a memory array 202 having NAND cell strings forming a memory block 204 and may have a block diagram of a flash memory device as shown in fig. 1. In the example shown in FIG. 14, only one NAND cell string of memory block 204 is shown. Furthermore, the virtual page addressing scheme shown in the table of FIG. 11 is for a two-bit MBC memory device 200. A program command packet issued to the memory device 200 includes an initial program Operation (OP) code field (PGM)206, a block address field (BA)208, a row address field (RA)210, a column address field (CA)212, a DATA field (DATA)214, and a confirmation program OP Code Field (CFRM) 216. In this example, OP code segment 206 comprises a predetermined binary sequence that indicates to memory device 200 that information related to the programming operation will follow. The block address field 208 contains a block address for selecting a particular storage block within the storage array 202. The row address field 210 contains the virtual page address of the selected physical row, with higher order bits, which are not LSBs, used to address the physical word line. The column address field 212 contains a starting column address for storage of data. The data field 214 contains the page of data to be programmed. The confirm program OP code field 216 comprises a predetermined binary sequence that indicates to the memory device 200 that the programming operation may proceed.

The currently displayed program command packets may be provided as a continuous bit stream or in parallel via an input port. The program command packet may be different for different memory systems and, therefore, OP code segments 206 and/or 216 may be omitted, or additional protocol information may be included. The order and format of the program command packets may vary. The program command packet requires address information for programming of a page of data.

In the current SBC storage mode example, the row address field 210 is limited to include virtual page addresses corresponding only to the lower page of each physical row. In FIG. 14, these virtual page addresses are boxed to illustrate that the virtual page addresses are bound to those addresses corresponding to the lower pages of memory block 204. Thus, to program a page of data to all physical rows of the memory block 204 in the SBC storage mode, successive program command packets are provided to the memory device 200, where each program command packet includes a page of data to be programmed and a lower page virtual page address. Although the memory device 200 is configured to program up to two pages of data per physical row, resulting in one of the four possible states as shown in FIG. 12B, programming only the lower page results in the two possible threshold voltage distributions shown in FIG. 12A. Thus, SBC storage mode programming is implemented in a two-bit MBC memory device.

Thus, when a subsection of the storage array 202 no longer reliably stores data in the full MBC storage mode (because it reaches the number of predetermined program/erase cycles), the subsection of the storage array 202 may be degraded to storing data in the SBC storage mode. The transition of subsegments from full MBC storage to SBC storage is referred to as "destaging" if the primary purpose of the subsegment is to maximize data storage capacity. Alternatively, such a conversion may be referred to as an "upgrade" if the primary purpose of the sub-segments is to reliably store data.

The same address binding principles are applicable to a three-bit MBC memory device, where the subsections are used to store data in the SBC storage mode. However, a three-bit or more-bit MBC memory device has an increased advantage in that the sub-segments may be gradually changed from a full MBC storage mode to the next lower partial MBC storage mode when the number of program/erase cycles of a particular storage mode is reached.

FIG. 15 illustrates an exemplary two-bit MBC programming operation of a three-bit MBC memory device, according to an embodiment of the invention. Referring to fig. 15, a three-bit MBC memory device 300 is controlled to store data into memory blocks in a two-bit MBC storage mode. The memory device 300 includes a memory array 302 having NAND cell strings forming a memory block 304. Only one NAND cell string of memory block 304 is shown. The virtual page addressing scheme shown in the table of FIG. 11 is for a three-bit MBC memory device. In this example, three consecutive program command packets 306, 308, and 310 are provided to the memory device 300. Each of the program command packets 306, 308, and 310 may have the same format as the program command packet previously shown in fig. 14. The program command packet 306 contains the data for page 1 and the corresponding lower page virtual address. The program command packet 308 contains the data for page 2 and the corresponding intermediate page virtual address. The program command packet 310 contains the data for page 4 and the corresponding lower page virtual address. In the case of a three-bit MBC memory device, a controller (e.g., controller 18 of memory device 10 of FIG. 1) will look at the last two valid bits of the virtual page address in order to determine which programming algorithm to use. This is due to the fact that: there are three page addresses per physical row and using only the LSBs is not sufficient to determine which programming algorithm to use.

Thus, when memory device 300 receives program command packet 306, a program operation is performed to program page 1 to the memory cells connected to WL 1. The resulting possible threshold voltage distributions for these memory cells are shown in either FIG. 12A or FIG. 13A. After memory device 300 receives program command packet 308, a program operation is performed to program page 1 to the memory cells connected to WL 1. Because the second page of data is programmed to the memory cells connected to WL1, a different programming algorithm is used than that used to program page 1. The resulting possible threshold voltage distributions for these memory cells are shown in FIG. 12B or FIG. 13B. The two-bit MBC programming of the memory cell connected to WL1 is now complete. A third program command packet 310 is received by the memory device 300 for programming a new lower page, page 4, to the next word line WL 2. Once programmed, the memory cells connected to WL1 have the possible threshold voltage distributions shown in fig. 12A or fig. 13A. Although not shown, additional program command packets are received by memory device 300 for programming data to the remaining physical rows of memory block 304. An advantage of using a three or more bit MBC memory device is that the subsegments can be used in a two-bit MBC storage mode and then later in an SBC storage mode.

FIG. 16 shows an example of an N-bit MBC flash memory controller. Referring to FIG. 16, an N-bit MBC flash memory controller 400 is configured using at least one address binding scheme for programming data in less than N-bit storage modes. Memory controller 400 generally includes a CPU and clock control block 402, a flash control block 404, and a mapping table 406. Although not shown, CPU and clock control block 402 includes a central processing unit for communicating with other subsystems via a common bus, a clock generator for providing the necessary clock signals to the other circuits of memory controller 400, and other circuits as may be necessary to achieve proper operation of the device. Flash control block 404 includes a file and memory management sub-block, an ECC (error correction code) sub-block, and a physical flash interface sub-block. The flash memory device is accessed through the physical flash interface sub-block. The accessed data from the flash memory device is checked and corrected by the ECC sub-block. The file and memory management sub-block provides logical to physical address translation and executes a wear leveling algorithm.

In general, flash control block 404 accurately tracks and updates attributes (information) of the memory devices, such as erase cycles, valid/empty, etc. per page or block of each flash device in the system to which it is connected. This information is stored in a local memory and constructed as a mapping table. An exemplary mapping table 408 is shown in fig. 16. Mapping table 408 stores information, referred to as metadata, for each memory device, which may include SBC/MBC status bits indicating the data storage mode of each block and the number of program/erase cycles for each block. An SBC/MBC status bit of "0" may indicate that the subsegment stores data in the MBC storage mode, and a "1" may indicate that the subsegment stores data in the SBC storage mode. It should be understood that for MBC memory devices that store more than three bits per cell, at least two status bits are used to indicate each possible data storage mode. Note that the flash controller also records the virtual page address range for each memory device, and for each address binding scheme, the flash controller is programmed using an algorithm to use only the allowed virtual page addresses for the particular storage mode.

The flash control block 404 continuously updates and monitors the mapping table 408 during the lifetime of the memory system. Note that the mapping table may be populated with information at power-up of the memory system, and information such as persistence and SBC/MBC states may be stored in additional data fields in the memory device associated with each physical row and/or memory block. If the page or block reaches the maximum number of program/erase cycles (10K cycles in MLC flash), then flash control block 404 may decide to change the storage mode to the SBC storage mode, thereby extending the program/erase cycles to 100K.

When the memory controller 400 receives a host request to program data, the flash control block 404 looks up the mapping table 406 to determine where the data should be programmed. If the selected memory block is configured for the SBC memory mode, a pre-programmed address binding scheme for using only the lower page virtual address of each physical row is applied. Assuming that multiple pages are to be programmed, command packets are prepared by the memory controller 400 and sent to the selected MBC memory devices, each command packet having a row address field containing only the lower page virtual address.

FIG. 17 is a flowchart of a method of operating a memory controller to issue commands in the SBC, full MBC, or partial MBC storage mode for the purpose of controlling an MBC memory device to store data, according to the present embodiment.

Referring to fig. 16 and 17, the method begins by powering on the memory system (step 500). The memory system includes a memory controller configured similarly to the memory controller 400 and at least one N-bit MBC memory device. This memory system may have the configuration shown in fig. 9 or fig. 10. As part of the power-up sequence, the memory controller performs a scan of at least one N-bit MBC memory device for device metadata, such as the persistence and SBC/MBC state information of its subsections (step 502). This information is collected and stored in a mapping table in the memory controller 400. Once the power-up sequence is complete, the memory controller 400 may receive a command from the host device. A host programming request is received by the memory controller 400 (step 504). This request may include a certain priority of the data to be programmed. For example, low priority data may be non-critical media data, while high priority data may be data indicated as requiring high reliability storage. Other algorithms of the memory controller 400 may be executed to determine the appropriate wear leveling technique to use based on parameters such as the size of the data to be programmed, the availability of free space in the memory device, and priorities such as those described previously.

The memory controller accesses its mapping table to identify where the data should be stored based on the aforementioned algorithm executed by the memory controller 400 (step 506). The memory controller then determines whether SLC storage is required for the host program request (step 508). If SLC storage is required, the memory controller 400 issues a command at step 510 to store data in the selected sub-segments using the SBC address binding scheme, wherein only the lower page virtual address of each physical row is used. Otherwise, the method continues to step 512, where the memory controller determines whether full MLC programming is required. If full MLC programming is required, the memory controller issues a command with a full virtual page address range for each physical row (step 514). Otherwise, a command is issued using a partial MLC address binding scheme in which a subset of the full range of virtual page addresses per physical row is used to program the data (step 516).

The commands issued by the memory controller according to the method of FIG. 17 do not require special commands to be issued for configuring the operation of the selected MBC memory device in another storage mode. This ensures higher performance of the memory system because commands are issued at runtime, so no clock cycles are wasted for configuring the MBC memory device. Furthermore, no reset of the memory device is required for setting it to the required storage mode.

FIG. 18 illustrates the operation of an N-bit MBC memory device receiving commands from a memory controller operating using the method outlined in FIG. 17. Referring to FIG. 18, the method begins, where a program command issued by the memory controller 400 is received by the MBC memory device (step 600). Collectively, these commands are used to program a set of data requested by the host, which may span multiple pages. It should be noted that the memory device may receive interleaved commands for programming different sets of data to different subsections of the memory device. In other words, one command may be received to begin programming data to one sub-segment, and a subsequent received command may be received to begin programming data to another sub-segment. A third command may then be received to continue programming more data to the first subsection. Subsequently, the MBC memory device checks at least the LSBs of the virtual page addresses associated with each page of data (step 602). The last two LSBs are checked if, for example, the MBC memory device is configured for up to three bits of data storage per cell. If, for example, the MBC memory device is configured for up to two bits of data storage per cell, then the last LSB is checked. Regardless of the maximum number of bits per cell that the memory device is configured to store, there will be a minimum number of virtual page addresses LSBs required to identify each virtual page of a physical row. These are the LSBs that were checked in step 602. The internal controller (also referred to as a command decoder) of the MBC memory device then executes the appropriate programming sequence or algorithm in response to the LSB at step 604. More specifically, the internal controller executes a partial MLC programming algorithm that includes less than the maximum number of bits per cell for the MBC memory device. This internal controller is shown, for example, as controller 18 in the flash memory device block diagram of fig. 1.

For example, if the LSB of the virtual page address is "0," the internal controller of the MBC memory device may execute the SBC programming algorithm. If no additional program command is received with a virtual page address of "1," the page is programmed to a physical row in the SBC storage mode. The resulting possible threshold voltages of the cells of a physical row may occur, for example, as shown in fig. 12A or 13A. In another example, a pair of program commands is received, wherein a first program command includes a dummy page address LSB of "0" and a second program command includes a dummy page address LSB of "1". In this case, the first page data is programmed using the SBC programming algorithm. The second page of data having LSBs of "1" is then programmed for the same physical row according to a 2-bit MBC programming algorithm executed by an internal controller of the memory device. The resulting possible threshold voltages of the cells of the physical row appear as shown in fig. 12B or 13B.

Fig. 19 illustrates a detailed exemplary operation of the memory system according to the embodiment. Beginning at step 700, assume that all of its subsections (e.g., memory blocks as an example) of an MBC memory device are configured for full N-bit MBC storage, where N is the maximum number of bits that can be stored per cell. In this example, N is assumed to be 2. Thus, the memory controller's mapping table will have the SLC/MLC status bit of each sub-segment set to indicate a full MLC data storage mode. A host request is received by the memory controller at step 702 and the memory controller determines whether the request is a program request or an erase request at step 704. If the host request is not both, then the request is executed at step 706 and the system waits for another host request. Otherwise, the method continues to step 708, where the memory controller further determines whether the data should be programmed in the MBC mode. If the data should be programmed in the MBC storage mode, the number of program/erase cycles of the selected memory block is checked in step 710. At step 712, a determination is made whether the maximum number of program/erase cycles for the selected memory block is reached. If not, an MLC program operation is performed in step 714 by issuing the required program command to the memory device.

On the other hand, if the maximum number of program/erase cycles for the selected memory block has been reached, the memory controller executes a block life extension algorithm. This algorithm begins at step 716, where new data is programmed into the available MLC or SLC configured memory blocks. Any resident data in the initially selected memory block is later copied to an available MLC or SLC configured memory block during background operations, which may be the same memory block to which new data was most recently programmed. This background operation may be scheduled by the memory controller.

At step 718, the selected block in the memory array is converted for use as an SLC memory block by updating its corresponding SLC/MLC tag bits. The memory controller's mapping table is updated at step 720 to reflect this change in the storage pattern of the selected memory block. This updating may also include resetting the number of program/erase cycles of the converted SLC memory block to the appropriate SLC program/erase limit. This limit may be, for example, between 10K and 100K cycles.

Returning to the determination at step 708, if the program request is for SLC storage, then at step 722 the number of program/erase cycles of the selected SLC memory block is checked to determine if the maximum number of cycles has been reached. If the maximum number of cycles has not been reached for the selected SLC memory block at step 724, then the SLC programming operation is performed at step 706 by sending the desired program command to the memory device. As discussed previously, the SLC address binding scheme is used by the memory controller to issue program commands having a virtual page address that is limited to the address of the lower page of each physical row. Otherwise, the SLC memory block cannot reliably store SLC data and the method continues to step 726 in which an SLC programming operation is performed for another available SLC memory block and any resident data in the originally selected SLC memory block is copied to the same available SLC memory block or another available SLC memory block. The initially selected SLC memory block is marked as invalid in the memory device at step 728 and the mapping table in the memory controller is updated accordingly at step 720. Marking a memory block as invalid has the effect that the memory block is no longer used in the future.

An advantage of the presently shown embodiments is that any mode of storage operation of the memory device that is less than the full MBC storage mode can be performed without the need to set any registers, reboot the memory device, or any other interruption to its normal operation.

In all of the previously discussed embodiments, the selective MBC or SBC process performed by the flash controller is done transparently to the user. No additional instructions or modification of instructions from the user are required because all determinations of SBC/MBC storage mode operation are made by the flash controller. Thus, there is minimal overhead required to implement the presently described flash memory system with a host system.

In the previous description, for purposes of explanation, numerous details were set forth in order to provide a thorough understanding of the embodiments. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the embodiments. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure aspects of the embodiments. For example, specific details are not provided as to whether the embodiments described herein are implemented as software routines, hardware circuits, firmware, or a combination thereof.

The above embodiments are intended to be examples only. Alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope, which is defined solely by the claims appended hereto.

Claims (29)

1. A method for programming a multi-bit per cell (MBC) flash memory device configured to store up to N pages of data per physical row, N being an integer greater than 1, the method comprising:

issuing a set of program commands for programming a plurality of pages of data to a subsection of the flash memory device having at least one physical row,

the set of programming commands is restricted to be associated with each of the at least one physical row

Addressing a selected logical page address subset of all the corresponding possible logical page addresses; and

programming less than N pages to each of the at least one physical row of the flash memory device in response to the subset of logical page addresses in the program command.

2. The method of claim 1, further comprising:

accessing a mapping table prior to issuing the set of programming commands, wherein the mapping table contains storage mode information for each subsection of the flash memory device.

3. The method of claim 2, wherein accessing the mapping table comprises:

a subsection is selected having a partial MBC storage mode in which less than N pages of data are stored per physical row.

4. The method of claim 3, further comprising:

selecting the subset of logical page addresses corresponding to the partial MBC storage mode.

5. The method of claim 4, wherein all possible logical page addresses corresponding to each of the at least one physical row comprise consecutive page addresses beginning with a lower page address and ending with an upper page address.

6. The method of claim 5, wherein the subset of logical page addresses includes the lower page address up to an intermediate page address, wherein the intermediate page address is between the upper page address and the lower page address of each of the at least one physical row.

7. The method of claim 5, wherein the subset of logical page addresses includes only lower page addresses of each of the at least one physical row.

8. The method of claim 5, wherein issuing a set of program commands comprises repeatedly providing program command packets, each program command packet containing one of the plurality of pages of data and one of the subset of logical page addresses.

9. The method of claim 8, wherein issuing a set of programming commands comprises:

m program command packets are provided for programming M pages of the plurality of pages of data to one physical row of the flash memory device, where M is an integer value less than N.

10. The method of claim 8, wherein issuing a set of programming commands comprises:

repeatedly providing a program command packet for programming one of the plurality of pages of data to one physical row of the flash memory device.

11. The method of claim 1, further comprising:

prior to issuing the set of program commands, receiving a host request to program the plurality of pages of data in a partial MBC storage mode.

12. The method of claim 1, further comprising:

prior to issuing the set of program commands, receiving a host request to program the plurality of pages of data in a full MBC storage mode.

13. The method of claim 12, comprising determining that a maximum number of MBC program/erase cycles for the subsection has been reached.

14. The method of claim 13, further comprising:

selecting another subsection configured to program the plurality of pages of data in the full MBC storage mode and setting the subsection to a partial MBC storage mode.

15. The method of claim 14, wherein the full MBC storage mode comprises a two-bit-per-cell storage mode and the partial MBC storage mode comprises a one-bit-per-cell storage mode.

16. A system, comprising:

a memory controller configured to issue a program command that is restricted to addressing a subset of logical page addresses selected from all possible logical page addresses corresponding to each physical row of a memory device, the memory device comprising:

a multi-bit per cell (MBC) memory device configured to:

storing a maximum of N pages per physical row, where N is an integer greater than 1, an

Programming less than N pages per physical row in response to the subset of logical page addresses in the program command received from the memory controller.

17. The system of claim 16, wherein the memory controller comprises:

a mapping table for storing metadata corresponding to subsections of the memory device.

18. The system of claim 17, wherein the mapping table is configured to include storage mode information for each of the subsections.

19. The system of claim 18, wherein the mapping table is configured to include address binding information associated with a storage mode of each of the subsections.

20. The system of claim 19, wherein the memory controller comprises:

control circuitry for accessing the mapping table and providing the programming command in response to the metadata in the mapping table.

21. The system of claim 20, wherein each of the programming commands comprises:

a page of data, address information for selecting subsections of the memory device and physical rows within the subsections, an

A logical page address of the page of data to be programmed into the physical row.

22. The system of claim 21, wherein:

the memory device is configured to store at most N-2 pages per physical row, and each of the two pages of each physical row is addressable by an upper page address and a lower page address.

23. The system of claim 22, wherein:

the upper page address has a first least significant bit, an

The lower page address has a second least significant bit different from the first least significant bit.

24. The system of claim 17, wherein the subdivisions of the memory device include memory blocks.

25. The system of claim 17, wherein the subdivisions of the memory device include sub-blocks of a memory block.

26. The system of claim 17, wherein the subdivisions of the memory device include physical rows of memory blocks.

27. A method for programming a multi-bit per cell (MBC) flash memory device configured to store up to N bits per cell, where N is an integer greater than 1, the method comprising:

receiving a host request to program a page of data;

determining that the data page is to be programmed in a partial MBC storage mode in which fewer than N virtually addressable data pages are stored in each physical row of the flash memory device;

accessing a mapping table containing metadata for the flash memory device to select subsections of the MBC flash memory device configured in the partial MBC storage mode; and

issuing at least one program command for programming the page of data to the subsection using a virtual page address limited to a subset of less than N possible virtual page addresses for programming a page to each physical row.

28. The method of claim 27, wherein:

n-2, and the possible virtual page addresses include a lower page address and an upper page address, an

Issuing at least one program command includes repeatedly issuing program commands, each program command including a page of data and a lower page address.

29. The method of claim 27, wherein:

n >2, and possible virtual page addresses include a lower page address, an upper page address, and at least one intermediate page address between the lower page address and the upper page address, an

Issuing at least one program command includes repeatedly issuing program commands, each program command including a page of data, and one of the lower page address and the at least one intermediate page address.