HK1260209B - Circuits, methods, and systems for adaptive voltage modulation - Google Patents

Description

Circuits, methods, and systems for adaptive voltage modulation

Priority requirement

The present application claims priority from U.S. provisional patent application No. 62/342,638 entitled "ADAPTIVE VOLTAGE MODULATION circuit FOR adjusting SUPPLY VOLTAGE TO MITIGATE SUPPLY VOLTAGE drop" (ADAPTIVE VOLTAGE MODULATION circuit FOR ADAPTIVE VOLTAGE SUPPLY TO minimum VOLTAGE SUPPLY VOLTAGE drop), filed on 27/5/2016, the contents of which are incorporated herein by reference in their entirety.

The present application claims priority from U.S. provisional patent application No. 15/604,038 entitled "ADAPTIVE VOLTAGE modulation circuit FOR ADJUSTING SUPPLY VOLTAGE TO REDUCE SUPPLY VOLTAGE drop and minimize POWER CONSUMPTION" (ADAPTIVE VOLTAGE modulation circuit FOR ADJUSTING SUPPLY VOLTAGE TO REDUCE SUPPLY VOLTAGE drop and minimize POWER CONSUMPTION) "filed on 24/5/2017, the contents of which are incorporated herein by reference in their entirety.

Technical Field

The techniques of this disclosure generally relate to supply voltage drop, and in particular to adjusting supply voltage to reduce supply voltage drop and power consumption.

Background

One factor that negatively affects circuit performance is the occurrence of supply voltage drops. The supply voltage is dropped to a temporary drop or reduction in a particular voltage level that is below the supply voltage provided by the power supply to one or more elements in the circuit. The supply voltage drop may be a result of a surge in the supply current provided by the power supply in response to a change in load current demand of a circuit powered by the power supply. For example, the load current requirements of the circuit may increase in response to transistors in circuit switching during circuit operation. The increase in load current demand causes a surge in the power supply current that creates a supply voltage drop. The reduction in supply voltage corresponding to the supply voltage drop reduces the speed at which the circuit operates, thus negatively impacting circuit performance.

Various techniques may be used to reduce or avoid the effects of supply voltage drops in the circuit. For example, a circuit element may be designed to operate in a particular voltage limit relative to a supply voltage. In this manner, the circuit element may achieve desired operation when receiving a voltage that exceeds or falls short of the supply voltage by a certain percentage (i.e., a limit, such as +/-10% of the supply voltage). However, such voltage limits are conventionally set to meet worst-case operating conditions, and as a result, power consumption may be increased and circuit performance reduced. As another example, a voltage regulator may be used to sense changes in the load current demand of a circuit and adjust the supply voltage in response to such changes. However, voltage regulators are typically too slow to effectively mitigate high frequency supply voltage drops. In addition, the voltage sensor may be used to detect a supply voltage drop and, in response to detecting the supply voltage drop, reduce the frequency of the clock signal to reduce the load current demand of the corresponding load circuit. However, reducing the frequency of the clock signal in this manner reduces the operating speed of the circuit. Thus, circuits experiencing multiple supply voltage drops are frequently tuned to lower clock frequencies with voltage sensors, which limits the performance of the circuits.

Disclosure of Invention

Aspects disclosed in the embodiments include an adaptive voltage modulation circuit for adjusting a supply voltage to reduce a supply voltage drop and minimize power consumption. In one aspect, an adaptive voltage modulation circuit is provided. The adaptive voltage modulation circuit detects whether the supply voltage drops below a drop threshold voltage (i.e., detects a supply voltage drop) and adjusts a clock signal provided to the load circuit for the duration of the supply voltage drop. Adjusting the clock signal may include reducing the frequency at which the load circuit operates to reduce or avoid timing glitches caused by supply voltage drops. In addition to mitigating the effects of supply voltage drops, the adaptive voltage modulation circuit counts the number of clock cycles during which the supply voltage is below a drop threshold voltage. In other words, the count indicates the length of time that the load circuit experiences a supply voltage drop. In response to the count exceeding an upper threshold, the adaptive voltage modulation circuit increases the supply voltage. In this way, the supply voltage is increased in response to operation of the load circuit corresponding to higher load current demand. Conversely, in response to the count being less than the lower threshold at the end of the defined period, the adaptive voltage modulation circuit decreases the supply voltage. In this way, the supply voltage is reduced in response to operation of the load circuit corresponding to a lower load current demand. Adjusting the supply voltage based on the operational requirements of the load circuit may reduce the occurrence of supply voltage drops and avoid setting the supply voltage greater than that required by the load circuit. Thus, the adaptive voltage modulation circuit mitigates the effects of supply voltage drop and also reduces the occurrence of supply voltage drop while minimizing power consumption of the load circuit.

In this regard, in one aspect, an adaptive voltage modulation circuit is provided. The adaptive voltage modulation circuit includes a supply voltage drop detection and mitigation circuit. The supply voltage drop detection and mitigation circuit includes a detection circuit configured to generate a drop detection signal in an active state in response to a supply voltage provided to the load circuit being less than a drop threshold voltage. The supply voltage drop detection and mitigation circuit further includes a clock adjustment circuit configured to adjust a load clock signal provided to the load circuit in response to the drop detection signal. The adaptive voltage modulation circuit further includes a supply voltage adjustment circuit. The supply voltage adjustment circuit includes a counter circuit configured to increment a count in response to each cycle of the reference clock signal, wherein the down detection signal is active. The supply voltage adjustment circuit also includes a voltage-adjust-up circuit configured to generate an active voltage-adjust-up signal in response to the count being greater than the adjust-up threshold. The supply voltage adjustment circuit further includes a voltage-reduction circuit configured to generate a voltage-reduction signal in an active state in response to the count being less than a reduction threshold at the end of the defined period as measured by the reference clock signal. The adaptive voltage modulation circuit further includes a supply voltage controller circuit. The supply voltage controller circuit is configured to increase a supply voltage provided to the load circuit in response to the voltage-adjust-high signal being active, and to decrease the supply voltage provided to the load circuit in response to the voltage-adjust-low signal being active.

In another aspect, an adaptive voltage modulation circuit is provided. The adaptive voltage modulation circuit includes means for generating a drop detection signal in an active state in response to the supply voltage being less than a drop threshold voltage. The adaptive voltage modulation circuit also includes means for adjusting a load clock signal provided to the load circuit in response to a fall detection signal, and means for incrementing a count in response to each cycle of a reference clock signal, wherein the fall detection signal is active. The adaptive voltage modulation circuit also includes means for generating an active voltage up signal in response to the count being greater than the up threshold, and means for generating an active voltage down signal in response to the count being less than the down threshold at the end of the defined period as measured by the reference clock signal. The adaptive voltage modulation circuit further includes means for increasing a supply voltage provided to the load circuit in response to the voltage-adjust-high signal being active, and means for decreasing the supply voltage provided to the load circuit in response to the voltage-adjust-low signal being active.

In another aspect, a method for adaptively modulating a supply voltage is provided. The method includes generating a drop detection signal in an active state in response to the supply voltage being less than a drop threshold voltage, and adjusting a load clock signal provided to the load circuit in response to the drop detection signal. The method further includes incrementing a count in response to each cycle of the reference clock signal, wherein the down detection signal is in an active state. The method also includes generating a voltage-up signal in an active state in response to the count being greater than the up threshold, and generating a voltage-down signal in an active state in response to the count being less than the down threshold at the end of the defined period as measured by the reference clock signal. The method also includes increasing a supply voltage provided to the load circuit in response to the voltage-up signal being active, and decreasing the supply voltage provided to the load circuit in response to the voltage-down signal being active.

In another aspect, a processor-based system is provided. The processor-based circuit includes a processor, a power management circuit configured to provide a supply voltage to the processor, and an adaptive voltage modulation circuit. The adaptive voltage modulation circuit includes a supply voltage drop detection and mitigation circuit. The supply voltage drop detection and mitigation circuit includes a detection circuit configured to generate a drop detection signal in an active state in response to the supply voltage being less than a drop threshold voltage, and a clock adjustment circuit configured to adjust a load clock signal provided to the processor in response to the drop detection signal. The adaptive voltage modulation circuit also includes a supply voltage adjustment circuit. The supply voltage adjustment circuit includes a counter circuit configured to increment a count in response to each cycle of the reference clock signal, wherein the down detection signal is active. The supply voltage adjustment circuit further includes a voltage up circuit configured to generate a voltage up signal in an active state in response to the count being greater than the up threshold, and a voltage down circuit configured to generate a voltage down signal in an active state in response to the count being less than the down threshold at the end of the defined period as measured by the reference clock signal. The adaptive voltage modulation circuit further includes a supply voltage controller circuit. The supply voltage controller circuit is configured to increase a supply voltage provided to the processor in response to the voltage-adjust-high signal being active, and to decrease the supply voltage provided to the processor in response to the voltage-adjust-low signal being active.

Drawings

FIG. 1 is a block diagram of an exemplary adaptive voltage modulation circuit for reducing supply voltage drop and minimizing power consumption;

FIG. 2 is a flow diagram illustrating an exemplary process that may be employed by the adaptive voltage modulation circuit in FIG. 1 to adaptively modulate a supply voltage to reduce supply voltage drop and minimize power consumption;

FIG. 3 is a block diagram of another exemplary adaptive voltage modulation circuit for reducing supply voltage drop and minimizing power consumption;

FIG. 4 is a block diagram of another exemplary adaptive voltage modulation circuit for reducing supply voltage drop and minimizing power consumption;

FIG. 5 is a block diagram of an exemplary processor-based system that may include an adaptive voltage modulation circuit for reducing supply voltage drops in FIGS. 1, 3, and 4; and

fig. 6 is a block diagram of an exemplary wireless communication device including Radio Frequency (RF) components, wherein the wireless communication device includes an adaptive voltage modulation circuit for reducing supply voltage drops in fig. 1, 3, and 4.

Detailed Description

Referring now to the drawings, several exemplary aspects of the present invention are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

Fig. 1 illustrates an exemplary adaptive voltage modulation circuit 100 that detects whether a supply voltage (V) provided to a load circuit 102 drops below a reduced threshold Voltage (VDT) (i.e., detects a supply voltage drop). As used herein, the supply voltage is dropped to a temporary drop or decrease to a particular voltage level that is below the supply voltage (V) provided to the load circuit 102 by the power supply. In response to detecting the supply voltage drop, the adaptive voltage modulation circuit 100 adjusts the duration for the supply voltage drop provided to the load circuit 102 to mitigate the effect of the supply voltage drop. In addition, the adaptive voltage modulation circuit 100 counts a length of time (e.g., a number of reference clock cycles) that the load circuit 102 experiences a supply voltage drop, and increases the supply voltage (V) in response to the count exceeding an upper threshold. Conversely, the adaptive voltage modulation circuit 100 decreases the supply voltage in response to the count being less than the lower threshold at the end of the defined period of time. As described in more detail below, adjusting the supply voltage (V) in this manner may reduce the occurrence of supply voltage drops and avoid setting the supply voltage (V) higher than required by the load circuit 102. Thus, the adaptive voltage modulation circuit 100 mitigates the effects of supply voltage drop and also reduces the occurrence of supply voltage drop while minimizing power consumption of the load circuit 102.

In this regard, with continued reference to fig. 1, the adaptive voltage modulation circuit 100 employs a supply voltage drop detection and mitigation circuit 104 that includes a detection circuit 106 configured to generate a drop detection signal 108 in an active state in response to the supply voltage (V) being less than a drop threshold Voltage (VDT). As described in more detail below, the detection circuit 106 may be implemented as a comparator circuit using an operational amplifier configured to generate a drop detection signal 108 based on a comparison of a supply voltage (V) and a drop threshold Voltage (VDT). Alternatively, the detection circuit 106 may be implemented using a Critical Path Voltage Monitoring (CPVM) circuit configured to generate the droop detection signal 108 in response to detecting that noise associated with the supply voltage (V) is sufficiently large to drop the supply voltage (V) below the droop threshold Voltage (VDT). The supply voltage drop detection and mitigation circuit 104 also includes a clock adjustment circuit 110 configured to adjust the load clock signal CLK LD provided to the load circuit 102 in response to the drop detection signal 108. For example, the clock adjustment circuit 110 may reduce the frequency of the load clock signal CLK _ LD to a frequency less than the root clock signal CLK _ RT received by the clock adjustment circuit 110 in response to the drop detection signal 108 transitioning to the active state (i.e., in response to detecting the supply voltage drop). As described in more detail below, the root clock signal CLK _ RT may be a system-level clock signal generated by system circuitry, such as a phase-locked loop (PLL).

With continued reference to fig. 1, reducing the frequency of the load clock signal CLK _ LD reduces the frequency at which the load circuit 102 operates, which may reduce or avoid timing glitches caused by supply voltage drops. As a non-limiting example, the clock adjustment circuit 110 in this aspect reduces the frequency of the load clock signal CLK _ LD by splitting the root clock signal CLK _ RT. In other aspects, the clock adjustment circuit 110 may adjust the root clock signal CLK _ RT in other ways, such as (but not limited to) gating the root clock signal CLK _ RT or switching a clock multiplexer to select different frequencies for the load clock signal CLK _ LD. In addition, the clock adjustment circuit 110 may also increase the frequency of the load clock signal CLK _ LD to be substantially equal to the frequency of the root clock signal CLK _ RT in response to the drop detection signal 108 transitioning to an inactive state (i.e., in response to detecting the absence of a supply voltage drop).

With continued reference to fig. 1, the adaptive voltage modulation circuit 100 also employs a supply voltage adjustment circuit 112 that includes a counter circuit 114 configured to count a number of cycles of the reference clock signal CLK REF during which the supply voltage (V) is less than the reduced threshold Voltage (VDT). In particular, the counter circuit 114 is configured to increase the count CNT in response to each cycle of the reference clock signal CLK _ REF, with the fall detection signal 108 in an active state. As used herein, a reference clock signal CLK _ REF, which may be a clock signal having a fixed frequency (e.g., twenty (20) megahertz (MHz)), is separate and distinct from the root clock signal CLK _ RT and the load clock signal CLK _ LD. Alternatively, the reference clock signal CLK _ REF may be the same as the root clock signal CLK _ RT. Additionally, the counter circuit 114 may be configured to increment the count CNT for a defined period as measured by the reference clock signal CLK _ REF and reset the count CNT to an initial count value at the end of the defined period. In this way, the count CNT indicates a percentage of the defined period of time that the load circuit 102 experiences a supply voltage drop, and thus is a percentage of the time that the load circuit 102 operates at a reduced frequency of the load clock signal CLK _ LD.

With continued reference to fig. 1, the supply voltage adjustment circuit 112 also includes a voltage-adjust-up circuit 116 configured to generate a voltage-adjust-up signal 118 in an active state in response to the count CNT being greater than an adjust-up threshold (AU). The voltage-adjust-high circuit 116 may also be configured to generate the voltage-adjust-high signal 118 in an inactive state in response to the count CNT being less than an adjust-high threshold (AU) at the end of the defined period. In addition, supply voltage adjustment circuit 112 includes a voltage-down circuit 120 configured to generate a voltage-down signal 122 in an active state in response to count CNT being less than a down threshold (AD) at the end of the defined period. The voltage-reduction circuit 120 may also be configured to generate the voltage-reduction signal 122 in an inactive state in response to the count CNT being greater than a reduction threshold (AD) at the end of the defined period. In other words, the voltage-ramp-up signal 118 is generated in an active state in response to the count CNT exceeding a ramp-up threshold (AU) at any time during the defined period. Conversely, the voltage-down signal 122 is generated in an active state in response to the count CNT being less than a down threshold (AD) at the end of the defined period.

With continued reference to fig. 1, the voltage-up signal 118 may also be generated in an inactive state in response to an acknowledgement signal from the supply voltage controller circuit 124 indicating that the supply voltage (V) has been adjusted up, wherein the acknowledgement signal also resets the count CNT. In addition, a voltage-down signal 122 may also be generated in an inactive state in response to an acknowledgement signal from the supply voltage controller circuit 124 indicating that the supply voltage (V) has been adjusted down, wherein the acknowledgement signal also resets the count CNT.

With continued reference to fig. 1, the adaptive voltage modulation circuit 100 also includes a supply voltage controller circuit 124 configured to increase the supply voltage (V) provided to the load circuit 102 in response to the voltage-adjust-up signal 118. In addition, the supply voltage controller circuit 124 is configured to reduce the supply voltage (V) provided to the load circuit 102 in response to the voltage-down signal 122. In this example, the supply voltage controller circuit 124 adjusts the supply voltage (V) by instructing the power management circuit 126 to change the supply voltage (V) to a particular level. In this manner, the supply voltage (V) may be increased in response to an amount of time (also referred to as a "percent adjust") by which the frequency of the load clock signal CLK _ LD is reduced over a defined period of time. Thus, the adaptive voltage modulation circuit 100 increases the supply voltage (V) (e.g., a higher adjustment percentage) in response to the load circuit 102 experiencing the supply voltage drop for a higher percentage of the defined period of time, and decreases the supply voltage (V) (e.g., a lower adjustment percentage) in response to the load circuit 102 experiencing the supply voltage drop for a lower percentage of the defined period of time. In some aspects, the adaptive voltage modulation circuit 100 may increase or decrease the supply voltage (V) as described above by a predefined voltage step. As a non-limiting example, if the unregulated supply voltage (V) is equal to 800 millivolts (mV), the adaptive voltage modulation circuit 100 may increase the supply voltage (V) by a predefined step of ten (10) mV or decrease the supply voltage (V) by a predefined step of 10 mV.

In this regard, the adaptive voltage modulation circuit 100 increases the supply voltage (V) in response to the load circuit 102 operating in response to a higher load current demand, causing the supply voltage drop to exceed the drop threshold Voltage (VDT) for a relatively longer duration. Conversely, the adaptive voltage modulation circuit 100 decreases the supply voltage (V) in response to the load circuit 102 operating corresponding to a lower load current demand, causing the supply voltage drop to exceed the drop threshold Voltage (VDT) for a relatively short duration. Adjusting the supply voltage (V) based on the operating requirements and the associated supply voltage drop magnitude and duration of the load circuit 102 may reduce the occurrence of the supply voltage drop and avoid setting the supply voltage (V) higher than required by the load circuit 102. For example, the adaptive voltage modulation circuit 100 increases the supply voltage (V) in response to determining that the load circuit 102 has a higher load current demand, but decreases the supply voltage (V) in response to determining that the load circuit 102 has a lower load current demand. Accordingly, the adaptive voltage modulation circuit 100 may reduce the occurrence of supply voltage drops, which reduces the amount of time the load circuit 102 operates at a reduced frequency, while also minimizing the power consumption of the load circuit 102.

With continued reference to fig. 1, as a non-limiting example, the adaptive voltage modulation circuit 100 is employed for a defined period of 1000 cycles. Further, the initial count value of the count CNT is set to zero (0), the turn-up threshold (AU) is set to thirty (30), and the turn-down threshold (AD) is set to ten (10). In response to the down detection signal 108 being active between cycle one (1) and cycle ten (10) of the defined period, the counter circuit 114 increases the count CNT to ten (10), and the clock adjustment circuit 110 decreases the frequency of the load clock signal CLK _ LD. Between cycle eleven (11) and cycle thirty (30) of the defined period, the drop detection signal 108 is in an inactive state, indicating that there is no supply voltage drop. However, between cycles thirty-one (31) and fifty-two (52) of the defined period, the down detection signal 108 is active, which causes the counter circuit 114 to increase the count CNT to thirty-one (31). In response to the count CNT being greater than an increase threshold (AU) of thirty (30), the voltage increase circuit 116 generates the voltage increase signal 118 in an active state, thus causing the supply voltage controller circuit 124 to increase the supply voltage (V) provided to the load circuit 102, thereby reducing the occurrence of a supply voltage drop.

Continuing with reference to fig. 1, as an alternative, non-limiting example, the fall detection signal 108 is active only between cycles twenty (20) and twenty-five (25) of the defined period. In this way, the count CNT is only increased to the value five (5) during 1000 cycles of the defined period. At the end of the defined period, voltage-down circuit 120 generates voltage-down signal 122 in an active state in response to count CNT being less than a turn-down threshold (AD) ten (10). Accordingly, the supply voltage controller circuit 124 reduces the supply voltage (V), thus minimizing power consumption of the load circuit 102.

Fig. 2 illustrates an exemplary process 200 that may be employed by the adaptive voltage modulation circuit 100 in fig. 1 to adaptively modulate the supply voltage (V) to reduce supply voltage drop and minimize power consumption. The process 200 includes the detection circuit 106 generating the fall detection signal 108 in an active state in response to the supply voltage (V) being less than the fall threshold Voltage (VDT) (block 202). The process 200 also includes the clock adjustment circuit 110 adjusting the load clock signal CLK _ LD provided to the load circuit 102 in response to the fall detection signal 108 (block 204). Additionally, the process 200 includes the counter circuit 114 incrementing the count CNT in response to each cycle of the reference clock signal CLK _ REF, with the fall detection signal 108 in an active state (block 206). The process 200 also includes the voltage-adjust-up circuit 116 generating the voltage-adjust-up signal 118 in an active state in response to the count CNT being greater than the adjust-up threshold (AU) (block 208). Further, the process 200 includes the voltage-reduction circuit 120 generating the voltage-reduction signal 122 in an active state in response to the count CNT being less than a reduction threshold (AD) at the end of the defined period as measured by the reference clock signal CLK _ REF (block 210). The process 200 also includes the supply voltage controller circuit 124 increasing the supply voltage (V) provided to the load circuit 102 in response to the voltage-adjust-up signal 118 being active (block 212). The process 200 also includes the supply voltage controller circuit 124 reducing the supply voltage (V) provided to the load circuit 102 in response to the voltage-down signal 122 being active (block 214). Adjusting the supply voltage (V) to meet the operational requirements of the load circuit 102 using the process 200 reduces the amount of time the load circuit 102 operates at a reduced frequency while minimizing the power consumption of the load circuit 102.

Fig. 3 illustrates another exemplary adaptive voltage modulation circuit 300 for reducing supply voltage drop and minimizing power consumption. The adaptive voltage modulation circuit 300 includes certain components in common with the adaptive voltage modulation circuit 100 of fig. 1, as indicated by the common reference numerals between fig. 1 and 3, and thus will not be described again herein.

Referring to fig. 3, an adaptive voltage modulation circuit 300 employs supply voltage drop detection and mitigation circuitry 302 that includes detection circuitry that may be implemented as comparator circuitry 106'. In particular, the comparator circuit 106' is configured to generate the drop detection signal 108' based on performing a comparison of the supply voltage (V) and the drop threshold voltage (VDT '). The reduced threshold voltage (VDT') in this aspect is determined based on a digital threshold (DV) stored in a reduced threshold register 304 included in the supply voltage drop detection and mitigation circuit 302. The digital threshold (DV) is a digital representation of a reduced threshold voltage (VDT'), where the reduced threshold register 304 is configured to provide the digital threshold (DV) on an output node 306 of the reduced threshold register 304. In addition, the supply voltage drop detection and mitigation circuit 302 includes a digital-to-analog converter (DAC)308 to convert the digital threshold (DV) to a reduced threshold voltage (VDT ') used by the comparator circuit 106'. In particular, the DAC 308 includes an input node 310 electrically coupled to the output node 306 of the drop threshold register 304, and an output node 312 on which the DAC 308 is configured to provide a drop threshold voltage (VDT').

With continued reference to fig. 3, the comparator circuit 106 'includes a first input node 314 electrically coupled to the output node 312 of the DAC 308 for receiving the reduced threshold voltage (VDT'), and a second input node 316 for receiving the supply voltage (V). The comparator circuit 106' also includes an output node 318 on which the comparator circuit 106' is configured to provide the fall detection signal 108 '. More specifically, in response to the falling threshold voltage (VDT ') being greater than the supply voltage (V), the falling detection signal 108' generated by the comparator circuit 106' transitions to an active state. In other words, in response to detecting a supply voltage drop, the drop detection signal 108' is active. In addition, in response to the falling threshold voltage (VDT ') being less than the supply voltage (V), the falling detection signal 108' generated by the comparator circuit 106' transitions to an inactive state. In other words, in response to detecting that there is currently no supply voltage drop, the drop detection signal 108' is in an inactive state.

With continued reference to fig. 3, the supply voltage drop detection and mitigation circuit 302 also includes a clock adjustment circuit 110 configured to adjust the load clock signal CLK _ LD 'provided to the load circuit 102 in response to the drop detection signal 108'. In particular, the clock adjustment circuit 110 includes a first input node 320 that receives a root clock signal CLK _ RT' generated in this regard by a Phase Locked Loop (PLL) 322. The clock adjustment circuit 110 also includes a second input node 324 electrically coupled to the output node 318 of the comparator circuit 106 'such that the second input node 324 receives the fall detection signal 108'. In addition, the clock adjustment circuit 110 includes an output node 326 on which the clock adjustment circuit 110 is configured to provide the load clock signal CLK _ LD'. As previously described above, adjusting the load clock signal CLK _ LD' in response to detecting the supply voltage drop may reduce or avoid timing glitches caused by the supply voltage drop while other portions of the adaptive voltage modulation circuit 300 adjust the supply voltage (V) to reduce the occurrence of the supply voltage drop.

With continued reference to fig. 3, the adaptive voltage modulation circuit 300 also employs a supply voltage adjustment circuit 328 that includes a counter circuit 114 'configured to count a number of periods of the reference clock signal CLK REF during which the supply voltage (V) is less than the reduced threshold voltage (VDT'). In this aspect, the counter circuit 114 'functions as a sixteen (16) bit counter circuit 114'. The counter circuit 114' includes a first input node 330, the counter circuit 114' being configured to receive the fall detection signal 108' thereon. The counter circuit 114 'also includes a second input node 332, the counter circuit 114' being configured to receive a reference clock signal CLK _ REF thereon. The counter circuit 114' is configured to maintain two separate counts, an UP count UP CNT and a down count DN CNT, each of which corresponds to a particular defined period of time, rather than maintaining a single count CNT as described with reference to fig. 1. More specifically, the counter circuit 114 'increases the UP count UP _ CNT in response to each cycle of the reference clock signal CLK _ REF, with the down detection signal 108' being active during the UP period and resetting the count CNT to the initial count value at the end of the UP period. In addition, the counter circuit 114 'increases the down count DN _ CNT in response to each cycle of the reference clock signal CLK _ REF, wherein the down detection signal 108' is active during the down cycle and resets the count CNT to the initial count value at the end of the down cycle.

With continued reference to fig. 3, employing separate ramp UP and ramp down counts UP _ CNT, DN _ CNT corresponding to separate ramp UP and ramp down periods allows this aspect to assign higher weights to higher performance or greater power savings. For example, applying a higher weight to higher performance, it may be defined that the turn-up period is shorter in duration than the turn-down period, so that the decision to increase the supply voltage (V) is evaluated more frequently than the decision to decrease the supply voltage (V). Conversely, applying a higher weight to greater power savings, it may be defined that the turn-down period is shorter in duration than the turn-up period, so that decisions to decrease the supply voltage (V) are evaluated more frequently than decisions to increase the supply voltage (V). To convey the count UP and down UP, DN _ CNT, the counter circuit 114 'includes a first output node 334(1), the counter circuit 114' configured to provide an UP count signal 336(1) thereon indicating the count UP _ CNT is turned UP; and a second output node 334(2), on which the counter circuit 114' is configured to provide a down count signal 336(2) indicative of a down count DN CNT.

With continued reference to fig. 3, to adjust the supply voltage (V) based on the turn-down and turn-UP counts UP _ CNT, DN _ CNT, the supply voltage adjustment circuit 328 also includes a turn-UP register 338 and a turn-down register 340. In particular, the up register 338 is configured to store an up threshold (AU) while the down register 340 is configured to store an down threshold (AD). The ramp-up register 338 includes an output node 342 on which the ramp-up register 338 is configured to provide a ramp-up threshold (AU). Similarly, the lower register 340 includes an output node 344 on which the lower register 340 is configured to provide a lower threshold (AD). As a non-limiting example, the up and down threshold values (AU), (AD) may be determined and stored in the up and down registers 338, 340 during testing of the corresponding chip.

With continued reference to fig. 3, the supply voltage adjustment circuit 328 also includes a voltage-adjust-UP circuit 116 'configured to generate a voltage-adjust-UP signal 118' in response to the adjusted-UP count UP _ CNT being greater than an adjusted-UP threshold (AU). Specifically, the voltage-up circuit 116 'includes a first input node 346 electrically coupled to the first output node 334(1) of the counter circuit 114' to receive the up-count signal 336 (1). The voltage-adjust-up circuit 116' also includes a second input node 348 electrically coupled to the output node 342 of the adjust-up register 338 to receive an adjust-up threshold (AU). The voltage-adjust-up circuit 116' further includes an output node 350, the voltage-adjust-up circuit 116' configured to provide a voltage-adjust-up signal 118' on the output node 350. Specifically, the voltage-UP signal 118' is initially in an inactive state, with the voltage-UP circuit 116' generating the voltage-UP signal 118' in an active state in response to the UP-count UP _ CNT being greater than the UP-threshold (AU) at any time during the defined period, as indicated by the UP-count signal 336 (1). In addition, the voltage-UP circuit 116 'resets the voltage-UP signal 118' to the inactive state in response to the UP count UP _ CNT being less than the UP threshold (AU) at the end of the UP period as indicated by the UP count signal 336 (1). In this manner, if the load circuit 102 experiences a supply voltage drop for a greater percentage of the turn-up period, the voltage turn-up signal 118' is active, which indicates that the supply voltage (V) should be increased to reduce or avoid the supply voltage drop. Further, the voltage-UP signal 118' may be generated in an inactive state in response to a reply signal from the supply voltage controller circuit 124 indicating that the supply voltage (V) has been turned down, wherein the reply signal also resets the count UP _ CNT.

With continued reference to fig. 3, the supply voltage adjust-up circuit 328 also includes a voltage-down circuit 120 'configured to generate a down signal 122' in response to the down count DN _ CNT being less than a down threshold (AD) at the end of the down period. Specifically, the voltage-down circuit 120 'includes a first input node 352 electrically coupled to the second output node 334(2) of the counter circuit 114' to receive the down-count signal 336 (2). The voltage down circuit 120' also includes a second input node 354 electrically coupled to the output node 344 of the down register 340 to receive a down threshold (AD). The voltage-reduction circuit 120' further includes an output node 356, the voltage-reduction circuit 120' being configured to provide a voltage-reduction signal 122' on the output node 356. Specifically, the voltage-down signal 122' is initially in an inactive state, where the voltage-down circuit 120' generates the voltage-down signal 122' in an active state in response to the down count DN _ CNT being less than the down threshold (AD) at the end of the down period as indicated by the down count signal 336 (2). In addition, the voltage-down circuit 120 'generates the voltage-down signal 122' in the inactive state in response to the down count DN _ CNT being greater than the down threshold (AD) at the end of the down period as indicated by the down count signal 336 (2). In this manner, if the load circuit 102 does not experience a supply voltage drop within a certain percentage of the turn-down period, the voltage turn-down signal 122' is in an active state, which indicates that the supply voltage (V) may be reduced to minimize power consumption by the load circuit 102. In addition, a voltage-down signal 122' in an inactive state may be generated in response to an acknowledgement signal from the supply voltage controller circuit 124 indicating that the supply voltage (V) has been pulled up, wherein the acknowledgement signal also resets the pull-down count DN _ CNT.

With continued reference to fig. 3, the adaptive voltage modulation circuit 300 also includes a supply voltage controller circuit 124 configured to adjust the supply voltage (V) by instructing the power management circuit 126 to change the supply voltage (V) to a particular level. As previously described, the supply voltage controller circuit 124 is configured to increase the supply voltage (V) provided to the load circuit 102 in response to the voltage adjust-up signal 118' being active. In addition, the supply voltage controller circuit 124 is configured to reduce the supply voltage (V) provided to the load circuit 102 in response to the voltage-down signal 122' being active. As a non-limiting example, in some aspects, the supply voltage controller circuit 124 may include a finite state machine to determine whether to increase or decrease the supply voltage (V). Such aspects may also include multiple instances of the supply voltage reduction circuit 328, each of which corresponds to a different instance of the load circuit 102, the supply voltage reduction circuit 328 in communication with the supply voltage controller circuit 124. Further, other aspects of the supply voltage controller circuit 124 may include a controller circuit configured to run firmware to perform the functions described above. In this manner, the supply voltage controller circuit 124 may arbitrate between the requirements of each of the supply voltage down circuits 328 and adjust the supply voltage (V) according to the requirements of the chip employing multiple instances of the load circuit 102.

Fig. 4 illustrates another exemplary adaptive voltage modulation circuit 400 for reducing supply voltage drop and minimizing power consumption. The adaptive voltage modulation circuit 400 includes certain components in common with the adaptive voltage modulation circuits 100 and 300 of fig. 1 and 3, which are shown by common reference numerals in fig. 1, 3, and 4, and thus will not be described again herein.

Referring to fig. 4, an adaptive voltage modulation circuit 400 employs supply voltage drop detection and mitigation circuitry 402 that includes detection circuitry that may be implemented as Critical Path Voltage Monitoring (CPVM) circuitry 106 ". The CPVM circuit 106 "is configured to generate a drop detection signal 108" in response to detecting that noise associated with the supply voltage (V) is large enough to reduce the supply voltage (V) below a drop threshold voltage (VDT "). As a non-limiting example, the CPVM circuit 106 "is powered by a supply voltage (V) on the power input 404 and includes flip-flop circuits 406, 408. The flip-flop circuit 406 is clocked by the root clock signal CLK _ RT' and includes an output node 410, the flip-flop circuit 406 being configured to provide an output signal 412 on the output node 410. Output node 410 is electrically coupled to input node 414 of buffer 416. The buffer 416 has an output node 418 electrically coupled to an input node 420 of an inverter 422, wherein the output node 424 of the inverter 422 is electrically coupled to an input node 426 of an AND-based gate 428 (e.g., AND gate 428). Additionally, an enable signal 430 is provided to a second input node 432 of the AND gate 428, AND an output node 434 of the AND gate 428 is electrically coupled to an input node 436 of the flip-flop circuit 406. In this manner, the flip-flop circuit 406 acts as a switched flip-flop circuit in response to the enable signal 430. More specifically, output signal 412 switches between a logic ' 1 ' value and a logic ' 0' value at a frequency approximately equal to one-half (1/2) of the frequency of the root clock signal CLK _ RT '. Additionally, the output node 418 of the buffer 416 is electrically coupled to a first input node 438 of an XOR-based gate 440 (e.g., XOR gate 440). First path 442 is generated in this manner using flip-flop circuit 406 and buffer 416. In particular, the first path 442 serves as a controlled reference path designed to provide a stable value to the first input node 438 of the XOR gate 440 even during a maximum amount of supply voltage drop.

With continued reference to fig. 4, the flip-flop circuit 408 is also clocked by the root clock signal CLK _ RT' AND includes an input node 444 electrically coupled to the output node 434 of the AND gate 428 AND an output node 446 on which the flip-flop circuit 408 is configured to provide an output signal 448. In this manner, flip-flop circuit 408 is configured to function as a two-state flip-flop circuit, with output signal 448 switching between logic ' 1 ' and logic ' 0' values at a frequency substantially equal to one-half the frequency of the root clock signal CLK _ RT ' (1/2). The output node 446 is electrically coupled to an input node 450 of a buffer 452(1), which is a first buffer 452(1) of a plurality of serially connected buffers 452(1) through 452 (N). In this example, the number N of buffers 452(1) through 452(N) is set to represent a delay value associated with a reduced threshold voltage (VDT "). Further, an output node 454 of buffer 452(N) (e.g., last buffer 452(N)) is electrically coupled to a second input node 456 of XOR gate 440.

With continued reference to FIG. 4, the output signal 458 of the XOR gate 440, which represents whether a supply voltage drop is present, is provided on the output node 460 of the XOR gate 440. As a non-limiting example, in an exemplary cycle of the root clock signal CLK _ RT ', flip-flop circuit 406 receives a logic ' 1 ' value, causing first path 442 to provide a logic ' 1 ' value to first input node 438 of XOR gate 440. In addition, flip-flop circuit 408 receives a logic '1' value. In this regard, where the supply voltage (V) has a sufficiently high value, the second path 462 corresponding to the flip-flop circuit 408 and the buffers 452(1) through 452(N) may provide a logic '1' value to the second input node 456 according to the delays corresponding to the buffers 452(1) through 452 (N). In response to both the first input node 438 and the second input node 456 receiving a logic '1' value, the output signal 458 has a logic '0' value, indicating that there is no supply voltage drop. However, in the event that the supply voltage (Vd) drops below the reduced threshold voltage (VDT "), the second path 462 is designed to have a delay corresponding to buffers 452(1) -452 (N), producing a logic '0' value in this example. Accordingly, the clock period based on the root clock signal CLK _ RT ' temporarily provides a logic ' 0' value to the second input node 456. Thus, in response to the second input node 456 receiving a logic '0' value while the first input node 438 receives a logic '1' value, the output signal 458 has a logic '1' value, which indicates that a supply voltage drop is present. As another non-limiting example, on subsequent cycles of the root clock signal CLK _ RT ', flip-flop circuit 406 receives a logic ' 0' value such that first path 442 provides a logic ' 0' value to first input node 438 of XOR gate 440. The flip-flop circuit 408 also receives a logic '0' value, wherein the second path 462 provides the logic '0' value to the second input node 456 without the supply voltage (V) falling below the reduced threshold voltage (VDT "), resulting in the output signal 458 having a logic '0' value indicating that there is no supply voltage drop. However, in the event that the supply voltage (V) drops below the falling threshold voltage (VDT "), the second path 462 provides a logical '1' value to the second input node 456, resulting in the output signal 458 having a logical '1' value indicating the presence of a supply voltage drop.

With continued reference to fig. 4, the CPVM circuit 106 ″ also includes a flip-flop circuit 464 that includes an input node 466 configured to receive the output signal 458, and that is clocked by the root clock signal CLK _ RT'. In addition, the flip-flop circuit 464 includes an output node 468, the flip-flop circuit 464 configured to generate a fall detection signal 108 "thereon based on the output signal 458. In particular, the delay corresponding to the second path 462 plus the delay corresponding to the XOR gate 440 is designed to miss the setup time of the flip-flop circuit 464 when the supply voltage (V) falls below the drop threshold voltage (VDT "), causing the drop detection signal 108" to indicate a supply voltage drop. The drop detection signal 108 "is used by the clock adjustment circuit 110 and the supply voltage adjustment circuit 328 as previously described. In this manner, the CPVM circuit 106 "may be employed to detect a supply voltage drop based on the timing-based determination described above rather than the voltage comparison determination described in fig. 3.

The elements described herein are sometimes referred to as means for performing a specified function. In this regard, the detection circuit 106 illustrated in fig. 1 is an example of a "means for generating a drop detection signal in an active state in response to the supply voltage being less than the drop threshold voltage". The detection circuit 106 illustrated in FIG. 1 is also an example of a "means for performing a comparison of a supply voltage to a reduced threshold voltage" and a "means for generating a reduced detection signal in an inactive state in response to the reduced threshold voltage being less than the supply voltage". The clock adjustment circuit 110 illustrated in fig. 1 is an example of a "means for adjusting a load clock signal provided to a load circuit in response to a fall detection signal". The clock adjustment circuit 110 illustrated in fig. 1 is also an example of a "means for reducing the frequency of the load clock signal in response to the fall detection signal transitioning to an active state such that the frequency of the load clock signal is lower than the frequency of the root clock signal". The clock adjustment circuit 110 illustrated in fig. 1 is also an example of a "means for increasing the frequency of the load clock signal in response to the drop detect signal transitioning to an inactive state to make the frequency of the load clock signal equal or substantially equal to the frequency of the root clock signal". The counter circuit 114 illustrated in fig. 1 is an example of "means for increasing a count in response to each cycle of a reference clock signal with a falling detection signal in an active state". The counter circuit 114 illustrated in fig. 1 is also an example of a "means for resetting the count to an initial count value in response to the end of the defined period of time".

Additionally, the voltage-adjust-high circuit 116 illustrated in FIG. 1 is an example of a "means for generating a voltage-adjust-high signal in an active state in response to the count being greater than the adjust-high threshold". The voltage-adjust-high circuit 116 illustrated in FIG. 1 is also an example of a "means for generating a voltage-adjust-high signal in an inactive state in response to the count being less than the adjust-high threshold". The voltage-reduction circuit 120 illustrated in fig. 1 is an example of a "means for generating a voltage-reduction signal in an active state in response to the count being less than a reduction threshold at the end of a defined period as measured by a reference clock signal". The voltage-reduction circuit 120 illustrated in FIG. 1 is also an example of a "means for generating a voltage-reduction signal in an inactive state in response to the count being greater than the reduction threshold". The supply voltage controller circuit 124 illustrated in fig. 1 is an example of a "means for increasing the supply voltage provided to the load circuit in response to the voltage-up signal being active". The supply voltage controller circuit 124 illustrated in fig. 1 is also an example of a "means for reducing the supply voltage provided to the load circuit in response to the voltage-down signal being active". The DAC 308 illustrated in FIG. 3 is an example of a "means for generating a reduced threshold voltage based on a digital threshold signal, where the digital threshold signal is a digital representation of a reduced threshold voltage of a register stored in the adaptive voltage modulation circuit".

An adaptive voltage modulation circuit for adjusting a supply voltage to reduce a supply voltage drop and minimize power consumption according to aspects disclosed herein may be provided or integrated in any processor-based device. Examples include, but are not limited to, set top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smart phones, Session Initiation Protocol (SIP) phones, tablet computers, tablet handsets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, Personal Digital Assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, Digital Video Disc (DVD) players, portable digital video players, portable audio devices, and the like, Car, vehicle subassembly, avionics system, unmanned aerial vehicle and many rotor crafts.

In this regard, fig. 5 illustrates an example of a processor-based system 500 that may use the adaptive voltage modulation circuits 100, 300, and 400 illustrated in fig. 1, 3, and 4, respectively. In this example, the processor-based system 500 includes one or more Central Processing Units (CPUs) 502, each including one or more processors 504. The CPU502 may have a cache memory 506 coupled to the processor 504 for fast access to temporarily stored data. The CPU502 is coupled to a system bus 508, and may couple master and slave devices included in the processor-based system 500 to each other. As is well known, the CPU502 communicates with these other devices by exchanging address, control, and data information over the system bus 508. For example, the CPU502 may communicate a bus transaction request to the memory controller 510 as an example of a slave device. Although not illustrated in fig. 5, multiple system buses 508 may be provided, with each system bus 508 constituting a different mesh architecture.

Other masters and slaves may be connected to the system bus 508. As illustrated in fig. 5, these devices may include, for example, a memory system 512, one or more input devices 514, one or more output devices 516, one or more network interface devices 518, and one or more display controllers 520. Input device 514 may include any type of input device including, but not limited to, input keys, switches, a speech processor, etc. The output devices 516 may include any type of output device, including but not limited to audio indicators, visual indicators, other visual indicators, and the like. Network interface device 518 may be any device configured to allow the exchange of data from and to network 522. Network 522 may be any type of network including, but not limited to, a wired or wireless network, a private or public network, a Local Area Network (LAN), a Wireless Local Area Network (WLAN), a Wide Area Network (WAN), BLUETOOTH^TMNetworks and the internet. The network interface device 518 may be configured to support any type of communication protocol desired. Memory system 512 may include one or more memory units 524(0) -524 (M).

The CPU502 may also be configured to access a display controller 520 via the system bus 508 to control information sent to one or more displays 526. Display controller 520 sends information to display 526 for display via one or more video processors 528, which process the information to be displayed into a format suitable for display 526. Display 526 may include any type of display including, but not limited to, a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), a plasma display, a Light Emitting Diode (LED) display, and the like.

Fig. 6 illustrates an example of a wireless communication device 600 that may include Radio Frequency (RF) components, where the wireless communication device 600 may include the adaptive voltage modulation circuits 100, 300, and 400 illustrated in fig. 1, 3, and 4, respectively. In this regard, the wireless communication device 600 may be provided in an Integrated Circuit (IC) 602. As an example, the wireless communication device 600 may include or be provided in any of the above-mentioned devices. As shown in fig. 6, the wireless communication device 600 includes a transceiver 604 and a data processor 606. The data processor 606 may include memory (not shown in FIG. 6) to store data and program code. The transceiver 604 includes a transmitter 608 and a receiver 610 that support bi-directional communication. In general, wireless communication device 600 may include any number of transmitters and/or receivers for any number of communication systems and frequency bands. All or a portion of the transceiver 604 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed signal ICs, and the like.

The transmitter or receiver may be implemented with a super heterodyne architecture or a direct conversion architecture. In the super-heterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, e.g., from RF to an Intermediate Frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In a direct conversion architecture, the signal is frequency converted between RF and baseband in one stage. The super heterodyne and direct conversion architectures may use different circuit blocks and/or have different requirements. In the wireless communication device 600 in fig. 6, the transmitter 608 and receiver 610 are implemented with a direct conversion architecture.

In the transmit path, data processor 606 processes data to be transmitted and provides I and Q analog output signals to transmitter 608. In the exemplary wireless communication device 600, the data processor 606 includes DACs 612(1), 612(2) for converting digital signals generated by the data processor 606 into I and Q analog output signals (e.g., I and Q output currents for further processing).

In transmitter 608, low pass filters 614(1), 614(2) filter the I and Q analog output signals, respectively, to remove undesirable signals resulting from previous digital-to-analog conversion. Amplifiers (AMP)616(1), 616(2) amplify the signals from lowpass filters 614(1), 614(2), respectively, and provide I and Q baseband signals. Up-converter 618 up-converts the I and Q baseband signals using I and Q Transmit (TX) Local Oscillator (LO) signals from TX LO signal generator 622 through mixers 620(1), 620(2) to provide up-converted signal 624. Filter 626 filters upconverted signal 624 to remove undesired signals resulting from the frequency upconversion as well as noise in the receive frequency band. A Power Amplifier (PA)628 amplifies the up-converted signal 624 from the filter 626 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 630 and transmitted via an antenna 632.

In the receive path, an antenna 632 receives signals through the base stations and provides a receive RF signal, which is routed through a duplexer or switch 630 and provided to a Low Noise Amplifier (LNA) 634. Duplexer or switch 630 is designed to operate with a particular Receive (RX) to TX duplexer frequency spacing to separate the RX signal from the TX signal. The received RF signal is amplified by LNA 634 and filtered by filter 636 to obtain the desired RF input signal. Down-conversion mixers 638(1), 638(2) mix the output of filter 636 provided with the I and Q RX LO signals (i.e., LO _ I and LO _ Q) from RX LO signal generator 640 to generate I and Q baseband signals. The I and Q baseband signals are amplified by Amplifiers (AMP)642(1), 642(2) and further filtered by low pass filters 644(1), 644(2) to obtain I and Q analog input signals, which are provided to data processor 606. In this example, the data processor 606 includes analog-to-digital converters (ADCs) 646(1), 646(2) for converting the I and Q analog input signals to digital signals for further processing by the data processor 606.

In wireless communication device 600 in fig. 6, TX LO signal generator 622 generates I and QTX LO signals for frequency up-conversion, while RX LO signal generator 640 generates I and Q RX LO signals for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. TX PLL circuit 648 receives timing information from data processor 606 and generates control signals used to adjust the frequency and/or phase of the I and Q TX LO signals from TX LO signal generator 622. Similarly, RX PLL circuit 650 receives timing information from data processor 606 and generates control signals used to adjust the frequency and/or phase of the I and Q RX LO signals from RX LO signal generator 640.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or combinations of both. As an example, the master and slave devices described herein may be used in any circuit, hardware component, Integrated Circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information as desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How this functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

Aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), registers, hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

It should also be noted that the operational steps described herein in any of the exemplary aspects are described to provide examples and discussion. The operations described may be performed in many different sequences than those illustrated. Moreover, the operations described in a single execution step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is understood that the operational steps illustrated in the flowcharts may be subject to numerous different modifications as will be apparent to those skilled in the art. Those of skill in the art would also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The previous description of the invention is provided to enable any person skilled in the art to make or use the present invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (30)

1. An adaptive voltage modulation circuit, comprising:

a supply voltage drop detection and mitigation circuit, comprising:

a detection circuit configured to generate a drop detection signal in an active state in response to a supply voltage provided to a load circuit being less than a drop threshold voltage, and to generate the drop detection signal in an inactive state in response to the supply voltage being greater than the drop threshold voltage; and

a clock adjustment circuit configured to decrease a frequency of a load clock signal provided to the load circuit in response to the falling detection signal transitioning to an active state and increase the frequency of the load clock signal in response to the falling detection signal transitioning to an inactive state;

a supply voltage adjustment circuit, comprising:

a counter circuit configured to increase a count in response to each cycle of a reference clock signal, wherein the fall detection signal is in an active state;

a voltage-adjust-high circuit configured to generate a voltage-adjust-high signal in an active state in response to the count being greater than an adjust-high threshold; and

a voltage-pull-down circuit configured to generate a voltage-pull-down signal in an active state in response to the count being less than a pull-down threshold at the end of a defined period of time as measured by the reference clock signal; and

a supply voltage controller circuit configured to:

increasing the supply voltage provided to the load circuit in response to the voltage-adjust-high signal being active; and

reducing the supply voltage provided to the load circuit in response to the voltage-down signal being active.

2. The adaptive voltage modulation circuit of claim 1, wherein:

the voltage-adjust-high circuit is further configured to generate the voltage-adjust-high signal in an inactive state in response to the count being less than the adjust-high threshold at the end of the defined period of time; and

the voltage-adjust-down circuit is further configured to generate the voltage-adjust-down signal in an inactive state in response to the count being greater than the adjust-down threshold at the end of the defined period of time.

3. The adaptive voltage modulation circuit of claim 1, wherein:

the voltage-adjust-high circuit is further configured to generate the voltage-adjust-high signal in an inactive state in response to an acknowledgement signal of the supply voltage controller circuit indicating that the supply voltage has been adjusted high; and

the voltage-reduction circuit is further configured to generate the voltage-reduction signal in an inactive state in response to an acknowledgement signal of the supply voltage controller circuit indicating that the supply voltage has been reduced.

4. The adaptive voltage modulation circuit of claim 3, wherein the counter circuit is configured to reset the count to an initial count value in response to the answer signal of the supply voltage controller circuit indicating that the supply voltage has been adjusted high.

5. The adaptive voltage modulation circuit of claim 3, wherein the counter circuit is configured to reset the count to an initial count value in response to the answer signal of the supply voltage controller circuit indicating that the supply voltage has been turned down.

6. The adaptive voltage modulation circuit of claim 1, wherein the counter circuit is configured to reset the count to an initial count value in response to the defined period of time ending.

7. The adaptive voltage modulation circuit of claim 1, wherein the counter circuit is further configured to:

during a turn-up period, increasing a turn-up count in response to each cycle of the reference clock signal, wherein the fall detection signal is active during the turn-up period; and

during a turn-down period, a turn-down count is incremented in response to each cycle of the reference clock signal, wherein the fall detection signal is active during the turn-down period.

8. The adaptive voltage modulation circuit of claim 7, wherein the counter circuit comprises:

a first input node;

a second input node;

a first output node; and

a second output node;

the counter circuit is configured to:

receiving the falling detection signal on the first input node of the counter circuit;

receiving the reference clock signal on the second input node of the counter circuit;

providing an up count signal on the first output node of the counter circuit indicative of the up count; and

providing a down count signal on the second output node of the counter circuit indicative of the down count.

9. The adaptive voltage modulation circuit of claim 8, wherein the supply voltage adjustment circuit further comprises:

a pull-up register comprising an output node and configured to:

storing the turn-up threshold; and

providing the ramp-up threshold on the output node of the ramp-up register; and

a pull-down register comprising an output node and configured to:

storing the turn-down threshold; and

providing the turn-down threshold on the output node of the turn-down register.

10. The adaptive voltage modulation circuit of claim 9, wherein:

the voltage-up circuit includes:

a first input node electrically coupled to the first output node of the counter circuit;

a second input node electrically coupled to the output node of the ramp-up register; and

an output node electrically coupled to a first input node of the supply voltage controller circuit;

the voltage-adjust-high circuit is configured to provide the voltage-adjust-high signal on the output node of the voltage-adjust-high circuit; and

the voltage reduction circuit includes:

a first input node electrically coupled to the second output node of the counter circuit;

a second input node electrically coupled to the output node of the turn-down register; and

an output node electrically coupled to a second input node of the supply voltage controller circuit;

the voltage reduction circuit is configured to provide the voltage reduction signal on the output node of the voltage reduction circuit.

11. The adaptive voltage modulation circuit of claim 1, wherein the supply voltage drop detection and mitigation circuit further comprises a threshold drop register comprising an output node and configured to:

a digital threshold signal stored as a digital representation of the reduced threshold voltage; and

providing the digital threshold signal on the output node of the drop threshold register.

12. The adaptive voltage modulation circuit of claim 11 wherein the supply voltage drop detection and mitigation circuit further comprises:

a digital-to-analog converter (DAC), comprising:

an input node electrically coupled to the output node of the degresh register; and

an output node;

the DAC is configured to provide the reduced threshold voltage on the output node of the DAC; and is

Wherein the detection circuit comprises a comparator circuit comprising:

a first input node electrically coupled to the output node of the DAC;

a second input node electrically coupled to the supply voltage; and

an output node;

the comparator circuit is configured to provide the fall detection signal on the output node of the comparator circuit, wherein:

the falling detection signal transitions to an active state in response to the falling threshold voltage being greater than the supply voltage; and is

The fall detection signal transitions to an inactive state in response to the fall threshold voltage being less than the supply voltage.

13. The adaptive voltage modulation circuit of claim 12 wherein the clock adjustment circuit comprises:

a first input node receiving a master clock signal;

a second input node electrically coupled to the output node of the comparator circuit; and

an output node;

the clock adjustment circuit is configured to provide the load clock signal on the output node of the clock adjustment circuit, wherein the load clock signal is based on the master clock signal.

14. The adaptive voltage modulation circuit of claim 13, wherein:

in response to the falling detect signal transitioning to the active state, lowering the frequency of the load clock signal below the frequency of the master clock signal by lowering the frequency of the load clock signal; and is

In response to the falling detection signal transitioning to the inactive state, the frequency of the load clock signal is made equal to the frequency of the master clock signal by increasing the frequency of the load clock signal.

15. The adaptive voltage modulation circuit of claim 1, wherein the detection circuit comprises a critical path voltage monitoring circuit powered by the supply voltage and including:

a first path comprising:

a first flip-flop circuit configured to be clocked by a master clock signal, comprising:

an input node; and

an output node;

a buffer, comprising:

an input node electrically coupled to the output node of the first flip-flop circuit; and

an output node;

an inverter, comprising:

an input node electrically coupled to the output node of the buffer; and

an output node;

an AND-based gate comprising:

a first input node electrically coupled to the output node of the inverter;

a second input node configured to receive an enable signal; and

an output node electrically coupled to an input node of the first flip-flop circuit;

a second path comprising:

a second flip-flop circuit configured to be clocked by the master clock signal, comprising:

an input node electrically coupled to the output node of the AND-based gate; and

an output node; and

a plurality of buffers in series, wherein:

a first buffer of the plurality of series buffers comprises an input node electrically coupled to the output node of the second flip-flop circuit; and is

A last buffer of the plurality of buffers in series comprises an output node;

an XOR-based gate, comprising:

a first input node electrically coupled to the output node of the buffer of the first path;

a second input node electrically coupled to the output node of the last buffer of the plurality of series buffers of the second path; and

an output node, the XOR-based gate configured to provide an output signal on its output node; and

a flip-flop circuit configured to be clocked by the master clock signal, comprising:

an input node electrically coupled to the output node of the XOR-based gate; and

an output node, the flip-flop circuit configured to provide the fall detection signal on its output node.

16. The adaptive voltage modulation circuit of claim 1 integrated into an Integrated Circuit (IC).

17. The adaptive voltage modulation circuit of claim 1 integrated into a device selected from one or more of the following: a computer; a monitor; a television set; a tuner; a music player; or a video player.

18. An adaptive voltage modulation circuit, comprising:

means for generating a drop detection signal in an active state in response to a supply voltage provided to a load circuit being less than a drop threshold voltage, and generating the drop detection signal in an inactive state in response to the supply voltage being greater than the drop threshold voltage;

means for reducing a frequency of a load clock signal provided to a load circuit in response to the falling detection signal transitioning to an active state, and increasing the frequency of the load clock signal in response to the falling detection signal transitioning to an inactive state;

means for incrementing a count in response to each cycle of a reference clock signal, wherein the fall detection signal is in an active state;

means for generating a voltage-up signal in an active state in response to the count being greater than an up threshold; means for generating a voltage-reduced signal in an active state in response to the count being less than a reduction threshold at the end of a defined period of time measured by the reference clock signal;

means for increasing the supply voltage provided to the load circuit in response to the voltage-adjust-up signal being active; and

means for reducing the supply voltage provided to the load circuit in response to the voltage-down signal being active.

19. The adaptive voltage modulation circuit of claim 18, further comprising:

means for generating the voltage-adjusted-high signal in an inactive state in response to the count being less than the adjusted-high threshold at the end of the defined period of time; and

means for generating the voltage-reduced signal in an inactive state in response to the count being greater than the reduction threshold at the end of the defined period of time.

20. The adaptive voltage modulation circuit of claim 18, further comprising means for resetting the count to an initial count value in response to the defined period ending.

21. The adaptive voltage modulation circuit of claim 18, further comprising means for generating the reduced threshold voltage based on a digital threshold signal, wherein the digital threshold signal is a digital representation of the reduced threshold voltage stored in a register in the adaptive voltage modulation circuit.

22. The adaptive voltage modulation circuit of claim 18, further comprising:

means for performing a comparison of the supply voltage to the reduced threshold voltage; and

means for generating the drop detection signal in an inactive state in response to the drop threshold voltage being less than the supply voltage.

23. The adaptive voltage modulation circuit of claim 22, wherein:

in response to the falling detect signal transitioning to the active state, lowering the frequency of the load clock signal below a frequency of a master clock signal by reducing the frequency of the load clock signal; and

in response to the falling detection signal transitioning to the inactive state, the frequency of the load clock signal is made equal to the frequency of the master clock signal by increasing the frequency of the load clock signal.

24. A method for adaptively modulating a supply voltage, comprising:

generating a drop detection signal in an active state in response to a supply voltage provided to a load circuit being less than a drop threshold voltage, and generating the drop detection signal in an inactive state in response to the supply voltage being greater than the drop threshold voltage;

reducing a frequency of a load clock signal provided to a load circuit in response to the falling detection signal transitioning to an active state and increasing the frequency of the load clock signal in response to the falling detection signal transitioning to an inactive state;

incrementing a count in response to each cycle of a reference clock signal, wherein the fall detection signal is in an active state;

generating a voltage-up signal in an active state in response to the count being greater than an up threshold;

generating an active voltage-reduced signal in response to the count being less than a reduction threshold at the end of a defined period as measured by the reference clock signal;

increasing the supply voltage provided to the load circuit in response to the voltage-adjust-high signal being active; and

reducing the supply voltage provided to the load circuit in response to the voltage-down signal being active.

25. The method of claim 24, further comprising:

generating the voltage-modulated-high signal in an inactive state in response to the count being less than the modulated-high threshold at the end of the defined period of time; and

generating the voltage-reduced signal in an inactive state in response to the count being greater than the reduction threshold at the end of the defined period of time.

26. The method of claim 24, further comprising resetting the count to an initial count value in response to the defined period of time ending.

27. The method of claim 24, further comprising generating the reduced threshold voltage based on a digital threshold signal, wherein the digital threshold signal is a digital representation of the reduced threshold voltage.

28. The method of claim 24, wherein generating the drop detection signal comprises:

performing a comparison of the supply voltage to the reduced threshold voltage; and

generating the drop detection signal in an inactive state in response to the drop threshold voltage being less than the supply voltage.

29. The method of claim 28, wherein:

in response to the falling detection signal being in the active state, lowering the frequency of the load clock signal below the frequency of a master clock signal by reducing the frequency of the load clock signal; and is

In response to the falling detection signal being in the inactive state, the frequency of the load clock signal is made equal to the frequency of the master clock signal by increasing the frequency of the load clock signal.

30. A processor-based system, comprising:

a processor;

a power management circuit configured to provide a supply voltage to the processor; and

an adaptive voltage modulation circuit, comprising:

a supply voltage drop detection and mitigation circuit, comprising:

a detection circuit configured to generate a fall detection signal in an active state in response to the supply voltage being less than a fall threshold voltage and to generate the fall detection signal in an inactive state in response to the supply voltage being greater than the fall threshold voltage; and

a clock adjustment circuit configured to decrease a frequency of a load clock signal provided to the processor in response to the falling detection signal transitioning to an active state and increase the frequency of the load clock signal in response to the falling detection signal transitioning to an inactive state;

a supply voltage adjustment circuit, comprising:

a counter circuit configured to increase a count in response to each cycle of a reference clock signal, wherein the fall detection signal is in an active state;

a voltage-adjust-high circuit configured to generate a voltage-adjust-high signal in an active state in response to the count being greater than an adjust-high threshold; and

a voltage-pull-down circuit configured to generate a voltage-pull-down signal in an active state in response to the count being less than a pull-down threshold at the end of a defined period of time as measured by the reference clock signal; and

a supply voltage controller circuit configured to:

increasing the supply voltage provided to the processor in response to the voltage-adjust-high signal being active; and is

Reducing the supply voltage provided to the processor in response to the voltage-down signal being active.