HK1256963B - Fully molded miniaturized semiconductor module - Google Patents

Description

Fully molded miniaturized semiconductor module

Cross Reference to Related Applications

This patent application claims the right (including the filing date) to U.S. provisional patent application No. 62/258,040 entitled Fully Molded Miniaturized Semiconductor Module (filed on 20/2015), the disclosure of which is hereby incorporated by reference. This patent application is also a partial continuation of U.S. application No. 14/930,514 entitled Semiconductor Device including Redistribution Layers and Method thereof (Semiconductor Device and Method Comprising Redistribution Layers) filed on day 11/2015, U.S. application No. 14/930,514 is a partial continuation of U.S. application No. 14/642,531 entitled Semiconductor Device including Thickened Redistribution Layers and Method thereof (Semiconductor Device and Method Comprising Thick Redistribution Layers) filed on day 9/2015, U.S. application No. 14/642,531 is a temporary Wafer-Level Chip-Scale package with Thick Redistribution Layer Traces filed on day 10/2014, U.S. application No. 61/950,743 is a temporary Wafer-Level Chip-Scale package with Thick Redistribution Layers filed on day 3/2014, and further is a full Fan-Level Fan-out package (full Fan-Up package) filed on day 12 Out Wafer Level Packaging), U.S. application No. 14/584,978, No. 14/584,978, a continuation of U.S. application No. 14/024,928 entitled Fully Molded Fan-Out Fan-Level Packaging (Die Up filled Fan-Out Fan-Level Packaging) filed on 12.9.2013, U.S. application No. 14/024,928, now issued as patent No. 8,922,021, a continuation of U.S. application No. 13/632,062 entitled Fully Molded Fan-Out Fan-Level Packaging filed on 30.9.2012, U.S. application No. 13/632,062, now issued as patent No. 8,535,978, an continuation of U.S. application No. 13/341,654 entitled Fully Molded Fan-Out (Fan-Out Molded Fan-Level Packaging) filed on 30.12.2011, U.S. application No. 13/341,654, the disclosure of which is now published as patent No. 8,604,600 and entitled application date of U.S. provisional patent No. 61/672,860 entitled Fan-Out Semiconductor Package (Fan-Out Semiconductor Package) filed on 7/18/2012, is hereby incorporated herein by reference.

Technical Field

The present disclosure relates to a full mold fan-out miniaturized module, a full mold fan-out module (FMFOM), or a miniaturized module (hereinafter referred to as "module" or "modules"). The modules may include technology for wearable, for internet of things (IoT) devices, or both.

Background

Semiconductor devices are common in modern electronic products. Semiconductor devices have different numbers and densities of electrical components. Discrete semiconductor devices typically contain one type of electrical component, such as Light Emitting Diodes (LEDs), small signal transistors, resistors, capacitors, inductors, and power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, Charge Coupled Devices (CCDs), solar cells, and Digital Micromirror Devices (DMDs).

Semiconductor devices perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronics, converting sunlight to electrical power, and creating visual projections for television displays. Semiconductor devices are found in the areas of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of a semiconductor material allows its conductivity to be manipulated by applying an electric field or base current or through a doping process. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

The semiconductor device includes active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of current. By varying the level of doping and the level of electric field or base current application, the transistor facilitates or limits the flow of current. Passive structures, including resistors, capacitors, and inductors, establish the relationship between voltage and current necessary to perform a wide variety of electrical functions. The passive and active structures are electrically connected to form a circuit that enables the semiconductor device to perform high speed calculations and other useful functions.

Semiconductor devices are typically manufactured using two complex manufacturing processes, front end fabrication and back end fabrication, each of which may involve hundreds of steps. Front end fabrication involves forming a plurality of semiconductor dies on a surface of a semiconductor wafer. Each semiconductor die is typically designed to be identical and contain circuitry formed by electrically connecting active and passive components. Back-end fabrication involves singulating individual semiconductor dies from a finished wafer and packaging the dies to provide structural support and environmental isolation. As used herein, the term "semiconductor die" refers to both the singular and plural forms of words and, thus, may refer to both a single semiconductor device and a plurality of semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices generally consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have smaller footprints, which is desirable for smaller end products. Smaller semiconductor die sizes can be achieved by improving front-end processing, resulting in semiconductor dies with smaller, higher density active and passive components. Back-end-of-line processes may produce semiconductor device packages with smaller footprints by improving electrical interconnections and packaging materials.

Back-end processing of semiconductor dies includes a variety of Surface Mount Technologies (SMT) used to connect semiconductor dies or integrated circuits to substrates and Printed Circuit Board (PCB) surfaces without the use of through-holes in the PCB. Quad Flat Pack (QFP) uses SMT including leads extending from each of the four sides of the package, sometimes referred to as "gull-wing leads. The QFP leads provide electrical input/output (I/O) interconnection between the semiconductor die within the package and the PCB or substrate to which the QFP is mounted. Other SMT packages are made in a leadless manner and are often referred to as flat leadless packages. Examples of flat no-lead packages are quad flat no-lead (QFNs) packages and dual flat no-lead (DFN) packages. QFN packages conventionally include a semiconductor die connected with wire bonds to a leadframe for I/O interconnection of the package.

Disclosure of Invention

There is an opportunity for improvement in semiconductor fabrication. Accordingly, in one aspect, a semiconductor module may include: a fully molded base portion including a planar surface, the fully molded base portion further including a semiconductor die including a contact pad, a conductive pillar coupled to the contact pad and extending to the planar surface, and an encapsulant disposed over the active surface, over four side surfaces, and surrounding the conductive pillar, wherein a tip of the conductive pillar is exposed from the encapsulant at the planar surface of the fully molded base portion. The build-up interconnect structure includes a wiring layer that may be disposed over the fully molded substrate portion. A photoimageable solder mask material may be disposed over the routing layer and include openings to form Surface Mount Device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. Surface Mount Technology (SMT) may be used to electrically couple SMD components to the SMD land pads.

The semiconductor module may further include: the photoimageable solder mask includes at least one of an epoxy solder resist, polyimide, PBO, and silicone. The SMD component can be electrically coupled to the SMD land pads, wherein the SMD component can include solderable terminals, the solder paste can be disposed over the SMD land pads, and the solderable terminals can be disposed over the SMD land pads and electrically coupled to the SMD land pads when the solderable terminals are in contact with the solder paste. The SMD land pads may include the following solderable surface treatments: nickel (Ni) and gold (Au); or Ni, palladium (Pd) and Au; or tin (Sn); or a solder; or an Organic Solderability Preservative (OSP). Solder bumps may be used to couple the SMD component to the land pads. The build-up interconnect structure may include a high density multilayer wiring layer. The SMD component can be partially within a footprint of the semiconductor die and partially not within a footprint of the semiconductor die, and at least one of the SMD land pads can be positioned over an edge of the footprint of the semiconductor die within the fully molded structure. The first output connector of the module may be adapted to couple to a battery and the second connector of the module may be adapted to couple to a display. The semiconductor die in the fully molded base portion can be fully tested before any SMD components are coupled to the SMD land pads.

In another aspect, a semiconductor module may include: a fully molded base portion comprising a planar surface, the base portion further comprising a semiconductor die comprising a contact pad, a conductive pillar coupled to the contact pad and extending to the planar surface, and an encapsulant disposed over the active surface, over four side surfaces, and surrounding the conductive pillar, wherein an end of the conductive pillar is exposed from the encapsulant at the planar surface of the fully molded base portion. The build-up interconnect structure may include a wiring layer disposed over the fully molded substrate portion. An SMD component may be electrically coupled to the routing layer.

The semiconductor module may further include an SMD component electrically coupled to the wiring layer. The SMD component may include: a solderable terminal; a solder paste which may be disposed over the wiring layer; and the solderable terminals can be disposed above and electrically coupled to the wiring layer when the solderable terminals are in contact with the solder paste. The SMD component may be coupled to the routing layer using solder bumps. The SMD component may be partially within the footprint of the semiconductor die and partially not within the footprint of the semiconductor die. The first output connector of the module may be adapted to couple to a battery and the second connector of the module may be adapted to couple to a display. The semiconductor die in the fully molded base portion can be fully tested before any SMD component is coupled to the SMD land pads.

In another aspect, a method of fabricating a semiconductor module may include: forming an electrical interconnect on a semiconductor die; and encapsulating the semiconductor die with an encapsulant to form a first embedded portion, wherein the electrical interconnect is exposed from the encapsulant. A build-up interconnect structure including a conductive RDL layer can be formed over the first embedded portion and electrically connected to the electrical interconnect. A Surface Mount Device (SMD) land pad may be formed electrically coupled to the conductive RDL layer. A SMD component can be coupled to the SMD land pads using Surface Mount Technology (SMT) to provide an electrical connection between the SMD component and the semiconductor die through the conductive pillars and the build-up interconnect structure.

The method of fabricating the semiconductor module may further include forming the SMD land pads by: disposing a photoimageable solder mask material over the conductive RDL layer; forming an opening in the photoimageable solder mask material over the conductive RDL layer; and applying the following solderable surface treatments on the SMD land pads: ni and Au; ni, Pd and Au; sn; welding flux; or OSP. Coupling the SMD component to the SMD land pads can further include: screen printing solder paste on each of the SMD land pads; placing solderable terminals of the SMD component over the first embedded portion such that the solderable terminals contact the solder paste over the SMD land pads; and reflowing the solder paste to couple the SMD component to the SMD land pads. The semiconductor die within the first embedded portion may be electrically tested prior to coupling any of the SMD components to the first embedded portion. The method can further include coupling the SMD component to the SMD land pads such that the SMD component is partially within a footprint of the semiconductor die and partially not within a footprint of the semiconductor die.

The foregoing and other aspects, features and advantages will be apparent to those skilled in the art from the detailed description and drawings, and from the claims.

Drawings

Fig. 1A-1D illustrate a native wafer or substrate including a plurality of semiconductor dies and conductive interconnects formed over the plurality of semiconductor dies.

Fig. 2A-2K illustrate various aspects of the formation of a semiconductor module, module or semiconductor die module.

Fig. 3 illustrates a process flow or flow diagram for forming a semiconductor module, module or semiconductor die module.

Detailed Description

In the following description, reference is made to the accompanying drawings that form a part hereof, and in which like numerals designate the same or similar components, the disclosure includes one or more aspects or embodiments. It will be appreciated by those skilled in the art that the present description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. In the description, numerous specific details are set forth, such as specific configurations, compositions, and procedures, etc., in order to provide a thorough understanding of the present disclosure. In other instances, well-known procedures and manufacturing techniques have not been described in detail so as not to obscure the disclosure. Furthermore, the various embodiments shown in the figures are illustrative representations and are not necessarily shown to scale.

The present disclosure, aspects, and embodiments thereof, are not limited to the particular apparatus, type of material, or other system component examples, or methods disclosed herein. Many additional components, manufacturing, and assembly procedures well known in the art consistent with manufacturing and packaging have been contemplated for use with specific embodiments from this disclosure. Thus, for example, although specific embodiments are disclosed, the embodiments and implemented components may include any components, models, types, materials, versions, amounts, and/or the like as are known in the art for the systems and implemented components consistent with the intended operation.

The words "exemplary," "example," or various forms thereof, as used herein are intended to be used as an example, case, or illustration. Any aspect or design described herein as "exemplary" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Additionally, examples are provided solely for purposes of clarity and understanding and are not intended to limit or define the disclosed subject matter or relevant portions of this disclosure in any way. It will be appreciated that a myriad of additional or alternative examples with different ranges may be presented, but have been omitted for purposes of brevity.

In the following examples, embodiments, and detailed description reference examples, it will be appreciated by those skilled in the art that other fabrication apparatus and examples can be intermixed with or substituted for the apparatus and examples provided. Where the description above refers to particular embodiments, it should be apparent that several modifications may be made without departing from the spirit thereof, and that these embodiments and implementations may also be applied to other technologies. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the present disclosure and within the knowledge of those skilled in the art.

Roughly speaking, semiconductor devices are manufactured using two complex manufacturing processes: front end fabrication and back end fabrication. Front end fabrication involves forming a plurality of dies on a surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form functional circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, establish the relationship between voltage and current necessary to perform the circuit function.

Passive and active devices are formed on the surface of a semiconductor wafer through a series of process steps, including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the conductivity of the semiconductor material in the active device, transforms the semiconductor material into an insulator, a conductor, or dynamically changes the conductivity of the semiconductor material in response to an electric field or base current. Transistors contain regions of different types and doping levels configured as necessary to enable the transistor to facilitate or restrict the flow of current when an electric field or base current is applied.

The active and passive components are formed from layers of materials having different electrical properties. The layers may be formed by a variety of deposition techniques, depending in part on the type of material deposited. For example, thin film deposition may involve Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), electrolytic plating, and electroless plating procedures. Generally, the layers are patterned to form active component portions, passive component portions, or electrical connections between components.

The layers may be patterned using photolithography, which involves depositing a photosensitive material (e.g., photoresist) over the layer to be patterned. Light is used to transfer a pattern from a photomask to a photoresist. In one embodiment, a solvent is used to remove portions of the photoresist pattern that are subjected to light, while exposing portions of the underlying layer to be patterned. In another embodiment, the portion of the photoresist pattern that is not exposed to light (negative photoresist) is removed using a solvent, exposing the portion of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind the patterned layer. Alternatively, some types of materials are patterned by depositing the material directly into the regions or voids formed by previous deposition/etch procedures using techniques such as electroless and electrolytic plating.

Patterning is a basic operation that removes portions of the top layer on the surface of the semiconductor wafer. Photolithography, photomasks, masks, oxide or metal removal, photography and stencil printing, and microetching can be used to remove portions of a semiconductor wafer. The photolithography method comprises: forming a pattern in a reticle or photomask; and transferring the pattern to a surface layer of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of a semiconductor wafer in a two-step process. In the first step, the pattern of the reticle or photomask is transferred onto the photoresist layer. Photoresists are photosensitive materials that undergo structural and property changes when exposed to light. The process of altering the structure and properties of the photoresist occurs as either a negative-acting photoresist or a positive-acting photoresist. The second step, the photoresist layer is transferred into the surface of the wafer. The transfer occurs when the etch removes portions of the top layer of the semiconductor wafer that are not covered by the photoresist. The chemical nature of the photoresist is such that the photoresist remains substantially intact and resists removal by chemical etching solutions while removing portions of the top layer of the semiconductor wafer not covered by the photoresist. The procedures for forming, exposing, and removing the photoresist, as well as the procedures for removing a portion of the semiconductor wafer, may be modified depending on the particular photoresist used and the results desired.

In negative-working photoresists, the photoresist is exposed to light and is changed from a soluble condition to an insoluble condition in a process known as polymerization. In polymerization, unpolymerized material is exposed to light or an energy source and the polymer forms a crosslinked material, which is a resist. In most negative photoresists, the polymer is polyisoprene. Removal of the soluble portions (i.e., the unexposed portions) with a chemical solvent or developer leaves holes in the photoresist layer that correspond to the opaque pattern on the reticle. A mask in which a pattern is present in the opaque areas is called a clear field mask.

In positive-working photoresists, the photoresist is exposed to light and is changed from a relatively insoluble state to a more soluble state in a process known as photodissolution. In photo-dissolution, a relatively insoluble photoresist is exposed to appropriate light energy and converted to a more soluble state. In the development procedure, the photo-dissolved portions of the photoresist may be removed by a solvent. The basic positive photoresist polymer is a phenol-formaldehyde polymer, also known as a phenol-formaldehyde novolac resin. Removal of the soluble portions (i.e., the exposed portions) with a chemical solvent or developer leaves holes in the photoresist layer that correspond to the transparent pattern on the reticle. The mask in which the pattern is present in the transparent region is called a dark field mask.

After removing the top portion of the semiconductor wafer not covered by the photoresist, the remaining portion of the photoresist is removed, leaving the patterned layer. Alternatively, some types of materials are patterned by depositing the material directly into the regions or voids formed by previous deposition/etch procedures using techniques such as electroless and electrolytic plating.

Depositing a thin film of material over an existing pattern increases the underlying pattern and creates a non-uniform planar surface. A uniform planar surface may be advantageous or necessary to produce smaller and more densely packed active and passive components. Planarization may be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. Abrasive materials and corrosive chemicals are added to the surface of the wafer during polishing. Alternatively, planarization is performed using mechanical polishing without using aggressive chemicals. In some embodiments, pure mechanical grinding is achieved by using a belt sander, a standard wafer backgrinder (backsgrind), or other similar machine. The combined abrasive mechanical action and chemical etching action removes any irregularities resulting in a uniformly flat surface.

Back-end fabrication refers to the dicing or singulation of the finished wafer into individual semiconductor dies and then packaging the semiconductor dies for structural support and environmental isolation. To singulate a semiconductor die, the wafer may be diced along non-functional areas of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Then, contact pads formed over the semiconductor die are connected to contact pads within the package. The electrical connection may be made with solder bumps, stud bumps, conductive paste, redistribution layers, or wire bonding. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into the electrical system and the functionality of the semiconductor device is made available to other system components.

The electrical system may be a stand-alone system that uses the semiconductor device to perform one or more electrical functions. Alternatively, the electrical system may be a sub-component of a larger system. For example, the electrical system may be part of a mobile phone, Personal Digital Assistant (PDA), Digital Video Camera (DVC), or other electronic communication device. Alternatively, the electrical system may be a graphics adapter, network adapter, or other signal processing card that may be inserted into a computer. A semiconductor package may include a microprocessor, memory, an Application Specific Integrated Circuit (ASIC), logic circuitry, analog circuitry, Radio Frequency (RF) circuitry, discrete devices, or other semiconductor die or electronic component. Miniaturization and weight reduction may be advantageous or necessary for market acceptance of the product. The distance between the semiconductor devices must be reduced to achieve higher density.

By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because the semiconductor package includes sophisticated functionality, electronic devices may be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and less expensive to manufacture, thereby reducing costs to the consumer.

Fig. 1A-1D show a plurality of semiconductor dies that have been formed according to the front end fabrication methods and procedures outlined above. More specifically, fig. 1A shows a semiconductor wafer 10 having a base substrate material 12 for structural support, such as, but not limited to, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide. A plurality of semiconductor dies or components 14 separated by inactive inter-die wafer regions or saw streets 16 as described above are formed on the wafer 10. The saw streets 16 provide cutting areas to singulate the semiconductor wafer 10 into individual semiconductor dies 14.

Fig. 1B shows a cross-sectional view of a plurality of semiconductor dies 14 from the native semiconductor wafer 10 shown in fig. 1A. Each semiconductor die 14 has a back side or surface 18 and an active surface 20 opposite the back side. Active surface 20 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry may include one or more transistors, diodes, and other circuit components formed within active surface 20 to implement analog circuitry or digital circuitry, such as Digital Signal Processing (DSP), ASIC, memory, or other signal processing circuitry. Semiconductor die 14 may also contain Integrated Product Development (IPD) for RF signal processing, such as inductors, capacitors, and resistors.

Conductive layer 22 is formed over active surface 20 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 22 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive material. Conductive layer 22 functions as a contact pad or bond pad that is electrically coupled or connected to circuitry on active surface 20. Conductive layer 22 can be formed as contact pads disposed side-by-side a first distance from an edge of semiconductor die 14, as shown in fig. 1B. The conductive layer 22 may also be formed as contact pads that are offset in a plurality of columns such that a first column of contact pads is disposed a first distance from the edge of the die and a second column of contact pads alternating with the first column is disposed a second distance from the edge of the die. In addition, the conductive layer 22 may be formed as contact pads configured as a full pad array distributed over the active area of a semiconductor die or chip. In some cases, the contact pads may be configured in an irregular or asymmetric array, with different pitches or multiple pitches between the contact pads.

Fig. 1C shows an optional insulating or passivation layer 26 conformally applied over active surface 20 and over conductive layer 22. Insulating layer 26 may comprise one or more layers applied using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable procedure. The insulating layer 26 may contain, but is not limited to, one or more of the following: silicon dioxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), tantalum pentoxide (Ta)₂O₅) Alumina (Al)₂O₃) Polymers, polyimides, benzocyclobutene (BCB), Polybenzoxazoles (PBO), or other materials with similar insulating and structural properties. Alternatively, no PBO layer is used to encapsulate the semiconductor die 14, and the insulating layer 26 may be formed of a different material or omitted entirely. In another embodiment, insulating layer 26 includes a passivation layer formed over active surface 20 and not disposed over conductive layer 22. When insulating layer 26 is present and formed over conductive layer 22, an opening is formed completely through insulating layer 26 to expose at least a portion of conductive layer 22 for subsequent mechanical and electrical interconnection. Or when insulating layer 26 is omitted, conductive layer 22 is exposed for subsequent electrical interconnection without the need to form an opening.

Fig. 1C also shows that electrical interconnect structure 28 may be formed as a pillar (column), pillar (pilar), post (post), post (stud), bump formed of a suitable conductive material, such as copper, disposed over conductive layer 22 and coupled or connected to conductive layer 22. Interconnect structure 28 may be formed directly on conductive layer 22 using a patterning and metal deposition process, such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. Interconnect structure 28 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, palladium (Pd), or other suitable conductive material and may include one or more Under Bump Metal (UBM) layers. In one embodiment, a photoresist layer is deposited over semiconductor die 14 and conductive layer 22. A portion of the photoresist layer is exposed and removed by an etch development process. Using a selective plating procedure, electrical interconnect structures 28 are formed as copper pillars in the removed portions of the photoresist agent and over conductive layer 22. The photoresist layer is removed leaving interconnect structure 28, which interconnect structure 28 provides subsequent mechanical and electrical interconnection and standoffs (standoff) with respect to active surface 20 and insulating layer 26, if present. Interconnect structure 28 may include a height H1 in the range of 10 to 100 micrometers (μm), or a height in the range of 20 μm to 50 μm, or a height of approximately 35 μm.

Fig. 1C further shows that the wafer 10 is subjected to an optional polishing operation with a polisher 30 to planarize the back surface 18 and reduce the wafer thickness. Chemical etching may also be used to remove and planarize a portion of the wafer 10.

Fig. 1D shows the wafer 10 singulated through the saw street 16 into individual semiconductor dies 14 by using a saw blade or laser cutting tool 32 after forming the interconnect structures 28 and optionally grinding the wafer 10.

Fig. 2A shows a carrier or substrate 36 containing a temporary or sacrificial base material for structural support, such as silicon, polymer, stainless steel, or other suitable low cost rigid material. An optional interface layer or double-sided tape 38 is formed over carrier 36 to act as a temporary adhesive bonding film or etch stop layer. In one embodiment, carrier 36 is an annular film frame that supports tape 38 at its periphery, the annular film frame including an open central portion, as shown in fig. 2B.

Fig. 2A further shows semiconductor die 14 from fig. 1D mounted face-up or die-up to carrier 36 and interface layer 38, with back side 18 oriented toward the substrate and active surface 20 oriented away from carrier 36. As used herein, face-up or die-up refers to a semiconductor die that includes an active surface and a back surface opposite the active surface, positioned such that the back surface is coupled to the carrier. The active surface of the semiconductor die may be oriented away from the carrier when the semiconductor die is mounted to the carrier. As used herein, face-down or die-down refers to a semiconductor die that includes an active surface and a back surface opposite the active surface, positioned such that the active surface is coupled to the carrier and oriented toward the carrier, the back surface of the semiconductor die being oriented away from the carrier when the semiconductor die is mounted to the carrier. Semiconductor die 14 may be placed on carrier 36 using a pick and place operation or other suitable operation. Optionally, adhesive 41 is disposed between backside 18 of semiconductor die 14 and carrier 36. The adhesive 41 may be a thermal epoxy, an epoxy resin, a B-staged epoxy film, an Ultraviolet (UV) B-staged film with an optional acrylic polymer, or other suitable material. In one embodiment, adhesive 41 may be disposed on back side 18 before semiconductor die 14 is mounted on carrier 36. Alternatively, adhesive 41 may be disposed on carrier 36 prior to mounting the semiconductor die to the carrier. In other embodiments, as shown in fig. 2B, the semiconductor die 14 may be mounted directly to the interface layer or support tape 38 without the use of an adhesive 41.

The semiconductor die 14 is mounted to the carrier 36 such that the semiconductor die are separated by a space or gap 40 when mounted over the carrier 36, which provides an area for a subsequently formed fan-out interconnect structure, including the connections between the high voltage lines and the buses. The size of the gap 40 includes sufficient area for optionally mounting a semiconductor device or component within a subsequently formed fan-out wafer level package (FOWLP).

Fig. 2C shows an encapsulant or molding compound 42, which may be formed from a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, a polymer containing a suitable filler, or other suitable material. Encapsulant 42 may be non-conductive, provide physical support, and environmentally protect semiconductor die 14 from external elements and contaminants. The encapsulant 42 may be deposited using a paste printing, compression molding, transfer molding, liquid encapsulant molding, lamination, vacuum lamination, spin coating, or other suitable applicator. Specifically, fig. 2C shows a mold 44 having a plurality of sidewalls 46 assembled with a top portion or plate 45, carrier 36, and interface layer 38 to enclose semiconductor die 14 within the mold for subsequent encapsulation. The mold 44 may also include a bottom portion on which the carrier 36 is placed and the sidewalls 46 may contact the bottom portion. In one embodiment, carrier 36 and interface layer 38 are used as a bottom mold portion for a subsequent sealing procedure. Alternatively, semiconductor die 14, carrier 36, and interface layer 38 may be disposed within a mold that includes multiple portions, such as a top portion and a bottom portion. The dies 44 are assembled together by moving the dies 44 around the semiconductor die 14 or, alternatively, by moving the semiconductor die into the dies.

Fig. 2C further shows mold 44 enclosing semiconductor die 14 within a cavity or open space 50. Cavity 50 extends between mold 44 to semiconductor die 14 and interface layer 38. A volume of encapsulant 42 is disposed over semiconductor die 14 and carrier 36. The inlet 48 may be an exhaust port having an optional vacuum assist 54 for providing vacuum in the chamber 50; however, the inlet 48 does not provide an escape path for the enclosure 42. The encapsulant 42 may be a polymer composite such as a filled epoxy resin, a filled epoxy acrylate, or a polymer containing a suitable filler. The volume of the encapsulant 42 is measured according to the space requirements of the chamber 50 minus the area occupied by the semiconductor die 14 and any additional semiconductor devices that may be present. Encapsulant 42 is disposed over semiconductor die 14 and between sidewalls 46. Top portion 45 of mold 44 is moved along sidewalls 46 toward encapsulant 42 and semiconductor die 14 until the top portion contacts the encapsulant, uniformly dispersing and distributing encapsulant 42 within cavity 50 surrounding semiconductor die 14. The viscosity and elevated temperature of the encapsulant 42 may be selected for uniform coverage, e.g., lower viscosity and elevated temperature may enhance the flow of the encapsulant for molding, paste printing, and spin coating. The temperature of the encapsulant 42 may also be controlled within the chamber 50 to facilitate curing of the encapsulant. Semiconductor die 14 are embedded together in an encapsulant 42, encapsulant 42 being non-conductive and environmentally protecting the semiconductor device from external elements and contaminants.

Fig. 2D shows a sealing procedure similar to that described with respect to fig. 2C. Fig. 2D differs from fig. 2C in the orientation of semiconductor die 14 relative to carrier 36 and interface layer 38. Fig. 2D shows an embodiment in which the semiconductor die 14 is mounted face down and the active surface 20 is oriented toward the carrier 36, rather than mounting the semiconductor die 14 face up and the active surface 20 is oriented away from the carrier 36 as shown in fig. 2C. Thus, adhesive 41 can be omitted from over back surface 18 of semiconductor die 14. Furthermore, although the processes subsequently shown in fig. 2E-2K are for the packaging of the semiconductor die 14 shown in fig. 2C, the subsequent processes are equally applicable to the packaging shown in fig. 2D.

Fig. 2E shows a cross-sectional profile view of the encapsulant 42 disposed around the semiconductor die 14 to form an embedded die panel, molded panel or panel 58. The panel 58 may include a footprint or form factor of any shape, such as circular, square, and rectangular, and also include a size that allows and facilitates subsequent processing. In some cases, the panel 58 may include a form factor similar to that of a 300 millimeter (mm) semiconductor wafer and include a circular footprint having a diameter of 300mm, although other sizes are possible. The panel 58 may include multiple portions or first embedded portions 60 that may be used for a plurality of subsequently formed semiconductor modules 100, each of which is subjected to processing on the panel 58 at the same time. Thus, while only two semiconductor dies 14 that may form part of a single semiconductor module 100 are shown in fig. 2E-2K for simplicity, those skilled in the art will appreciate that more semiconductor dies 14 and first embedded portions 60 may be included and formed from panel 58. The first embedded portion 60 may also be referred to and understood as a fully molded substrate portion, an embedded grain, a substrate portion, or a first portion. The first embedded portion 60 of the panel 58 may include, in addition to one or more semiconductor dies 14, Integrated Circuits (ICs), passive devices, Wafer Level Chip Scale Packages (WLCSP), and other components.

Consistent with the foregoing, fig. 2F shows a plan view of a panel 58 including a plurality of first embedded portions 60. Fig. 2F also shows a section line 2E on the panel 58 from which a cross-sectional view is taken for the single first insert portion 60 in fig. 2E.

In fig. 2E, semiconductor die 14 is removed from mold 44 and embedded die panel or plates 58 are optionally subjected to a curing procedure to cure encapsulant 42. Optionally, carrier 36 and interface layer 38 may be removed by chemical etching, mechanical peel-off, CMP, mechanical polishing, thermal bake, UV light, laser scanning, or wet stripping to expose encapsulant 42. Alternatively, carrier 36 and interface layer 38 may survive for subsequent processing and later removal. In some cases, as with adhesive 41, interface layer 38 may continue to be present over semiconductor die 14 and encapsulant 42 to become part of the final module structure. For example, interface layer 38 may be formed as a backside coating (formed from an epoxy laminate or other suitable material for sealing backside 18 of semiconductor die 14) and form a backside or outer surface of semiconductor module 100. When formed as a backside coating, the interface layer 38 may be formed at any suitable time during the formation of the semiconductor module 100. Thus, the final module may include the interface layer 31, the adhesive 41, or both. First surface 55 of encapsulant 42 may be substantially coplanar with one or more of backside 18 of semiconductor die 14, adhesive 41, and interface layer 38. First surface 55 of encapsulant 42 may be substantially coplanar with backside 18, exposing encapsulant 42 by removing carrier 36 and interface layer 38.

Fig. 2E also shows that the panel 58 can be subjected to an optional polishing operation using a polisher 62 to planarize the second surface 56 of the encapsulant 42 (which is opposite the first surface 55) and reduce the thickness of the panel 58 or the first inset portion 60. Chemical etching may also be used to remove and planarize a portion of the encapsulant 42 in the panel 58, such as the second surface 56. Accordingly, a surface 63 of interconnect structure 28 may be exposed relative to surface 56 of encapsulant 42, or at an edge of panel 58, to provide an electrical connection between semiconductor die 14 and a subsequently formed build-up interconnect structure or fan-out interconnect structure 70.

Fig. 2E also shows that the actual position of the semiconductor die 14 within the reconstruction panel 58 can be measured with an inspection device or optical inspection device 64. Accordingly, subsequent processing of the fully molded panel 58 may be conducted relative to the actual location of the semiconductor die 14 within the reconstituted panel 58, as shown and described with respect to subsequent figures.

As described above, fig. 2F shows a plan view of the panel 58. Fig. 2F also shows that the panel 58 may include a plurality of streets or inter-module regions 66 that may be disposed between the first embedded portions 60 and extend along the first embedded portions 60, similar to the manner in which the streets 16 separate the semiconductor dies 14 in the native semiconductor wafer 10 thereof.

Fig. 2G shows the formation of a build-up interconnect structure 70 over the molded panel 58 to electrically connect the conductive interconnects 28 and provide routing with respect to the conductive interconnects 28. Accordingly, the build-up interconnect structure 70 may include a high density multi-layer wiring layer. Although the build-up interconnect structure 70 is shown to include three conductive layers 74,78,82 and three insulating layers 72, 76, 80, those skilled in the art will appreciate that fewer layers or more layers may be used, depending on the configuration and design of the semiconductor module 100.

Optionally, the build-up interconnect structure 70 may include a first insulating or passivation layer 72 formed or disposed over the reconstruction panel 58. The first insulating layer 72 may comprise one or more layers of SiO₂、Si₃N₄、SiON、Ta₂O₅、Al₂O₃Or other materials having similar insulating and structural properties. Insulating layer 72 may be formed using PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. An opening or first level via may be formed through insulating layer 72 over interconnect structure 28 to connect with semiconductor die 14. In some cases, the opening or first level via may be filled with a conductive material or formed as a first level conductive via prior to forming first conductive layer 74. Alternatively, the first level via may be filled with a conductive material and formed as the first level conductive via at the same time as the formation of first conductive layer 74 and at the same time as the formation of first conductive layer 74.

A first conductive layer or wire 74 may be formed over the reconstruction panel 58 and over the first insulating layer 72 as a first RDL layer to: extend through openings in first insulating layer 72, electrically connect with first-level conductive vias, and electrically connect with electrical interconnect structure 28. Conductive layer 74 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material formed using patterning and metal deposition processes, such as sputtering, electrolytic plating, and electroless plating, or other suitable processes.

A second insulating or passivation layer 76, which may be similar or identical to first insulating layer 72, may be disposed or formed over the reconfigured panel 58, first conductive layer 74, and first insulating layer 72. An opening or second level via may be formed through second insulating layer 76 to connect with first conductive layer 74. In some cases, the opening or second-level via may be filled with a conductive material or formed as a second-level conductive via prior to forming second conductive layer 78. Alternatively, in conjunction with forming second conductive layer 78 and at the same time as second conductive layer 78, the second-level vias may be filled with conductive material and formed as second-level conductive vias.

A second conductive layer or wiring layer 78 (which may be similar or identical to first conductive layer 74) may be formed as a second RDL layer over reconstituted panel 58, over first insulating layer 72, over first conductive layer 74, over second-level conductive vias, or within openings of second insulating layer 72 to electrically connect first conductive layer 74, first-level conductive vias and second-level conductive vias, electrical interconnect structure 28, and semiconductor die 14.

A third insulating or passivation layer 80 (which may be similar or identical to first insulating layer 72) may be disposed or formed over second conductive layer 78 and second insulating layer 76. An opening or third level via may also be formed in the third insulating layer 80 or formed through the third insulating layer 80 to connect with the second conductive layer 78. In some cases, the opening or third level via may be filled with a conductive material or formed as a third level conductive via prior to forming the third conductive layer 82. Alternatively, in conjunction with forming third conductive layer 82 and at the same time as third conductive layer 82 is formed, the third level via may be filled with a conductive material and formed as a third level conductive via.

A third conductive layer or wiring level 82 may be formed over third insulating layer 80 to electrically connect to other conductive layers and conductive vias within build-up interconnect structure 70 and to semiconductor die 14 and electrical interconnect structure 28. Similar to all layers formed by an electroplating procedure, plating layers, or conductive layers as shown herein, conductive layer 82 may be a multi-metal stack including one or more of an adhesion layer, a barrier layer, a seed layer, or a wetting layer. The adhesion layer may include titanium (Ti), or titanium nitride (TiN), titanium Tungsten (TiW), Al, or chromium (Cr). The barrier layer may be formed on the adhesion layer and may be made of Ni, NiV, platinum (Pt), Pd, TiW, or chromium copper (CrCu). In some cases, the barrier layer may be a TiW or Ti sputtered layer, and may serve as both an adhesion layer and a barrier layer. In either case, the barrier layer can inhibit poor diffusion of materials such as Cu. The seed layer may be Cu, Ni, NiV, Au, Al, or other suitable material. For example, the seed layer can be a Cu sputter layer including a thickness of about 2000 angstroms (e.g., 2000 + -0-600 angstroms). A seed layer may be formed over the barrier layer and may serve as an intermediate conductive layer under a subsequently placed Surface Mount Device (SMD) component or device 90. In some cases, the wetting layer may include a Cu layer having a thickness in a range of about 5 μm to 11 μm or 7 μm to 9 μm. Such as illustrated in fig. 2H, the subsequently placed SMD component 90 may include solder (such as SnAg solder) that consumes some of the Cu of the conductive layer 84 during reflow and forms intermetallic compounds at the interface between the solder and the Cu of the wetting layer. However, the Cu of the wetting layer can be made thick enough to prevent the Cu pad from being completely consumed by the solder during high temperature aging.

The photoimageable solder mask material 84 may be disposed over the build-up interconnect structure 70 and one or more of the conductive routing layers 74,78, or 82 (such as the top routing layers), around the build-up interconnect structure 70 and one or more of the conductive routing layers 74,78, or 82 (such as the top routing layers), or over the build-up interconnect structure 70 and one or more of the conductive routing layers 74,78, or 82 (such as the top routing layers) and around the build-up interconnect structure 70 and one or more of the conductive routing layers 74,78, or 82 (such as the top routing layers). Although the number of conductive routing layers within the build-up interconnect structure may vary, those skilled in the art will appreciate that the description of the placement of the photoimageable solder mask material 84 is not limited with respect to the conductive routing layers 82. The photoimageable solder mask material 84 may comprise epoxy, solder resist, polyimide, PBO, silicone, or other similar or suitable material. Photoimageable solder mask material 84 may include openings around conductive routing layer 78 to form Surface Mount Device (SMD) land pads 86, which may be electrically coupled to semiconductor die 14 and conductive pillars 28, such as through the build-up interconnect structure 70. The SMD land pads 86 may further include the following solderable surface treatments: ni and Au; ni, Pd, and Au; sn; welding flux; an Organic Solderability Preservative (OSP); or other suitable material. In some cases, the solder mask material 84 and the SMD land pads 86 may be formed as part of the build-up interconnect structure 70.

With the build-up interconnect structure 70 formed over the embedded die panel 58 and the embedded portion 60, the semiconductor die 14 embedded in the fully molded base portion 60 can be fully tested before any SMD components 90 are coupled to the SMD land pads 86. Likewise, semiconductor die 14 embedded in fully molded substrate portion 60 may also be fully tested before build-up interconnect structure 70 is formed over embedded die panel 58 and embedded portion 60 (including after electrical interconnect structure 28 is formed over semiconductor wafer 10, but before embedded die panel 58 is formed). As used herein, the ability to test the electrical connections, interconnections, and functionality of components, such as semiconductor die 14 and build-up interconnect structure 70, including whether the connections, interconnections, and functionality are appropriate, and to ensure that undesirable defects, such as bridging or low quality performance, are present due to the defects, may be fully tested.

When the position of semiconductor die 14 and interconnect structure 28 is shifted from a nominal position, such as during placement and encapsulation of semiconductor die 14 used to form panel 58, the true or actual position of semiconductor die 14 may not be sufficiently aligned with the nominal design of the fan-out interconnect structure to provide the desired reliability for the package interconnect at a given wiring density and pitch tolerance. When the positional variation of semiconductor die 14 is small, there is no need to adjust the position of the opening in insulating layer 72 or the positioning or configuration of conductive layer 74 to interconnect withThe structures 28 are properly aligned. However, when the positions of semiconductor die 14 and interconnect structure 28 vary such that the nominal positions do not provide proper alignment with and exposure to interconnect structure 28, then cell-specific Patterning, module-specific Patterning, or Adaptive Patterning may be used^TM(hereinafter referred to as "cell-specific patterning") the position of the openings in the insulating layer 72 and the positioning and configuration of the conductive layer 74 are adjusted as described in more detail in U.S. patent application No. 13/891,006, U.S. patent No. 9,196,509, filed on 2013, 5, month 9, the disclosure of which is incorporated herein by reference. Alternatively, the unit specific patterning may adjust the position of the opening 66 individually for each semiconductor die 14, or may adjust the position simultaneously for several semiconductor dies 14. The position, alignment, or position and alignment of the openings in insulating layer 72 and the position and configuration of conductive layer 74 may be adjusted by x-y translation or rotation angle θ relative to its nominal position or relative to a datum or reference point on panel 58.

In some cases, optionally, a two-dimensional code may be formed within the build-up interconnect layer 70, such as one or more of the electrically functional RDL layers or conductive layers 74,78,82, the two-dimensional code uniquely identifying each semiconductor die 14, first embedded portion 60, or one or more SMD components 90 within the semiconductor module 100. The unique two-dimensional code can be identified in U.S. patent application No. 14/836,525 filed on 26.8.2015, namely U.S. patent No.9,520,364Formed as described in Front end Package-Level Serialization (Front Side Package-Level Serialization for packaging agents sharing Unique Identifiers), the entire contents of which are incorporated herein by this reference.

Fig. 2H shows multiple SMD components 90 being electrically coupled to SMD land pads 86 using SMT. The SMD component 90 may include terminals or contact pads 91 for interconnection or electrical interconnection between the SMD component 90 and the SMD land pads 86. The SMD components 90 may include a wide variety of semiconductor dies, Wafer Level Chip Scale Packages (WLCSP), or ICs 92, surface mount or active devices 94, and passive devices 96 (including solderable passive components such as resistors or capacitors), among other components, which may be mounted to the first embedded portion 60 and adapted or configured to electrically communicate with the semiconductor dies 14 or other devices embedded within the first embedded portion 60. By being mounted or connected directly to the first embedded portion 60, the SMD component 90 need not be mounted to or route signals through a PCB or other substrate before reaching the first embedded portion 60. Instead, a sophisticated semiconductor module 100 may be built which obviates the need for a PCB or substrate to be used for interconnecting the various SMD components with the first embedded portion 60. The improved integration and reduced size of semiconductor module 100 is well suited for use in miniature electronic systems, such as smart watches and other IoT devices that require the smallest possible form factor.

The SMT 97 used to electrically couple the SMD component 90 to the SMD land pads or flex (flex) connectors 86 may include solder, solder paste, solder bumps, or balls. As indicated above, the solderable landing pads or flex connectors 86 for SMT 97 may be formed as part of, or formed over and coupled to, the multi-layer routing of build-up interconnect structure 70 and conductive layers 74,78,82 to allow for large variations in the size of SMT 97. In some cases, the SMD component 90 electrically coupled to the SMD land pads further includes: an SMD component 90 including solderable terminals 91; a solder paste 97 disposed over the SMD land pads 86; and solderable terminals 91 disposed over the SMD land pads 86 and electrically coupled to the SMD land pads 86, with solderable terminals 91 in contact with solder paste 97. Likewise, in some cases, at least one of the SMD components 90 coupled to the land pads 86 will be coupled with the solder bumps 97.

When SMT 97 includes solder, the solder may be placed on SMD land pads 86 to facilitate electrical communication between SMDs 90 and build-up interconnect structure 70 and first embedded portion 60. The solder may comprise Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, plus an optional flux solution (flux solution). For example, the solder may be eutectic (eutectic) Sn/Pb, high lead solder, or lead-free solder. Solder may be deposited on the first embedded portion 60 and on the SMD land pads 68 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. In some embodiments, the solder is Sn solder paste deposited using screen printing. After the SMD 90 is coupled to the first embedded portion 60 with solder, the solder may be subjected to a reflow process or reflowed to improve electrical contact between the SMD 90 and the SMD land pads 58 or the first embedded portion 60. After reflow, the embedded die panel 58 or the first embedded portion 60 and the SMDs 90 may optionally be subjected to one or more of aqueous cleaning, Automated Optical Inspection (AOI), and plasma cleaning.

Fig. 2I shows that after the SMD components 90 are mounted to the inter-die panel 58, the inter-die panel 58 can be cut or singulated through the dicing street 66 with a saw blade or laser cutting tool 98 to form a semiconductor module, module or semiconductor die module 100. The semiconductor module 100 may include a plurality of fully molded or encapsulated semiconductor dies 14, and a passive member 96 along with other SMD components 90, which may be in a face-up position, a face-down position, or both. Thus, the semiconductor module 100 can be formed as a compact module that eliminates the need for a PCB or other substrate to be used for interconnecting various SMD components with the first embedded portion 60. The improved integration and reduced size of semiconductor module 100 is well suited for use in miniature electronic systems, such as smart watches and other IoT devices that require the smallest possible form factor. In some cases, the overall size or overall dimensions of singulated semiconductor module 100 may include a 10%, 20%, 30% or more reduction in height as compared to more well-known packages that use a PCB or other substrate for the interconnection of components on opposite sides of the package, such as semiconductor die 14 and components 92,94, and 96.

In addition to providing the benefits of being of a compact size, module 100 may also provide improved magnitude due to the robust design. For example, the semiconductor module 100 may include: at least one of the SMD components 90 is partially within the footprint of one of the semiconductor dies 14 and partially not within the footprint of that semiconductor die 14. Further, at least one of the SMD land pads 86 may be positioned over an edge of a footprint of the semiconductor die 14 within the fully molded substrate portion 60. The addition of molding compound 42 over the face or active surface 20 of semiconductor die 14 and over the edges 17 of semiconductor die 14 may improve the mechanical performance of semiconductor module 100. Specifically, in designs including SMD land pads 86 positioned over the edge 17 of the semiconductor die 14, the fully molded base portion 60 provides a flat second surface 56 that is mechanically isolated from the edge 17 of the semiconductor die 14. In contrast, if a face-down fan-out structure is built and the fan-out structure is stacked under a semiconductor die, the SMD component may be partially mechanically coupled to the semiconductor die and partially coupled to the molding compound, which may result in higher thermo-mechanical stress on the solder dots, resulting in solder dot failure.

In some cases, the build-up interconnect structure 70 may be built or formed using cell-specific patterning. Thus, unit specific patterning may be used to adjust the first conductive layer 74 of the build-up interconnect structure 70 for each first embedded portion 60 within the molded panel 58 to align the actual position of each semiconductor die 14 within each first embedded portion 60, thereby maintaining a constant alignment between the SMD land pads 86 and the outline of the module package 100.

Continuing with fig. 2I, fig. 2J shows that a semiconductor module, or semiconductor die module 110 (similar to semiconductor module 100) can be formed with an encapsulant or molding compound 106. After the SMD component 90 is mounted to the in-die panel 58, the SMD component 90 may be sealed, overmolded, or disposed within an encapsulant or molding compound 106. The encapsulant or molding compound 106 may be formed of a material similar or identical to that of the encapsulant 42, including polymer composite materials such as epoxy resin containing fillers, epoxy acrylate containing fillers, polymers containing suitable fillers, or other suitable materials. The encapsulant 106 may be non-conductive, provide physical support, and environmentally protect the SMD component 90 from external elements and contaminants. The encapsulant or molding compound 106 may be deposited using a paste printing, compression molding, transfer molding, liquid encapsulant molding, lamination, vacuum lamination, spin coating, or other suitable applicator, similar or identical to the procedure shown and described for the encapsulant 42.

The second embedded portion, fully molded top portion, embedded die, top portion, or second portion 108 may be formed by encapsulation 106 or over-molding the SMD component 90. The second embedded portion 108 may be opposite the first embedded portion 60 and coupled to the first embedded portion 60, and the first embedded portion 60 and the second embedded portion 108 may be interconnected by a build-up interconnect structure 70 to form a semiconductor module, module or semiconductor die module 110. Molding of the encapsulant 106 may occur before or after singulation by a saw blade or laser cutting tool 98 to form the semiconductor modules 110.

Fig. 2K shows a semiconductor module, module or semiconductor die module 114, which is similar to the semiconductor module 110 shown in fig. 2J. Module 114 shows some additional features that may optionally be included in addition to those shown in modules 100 and 110. For example, the semiconductor module 114 may further include: a first set of input/output (i/o) connectors or pads 116 of the module 114, which may be adapted to couple to a battery; and a second set of i/o connectors or pads 118 of the module 114 adapted to couple to a display or screen. In some cases, the cells may be electrically connected to at least 2 terminals or pads 116 of the module 114. In some cases, the display may be electrically connected to the module 114 through a flexible connector. Further, optionally, solder balls or other suitable electrical interconnect components may be attached to the module 114 (such as a top or bottom portion of the module 114) as i/o interconnects.

As further shown in fig. 2K, the module 114 may also include an embedded device, passive component, or 3D interconnect component 120 integrated within the thickness of the molding compound 42 (alongside the semiconductor die 14 within the first embedded portion 60). In some cases, the embedded device 120 may include SMDs 122 coupled to vertical interconnects or substrates 124, which together may form the embedded device 120. In other cases, the embedded device may be only SMDs 122 or only vertical interconnects 124. In some cases, the embedded device 120 may be formed within the module 114, as disclosed in U.S. application No. 15/141,028, filed 2016, 4-28, U.S. patent No. 9,502,397, entitled three-dimensional Interconnect for all-mold packaging (3D Interconnect for filled Molded Packages), the disclosure of which is incorporated herein by reference in its entirety.

Fig. 2K also shows that the module 114 may also include a shielding layer 126. The shield 126 may include one or more conductive or metallic materials such as Al, ferrite or carbonyl iron, stainless steel, nickel silver, mild steel, silicon iron steel, foil, conductive resins, and other metals and composites capable of blocking or absorbing electromagnetic interference (EMI), Radio Frequency Interference (RFI), harmonic distortion, and other inter-device interference. The shield layer 126 may be patterned and conformally (conformally) deposited using electrolytic plating, electroless plating, sputtering, PVD, CVD, or other suitable deposition procedure. The shield layer 126 may also be a non-metallic material, such as carbon black or aluminum flakes, to reduce EMI and RFI effects. For non-metallic materials, the barrier layer 126 may be applied by lamination, spraying, painting, or other suitable procedure. The shield layer 126 may also be electrically connected to an external low impedance ground point. A shield layer 126 may be added over the upper and lower portions of module 114, and a backside contact between one or more of the semiconductor die or SMT features (such as backside 18 of semiconductor die 14) may contact, directly contact, or be coupled to shield layer 126. In some cases, contact between the side, surface, or backside of one or more semiconductor dies or SMT features and the shield layer 126 may be used as a heat spreader or for thermal management. Optionally, the shielding layer 126 may be formed as a conformable EMI shield that may cover all or most of the top and side surfaces of the module 114, including 90% to 100% of the top and side surfaces, and in some cases the shielding layer 126 may also cover more than 50% of the sixth side of the module 114 (such as the bottom side of the module 114).

FIG. 3 shows a non-limiting example of a program flow or chart 130 for forming a module (such as module 100,110,114) or similar module (such as a thermally enhanced full mold fan-out module). The process flow 130 is shown in schematic form and described with respect to elements, acts, steps or procedures 132-162. Elements 132-162 are presented by way of illustration, and not limitation, and although elements may be performed in the order or sequence presented below, they are not required. Fewer or additional elements used to form a module, as well as the order or sequence of various elements, may be modified.

At element 132, the electrical interconnects 28 may be electroplated on the plurality of semiconductor dies 14 at the level of the native semiconductor wafer 12. At element 134, each of the semiconductor wafers 12 may be probed to test a respective function of the semiconductor dies 14 in or on the semiconductor wafers 12. At element 136, the semiconductor wafer 12 may be thinned to a finished Si thickness of less than 500 μm or less than 350 microns. In element 138, the semiconductor die 14 may be singulated from the semiconductor wafer 12. In element 140, a known well-mounted semiconductor die 14 may be placed face-up on a temporary carrier or substrate 36. In element 142, semiconductor die 14 can be molded or encapsulated with an encapsulant or molding compound 42 to form a reconstituted wafer, embedded die panel, or plastic panel 58 of any desired size and shape. At element 144, carrier 36 can be removed to expose back side 18 of molded semiconductor die 14. At element 146, the second surface or front side 56 of the inset panel 58 can be subjected to a grinding procedure to expose the electrical interconnects 28. At element 148, panel 58 can be scanned to measure a position and orientation of each semiconductor die 14 within panel 58, within the plurality of first embedded portions 60, or within each first embedded portion 60.

At element 150, a build-up interconnect structure or high-density, multi-layer RDL wiring pattern 70 can be formed (using, for example, unit-specific patterning) to align the build-up interconnect structure 70 with each semiconductor die 14. At element 152, a photoimageable solder mask material 84 may be formed over the final RDL layer to form SMD land pads 86. At element 154, a solderable surface treatment may be applied over the exposed SMD land pads 86 to facilitate surface mount assembly of the component. In element 156, panel 58 can optionally be probed to test the functionality of each embedded portion 60 within panel 58. At element 158, optionally, panel 58 can be thinned by grinding or polishing the back of panel 58 to reduce the thickness of embedded semiconductor die 14, such as to a thickness of less than 250 μm. In element 160, the SMD component 90 may be attached to the SMD land pads 86 using an SMT assembly procedure, which may include screen printing a solder paste 97 over each SMD land pad 86 and placing the SMD component 90 on the panel 58 such that the solderable terminals 91 of the SMD component 90 contact the land pads 86 and the solder 97 may be reflowed to couple the SMD component 90 to the SMD pads 86 on the panel 58. Finally, at element 162, modular unit 100,110,114 may be singulated to separate the modular unit from panel 58.

Accordingly, several advantages may be provided or facilitated by modules 100,110, and 114, an exemplary and non-limiting list of which includes: improved control over the contact resistance of the contact pads 22 on the semiconductor die 14; improving the RF performance of the modules 110, and 114; improving thermal performance and power distribution of the module; the mechanical reliability of the module is improved; a planar surface for fine pitch lithography for building up interconnect structures 70; the molding compound 42 replaces the first fan-out dielectric layer; a high contrast surface for optical die position measurement between the encapsulant 42 and the conductive interconnects 28; fully protecting the semiconductor die 14 edges for low-k devices; and a flat surface with low panel warpage that simplifies SMT assembly.

Improved control over the contact resistance of contact pads 22 (such as Al contact pads 22) on semiconductor die 14 may be provided. The improvement over a face-down wafer level fan-out structure (WLFO), such as eWLB, typically requires sputtering of barrier layers and seed layers to a plastic panel or mold compound to contact Al bond pads or contact pads on the semiconductor die to prevent the formation of aluminum oxide. Plastic panels or plastic wafers can be problematic in sputter deposition of barrier layers, such as Ti or TiW barrier layers, because plastic tends to outgas (out-gas), and the presence of trace amounts of oxygen during sputter etching and before seed layer deposition (trace amount) forms a few angstroms of aluminum oxide on the contact pads, resulting in high contact resistance, which can hinder the performance of the semiconductor die. The management or prevention of alumina formation can be achieved by: storing the panel in nitrogen prior to sputtering; extending the outgassing time in a sputtering tool; extend pump down time to ensure very low base pressure in the etch chamber; or through other suitable procedures. In the fully molded configuration of the first embedded portion 60 of the module 100,110 or 114, the electrical interconnects 28 may be positioned within the encapsulant 42 to provide superior contact resistance with respect to the Al or other contact pads 22 by applying the Cu or other conductive interconnects 28 to the Si or native wafer 10 as is done in a flip-chip bump or wafer WLP process. As a result, the contact pads 22 of the semiconductor die 14 are protected by the molded or encapsulated bond between the electrical interconnects 28 and the contact pads 22, so that the process risk (exposure and oxidation) of the embedded die panel 58 or first embedded portion 60 is much lower compared to a face-down fan-out structure without pillars, posts, or pillars.

Improved RF performance of the module 100,110 or 114 may also be obtained by: disposing a layer of molding compound 42 over the active surface 20 of the semiconductor die 14 and around the electrical interconnects 28 may establish an offset or gap of about 10 μm to 100 μm, 20 μm to 50 μm, or 30 μm (plus or minus 5 μm) between the active surface 20 of the semiconductor die 14 and the stacked interconnect structure 70, the high-density multi-layer wiring layer, or the fan-out RDL layer. The additional offset may provide a buffer or space that facilitates desired performance of features having a higher quality factor (Q), such as inductors.

By forming conductive interconnects 28 of any size and shape, improved thermal performance and power distribution of modules 100,110, and 114 may also be obtained. For example, the conductive interconnects 28 may be formed with small fine pitch Cu pillars, with large Cu pillars, and may also include power or ground planes formed on the same semiconductor die 14. Because the conductive interconnects 28 can be planarized after the molding compound 42 is placed over the front side 20 of the upward-facing semiconductor die 14, concerns over bump height uniformity are reduced or eliminated (even with large variations in bump size or size of the conductive interconnects 28 coupled to the semiconductor die 14). With little or no concern regarding bump size uniformity, large areas of conductive interconnects (including Cu interconnects) can be used to more efficiently distribute power to the semiconductor die 14. In some cases, a plane of thick Cu may be established as part of the conductive interconnect 28, or as one or more conductive interconnects 28, to improve thermal performance. Furthermore, the thickness of the Cu layer may be adjusted to tailor the performance for different applications. The above advantages may be achieved with respect to any "chip-on-chip" or flip-chip type structure in which all solder bumps or conductive interconnects must have identical, or substantially similar sizes and shapes.

Improved mechanical reliability of modules 100,110 and 114 may also be obtained by adding molding compound 42 over the face or active surface 20 of semiconductor die 14 and over and around die edge 17. In particular, in designs having SMD land pads 86 positioned over the edge 17 of the semiconductor die 14, the fully molded structure or first embedded portion 60 may provide a planar surface that is mechanically isolated from the topography of the semiconductor die edge 17. In a face down fan-out structure, the fan-out stack-up under the SMD component can be mechanically coupled at least in part to the semiconductor die and in part to the molding compound, which can result in high thermo-mechanical stress on interconnects (such as solder points), causing solder point failure or other failures.

The improvements of modules 100,110, and 114 may also include a flat surface for fine pitch lithography (which may be present because the embedded die panel 58 is planarized after molding), facilitating fine pitch lithography, such as forming the build-up interconnect structure 70 at a small depth of field in the exposure. Further, a first layer of the build-up interconnect structure 70 (whether a dielectric layer such as insulating layer 72 or a metal layer such as conductive layer 74) can be formed over the single molding compound 42 with the coplanar exposed surfaces or ends of the conductive interconnects 28. The above improvements are in contrast to face-down fan-out or embedded die in substrate structures where a first layer is formed over more than one substrate material, such as a semiconductor die and an encapsulant surrounding the semiconductor die. Thus, feature size is limited only by the capabilities of the lithography tool, which now, using roadmapping, can be lines and spaces in the range of about 2 μm to 5 μm (or 4 μm to 10 μm pitch) or less. A thinner photopolymer layer can be applied to the panel because there is no edge profile as in a face-down structure. With a flat-faced up structure, there is no problem with very fine traces running across the die edge.

The improvement of modules 100,110, and 114 may also include the mold compound 42 replacing the first fan-out dielectric layer, such as insulating layer 72, such that the first conductive layer 74 is placed in direct contact with the encapsulant 42. Omitting the first fan-out dielectric layer and applying the fan-out RDL 74 directly to the embedded die panel 58 may reduce cost, which may be beneficial for smaller components with low interconnect density.

Within the in-line die panel 58, there may also be a high contrast surface for optically measuring the position of the semiconductor die 14 relative to the encapsulant 42. The fully molded structure performs well during inspection because it creates a very high contrast surface for inspection, which may include, for example, Cu bumps appearing white against a black background. The encapsulant 42 over the active surface 20 of the semiconductor die 14 removes distracting features from the optical inspection process that are present at the active surface 20 and that may slow or complicate inspection. Thus, the high contrast images produced by current designs allow for very fast and reliable scanning, reducing cost.

The improvements of modules 100,110, and 114 also allow for complete protection of die edge 17 for low-k devices. Low-k devices typically require the formation of laser grooves prior to dicing of the semiconductor die, which can create additional topography at the die edges. Laser slots prior to cutting are an additional process step that adds time and expense, but are generally a necessary step to prevent certain failure modes. This particular failure mode occurs in the face-down structure, which lifts or moves the test pads in the saw lanes during singulation, so that when a thin photopolymer layer is used, the lifted pads (which are conductive) will contact or short the RDL or interconnect structure. The presently disclosed modules 100,110 and 114 allow for complete encapsulation of sensitive die edge structures with a single mold compound 42, rather than forming the mold compound to the photopolymer interface at or near the edges of the low-k device structures to avoid lifted structures and prevent shorting.

The improvements of modules 100,110 and 114 also allow for a flat surface with low warpage of embedded die panel 58, which simplifies SMD and SMT assembly. The structure of modules 100,110 and 114 may be balanced with portions or layers of encapsulant 42 of similar thickness and material properties disposed on the top and bottom of semiconductor die 14. Thus, the stresses induced by the CTE mismatch between the semiconductor die 14 and the encapsulant 42 may be substantially balanced on both sides of the semiconductor die 14. Thus, the embedded die panel 58 may remain relatively flat during SMT procedures and mounting of the SMD component 90 (which may include placing the component at room temperature followed by reflowing the solder at an elevated temperature in excess of 230 degrees celsius).

While this disclosure includes several embodiments in different forms, specific embodiment details are presented in the drawings and the following written description with the understanding that the present disclosure is to be considered an exemplification of the disclosed methods and systems and principles, and is not intended to limit the broad aspect of the disclosed concepts to the embodiments illustrated. Further, those of skill in the art will appreciate that other structures, fabrication devices, and examples can be intermixed with or substituted for the structures, fabrication devices, and examples provided. Where the description above refers to particular embodiments, it should be apparent that several modifications may be made without departing from the spirit thereof, and that these embodiments and implementations may also be applied to other technologies. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the present disclosure and within the knowledge of those skilled in the art. It will, therefore, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of such invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims (17)

1. A semiconductor module, comprising:

a fully molded base portion comprising:

the surface of the flat plate is provided with a plurality of grooves,

a first semiconductor die and a second semiconductor die disposed inside the fully molded base portion, the first and second semiconductor dies each including an active surface including a contact pad,

a conductive pillar coupled to the contact pads of the first and second semiconductor dies, the conductive pillar extending to the planar surface, and

an encapsulant disposed over the active surface, over four side surfaces, and surrounding the conductive pillars, wherein tips of the conductive pillars are exposed from the encapsulant at a planar surface of the fully molded base portion;

a build-up interconnect structure including a wiring layer disposed over the fully molded substrate portion and interconnected with the first and second semiconductor die;

a Surface Mount Device (SMD) land pad formed on the build-up interconnect structure and electrically coupled to the first semiconductor die, the second semiconductor die, and the conductive pillar;

an SMD component electrically coupled to the SMD land pads using Surface Mount Technology (SMT);

a second encapsulant disposed over and around the SMD component to form a fully molded top portion;

a shield layer disposed on the encapsulant of the fully molded base portion and the second encapsulant of the fully molded top portion, the shield layer coupled with the build-up interconnect structure;

a first output connector of the module adapted to be coupled to a battery; and

a second connector of the module adapted to couple to a display.

2. The semiconductor module of claim 1, wherein the SMD component includes at least one of a semiconductor die, a wafer-level chip scale package (WLCSP), an Integrated Circuit (IC), a surface-mounted device, an active device, or a passive device, or a solderable passive device such as a resistor or a capacitor.

3. The semiconductor module of claim 1, wherein the SMD component electrically coupled to the SMD land pads further comprises:

said SMD component including solderable terminals;

a solder paste disposed over the SMD land pads; and is

The solderable terminal is disposed over and electrically coupled to the SMD land pads when the solderable terminal is in contact with the solder paste.

4. The semiconductor module of claim 3, wherein the SMD land pads include a solderable surface treatment: nickel (Ni) and gold (Au); ni, palladium (Pd), and Au; tin (Sn); welding flux; or an Organic Solderability Preservative (OSP).

5. The semiconductor module of claim 1, wherein the SMD component is coupled to the land pads with solder bumps.

6. The semiconductor module of claim 1, wherein the build-up interconnect structure comprises a high-density multilayer wiring layer.

7. The semiconductor module of claim 1, wherein:

the SMD component is partially within a footprint of the semiconductor die and partially not within a footprint of the semiconductor die; and is

At least one of the SMD land pads is positioned over an edge of a footprint of the semiconductor die within the fully molded base portion.

8. A semiconductor module, comprising:

a fully molded substrate portion comprising:

a flat surface;

a semiconductor die disposed inside the fully molded base portion, the semiconductor die including an active surface including a contact pad,

a conductive post coupled to the contact pad and extending to the planar surface, an

An encapsulant disposed over the active surface, over four side surfaces, and around the conductive pillars, wherein tips of the conductive pillars are exposed from the encapsulant at a planar surface of the fully molded base portion;

a build-up interconnect structure including a wiring layer disposed over the fully molded substrate portion;

an SMD component electrically coupled to the routing layer:

a second encapsulant disposed over and around the SMD component to form a fully molded top portion; and

a shield layer disposed over the encapsulant of the fully molded base portion and the second encapsulant of the fully molded top portion, the shield layer coupled to the build-up interconnect structure.

9. The semiconductor module of claim 8, wherein the SMD component electrically coupled to the routing layer further comprises:

said SMD component including solderable terminals;

a solder paste disposed over the wiring layer; and is provided with

The solderable terminations are disposed over and electrically coupled to the wiring layer when the solderable terminations are in contact with the solder paste.

10. The semiconductor module of claim 8, wherein:

the SMD component includes one or more of a semiconductor die, a Wafer Level Chip Scale Package (WLCSP), an Integrated Circuit (IC), a surface mount device, an active device, or a passive device, or a solderable passive device such as a resistor or capacitor; and

a second encapsulant is disposed over and around the SMD component to form a fully molded top portion.

11. The semiconductor module of claim 8, wherein:

the SMD component is partially within a footprint of the semiconductor die and partially not within a footprint of the semiconductor die.

12. The semiconductor module of claim 8, wherein a material of an encapsulant of the fully molded base portion is the same as a material of the second encapsulant of the fully molded top portion.

13. A method of fabricating a semiconductor module, comprising:

forming an electrical interconnect on the semiconductor die;

encapsulating the semiconductor die with a first encapsulant to form a first embedded portion, wherein the electrical interconnect is exposed from the first encapsulant;

forming a build-up interconnect structure comprising a conductive RDL layer over the first embedded portion after encapsulating the semiconductor die, the build-up interconnect structure electrically connected to the electrical interconnect;

forming a Surface Mount Device (SMD) land pad electrically coupled to the conductive RDL layer;

coupling an SMD component to the SMD land pads using Surface Mount Technology (SMT) to provide an electrical connection between the SMD component and the semiconductor die through conductive pillars and the build-up interconnect structure; and

a second encapsulant is provided, the second encapsulant being disposed over and around the SMD component to form a fully molded top portion.

14. The method of claim 13, further comprising forming the build-up interconnect structure comprising the conductive RDL layer, the conductive RDL layer adjusted by unit-specific patterning to compensate for movement of the semiconductor die within the first embedded portion.

15. The method of claim 13, wherein the SMD component includes a semiconductor die, a wafer-level chip scale package (WLCSP), an Integrated Circuit (IC), a surface-mounted device, an active device, or a passive device, or a solderable passive device such as a resistor or capacitor.

16. The method of claim 13 further comprising electrically testing the semiconductor die within the first embedded portion prior to coupling any of the SMD components to the first embedded portion.

17. The method of claim 13, further comprising coupling the SMD component to the SMD land pads such that the SMD component is partially within a footprint of the semiconductor die and partially not within a footprint of the semiconductor die.