HK1249946B - Modulating processor core operations - Google Patents

Description

Regulating processor core operations

Technical Field

This specification relates to techniques for modifying processor performance.

Background Art

Modern computer processors typically include multiple independent processor cores. Current computing systems have been optimized to efficiently process events that take milliseconds (through various programming mechanisms supported by the operating system, such as process context switching) or tens of nanoseconds (through hardware processor features, such as prefetching, out-of-order execution, prediction, etc.).

In particular, efficiently supporting events that take several microseconds remains a challenge when low-latency response times are required. Such microsecond-granularity events are becoming more common with the advent of high-performance networking fabrics, new non-volatile storage technologies such as flash and phase-change memory, or data exchange using computational accelerators such as graphics processing units (GPUs). Microsecond-scale events are too short to incur the overhead of context switches and operating system interrupts, yet too long to be easily addressed by hardware processor architecture features in today's microprocessors.

Dedicating a processor core to handling a specific low-latency operation (sometimes referred to as spinning) is a possible solution to achieving low latency in microsecond granularity operations. However, dedicating a processor to a specific I/O operation can deduct a large amount of computing power from a multi-core processor.

Summary of the Invention

In general, one innovative aspect of the subject matter described herein can be embodied in a method comprising actions implemented in a multi-core processor having n cores, including: selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, m cores are unselected, and each core of the multi-core processor has a rated core capacity. The method operates the selected k cores at less than the rated core capacity, such that the k cores are collectively underutilized due to underutilized capacity, and operates one or more of the m cores at a capacity exceeding the rated core capacity, such that the m cores operate at a collective capacity exceeding the rated core capacity of the m cores.

Other embodiments of this aspect include corresponding systems, apparatus, and computer programs configured to perform the actions of the method encoded on computer storage devices.

Specific embodiments of the subject matter described in this specification can be implemented to achieve one or more of the following advantages. The present systems and methods enable a specific number of independent processor cores of a multi-core processor to be dedicated to performing only input/output (I/O) operations but at a reduced operating capacity, which in turn provides additional operating capacity for the remaining cores of the multi-core processor. Dedicating processor cores to low-latency operations can achieve consistent low latency for the multi-core processor while reducing the negative effects of dedicating cores to low-latency operations at full capacity. By dedicating processor cores to low-latency operations at a reduced capacity, energy available from underutilized dedicated processor cores can be used to improve the performance of the remaining cores in the multi-core processor.

The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

1 is a block diagram of an environment in which a certain number of processor cores may be dedicated to low-latency operations, where each dedicated processing core is underutilized.

2 is a flow diagram of an example process for improving the performance of a generally operating processor core by using excess energy from an underutilized processor core.

Like reference numbers and designations throughout the various drawings indicate like elements.

DETAILED DESCRIPTION

The systems and methods described below relate to enabling independent processor cores within a multi-core CPU (e.g., a processor) to achieve low latency and improve overall general-purpose processor core performance. In some embodiments, a first group of processor cores in a multi-core processor is dedicated to performing low-latency operations. For example, low-latency operations may include input/output (I/O) operations, accessing data in a memory (e.g., a solid-state drive, a flash memory device, etc.) that communicates with other processor cores, non-volatile storage technologies such as supercomputing network structures for exchanging very fast messages (e.g., 1 μS-100 μS), and other low-latency operations. The second group of processor cores in a multi-core processor is not limited to processor cores that only perform low-latency operations. For example, the second group of processor cores can perform a large number of different operations required by the processor. Typically, for an n-core processor, k cores are selected for dedicated low-latency operations, and the remaining cores are selected to perform the remaining operations. However, the second group of cores does not necessarily include the remaining cores. For example, for an n-core processor, when n-k=m, the second group of cores can have a cardinality of m or less than m.

Typically, multi-core processors with processor cores dedicated to low-latency operations underutilize the dedicated low-latency processor cores, leaving unused amounts of available energy. Multi-core processors can reduce the amount of power (e.g., voltage/frequency) utilized by the low-latency processor cores. The excess power capacity created by reducing the power consumption of the low-latency processor cores can be added to the overall power capacity available to the remaining general-purpose processor cores. Utilizing the additional power capacity available to the general-purpose processor cores improves the performance of the remaining general-purpose processor cores, eliminating some stranded computing capacity.

These and other features are described in more detail below.

FIG1 is a block diagram of an environment 100 in which a specific number of processor cores can be dedicated to low-latency operations, wherein each dedicated processing core is not fully utilized. As shown, environment 100 includes a multi-core processor 102 connected to a bus 108. Bus 108 communicatively couples processor 102 to a set of external resources, including flash memory 110, random access memory (RAM) 112, and a graphics processing unit (GPU) 114. Multi-core processor 102 includes processor cores 104-1 to 104-n (n cores) operable to execute instructions. Multi-core processor 102 also has a first group of k processor cores 106 including processor core 104-1 and processor core 104-2. Although the value of k is 2 in the example of FIG1 , other values of k may be utilized.

The multi-core processor 102 can be a single central processing unit (CPU) chip that includes multiple processor cores, memory resources, and other components. The multi-core processor 102 can also include firmware or microcode instructions stored in on-chip memory and operable to implement the techniques described herein. In some embodiments, the instructions necessary to implement the techniques described herein can be implemented in silicon. The multi-core processor 102 can also include multiple processors, each processor including its own processor core, memory resources, and/or other components.

The multi-core processor 102 is connected to a data bus 108. In some embodiments, the data bus 108 may be a high-speed data transfer mechanism for transferring data between components within a computing device chassis. The data bus 108 may be any type of bus capable of performing such data transfer.

A number of resources, including flash memory 110, RAM 112, and GPU 114, are connected to data bus 108. In some implementations, additional resources may be connected to data bus 108, including, but not limited to, a direct memory access (DMA) controller, a graphics card, a network card, a RAID controller, and/or other resources.

As shown, the multi-core processor 102 includes processor cores 104-1 through 104-n. The processor cores 104-1 through 104-n may be separate components connected to other components of the multi-core processor 102 via data buses or bridges. The multi-core processor 102 includes processor cores 104-1 through 104-n, where n is any suitable number of processor cores for performing the common multi-core processor 102 functions.

Each processor core 104 in the multi-core processor 102 has a rated core capacity. The rated core capacity can be a measure of maximum performance capacity (e.g., the highest voltage/frequency ratio that the processor core can achieve and maintain proper operation of the processor core without causing damage to the processor core), which describes how much power each processor core 104 can consume without causing damage to the processor core. Capacity can be measured in various ways, such as by power consumption, maximum frequency, maximum frequency for a given voltage, maximum current, maximum operating temperature, or by any other measurement that indicates core power consumption.

In some implementations, the processor core 104 may include other integrated components, for example, dedicated cache memory such as an L1 cache, hardware context storage, firmware storage, microcode storage, and/or other integrated components.

Threads may be assigned to processor cores 104-1-n. In some implementations, a thread may be a collection of instructions to be executed on a processor core 104. For example, a thread may be a software application executing on a multi-core processor 102. A thread may also be one of many threads within a single software application executing on a multi-core processor 102.

The k processor cores 106 can be a specific number of processing cores dedicated only to low-latency operations. When dedicated only to I/O operations, the k processor cores 106 cannot be used by the operating system scheduler to assign general processing tasks and only execute instructions related to I/O (e.g., retrieving/sending data from flash memory 110, retrieving/sending data from RAM 112, retrieving/sending data from GPU 114, etc.). In some embodiments, low-latency operations are microsecond low-latency operations as a measure of the speed of each operation. In other embodiments, the low-latency operations that can be performed by dedicated cores can include nanosecond and microsecond operations. As shown in Figure 1, the k processor cores 106 include two processor cores 106-1 and 106-2. In some embodiments, the k processor cores 106 may include any suitable number of processor cores, but less than the total number of processing cores to ensure the proper operation of the processor 102, that is, k<n.

The k processor cores 106 reduce the latency of the processor 102 by reducing the response time of the multi-core processor 102 for low-latency operations. The response time of the multi-core processor 102 is reduced by running low-latency operations in k cores, which eliminates the need to pause other threads in the remaining m cores so that low-latency operations can be performed by the other cores.

The k processor cores 106 are not utilized to their full capacity due to high utilization, resulting in a temporary buildup of processing queues, which increases latency in the processor 102. The remaining processor cores 104-k through 104-n (e.g., m cores) are dedicated to general processing tasks. Typically, the number m of remaining processor cores 104-k through 104-n is equal to the total number of processing cores minus the k processor cores 106. For example, in an n-core processor, the number of n cores is equal to the number of m cores plus the number of k cores.

To reduce the consumption of processing cores, processor 102 can periodically cycle the selection of k cores (e.g., dedicated low-latency processor cores) in the multi-core processor. Cycling the k cores ensures that each core is underutilized for the same period of time as the other cores during a certain time period, which promotes uniform consumption among the processing cores.

As previously mentioned, each of the k processor cores 106 used as dedicated low-latency processor cores is not fully utilized. Each core in a multi-core processor has a rated core capacity. Typically, the rated core capacity is the same for each core.

Each of the k processor cores consumes less power than the full rated core capacity. The remaining excess power capacity from the k processor cores 106 is used by the m cores to improve the performance of the m cores. Our solution relies on the fact that modern multi-core CPUs are built so that not all cores can run at their maximum performance simultaneously (see earlier Dark Silicon references), because doing so would require more energy than the CPU package is able to dissipate while staying within the operating temperature range. Therefore, the CPU can have a subset of its cores run at their maximum performance (highest frequency/voltage setting) only when the remaining CPUs are less active, thereby generating less heat and potentially running at a lower frequency/voltage setting.

For a given thermal design power (TDP) constraint, the underutilization of k cores can be considered the amount of silicon that can be powered at the nominal operating voltage. The resulting commensurate reduction in general-purpose computing power is less than k/n, which reduces the negative impact of specialized cores achieving relatively low latency for microsecond I/O operations.

2 is a flow diagram of an example process for using excess energy to improve the performance of general-purpose operating processor cores as a result of underutilized processor cores.

This process may be implemented in a multi-core processor having n cores.The multi-core processor 102 has an energy rating/capacity of n*E, where n is the number of cores and E is the rated core capacity of each core.

The process selects k cores out of n cores of the multi-core processor 102 to perform dedicated input/output operations for the n-core processor 102, where k is less than n and m cores are not selected, and where each core of the multi-core processor has a rated core capacity (202). The rated core capacity is a technical limit (e.g., thermal design power, clock speed, power consumption, etc.) at which the processing core 104 can operate without suffering damage. For example, the rated core capacity can be a rated core operating frequency, a rated core power consumption, a rated core operating temperature, or a ratio of the amount of voltage utilized by the processing core per clock speed (i.e., frequency).

In some embodiments, the rated core capacity is equal to the maximum performance level of the processing core 104 (e.g., the highest voltage/frequency ratio that the processing core can achieve and maintain proper operation of the processing core without causing damage to the processing core). Also note that a core can operate beyond its rated capacity for some period of time without suffering damage.

Furthermore, an n-core processor may have a processor rated capacity. The rated capacity of the processor may be equal to the sum of the rated core capacities, e.g., n*E. However, for some processors, the rated processor capacity may be less than the sum of the rated core capacities. This is due to the dark silicon effect, which defines the amount of silicon that cannot be powered at the nominal operating voltage for a given thermal design power (TDP) constraint.

The process operates the selected k cores at less than the rated core capacity, such that the k cores are collectively underutilized due to the underutilized capacity (204). As previously described, the k cores operate at z capacity and the underutilized capacity (u) can be calculated according to the following equation (1):

u＝(100% capacity-z capacity) (1)

The underutilized capacity provides additional power availability to the multi-core processor 102. For the reasons set forth above, not all of the underutilized capacity may be utilized by the processor.

The process operates one or more of the m cores at a capacity exceeding the rated core capacity such that the m cores operate at a collective capacity exceeding the collective rated core capacity of the m cores (206). In some embodiments, the processor 102 may select fewer than all remaining cores to operate at a capacity exceeding the rated core capacity, but still operate at a capacity greater than the sum of all remaining processor cores. One or more of the m cores may operate at or up to an energy level/capacity described by the following equation (2):

m-core power utilization rate = [(n-k)+(u)*k]*E (2)

In some embodiments, operating one or more of the m cores at a capacity exceeding the rated core capacity includes operating one or more of the m cores at a capacity temporarily exceeding the sum of the m rated core capacities and underutilized capacity. One or more processor cores may individually or collectively temporarily exceed the rated core capacity.

In other embodiments, operating one or more of the m cores at a capacity exceeding the rated core capacity includes operating one or more of the m cores at a capacity that does not exceed the sum of the m rated core capacities and the underutilized capacity. The m rated cores may be operated at a capacity that only exceeds the underutilized capacity of k cores, which may be less than or equal to the rated processor capacity. For example, operating one or more of the m cores at a capacity exceeding the rated core capacity includes operating one or more of the m cores at a capacity such that the sum of the capacities at which the m cores are operating and the sum of the capacities at which the k cores are operating does not exceed the rated capacity of the processor.

Similar to the rated core capacity, the rated processor capacity can be described as the technical limit at which a processor can operate without suffering damage while still operating at an optimal performance level (e.g., a voltage/frequency ratio that produces fast performance without consuming too much power). The processor rated capacity can be defined as the sum of the rated core capacities of the lesser n cores.

In situations where the systems discussed herein collect personal information about users or can utilize personal information, users can be provided with the opportunity to control whether applications or features collect user information (e.g., information about the user's social network, social actions or activities, occupation, the user's preferences, or the user's current location) or to control whether and/or how content that may be more relevant to the user is received. In addition, certain data can be processed in one or more ways before it is stored or used so that personally identifiable information is removed. For example, the user's identity can be processed so that personally identifiable information cannot be determined for the user, or the user's geographic location can be generalized (such as to a city, zip code, or state level) if location information is available so that the user's specific location cannot be determined. Thus, users can control how information is collected about them and used by content servers.

Embodiments of the subject matter and operations described in this specification may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of these. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs (i.e., one or more modules of computer program instructions) encoded on computer storage media for execution by, or to control the operation of, data processing apparatus.

A computer storage medium can be or be included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. Additionally, while a computer storage medium is not a propagated signal, a computer storage medium can be a source or destination of computer program instructions encoded in an artificially generated propagated signal. A computer storage medium can also be or be included in one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices).

The operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

The term "data processing device" includes all types of equipment, devices and machines for processing data, including, by way of example, a programmable processor, a computer, a system on a chip or multiple programmable processors, computers, systems on a chip, or a combination thereof. The device may include dedicated logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, the device may also include code that creates an execution environment for the computer program, for example, code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of these. The device and execution environment can implement a variety of different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructure.

A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but does not necessarily, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated files (e.g., files that store portions of one or more modules, subroutines, or code). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input data and generating output. The processes and logic flows can also be performed by, and the apparatus can also be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

As an example, processors suitable for executing computer programs include both general-purpose microprocessors and special-purpose microprocessors, as well as any one or more processors of any type of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a processor for performing actions in accordance with instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, or be operationally coupled to receive data from one or more mass storage devices for storing data or transfer data to one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks. However, a computer does not necessarily have such devices. In addition, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name a few. Suitable means for storing computer program instructions and data include all forms of nonvolatile memory, media, and storage devices, including, by way of example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory can be supplemented by, or incorporated in, special purpose logic circuitry.

To provide for interaction with a user, embodiments of the subject matter described in this specification may be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user, and a keyboard and pointing device, such as a mouse or trackball, that the user can use to provide input to the computer. Other types of devices may also be used to provide for interaction with the user; for example, feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user may be received in any form, including acoustic, voice, or tactile input. In addition, a computer may interact with a user by sending documents to and receiving documents from a device used by the user; for example, by sending web pages to a web browser on a user's user device in response to a request received from the web browser.

Embodiments of the subject matter described in this specification may be implemented in a computing system that includes a back-end component (e.g., as a data server), or includes a middleware component (e.g., an application server), or includes a front-end component, such as a user computer having a graphical user interface or a web browser that a user can use to interact with implementations of the subject matter described in this specification, or includes any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), internetworks (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).

A computing system may include a user and a server. The user and the server are typically remote from each other and typically interact via a communication network. The relationship between the user and the server arises by means of computer programs running on respective computers and having a user-server relationship with each other. In some embodiments, the server sends data (e.g., an HTML page) to the user device (e.g., to display data to a user interacting with the user device and to receive user input from the user interacting with the user device). Data generated at the user device (e.g., the results of the user interaction) may be received at the server from the user device.

Although this specification contains many specific implementation details, these should not be interpreted as limiting the scope of any feature or that may be claimed, but rather as descriptions of features specific to a particular embodiment. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable subcombination. Furthermore, although features may be described above as acting in accordance with certain combinations and therefore even initially claimed, one or more features from a claimed combination may in some cases be deleted from that combination, and a claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed to achieve the desired results. In some cases, multitasking and parallel processing can be advantageous. Furthermore, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing may be advantageous.

Claims (22)

1. A method implemented in a multi-core processor with n cores, comprising: Select k cores from the n cores of the multi-core processor to perform dedicated low-latency operations for the multi-core processor, wherein: k is less than n; m cores were not selected; and Each core of the multi-core processor has a rated core capacity; Operating the selected k cores below the rated core capacity, such that the k cores are collectively underutilized due to underutilized capacity; and One or more of the m cores are operated at a capacity exceeding the rated core capacity, such that the m cores operate at a collective capacity exceeding the collective capacity of the rated core capacity of the m cores, and wherein the selection of the k cores in the multi-core processor is periodically cyclical, such that a different group of k cores is selected each time. 2. The method of claim 1, wherein operating one or more of the m cores at a capacity exceeding the rated core capacity comprises: operating one or more of the m cores at a capacity not exceeding the sum of the rated core capacity of the m cores and the underutilized capacity. 3. The method of claim 1, wherein operating one or more of the m cores at a capacity exceeding the rated core capacity comprises: operating one or more of the m cores at a capacity temporarily exceeding the sum of the rated core capacity and the underutilized capacity. 4. The method according to claim 1, wherein: The multi-core processor has a rated processor capacity; and Operating one or more of the m cores at a capacity exceeding the rated core capacity includes operating one or more of the m cores at a capacity such that the sum of the capacities at which the m cores are operating and the sum of the capacities at which the k cores are operating do not exceed the rated capacity of the processor. 5. The method according to claim 4, wherein the rated capacity of the processor is less than the sum of the rated core capacities of the n cores. 6. The method according to claim 1, wherein the rated core capacity is the rated core operating frequency. 7. The method according to claim 1, wherein the rated core capacity is the rated core power consumption. 8. The method according to claim 1, wherein the rated core capacity is the rated core operating temperature. 9. The method according to claim 1, wherein k+m equals n. 10. The method of claim 1, wherein the dedicated low-latency operation includes at least one of memory access operation, I/O operation, and inter-processor communication. 11. The method of claim 10, wherein the I/O operation is a microsecond I/O operation. 12. A non-transitory storage medium that communicates data with a multi-core processor having n cores and stores instructions for the multi-core processor to perform operations, the operations including: Select k cores from the n cores of the multi-core processor to perform dedicated low-latency operations for the multi-core processor, where k is less than n, and m cores are not selected, and each core of the multi-core processor has a rated core capacity; Operating the selected k cores below the rated core capacity, such that the k cores are collectively underutilized due to underutilized capacity, and the selection of the k cores in the multi-core processor is periodically cyclical; and One or more of the m cores are operated at a capacity exceeding the rated core capacity, such that the m cores operate at a collective capacity exceeding the collective capacity of the rated core capacity of the m cores. 13. The non-transitory storage medium of claim 12, wherein operating one or more of the m cores at a capacity exceeding the rated core capacity comprises: operating one or more of the m cores at a capacity not exceeding the sum of the rated core capacity of the m cores and the underutilized capacity. 14. The non-transitory storage medium of claim 12, wherein operating one or more of the m cores at a capacity exceeding the rated core capacity comprises: operating one or more of the m cores at a capacity temporarily exceeding the sum of the rated core capacity and the underutilized capacity. 15. The non-transitory storage medium according to claim 12, wherein: The multi-core processor has a rated processor capacity; and Operating one or more of the m cores at a capacity exceeding the rated core capacity includes operating one or more of the m cores at a capacity such that the sum of the capacities of the m cores being operated and the sum of the capacities of the k cores being operated do not exceed the rated capacity of the processor. 16. The non-transitory storage medium according to claim 15, wherein the rated capacity of the processor is less than the sum of the rated core capacities of the n cores. 17. The non-transitory storage medium according to claim 12, wherein the rated core capacity is the rated core operating frequency. 18. The non-transitory storage medium according to claim 12, wherein the rated core capacity is the rated core power consumption. 19. The non-transitory storage medium according to claim 12, wherein the rated core capacity is the rated core operating temperature. 20. The non-transitory storage medium according to claim 12, wherein k+m equals n. 21. The non-transitory storage medium of claim 12, wherein the dedicated low-latency operation includes at least one of memory access operation, I/O operation, and inter-processor communication. 22. The non-transitory storage medium according to claim 21, wherein the I/O operation is a microsecond I/O operation.