HK1249807B - Radio-frequency switch modules and systems, wireless devices, semiconductor dies and methods for fabricating semiconductor dies - Google Patents

Description

Radio frequency switch module and system, wireless device, semiconductor bare core and manufacturing method thereof

This application is a divisional application of an invention patent application with an application date of July 6, 2013, application number 201380046576.5 (international application number PCT/US2013/049500), and invention name “Circuits, devices and methods related to radio frequency switches based on silicon on insulators and combinations thereof”.

Related applications

This application claims the benefit of priority under 35 U.S.C. §119(e) to the following U.S. provisional applications: U.S. Provisional Application No. 61/669,034, filed on July 7, 2012, entitled “RADIO-FREQUENCY SWITCH HAVING DYNAMIC BODY COUPLING”; U.S. Provisional Application No. 61/669,035, filed on July 7, 2012, entitled “SWITCH LINEARIZATION BY NON-LINEAR COMPENSATION OF AFIELD-EFFECT TRANSISTOR”; U.S. Provisional Application No. 61/669,037, filed on July 7, 2012, entitled “RADIO-FREQUENCY SWITCH HAVING DYNAMIC GATE BIASRESISTANCE AND BODY CONTACT”; and U.S. Provisional Application No. 61/669,038, filed on July 7, 2012, entitled “RADIO-FREQUENCY SWITCH HAVING DYNAMIC BODY COUPLING”. U.S. Provisional Application No. 61/669,039, filed on July 7, 2012, entitled “Switches Having Frequency-Tuned Body Bias”; U.S. Provisional Application No. 61/669,054, filed on July 7, 2012, entitled “Body-Gate Coupling to Reduce Distortion in Radio-Frequency Switch”; U.S. Provisional Application No. 61/760,561, filed on February 4, 2013, entitled “RF Switches Having Increased Voltage Swing Uniformity”; U.S. Provisional Application No. 61/760,561, filed on February 4, 2013, entitled “Switching Device Having A Discharge Circuit for Improved Intermodulation Distortion”; U.S. Provisional Application No. 61/669,039, filed on July 7, 2012, entitled “Body-Gate Coupling to Reduce Distortion in Radio-Frequency Switch” U.S. Provisional Application No. 61/669,042, filed on July 7, 2012, entitled “FEED-FORWARD CIRCUIT TO IMPROVE INTERMODULATION DISTORTION PERFORMANCE OF RADIO-FREQUENCY SWITCH”; U.S. Provisional Application No. 61/669,044, filed on July 7, 2012, entitled “RADIO-FREQUENCY SWITCH SYSTEM HAVING IMPROVED INTERMODULATION DISTORTION PERFORMANCE”; U.S. Provisional Application No. 61/669,045, filed on July 7, 2012, entitled “RADIO-FREQUENCY SWITCH SYSTEM HAVING IMPROVED INTERMODULATION DISTORTION PERFORMANCE”; U.S. Provisional Application No. 61/669,046, filed on July 7, 2012, entitled “ADJUSTABLE GATE AND/OR BODY RESISTANCE FOR IMPROVED INTERMODULATION DISTORTION PERFORMANCE OF RADIO-FREQUENCY U.S. Provisional Application No. 61/669,047, filed on July 7, 2012, entitled “RADIO-FREQUENCY SWITCH HAVING GATE NODE VOLTAGE COMPENSATION NETWORK”; U.S. Provisional Application No. 61/669,049, filed on July 7, 2012, entitled “RADIO-FREQUENCY SWITCH HAVING GATE NODE VOLTAGE COMPENSATION NETWORK”; U.S. Provisional Application No. 61/669,050, filed on July 7, 2012, entitled “BODY-GATE COUPLING TO IMPROVELINEARITY OF RADIO-FREQUENCY SWITCH”; and U.S. Provisional Application No. 61/669,050, filed on July 7, 2012, entitled “CIRCUITS, DEVICES, METHODS AND APPLICATIONS RELATED TO SILICON-ON-INSULATOR BASED RADIO-FREQUENCY SWITCHES”, the disclosure of which is expressly incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to a radio frequency switch system, a semiconductor die, a method for manufacturing a semiconductor die, a radio frequency switch module, and a wireless device.

Background Art

Radio frequency (RF) switches, such as transistor switches, can be used to switch signals between one or more poles and one or more throws. A transistor switch, or portions thereof, can be controlled by transistor biasing and/or coupling. The design and use of biasing and/or coupling circuitry associated with the RF switch can affect switch performance.

Summary of the Invention

In particular, various examples of circuits for coupling different portions of field effect transistors (FETs) and/or different FETs to produce a desired performance improvement for an RF switch system are disclosed. In some embodiments, one or more features of a given example can provide such a performance improvement. In some embodiments, features from different examples can be combined to produce such a performance improvement. For example, in the context below, certain embodiments disclosed herein provide a radio frequency (RF) switch comprising a plurality of field effect transistors (FETs) connected in series between a first and a second node, each FET having a gate and a body. The RF switch may further include a compensation network comprising a gate coupling circuit for coupling the gates of each pair of adjacent FETs, the compensation network further comprising a body coupling circuit for coupling the bodies of each pair of adjacent FETs. In some embodiments, at least some of the FETs are silicon-on-insulator (SOI) FETs. The gate coupling circuit may include a capacitor and may include a resistor in series with the capacitor.

In some embodiments, the gate coupling circuit includes a resistor. The body coupling circuit may include a capacitor. The body coupling circuit may further include a resistor connected in series with the capacitor. In some embodiments, the body coupling circuit includes a resistor.

Certain embodiments disclosed herein provide a process for operating a radio frequency (RF) switch. The process may include controlling a plurality of field effect transistors (FETs) connected in series between a first node and a second node so that the FETs are collectively in an on state or an off state. Each FET has a gate and a body. The process may further include coupling the gates of each adjacent FET to reduce a voltage swing across each of the plurality of FETs, and coupling the bodies of each adjacent FET to reduce a voltage swing across each of the plurality of FETs.

Certain embodiments disclosed herein provide a semiconductor die comprising a semiconductor substrate and a plurality of field-effect transistors (FETs) formed on the semiconductor substrate and connected in series, each FET comprising a gate and a body. The semiconductor die may further comprise a compensation network formed on the semiconductor die, the compensation network comprising a gate coupling circuit coupling the gates of each pair of adjacent FETs, and the compensation network further comprising a body coupling circuit coupling the bodies of each pair of adjacent FETs.

The semiconductor die may further include an insulator layer disposed between the FET and the semiconductor die. In some embodiments, the die is a silicon-on-insulator (SOI) die.

Certain embodiments provide a process for manufacturing a semiconductor die. The process may include providing a semiconductor substrate and forming a plurality of field effect transistors (FETs) on the semiconductor substrate, such that the plurality of field effect transistors (FETs) are connected in series, each FET having a gate and a body. The process may further include forming a gate coupling circuit on the semiconductor substrate to couple the gates of each pair of adjacent FETs, and forming a body coupling circuit on the semiconductor substrate to couple the bodies of each pair of adjacent FETs. In certain embodiments, the process further includes forming an insulator layer between the FETs and the semiconductor substrate.

Certain embodiments disclosed herein provide a radio frequency (RF) switch module comprising: a package substrate configured to house a plurality of components; and a semiconductor die mounted on the package substrate, the die comprising a plurality of field effect transistors (FETs) connected in series, each FET comprising a gate and a body. The RF switch module further comprises a compensation network comprising a gate coupling circuit coupling the gates of each pair of adjacent FETs, and a body coupling circuit coupling the bodies of each pair of adjacent FETs.

The semiconductor die can be a silicon-on-insulator (SOI) die. In some embodiments, the compensation network is part of the same semiconductor die as the plurality of FETs. The compensation network can be part of a second die mounted on a package substrate. In some embodiments, the compensation network is disposed at a location external to the semiconductor die.

Certain embodiments disclosed herein provide a wireless device comprising a transceiver and an antenna in communication with the transceiver, the transceiver being configured to process RF signals and the antenna being configured to facilitate transmission of amplified RF signals. The wireless device further comprises a power amplifier coupled to the transceiver and configured to generate the amplified RF signals, and a switch coupled to the antenna and the power amplifier and configured to selectively route the amplified RF signals to the antenna, the switch comprising a plurality of field effect transistors (FETs) coupled in series, each FET comprising a gate and a body, the switch further comprising a compensation network having a gate coupling circuit coupling the gates of each pair of adjacent FETs and a body coupling circuit coupling the bodies of each pair of adjacent FETs.

Certain embodiments disclosed herein provide a radio frequency switching system, comprising: a first switching circuit connected between an antenna node and a transmitting node; a second switching circuit connected between the antenna node and a receiving node; a first capacitor connected in series with the first switching circuit between the first switching circuit and the antenna node; a second capacitor connected in series with the second switching circuit between the second switching circuit and the antenna node; a first shunt arm connected to the first switching circuit and the transmitting node, the first shunt arm including a third switching circuit connected to ground; and a second shunt arm connected to the second switching circuit and the receiving node, the second shunt arm including a fourth switching circuit connected to ground.

Certain embodiments disclosed herein provide a radio frequency switching system, comprising: a first switching circuit connected between an antenna node and a transmitting node; a second switching circuit connected between the antenna node and a receiving node; a first capacitor connected in series with the first switching circuit between the first switching circuit and the antenna node; a second capacitor connected in series with the second switching circuit between the second switching circuit and the antenna node; and a first shunt arm connected to the first switching circuit and the transmitting node, the first shunt arm comprising a third switching circuit connected to ground and a third capacitor connected between the third switching circuit and the transmitting node.

Certain embodiments disclosed herein provide a semiconductor die comprising: a semiconductor substrate; a first switching circuit formed on the semiconductor substrate and connected between an antenna node and a transmitting node; a second switching circuit formed on the semiconductor substrate and connected between the antenna node and a receiving node; a first capacitor formed on the semiconductor substrate and connected in series with the first switching circuit between the first switching circuit and the antenna node; a second capacitor formed on the semiconductor substrate and connected in series with the second switching circuit between the second switching circuit and the antenna node; a first shunt arm connected to the first switching circuit and the transmitting node, the first shunt arm including a third switching circuit connected to ground; and a second shunt arm connected to the second switching circuit and the receiving node, the second shunt arm including a fourth switching circuit connected to ground.

Certain embodiments disclosed herein provide a method for manufacturing a semiconductor bare core, the method comprising: providing a semiconductor substrate; forming a first switching circuit on the semiconductor substrate so that the first switching circuit is connected between an antenna node and a transmitting node; forming a second switching circuit on the semiconductor substrate so that the second switching circuit is connected between the antenna node and a receiving node; forming a first capacitor on the semiconductor substrate so that the first capacitor is connected in series with the first switching circuit between the first switching circuit and the antenna node; forming a second capacitor on the semiconductor substrate so that the second capacitor is connected in series with the second switching circuit between the second switching circuit and the antenna node; forming a first shunt arm connected to the first switching circuit and the transmitting node, the first shunt arm including a third switching circuit connected to ground; and forming a second shunt arm connected to the second switching circuit and the receiving node, the second shunt arm including a fourth switching circuit connected to ground.

Certain embodiments disclosed herein provide a radio frequency switch module, comprising: a packaging substrate configured to accommodate multiple components; a semiconductor die mounted on the packaging substrate, the die including a first switching circuit and a second switching circuit, the first switching circuit being connected between an antenna node and a transmitting node, the second switching circuit being connected between the antenna node and a receiving node; a first capacitor connected in series with the first switching circuit between the first switching circuit and the antenna node; a second capacitor connected in series with the second switching circuit between the second switching circuit and the antenna node; a first shunt arm connected to the first switching circuit and the transmitting node, the first shunt arm including a third switching circuit connected to ground; and a second shunt arm connected to the second switching circuit and the receiving node, the second shunt arm including a fourth switching circuit connected to ground.

Certain embodiments disclosed herein provide a wireless device including: a transceiver configured to process radio frequency signals; an antenna in communication with the transceiver; and a switch module interconnected with the antenna and the transceiver and configured to selectively route the radio frequency signals to and from the antenna, the switch module including a first switch circuit connected between an antenna node and a transmitting node, a second switch circuit connected between the antenna node and a receiving node, a first capacitor connected in series with the first switch circuit between the first switch circuit and the antenna node, a second capacitor connected in series with the second switch circuit between the second switch circuit and the antenna node, a first shunt arm connected to the first switch circuit and the transmitting node, and a second shunt arm connected to the second switch circuit and the receiving node, the first shunt arm including a third switch circuit connected to ground, and the second shunt arm including a fourth switch circuit connected to ground.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments are depicted in the accompanying drawings for purposes of illustration and should in no way be construed as limiting the scope of the present invention. In addition, various features of the disclosed embodiments may be combined to form additional embodiments, which are part of this disclosure. Reference numerals may be reused throughout the drawings to indicate corresponding relationships between reference elements.

FIG1 schematically illustrates a radio frequency (RF) switch configured to switch one or more signals between one or more poles and one or more throws.

FIG2 shows that the RF switch 100 of FIG1 may include an RF core and an energy management (EM) core.

FIG3 shows an example of an RF core implemented in a single-pole double-throw (SPDT) configuration.

FIG4 shows an example of an RF core implemented in a SPDT configuration, where each switch leg may include multiple field effect transistors (FETs) connected in series.

5 schematically illustrates that control of one or more FETs in an RF switch may be facilitated by circuitry configured to bias and/or couple one or more portions of the FETs.

FIG6 shows an example of a biasing/coupling circuit implemented on different portions of multiple FETs in a switch arm.

7A and 7B illustrate top and side cross-sectional views of an example finger-based FET device implemented in a silicon-on-insulator (SOI) configuration.

8A and 8B illustrate top and side cross-sectional views of an example of a multiple-finger FET device implemented in an SOI configuration.

9 shows a first example of an RF switching circuit having a nonlinear capacitor connected to a source terminal of a FET and configured, for example, to cancel or reduce nonlinear effects generated by the FET.

FIG. 10 illustrates one or more features of FIG. 9 that may be implemented in a switch leg having multiple FETs.

11A-11F illustrate a variation of a second example of an RF switching circuit in which one or both of the gate and body terminals of a FET may be coupled to a source terminal via one or more coupling circuits having a capacitor in series with a resistor to, for example, allow discharge of interface charge from the coupled gate and/or body.

12A-12F illustrate that one or more features of FIGs. 11A-11F may be implemented in a switch leg having multiple FETs.

13 shows a third example of an RF switch circuit having a body bias circuit including an LC circuit that may be configured, for example, to provide reduced or minimal insertion loss when the switch circuit is on and to provide a DC short or fixed DC voltage to the body when the switch circuit is off.

FIG. 14 shows that one or more features of FIG. 13 may be implemented in a switch leg having multiple FETs.

15 shows a fourth example of an RF switch circuit having a coupling circuit that couples the body and gate of a FET through a diode in series with a resistor to, for example, facilitate improved distribution of excess charge from the body.

FIG. 16 shows that one or more features of FIG. 15 may be implemented in a switch leg having multiple FETs.

17A and 17B illustrate a variation of a fifth example of an RF switch circuit in which additional resistance may be switchably provided to one or both of the gate and body of a FET to, for example, provide improved intermodulation distortion (IMD) performance.

18A and 18B illustrate that one or more features of FIGs. 17A and 17B may be implemented in a switch arm having multiple FETs.

19 shows a sixth example of an RF switch circuit having a coupling circuit that couples the body and gate of a FET through a capacitor in series with a resistor to, for example, provide improved intermodulation distortion (IMD) performance.

FIG. 20 shows that one or more features of FIG. 19 may be implemented in a switch leg having multiple FETs.

Figure 21 shows a seventh example of an RF switching circuit having the body of a FET resistively coupled to the gate in a switchable manner to provide minimal or reduced insertion loss, for example, when the switching circuit is turned on, and providing a DC voltage to both the body and gate of the FET to prevent or reduce a parasitic node diode from being turned on.

FIG. 22 illustrates that one or more features of FIG. 21 may be implemented in a switch arm having multiple FETs.

23A and 23B illustrate a variation of an eighth example of an RF switch circuit having a FET whose body and gate may be coupled through a capacitor or a parallel combination of a capacitor and a diode, eg, to help improve harmonic management, including IMD3 and IMD2.

24A and 24B illustrate that one or more features of FIGs. 23A and 23B may be implemented in a switch arm having multiple FETs.

25A-25D illustrate examples of the improved performance that may be provided by the configuration of Figs. 23 and 24. In the embodiment of Figs.

26 shows a ninth example of an RF switch circuit having a switchable coupling between the body and gate of a FET to provide, for example, minimal or reduced insertion loss when the switch is on, and reduced distortion associated with large voltage swings.

FIG. 27 illustrates that one or more features of FIG. 26 may be implemented in a switch arm having multiple FETs.

28-30 illustrate variations of a tenth example of an RF switch circuit having FETs whose gates may be voltage compensated, for example, to produce an improved voltage distribution across each FET.

FIG. 31 illustrates an example of the performance improvement achieved using the gate compensation feature of FIGs. 28-30 .

FIG32 shows an eleventh example in which the RF switch configuration may include one or more capacitors to, for example, inhibit low frequency blockers from mixing with the fundamental frequency.

FIG33 shows an example in which the switch configuration of FIG32 is in transmission mode.

34 schematically depicts a switching device including a switching circuit having a voltage distribution equalization circuit, wherein the switching device is configured to allow a signal, such as a radio frequency (RF) signal, to pass between a first and a second port when in a first state.

FIG35 shows a switching circuit comprising five FETs connected in series defining an RF signal path between the input and output terminals.

FIG36 shows a switching circuit including five FETs connected in series, defining input and output terminals, and including an implementation of a body node voltage compensation technique.

37 shows a comparison of the voltage swing performance across the FETs of a switch circuit including an embodiment of the body node voltage compensation technique with the performance of a switch circuit not including the technique.

FIG38 shows a switching circuit including five FETs connected in series to define an RF signal path between an input terminal and an output terminal, and including an implementation of a body node voltage compensation technique.

FIG39 shows a switching circuit including five FETs connected in series to define an RF signal path between an input terminal and an output terminal, and including an implementation of a body node voltage compensation technique.

40 illustrates an example switching circuit including two FETs connected in series to define an RF signal path between an input and an output, and including an implementation of a body node voltage compensation technique.

FIG. 41 illustrates a process that may be applied to fabricate a switching circuit having one or more features described herein.

FIG42 shows a process that can be used as a more specific example of the process of FIG10.

43A-43D illustrate examples of how various components for biasing, coupling, and/or facilitating the example configurations of FIGS. 9-42 may be implemented.

44A and 44B illustrate examples of packaged modules that may incorporate one or more features described herein.

45 illustrates that in some embodiments, one or more features of the present disclosure may be implemented in a switching device, such as a single-pole, multiple-throw (SPMT) switch configured to facilitate multi-band, multi-mode wireless operation.

FIG46 illustrates an example of a wireless device that may incorporate one or more features described herein.

FIG. 47 illustrates that in some implementations, one or more features associated with a given example configuration can be combined with one or more features associated with another example configuration.

DETAILED DESCRIPTION

The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

Example components of a switching device:

FIG1 schematically illustrates a radio frequency (RF) switch 100 configured to switch one or more signals between one or more poles 102 and one or more throws 104. In some embodiments, such a switch may be based on one or more field effect transistors (FETs), such as silicon-on-insulator (SOI) FETs. When a particular pole is connected to a particular throw, that path is typically referred to as closed or in the on-state. When a given path between a pole and a throw is not connected, that connection is typically referred to as open or in the off-state.

FIG2 shows that in some implementations, the RF switch 100 of FIG1 can include an RF core 110 and an energy management (EM) core 112. The RF core 110 can be configured to route RF signals between a first port and a second port. In the example single-pole double-throw (SPDT) configuration shown in FIG2, such first and second ports can include a pole 102a and a first throw 104a, or a pole 102a and a second throw 104b.

In some embodiments, the EM core 112 may be configured to provide, for example, voltage control signals to the RF core. The EM core 112 may further be configured to provide logic decoding and/or power regulation capabilities to the RF switch 100.

In some embodiments, the RF core 110 may include one or more poles and one or more throws to enable passage of RF signals between one or more inputs and one or more outputs of the switch 100. For example, the RF core 110 may include a single-pole double-throw (SPDT or SP2T) configuration as shown in FIG2 .

In the context of an example SPDT, FIG3 shows a more detailed example configuration of the RF core 110. The RF core 110 is shown as including a single pole 102a coupled to first and second throw nodes 104a, 104b via first and second transistors (e.g., FETs) 120a, 120b. The first throw node 104a is shown coupled to RF ground via FET 122a to provide shunting capability for node 104a. Similarly, the second throw node 104b is shown coupled to RF ground via FET 122b to provide shunting capability for node 104b.

In an exemplary operation, when the RF core 110 is in a state in which an RF signal passes between the pole 102a and the first throw 104a, the FET 120a between the pole 102a and the first throw node 104a can be in an on-state, and the FET 120b between the pole 102a and the second throw node 104b can be in an off-state. Regarding the shunt FETs 122a, 122b, the shunt FET 122a can be in an off-state so that the RF signal is not shunted to ground when traveling from the pole 102a to the first throw node 104a. The shunt FET 122b associated with the second throw node 104b can be in an on-state so that any RF signal or noise reaching the RF core 110 through the second throw node 104b is shunted to ground to reduce undesirable interference effects on the pole-to-first throw operation.

While the above examples are described in the context of a single-pole, double-throw configuration, it will be appreciated that the RF core may be configured using other numbers of poles and throws. For example, there may be more than one pole, and the number of throws may be less than or greater than the example number two.

3, the transistor between the pole 102a and the two throw nodes 104a, 104b is depicted as a single transistor. In some implementations, such switching functionality between one or more poles and one or more throws can be provided by switch arm components, each of which includes multiple transistors, such as FETs.

An example RF core configuration 130 of an RF core having such a switch arm assembly is shown in FIG4 . In this example, the pole 102 a and the first throw node 104 a are shown coupled via a first switch arm assembly 140 a. Similarly, the pole 102 a and the second throw node 104 b are shown coupled via a second switch arm assembly 140 b. The first throw node 104 a is shown capable of being shunted to RF ground via a first shunt arm assembly 142 a. Similarly, the second throw node 104 b is shown capable of being shunted to RF ground via a second shunt arm assembly 142 b.

In an exemplary operation, when the RF core 130 is in a state in which an RF signal passes between the pole 102a and the first throw 104a, all FETs in the first switch arm 140a can be in an on-state, and all FETs in the second switch arm 140b can be in an off-state. The first shunt arm 142a for the first throw node 104a can have all of its FETs in an off-state so that the RF signal is not shunted to ground when traveling from the pole 102a to the first throw node 104a. All FETs in the second shunt arm 142a associated with the second throw node 104b can be in an on-state so that any RF signal or noise reaching the RF core 130 through the second throw node 104b is shunted to ground to reduce undesirable interference effects on the pole-to-first throw operation.

Furthermore, while described in the context of an SP2T configuration, it will be understood that RF cores having other numbers of poles and throws may also be implemented.

In some implementations, the switch arm components (e.g., 140a, 140b, 142a, 142b) can include one or more semiconductor transistors, such as FETs. In some embodiments, the FETs can be in a first state or a second state and can include a gate, a drain, a source, and a body (sometimes also referred to as a substrate). In some embodiments, the FETs can include metal oxide semiconductor field effect transistors (MOSFETs). In some embodiments, the one or more FETs can be connected in series to form a first end and a second end, such that when the FETs are in a first state (e.g., an on state), an RF signal can be routed between the first end and the second end.

At least some of the present disclosure relates to how a FET or a group of FETs can be controlled to provide a switching function in a desired manner. FIG5 schematically illustrates that in some implementations, such control of the FET 120 can be facilitated by a circuit 150 configured to bias and/or couple one or more portions of the FET 120. In some embodiments, such circuit 150 can include one or more circuits configured to bias and/or couple the gate of the FET 120, bias and/or couple the body of the FET 120, and/or couple the source/drain of the FET 120.

A schematic example of how to bias and/or couple different portions of one or more FETs is described with reference to FIG6 . In FIG6 , a switch arm segment 140 (which may be, for example, one of the example switch arm segments 140 a, 140 b, 142 a, 142 b of the example of FIG4 ) between nodes 144, 146 is shown as including a plurality of FETs 120. The operation of such FETs may be controlled and/or facilitated by gate bias/coupling circuitry 150 a, body bias/coupling circuitry 150 c, and/or source/drain coupling circuitry 150 b.

Gate bias/coupling circuit

6 , the gate of each FET 120 can be connected to a gate bias/coupling circuit 150 a to receive a gate bias signal and/or couple the gate to another portion of the FET 120 or the switch arm 140. In some implementations, the design or features of the gate bias/coupling circuit 150 a can improve the performance of the switch arm 140. Such performance improvements can include, but are not limited to, device insertion loss, isolation performance, power handling capability, and/or switching device linearity.

Body bias/coupling circuit

6 , the body of each FET 120 can be connected to a body bias/coupling circuit 150 c to receive a body bias signal and/or couple the body to another portion of the FET 120 or the switch arm 140. In some implementations, the design or features of the body bias/coupling circuit 150 c can improve the performance of the switch arm 140. Such performance improvements can include, but are not limited to, device insertion loss, isolation performance, power handling capability, and/or switching device linearity.

Source/drain coupling circuit

6 , the source/drain of each FET 120 can be connected to a coupling circuit 150 b to couple the source/drain to another portion of the FET 120 or the switch arm 140. In some implementations, the design and features of the coupling circuit 150 b can improve the performance of the switch arm 140. Such performance improvements can include, but are not limited to, device insertion loss, isolation performance, power handling capability, and/or switching device linearity.

Examples of switch performance parameters:

Insertion loss

Switching device performance parameters may include a measure of insertion loss. Switching device insertion loss may be a measure of the attenuation of an RF signal routed through an RF switching device. For example, the amplitude of the RF signal at the output port of the switching device may be less than the amplitude of the RF signal at the input port of the switching device. In some embodiments, the switching device may include device components that introduce parasitic capacitance, inductance, resistance, or conductance into the device, which contributes to increased switching device insertion loss. In some embodiments, the switching device insertion loss may be measured as the ratio of the power or voltage of the RF signal at the input port of the switching device to the power or voltage of the RF signal at the output port of the switching device. Reduced switching device insertion loss may be desirable for improving RF signal transmission.

Isolation

Switch device performance parameters may also include a measure of isolation. Switch device isolation may be a measure of the RF isolation between an input port and an output port of an RF switch device. In some embodiments, the switch device isolation may be a measure of the RF isolation of the switch device when the input port and the output port are electrically isolated, such as when the switch device is in an off state. Increased switch device isolation may improve RF signal integrity. In certain embodiments, increased isolation may improve wireless communication device performance.

Intermodulation distortion

The switching device performance parameters may further include a measure of intermodulation distortion (IMD) performance. Intermodulation distortion (IMD) may be a measure of nonlinearity in an RF switching device.

IMD can result from two or more signals mixing together and producing non-harmonic frequencies. For example, suppose two signals have fundamental frequencies _f1 and _f2 that are relatively close to each other in frequency space ( _f2 > _f1 ). This mixing of signals can result in peaks in the spectrum at frequencies corresponding to different products of the fundamental and harmonic frequencies of the two signals. For example, second-order intermodulation distortion (also known as IMD2) is generally considered to include frequencies _f1 + _f2 , _f2 - _f1 , _2f1 , and _2f2 . Third-order IMD (also known as IMD3) is generally considered to include frequencies _2f1 + _f2 , _2f1 - _f2 , _f1 + _2f2 , and _f1-2f2 . Higher-order products _can be formed in a similar manner.

Typically, as the IMD order increases, the power level decreases. Accordingly, second and third order may be of particular interest as unwanted effects. In some cases, higher orders such as fourth and fifth order may also be of interest.

In some RF applications, it is desirable to reduce the susceptibility to interference within the RF system. Nonlinearities in the RF system can result in the introduction of spurious signals into the system. Spurious signals in the RF system can cause interference within the system and degrade the information conveyed by the RF signal. RF systems with increased nonlinearities can exhibit increased susceptibility to interference. Nonlinearities in system components, such as switching devices, can contribute to the introduction of spurious signals into the RF system, thereby contributing to degradation of the linearity and IMD performance of the overall RF system.

In some embodiments, an RF switching device can be implemented as part of an RF system comprising a wireless communication system. The IMD performance of the system can be improved by increasing the linearity of system components, such as the linearity of the RF switching device. In some embodiments, the wireless communication system can operate in a multi-band and/or multi-mode environment. Improvements in intermodulation distortion (IMD) performance may be desirable in wireless communication systems operating in a multi-band and/or multi-mode environment. In some embodiments, improvements in the IMD performance of the switching device can improve the IMD performance of the wireless communication system operating in a multi-band and/or multi-mode environment.

Improved switching device IMD performance may be desirable for wireless communication devices operating in various wireless communication standards, such as wireless communication devices operating in the LTE communication standard. In some RF applications, it may be desirable to improve the linearity of switching devices operating in wireless communication devices that enable simultaneous transmission of data and voice communications. For example, improved IMD performance in switching devices may be desirable for wireless communication devices operating in the LTE communication standard and performing simultaneous transmission of voice and data communications (e.g., SVLTE).

High power handling capability

In some RF applications, it may be desirable to operate an RF switching device at high power while reducing degradation of other device performance parameters. In some embodiments, it may be desirable to operate an RF switching device at high power with improved intermodulation distortion, insertion loss, and/or isolation performance.

In some embodiments, an increased number of transistors can be implemented in a switch arm portion of a switching device to improve the power handling capability of the switching device. For example, the switch arm portion can include an increased number of FETs connected in series, with an increased FET stack height, to improve device performance at high power. However, in some embodiments, the increased FET stack height can degrade the insertion loss performance of the switching device.

Examples of FET structures and manufacturing process technologies:

The switching device can be implemented as a bare die, a bare die (off-die) or some combination thereof. The switching device can also be manufactured using various technologies. In some embodiments, the RF switching device can be manufactured using silicon or silicon on insulator (SOI) technology.

As described herein, RF switching devices can be implemented using silicon-on-insulator (SOI) technology. In some embodiments, SOI technology can include a semiconductor substrate having an embedded layer of electrically insulating material, such as a buried oxide layer, beneath a silicon device layer. For example, an SOI substrate can include an oxide layer embedded beneath a silicon layer. Other insulating materials known in the art can also be used.

The implementation of RF applications (e.g., RF switching devices) using SOI technology can improve switching device performance. In some embodiments, SOI technology can reduce power consumption. Reduced power consumption can be desirable in RF applications including RF applications associated with wireless communication devices. Due to the reduction in parasitic capacitance of the transistor and the interconnect metallization of the silicon substrate, SOI technology can reduce the power consumption of the device circuit. The presence of a buried oxide layer can also reduce the use of junction capacitance or a high resistivity substrate, making it possible to reduce RF losses associated with the substrate. Electrically isolated SOI transistors can facilitate stacking, contributing to chip size reduction.

In some SOI FET configurations, each transistor can be configured as a finger-based device, in which the source and drain are rectangular in shape (in a top view) and the gate structure extends between the source and drain like a rectangular-shaped finger. Figures 7A and 7B show a top cross-sectional view and a side cross-sectional view of an example finger-based FET implemented on SOI. As shown, the FET devices described herein can include p-type FETs or n-type FETs. Therefore, although some FET devices are described herein as p-type devices, it will be understood that the various concepts associated with such p-type devices can also be used for n-type devices.

As shown in Figures 7A and 7B, a pMOSFET can include an insulator layer formed on a semiconductor substrate. The insulator layer can be formed of materials such as silicon dioxide or sapphire. The n-well is shown as being formed in the insulator such that the exposed surface generally defines a rectangular region. The source (S) and drain (D) are shown such that their exposed surfaces generally define rectangular p-doped regions. As shown, the S/D regions can be configured such that the source and drain functions are opposite.

7A and 7B further illustrate that a gate (G) can be formed on an n-well so as to be located between the source and drain. An example gate is depicted as having a rectangular shape extending along the source and drain. An n-type body contact is also shown. The formation of the rectangular well, source and drain regions, and body contact can be achieved by a variety of known techniques. In some embodiments, the source and drain regions can be formed adjacent to the ends of their corresponding upper insulator layers, and the junction between the body and the source/drain regions on the opposite side of the body can extend substantially all the way down to the end of the buried insulator layer. This configuration can provide, for example, reduced source/drain junction capacitance. In order to form a body contact for this configuration, an additional gate region can be provided on this side to allow, for example, an isolated P+ region to contact the P-well.

8A and 8B show top and side cross-sectional views of an example of a multi-finger FET device implemented on SOI. The rectangular n-well, rectangular p-doped region, rectangular gate, and n-type body contact can be implemented in a manner similar to that described with reference to FIG7A and 7B.

The example multi-finger FET device of Figures 8A and 8B can be operated so that the drain of one FET serves as the source of its adjacent FET. Thus, the entire multi-finger FET device can provide a voltage division function. For example, an RF signal can be provided to one of the outermost p-doped regions (e.g., the leftmost p-doped region), and as the signal passes through a series of FETs, the voltage of the signal can be divided among these FETs. In this example, the rightmost p-doped region can serve as the overall drain of the multi-finger FET device.

In some implementations, multiple of the aforementioned multi-finger FET devices can be connected in series as a switch, for example, to further facilitate the voltage division function. A number of such multi-finger FET devices can be selected based on, for example, the power handling requirements of the switch.

Examples of Biasing and/or Coupling Configurations for Improved Performance

Described herein are various examples of how FET-based switching circuits can be biased and/or coupled to produce one or more performance improvements. In some embodiments, such biasing/coupling configurations can be implemented in SOI FET-based switching circuits. It will be appreciated that some of the example biasing/coupling configurations can be combined to produce a combination of desired features not available with a single configuration. It will also be appreciated that, while described in the context of RF switching applications, one or more of the features described herein can also be applied to other circuits and devices utilizing FETs, such as SOI FETs.

Description of Example 1

In some radio frequency (RF) applications, it is desirable to utilize switches with high linearity and management of intermodulation distortion, such as IMD3 and IMD2. Such switch-related performance characteristics can significantly contribute to the system-level performance of cellular devices. In the context of silicon-on-oxide (SOI) switches, factors such as substrate coupling (sometimes also referred to as substrate parasitics) and the SOI process can limit the achievable performance.

This limitation in SOI switch performance can be addressed through extensive substrate crosstalk reduction techniques, such as capacitive guard rings, and/or trap-rich or deep trench isolation techniques. Such techniques often have undesirable characteristics associated with them, such as being expensive, requiring relatively large areas, and requiring additional process steps. Furthermore, such techniques may produce desired effects that are limited to isolation features.

In some implementations, the performance of SOI switches can be improved by overcoming or reducing the aforementioned effects associated with substrate parasitics and/or process variations. By way of example, FIG9 illustrates a switch circuit 200 having an SOI FET 120 configured to provide a switching function between a first node 144 and a second node 146. The gate terminal of the FET 120 is shown as being biased by a bias voltage Vg provided by a gate bias circuit, and the body terminal of the FET 120 is shown as being biased by a bias voltage Vsb1 provided by a body bias circuit. In some embodiments, the body terminal can be connected to the source terminal such that the bias voltage Vsb1 is provided to both terminals.

In some embodiments, the source terminal of FET 120 can be connected to a nonlinear capacitor 202. In embodiments where FET 120 is a MOSFET device, capacitor 202 can be a MOSFET capacitor configured to provide one or more desired capacitance values. MOS capacitor 202 can be configured to generate one or more harmonics to cancel or reduce the nonlinear effects generated by MOSFET 120. MOS capacitor 202 is shown as being biased by Vsb2. In some embodiments, one or both of Vsb1 and Vsb2 can be adjusted to produce a desired level of nonlinear cancellation. Although described in the context of the source side of FET 120, it will be understood that MOS capacitor 202 can also be implemented on the drain side of the FET.

FIG10 shows a switch arm 210 having a plurality of switch circuits 200 as described with reference to FIG9 . In the example, N such switch circuits are shown connected in series in a stack to provide switching functionality between terminals 144, 146. In some embodiments, the number of FETs (N) in such a stack may be selected based on the power to be transferred between terminals 144, 146. For example, N may be larger for higher power situations.

In some embodiments, the gate bias voltage (Vg) for the multiple FETs 120 can be substantially the same and provided by a common gate bias circuit. This common gate bias voltage Vg is shown as being provided to the gate via a gate resistor Rg. Similarly, the body bias voltage (Vsb1) for the multiple FETs 120 can be substantially the same and provided by a common body bias circuit. Similarly, the body bias voltage (Vsb2) for the multiple MOS capacitors 202 can be substantially the same and provided by a common body bias circuit (not shown). In some implementations, some or all of the bodies of the FETs 120 and/or MOS capacitors 202 can be biased separately. In some cases, depending on the frequency of operation, such biasing can be beneficial.

In some implementations, the example configurations described above with reference to Figures 9 and 10 can allow for significant or substantially complete elimination of nonlinear effects associated with RF switches based on one or more SOI FETs. In some embodiments, such configurations can be implemented so that minimal or relatively small additional area is required.

Summary of Example 1

According to some implementations, Example 1 relates to a radio frequency (RF) switch comprising at least one field effect transistor (FET) disposed between first and second nodes, wherein each of the at least one FET has a corresponding source and a drain. The switch further comprises a compensation circuit connected to the corresponding source or the corresponding drain of each of the at least one FET. The compensation circuit is configured to compensate for nonlinear effects generated by the at least one FET.

In some embodiments, the FET may be a silicon-on-insulator (SOI) FET. In some embodiments, the compensation circuit may include a nonlinear capacitor. The nonlinear capacitor may include a metal oxide semiconductor (MOS) capacitor. The MOS capacitor may be configured to generate one or more harmonics to substantially cancel the nonlinear effects generated by the FET. The MOS capacitor may include a FET structure. The one or more harmonics generated by the MOS capacitor may be controlled, at least in part, by a body bias signal provided to the FET structure of the MOS capacitor.

In some embodiments, the non-linear capacitor may be connected to the source of the FET.

In some embodiments, the switch may further include a gate bias circuit connected to the gate of the FET and configured to provide a bias signal to the gate of the FET.

In some embodiments, the switch may further include a body bias circuit connected to the body of the FET and configured to provide a bias signal to the body of the FET.

In some embodiments, when the FET is in an on-state, the first node can be configured to receive an RF signal having a power value and the second node can be configured to output the RF signal. The at least one FET can include N FETs connected in series, where the number N is selected to allow the switching circuit to handle the power of the RF signal.

In some implementations, Example 1 relates to a method for operating a radio frequency (RF) switch. The method includes controlling at least one field effect transistor (FET) disposed between first and second nodes so that each of the at least one FET is in an on state or an off state. The method further includes compensating for a nonlinear effect of the at least one FET by applying another nonlinear signal to a corresponding source or a corresponding drain of each of the at least one FET.

According to many implementations, Example 1 relates to a semiconductor die comprising a semiconductor substrate and at least one field effect transistor (FET) formed on the semiconductor substrate. The die further comprises a compensation circuit connected to a corresponding source or a corresponding drain of each of the at least one FET. The compensation circuit is configured to compensate for nonlinear effects generated by the at least one FET.

In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. The die may be a silicon-on-insulator (SOI) die.

In many implementations, Example 1 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate and forming at least one field effect transistor (FET) on the semiconductor substrate, wherein each of the at least one FET has a corresponding source and a corresponding drain. The method further includes forming a compensation circuit on the semiconductor substrate. The method further includes connecting the compensation circuit to the corresponding source or the corresponding drain of each of the at least one FET, thereby allowing the compensation circuit to compensate for nonlinear effects generated by the at least one FET.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

According to some implementations, Example 1 relates to a radio frequency (RF) switch module, comprising a package substrate configured to accommodate a plurality of components. The module further comprises a semiconductor die mounted on the package substrate, wherein the die comprises at least one field effect transistor (FET). The module further comprises a compensation circuit connected to a corresponding source or a corresponding drain of each of the at least one FET. The compensation circuit is configured to compensate for nonlinear effects generated by the at least one FET.

In some embodiments, the semiconductor die may be a silicon-on-insulator (SOI) die. In some embodiments, the compensation circuit may be part of the same semiconductor die as the at least one FET. In some embodiments, the compensation circuit may be part of a second die mounted on the package substrate. In certain embodiments, the compensation circuit may be disposed at a location external to the semiconductor die.

In some implementations, Example 1 relates to a wireless device comprising a transceiver configured to process an RF signal. The wireless device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises at least one field effect transistor (FET). The switch further comprises a compensation circuit connected to a corresponding source or a corresponding drain of each of the at least one FET. The compensation circuit is configured to compensate for nonlinear effects generated by the at least one FET.

Description of Example 2

As described herein, intermodulation distortion (IMD) is a measure of unwanted signals added to a desired signal due to mixing products from other radio frequency (RF) signals. This distortion can be particularly pronounced in multimode, multiband environments.

IMD can result from two or more signals mixing together and producing non-harmonic frequencies. In some implementations, susceptibility to such interference can be reduced by improving the linearity of the system, as the linearity of the system can manage how much IMD (and thus interference) will occur. By improving the linearity of the building blocks of the system (e.g., RF switches), the overall susceptibility of the system to interference can be reduced.

The desire for lower IMD in RF switches can play an important role in various wireless system designs. There are numerous efforts in the wireless industry to reduce IMD in switches. For example, Long Term Evolution (LTE) systems can significantly benefit from RF switches with reduced IMD. As a more specific example, simultaneous voice and data over LTE (SVLTE) system designs can significantly benefit from RF switches with ultra-low levels of IMD.

In some implementations, the gate terminal and one of the source terminal and the drain terminal of the FET can be coupled by a circuit for IMD performance improvement. For the purpose of description, it will be assumed that such a circuit couples the gate terminal and the source terminal; however, it will be understood that the circuit can couple the gate terminal and the drain terminal.

In some implementations, the body terminal and one of the source terminal and the drain terminal of the FET can be coupled by a circuit for IMD performance improvement. For the purposes of this description, it will be assumed that such a circuit couples the body terminal and the source terminal; however, it will be understood that the circuit can couple the body terminal and the drain terminal.

In some implementations, each of the gate and body terminals of a FET and one of the source and drain terminals can be coupled by a circuit for improved IMD performance. For the purposes of this description, it will be assumed that such a circuit couples each of the gate and body terminals to the source terminal; however, it will be understood that such coupling can be changed to the drain terminal.

11A-11F illustrate an example switching circuit 220 having an SOI FET 120 configured to provide a switching function between a first node 144 and a second node 146. The gate terminal of the FET 120 is shown biased by a gate resistor Rg. The gate resistor Rg can be configured to float the gate. FIG11A, 11C, and 11E illustrate a configuration with a resistor-body connection (using a body resistor Rb that can be configured to float the body); and FIG11B, 11D, and 11F illustrate a configuration with a diode-body connection (using a diode 226).

11A-11F , one or both of the gate and body terminals may be coupled to the source terminal through one or more coupling circuits having a capacitor 222 in series with a resistor 224. For purposes of describing FIG11A-11F , this coupling circuit is referred to as an RC circuit.

This coupling can allow for discharge of interface charge from the coupled gate and/or bulk. This discharge of interface charge can lead to improved IMD performance, particularly for low-frequency blockers. For configurations in which an RC circuit is coupled to the gate, the RC circuit can present a high impedance to low-frequency signals, which prevents or reduces leakage of the low-frequency signal to the gate. Similarly, for configurations in which the RC circuit is coupled to the bulk, the RC circuit can present a high impedance to low-frequency signals, which prevents or reduces leakage of the low-frequency signal to the bulk.

11A shows a switch circuit 220 in which an RC circuit having a capacitor 222 (capacitance C) in series with a resistor 224 (resistance R) couples the source terminal to the gate terminal of the SOI FET 120. In this example, both the gate and body are floating through their respective resistors Rg and Rb.

11B shows a switch circuit 220 in which an RC circuit having a capacitor 222 (capacitance C) in series with a resistor 224 (resistance R) couples the source terminal to the gate terminal of the SOI FET 120. In this example, the gate is floated by resistor Rg and provides a diode-body connection.

11C shows a switch circuit 220 in which an RC circuit having a capacitor 222 (capacitance C) in series with a resistor 224 (resistance R) couples the source terminal to the body terminal of the SOI FET 120. In this example, both the gate and body are floating through their respective resistors Rg and Rb.

11D shows a switch circuit 220 in which an RC circuit having a capacitor 222 (capacitance C) in series with a resistor 224 (resistance R) couples the source terminal to the body terminal of the SOI FET 120. In this example, the gate is floated by resistor Rg and provides a diode-body connection.

FIG11E shows a switch circuit 220 in which an RC circuit having a capacitor 222 (capacitance C) in series with a resistor 224 (resistance R) couples the source terminal of the SOI FET 120 to the body terminal. Another RC circuit having a capacitor 222′ (capacitance C′) in series with a resistor 224′ (resistance R′) couples the source terminal of the FET 120 to the gate terminal. In this example, both the gate and the body are floating through their respective resistors Rg and Rb.

FIG11F shows a switch circuit 220 in which an RC circuit having a capacitor 222 (capacitance C) in series with a resistor 224 (resistance R) couples the source terminal of the SOI FET 120 to the body terminal. Another RC circuit having a capacitor 222′ (capacitance C′) in series with a resistor 224′ (resistance R′) couples the source terminal of the FET 120 to the gate terminal. In this example, the gate is floated by resistor Rg and provides a diode-body connection.

12A-12F illustrate a switch arm 230 having the switch circuit 220 described with reference to FIGs. 11A-11F. In each example, N such switch circuits are shown connected in series to provide a switching function between the terminals 144,146.

In some embodiments, the gate bias voltage (Vg) for the plurality of FETs 120 can be substantially the same and provided through a common gate bias circuit. This common gate bias voltage Vg is shown as being provided to the gate via a gate resistor Rg. Similarly, the body bias voltage (Vb) for the plurality of FETs 120 can be substantially the same and provided through a common body bias circuit to an example having a resistor-body connection.

In some embodiments, some or all of the gates of the FETs 120 can be biased separately. In some cases, such as when it is desired that the voltage division across the FETs is substantially equal, it may be advantageous to implement such separate biasing of the gates. Similarly, in some embodiments, some or all of the bodies of the FETs 120 can be biased separately. In some cases, such as when it is desired that the voltage division across the FETs is substantially equal, it may be advantageous to implement such separate biasing of the bodies.

In some implementations, and as described herein, the foregoing example configurations described with reference to Figures 11 and 12 can produce IMD performance improvements, particularly for low-frequency blockers.

Summary of Example 2

In many implementations, Example 2 relates to a radio frequency (RF) switch comprising at least one field effect transistor (FET) disposed between first and second nodes, wherein each of the at least one FET has a corresponding source, drain, gate, and body. The RF switch further comprises a coupling circuit having at least one of a first and a second path, wherein the first path is between the corresponding source or drain and the corresponding gate of each FET, and the second path is between the corresponding source or drain and the corresponding body of each FET. The coupling path is configured to allow discharge of interface charge from one or both of the coupled gate and body.

In some embodiments, the FET may be a silicon-on-insulator (SOI) FET. In some embodiments, the coupling circuit may include the first path but not the second path, wherein the coupling circuit includes an RC circuit having a capacitor in series with a resistor, thereby allowing discharge from the gate. In some embodiments, the coupling circuit may include the second path but not the first path, wherein the coupling circuit includes an RC circuit having a capacitor in series with a resistor, thereby allowing discharge from the body. In some embodiments, the coupling circuit may include both the first and second paths, wherein the coupling circuit includes first and second RC circuits. The first RC circuit may have a first capacitor in series with a first resistor, thereby allowing discharge from the gate. The second RC circuit may have a second capacitor in series with a second resistor, thereby allowing discharge from the body.

In some embodiments, each of the first and second paths may be connected to the drain. In some embodiments, the RF switch may further include a gate resistor connected to the gate and configured to float the gate. In some embodiments, the RF switch may further include a body resistor connected to the body and configured to float the body. In some embodiments, the RF switch may further include a diode-body connection between the body and the gate.

In some embodiments, when the FET is in an on-state, the first node can be configured to receive an RF signal having a power value, and the second node can be configured to output the RF signal. The at least one FET can include N FETs connected in series, where the number N is selected to allow the switching circuit to handle the power of the RF signal.

According to some implementations, Example 2 relates to a method for operating a radio frequency (RF) switch. The method includes controlling at least one field effect transistor (FET) disposed between first and second nodes. The method further includes discharging interface charge from at least one of a gate and a body of each FET by providing at least one of a first and a second path, wherein the first path is between a source or drain and the gate of each FET, and the second path is between the source or drain and the body of each FET.

According to many implementations, Example 1 relates to a semiconductor die comprising a semiconductor substrate and at least one field effect transistor (FET) formed on the semiconductor substrate. The die further comprises a coupling circuit having at least one of a first and a second path, wherein the first path is between a source or drain and a gate of each FET, and the second path is between a source or drain and a body of each FET. The coupling circuit is configured to allow discharge of interface charge from one or both of the coupled gate and body.

In some embodiments, the coupling circuit may include at least one RC circuit having a capacitor connected in series with a resistor. In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. The die may be a silicon-on-insulator (SOI) die.

In some implementations, Example 2 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate and forming at least one field effect transistor (FET) on the semiconductor substrate, wherein each of the at least one FET has a corresponding gate, a body, a source, and a corresponding drain. The method further includes forming a coupling circuit on the semiconductor substrate. The method further includes forming at least one of the first and second paths using the coupling circuit, wherein the first path is between the corresponding source or drain of each FET and the corresponding gate, and the second path is between the corresponding source or drain of each FET and the corresponding body. The coupling circuit is configured to allow discharge of interface charge from one or both of the coupled gate and body.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

According to many implementations, Example 2 relates to a radio frequency (RF) switch module comprising a package substrate configured to house a plurality of components. The module further comprises a semiconductor die mounted on the package substrate, wherein the die comprises at least one field effect transistor (FET). The module further comprises a coupling circuit having at least one of a first and a second path, wherein the first path is between a source or drain and a gate of each FET, and the second path is between a source or drain and a body of each FET. The coupling circuit is configured to allow discharge of interface charge from one or both of the coupled gate and body.

In some embodiments, the semiconductor die may be a silicon on insulator (SOI) die. In some embodiments, the coupling circuit may include at least one RC circuit having a capacitor in series with a resistor. In some embodiments, the RC circuit may be part of the same semiconductor die as the at least one FET. In some embodiments, at least some of the RC circuits may be part of a second die mounted on the package substrate. In some embodiments, at least some of the RC circuits may be arranged at a location external to the semiconductor die.

In many implementations, Example 2 relates to a wireless device comprising a transceiver configured to process an RF signal. The wireless device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises at least one field effect transistor (FET). The switch further comprises a coupling circuit having at least one of a first and a second path, wherein the first path is between a source or drain and a gate of each FET, and the second path is between a source or drain and a body of each FET. The coupling circuit is configured to allow discharge of interface charge from one or both of the coupled gate and body.

In some embodiments, the coupling circuit may include at least one RC circuit having a capacitor in series with a resistor.In some embodiments, the wireless device may be configured to operate in an LTE communication system.

Description of Example 3

Some wireless systems such as Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), and Code Division Multiple Access (CDMA) may require very high linearity radio frequency (RF) switches. In some embodiments, such RF switches may be implemented based on FETs such as SOI FETs.

Challenges associated with such highly linear FET switches can include providing very low-frequency IMD2 and IMD3 performance specifications. In some cases, the FETs used in such switches can behave like MOS capacitors due to the fixed charge in the FET's body; and such MOS capacitors can be highly nonlinear. This effect can be further characterized at low frequencies. In the context of IMD, low-frequency IMD can be more difficult to manage due to, for example, process limitations.

Some solutions rely on low-pass filters at the antenna terminals. Other solutions utilize guard rings, rich wells, or deep isolation trenches. These solutions can be relatively expensive and often require additional space and process steps.

In some implementations, one or more of the aforementioned challenges can be addressed by connecting a frequency-tuning circuit to the body of the FET. In some embodiments, this circuit can be turned on or off. Accordingly, this configuration can provide a dynamic way to control the body using frequency-dependent components.

In some embodiments, the frequency tuning circuit can behave like a short circuit at low frequencies and like an open circuit at operating frequencies. This configuration can remove fixed surface charge in the body at low frequencies by effectively shorting the low-frequency distortion to RF ground while not affecting the behavior of the switching circuit at the operating frequencies. For purposes of this description, the operating frequencies can include, for example, frequencies in the range of approximately 700 to 6,000 MHz. Low frequencies corresponding to such operating frequencies can include, for example, frequencies below approximately 200 MHz (e.g., 90 to 180 MHz).

13 shows an example switching circuit 300 having an SOI FET 120 configured to provide a switching function between a first node 144 and a second node 146. The gate terminal of the FET 120 is shown as being biased from a gate bias circuit.

As shown in FIG13 , the body bias circuit 302 may include an LC circuit having an inductor 308 (inductance L) and a capacitor 310 (capacitance C). The values of L and C may be selected to produce a desired resonant frequency of the LC circuit. The LC circuit is shown as being connectable to ground via a switch 306 (e.g., another FET designated “M2”). Gate control of FET M2 is shown as being provided by its gate bias voltage V_control via its gate resistor R.

When SOI FET 120 (denoted as "M1") is on, switch 300 conducts between nodes 144 and 146, and M2 is off. This configuration can provide reduced or minimal insertion loss by floating the body of M1. When M1 is off, switch 300 is disconnected between nodes 144 and 146, and M2 is on. This configuration can provide a DC short circuit (as shown in the example of FIG13) or a fixed DC voltage to the body substrate. Thus, this configuration can prevent or reduce conduction of the parasitic junction diode, thereby reducing distortion associated with large voltage swings. At higher frequencies, the LC circuit can present a high impedance and minimize loading effects that can increase the insertion loss of switch 300.

Figure 14 shows a switching arm 310 having a plurality of switching circuits 300 as described with reference to Figure 14. In the example configuration 310, N such switching circuits are shown connected in series to provide a switching function between the terminals 144,146.

In some embodiments, the gate bias voltages (Vg) for the multiple FETs 120 can be substantially the same and provided by a common gate bias circuit. This common gate bias voltage Vg is shown as being provided to the gates via gate resistors Rg. In some embodiments, some or all of the gates of the FETs 120 can be biased separately. In some cases, such as when it is desired that the voltage division across the FETs is substantially equal or when additional isolation between the FETs is desired, it can be advantageous to implement such separate biasing of the gates.

In the example configuration 310 of FIG14 , each switching circuit 310 is depicted as including a frequency-tuned body bias circuit. In some embodiments, a common frequency-tuned body bias circuit can provide a common bias connection to some or all of the FETs 120. In some embodiments, some or all of the bodies of the FETs 120 can be biased separately. In some cases, such as when it is desired that the voltage division across the FETs be substantially equal, it may be advantageous to implement such separate biasing of the bodies.

In some implementations, and as described herein, the aforementioned example configurations described with reference to Figures 13 and 14 can produce improvements at low frequencies without significantly impacting operating frequency performance. Another advantage that can be provided includes a feature in which, when the switch is on, the body bias can be disconnected to float the body, thereby improving insertion loss performance.

Summary of Example 3

According to some implementations, Example 3 relates to a radio frequency (RF) switch comprising at least one field effect transistor (FET) disposed between first and second nodes, wherein each of the at least one FET has a corresponding body. The RF switch further comprises a resonant circuit connecting the corresponding body of each FET to a reference node. The resonant circuit is configured to behave as a nearly closed circuit at low frequencies below a selected value and as a nearly open circuit at an operating frequency, wherein the nearly closed circuit allows surface charge to be removed from the corresponding body to the reference node.

In some embodiments, the FET may be a silicon-on-insulator (SOI) FET. In some embodiments, the resonant circuit may include an LC circuit having an inductor electrically connected in parallel with a capacitor. The resonant circuit may further include a body switch configured to connect the body to the reference node or disconnect the body from the reference node. The body switch may include a second FET. When the first FET is on, the second FET may be configured to be off, thereby floating the body of the first FET. When the first FET is off, the second FET may be further configured to be on to facilitate removal of surface charge from the body to the reference node.

In some embodiments, the reference node may include a ground node. In some embodiments, the RF switch may further include a gate bias circuit connected to the gate of the FET and configured to provide a bias signal to the gate of the FET.

In some embodiments, when the FET is in an on-state, the first node can be configured to receive an RF signal having a power value, and the second node can be configured to output the RF signal. The at least one FET can include N FETs connected in series, where the number N is selected to allow the switching circuit to handle the power of the RF signal.

In many implementations, Example 3 relates to a method for operating a radio frequency (RF) switch. The method includes controlling at least one field effect transistor (FET) disposed between first and second nodes such that each of the at least one FET is in an on state or an off state. The method further includes selectively removing surface charge from a corresponding body of each of the at least one FET at a lower frequency below a selected value. The selective removal is facilitated by a resonant circuit that behaves as a nearly closed circuit at low frequencies.

In some embodiments, the resonant circuit may further behave as a nearly open circuit at an operating frequency. In some embodiments, the resonant circuit may include an LC circuit.

In some implementations, Example 3 relates to a semiconductor die comprising a semiconductor substrate and at least one field effect transistor (FET) formed on the semiconductor substrate. The die further comprises a resonant circuit connecting a corresponding body of each of the at least one FET to a reference node. The resonant circuit is configured to behave as a nearly closed circuit at low frequencies below a selected value and as a nearly open circuit at an operating frequency. The nearly closed circuit allows surface charge to be removed from the corresponding body to the reference node.

In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. The die may be a silicon-on-insulator (SOI) die.

According to many implementations, Example 3 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate and forming at least one field effect transistor (FET) on the semiconductor substrate, wherein each of the at least one FET has a body. The method further includes forming a resonant circuit on the semiconductor substrate. The resonant circuit is configured to behave as an approximately closed circuit at a low frequency below a selected value and behave as an approximately open circuit at an operating frequency. The method further includes: when the resonant circuit is approximately closed, connecting the resonant circuit between the respective bodies of the at least one FET to a reference node to allow surface charge to be removed from the respective bodies to the reference node.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

According to some implementations, Example 3 relates to a radio frequency (RF) switch module comprising a package substrate configured to accommodate a plurality of components. The module further comprises a semiconductor die mounted on the package substrate, wherein the die comprises at least one field effect transistor (FET). The module further comprises a resonant circuit connecting a corresponding body of each of the at least one FET to a reference node. The resonant circuit is configured to behave as a nearly closed circuit at low frequencies below a selected value and as a nearly open circuit at an operating frequency. The nearly closed circuit allows surface charge to be removed from the corresponding body to the reference node.

In some embodiments, the semiconductor die may be a silicon-on-insulator (SOI) die. In some embodiments, the resonant circuit may be part of the same semiconductor die as the at least one FET. In some embodiments, the resonant circuit may be part of a second die mounted on the package substrate. In some embodiments, the resonant circuit may be disposed at a location external to the semiconductor die.

In some implementations, Example 3 relates to a wireless device comprising a transceiver configured to process RF signals. The wireless device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises at least one field effect transistor (FET). The switch further comprises a resonant circuit connecting a corresponding body of each of the at least one FET to a reference node. The resonant circuit is configured to behave as a nearly closed circuit at low frequencies below a selected value and as a nearly open circuit at an operating frequency. The nearly closed circuit allows surface charge to be removed from the corresponding body to the reference node.

Description of Example 4

In many radio frequency (RF) transmission applications, switch designs often require higher power handling capabilities, especially in the presence of mismatches. For example, switches used for antenna tuning are expected to tolerate up to a 20:1 mismatch at +35dBm input power. In addition, some switches utilized in wireless systems such as GSM are expected to tolerate a 5:1 mismatch at +35dBm input power. Higher field effect transistor (FET) stack heights are often used to tolerate high power and improve compression point.

Another important metric for linearity is intermodulation distortion (IMD). IMD measures the unwanted signals added to the desired signal due to mixing products from other radio frequency (RF) signals. This effect is particularly pronounced in multimode, multiband environments. IMD can result from two or more signals mixing together and producing non-harmonic frequencies.

System designers often strive to reduce interference susceptibility by, for example, improving linearity. The linearity of a given system can govern how much IMD will occur within it, which in turn can generate interference. By improving the linearity of system building blocks (such as RF switches), the system's overall susceptibility to interference can be reduced.

15 shows a switching circuit example 320 having an SOI FET 120 configured to provide a switching function between a first node 144 and a second node 146. The gate terminal of the FET 120 may be biased by a gate resistor Rg.

In some embodiments, the switching circuit 320 can be implemented so that the body terminal of the FET 120 is used for power handling and IMD improvement. By way of example, a circuit having a diode 322 in series with a resistor 324 (resistance R) can couple the body and gate of the FET 120. In this example, the anode of the diode 322 can be connected to the body of the FET 120, and the cathode can be connected to one of the resistor terminals. The other terminal of the resistor 324 is connected to the gate of the FET 120. This configuration can contribute to a better distribution of excess charge from the body, which in turn can result in improvements in, for example, compression roll-off characteristics (e.g., higher P1dB) and IMD performance. The size of the diode 322 and the value of the resistor 324 can be selected to optimize or produce desired performance associated with P1dB and IMD.

FIG16 shows a switch arm 330 having multiple switch circuits 320 as described with reference to FIG15 . In the example configuration 330 , N such switch circuits are shown connected in series to provide switching functionality between terminals 144 , 146 . The number N can be selected based on power handling requirements. For example, N can be increased to handle higher power.

In some embodiments, the gate bias voltage (Vg) for the plurality of FETs 120 can be substantially the same and provided by a common gate bias circuit. This common gate bias voltage Vg is shown as being provided to the gate via a gate resistor Rg. In some embodiments, some or all of the gates of the FETs 120 can be biased separately. In some cases, such as when it is desired that the voltage division across the FETs be substantially equal, it can be advantageous to implement such separate biasing of the gates.

In the example configuration 330 of FIG. 16 , circuitry having diodes and resistors as described with reference to FIG. 15 may be provided to each of the N individual switch circuits 320 , may provide a common coupling between the bodies and gates of the N FETs, or any combination thereof.

In some embodiments, the one or more diodes and one or more resistors described with reference to Figures 15 and 16 can be implemented on the same die as the one or more switching circuits 320, implemented off the die, or any combination thereof.

In some implementations, as described herein, the aforementioned example configurations described with reference to Figures 15 and 16 can be relatively simple and easy to implement and can yield numerous improvements. For example, the technique can improve the compression roll-off characteristics (e.g., smooth roll-off) of an RF switch. In another example, the technique can improve the IMD performance of an RF switch. In yet another example, the technique can allow an RF switch design to eliminate a resistor-body contact topology that requires additional area overhead associated with, for example, a body resistor, control lines, and level shifters.

Summary of Example 4

According to many implementations, Example 4 relates to a radio frequency (RF) switch comprising at least one field effect transistor (FET) disposed between first and second nodes, each of the at least one FET having a corresponding body and a gate. The RF switch further comprises a coupling circuit coupling the corresponding body and gate of each FET. The coupling circuit comprises a diode connected in series with a resistor and configured to facilitate removal of excess charge from the corresponding body.

In some embodiments, the FET can be a silicon-on-insulator (SOI) FET. In some embodiments, the anode of the diode can be connected to the body, and the cathode of the diode can be connected to one end of the resistor, wherein the other end of the resistor is connected to the gate. The diode and the resistor can be configured to produce improved P1dB and IMD performance of the switch.

In some embodiments, the RF switch may further include a gate resistor connected to the gate to facilitate floating the gate. In some embodiments, when the FET is in an on-state, the first node may be configured to receive an RF signal having a power value, and the second node may be configured to output the RF signal. The at least one FET may include N FETs connected in series, where the number N is selected to allow the switch circuit to handle the power of the RF signal.

In many implementations, Example 4 relates to a method for operating a radio frequency (RF) switch. The method includes controlling at least one field effect transistor (FET) disposed between first and second nodes so that each FET is in an on state or an off state. The method further includes removing excess charge from the body of each FET by coupling a coupling circuit that couples the body of the FET to a gate. The coupling circuit includes a diode connected in series with a resistor.

According to some implementations, Example 4 relates to a semiconductor die comprising a semiconductor substrate and at least one field effect transistor (FET) formed on the semiconductor substrate. The die further comprises a coupling circuit coupling a body and a gate of each FET. The coupling circuit comprises a diode connected in series with a resistor and configured to facilitate removal of excess charge from the body of each FET.

In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. The die may be a silicon-on-insulator (SOI) die.

In many implementations, Example 4 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate and forming at least one field effect transistor (FET) on the semiconductor substrate, wherein each of the FETs has a corresponding gate and body. The method further includes forming a coupling circuit on the semiconductor substrate. The coupling circuit includes a diode connected in series with a resistor. The method further includes connecting the coupling circuit between the body and the gate of each FET to facilitate removing excess charge from the body.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

According to many implementations, Example 4 relates to a radio frequency (RF) switch module comprising a package substrate configured to house a plurality of components. The module further comprises a semiconductor die mounted on the package substrate, the die having at least one field effect transistor (FET). The module further comprises a coupling circuit coupling a body and a gate of each FET. The coupling circuit comprises a diode connected in series with a resistor and configured to facilitate removal of excess charge from the body of each FET.

In some embodiments, the semiconductor die may be a silicon-on-insulator (SOI) die. In some embodiments, the coupling circuit may be part of the same semiconductor die as the at least one FET. In some embodiments, the coupling circuit may be part of a second die mounted on the package substrate. In some embodiments, the coupling circuit may be disposed at a location external to the semiconductor die.

In some implementations, Example 4 relates to a wireless device comprising a transceiver configured to process an RF signal. The wireless device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises at least one field effect transistor (FET). The switch further comprises a coupling circuit coupling a body and a gate of each FET. The coupling circuit comprises a diode connected in series with a resistor and configured to facilitate removal of excess charge from the body of each FET.

Description of Example 5

Intermodulation distortion (IMD) measures unwanted signals added to a desired signal due to mixing products from other RF signals. This effect can be particularly pronounced in multimode, multiband environments. IMD can result from two or more signals mixing together to produce non-harmonic frequencies.

System designers often strive to reduce interference susceptibility by, for example, improving linearity. The linearity of a given system can govern how much IMD will occur within it, which in turn can generate interference. By improving the linearity of system building blocks (such as RF switches), the system's overall susceptibility to interference can be reduced.

Performance characteristics such as lower IMD in RF switches can be important factors in wireless device design. For example, Long Term Evolution (LTE) systems can significantly benefit from RF switches with reduced IMD. As a more specific example, simultaneous voice and data over LTE (SVLTE) system designs can significantly benefit from RF switches with ultra-low levels of IMD.

17A shows an example switching circuit 340 having an SOI FET 120 configured to provide a switching function between a first node 144 and a second node 146. A gate bias signal may be provided to the gate of the FET 120 via a gate resistor (resistance Rg). A body bias signal may be provided to the body of the FET 120 via a body resistor (resistance Rb).

In some implementations, one or more additional gate and/or body resistors can be provided to the FET 120. In the example configuration 340, an additional gate resistor (resistor R1) is shown connected in series with the gate resistor Rg. In some embodiments, such additional gate resistance can be introduced in a selective manner, for example, by a switch S1 (e.g., another FET). For example, opening the switch S1 causes the additional resistor R1 to be connected in series with Rg; and closing S1 causes the additional resistor R1 to be bypassed when no additional resistance is required or desired (e.g., for improved switching time).

In the example configuration 340, an additional bulk resistor (resistance R2) is shown connected in series with bulk resistor Rb. In some embodiments, this additional bulk resistance can be introduced in a selective manner, for example, by switch S2 (e.g., another FET). For example, opening switch S2 causes additional resistor R2 to be connected in series with Rb; and closing S2 causes additional resistor R2 to be bypassed when additional resistance is not required or desired (e.g., for improved switching time).

In some implementations, the additional resistance for the gate and body can be turned on or off together, or independently of each other. In some embodiments, only one of the additional resistances can be provided to the gate or the body. For example, FIG17B shows an example configuration 340 in which additional gate resistance is provided as described with reference to FIG17A , but the body is configured to have a diode (D) body contact.

18A and 18B illustrate a switch arm 350 having the switching circuits described with reference to FIGs. 17A and 17B. In the example configuration 350 of FIG18A, N switching circuits having gate resistors Rg and body resistors Rb are connected in series to provide a switching function between terminals 144, 146. A common additional resistor R1 is shown as being provided to the gate of FET 120; and this additional resistor R1 can be switched on and off by a common switch S1. A common additional resistor R2 is shown as being provided to the body of FET 120; and this additional resistor R2 can be switched on and off by a common switch S2. In some embodiments, this switchable additional resistor can be provided separately to individual gates and/or bodies of the FETs in the switch arm 350, or to some of the gates and/or bodies of the FETs.

In the example configuration 350 of FIG18B , N switching circuits having gate resistors Rg and diode body contacts are connected in series to provide a switching function between terminals 144, 146. A common additional resistor R1 is shown as being provided to the gate of FET 120; and this additional resistor R1 can be switched on and off by a common switch S1. In some embodiments, this switchable additional resistor can be provided separately to individual gates and/or bodies of the FETs in the switching arm 350, or to some of the gates and/or bodies of the FETs.

The number N of switching circuits in the switching arm 350 may be selected based on power handling requirements. For example, N may be increased to handle higher power.

In some embodiments, one or more additional resistors (R1 and/or R2) and one or more of their corresponding switches described with reference to Figures 17 and 18 can be implemented on the same die, below the die, or in any combination thereof as one or more switching circuits 340.

In some embodiments, the values of one or more additional resistors (R1 and/or R2) can be selected to optimize or improve IMD performance so as to minimize or reduce the impact on the switching time of the switch circuit 340. This configuration can result in improved IMD performance, including improved low-frequency blocking. For example, the additional resistors (R1 and R2) can be selected to create a high impedance at the gate and body for low-frequency signals, thereby preventing or reducing leakage of such low-frequency signals to the gate and body.

In some implementations, and as described herein, the aforementioned example configurations described with reference to Figures 17 and 18 can be relatively simple and easy to implement and can yield numerous improvements. For example, the technique can improve the IMD performance of RF switches, including at low frequencies.

Summary of Example 5

According to many implementations, Example 5 relates to a radio frequency (RF) switch comprising at least one field effect transistor (FET) disposed between first and second nodes, each of the at least one FET having a corresponding body and a gate. The RF switch further comprises an adjustable resistance circuit connected to at least one of the corresponding gate and body of each FET.

In some embodiments, the FET may be a silicon-on-insulator (SOI) FET. In some embodiments, the adjustable resistance circuit may include a first resistor connected in series with a parallel combination of a second resistor and a bypass switch. Closing the bypass switch may cause the second resistor to be bypassed to produce a first resistance of the adjustable resistance, and opening the bypass switch may result in a second resistance that is approximately the same value as the first resistance. The first resistor may include a bias resistor. The second resistor may be selected to improve intermodulation distortion (IMD) performance, and the first resistor may be selected to have a reduced effect on the switching time of the FET.

In some embodiments, the adjustable resistance circuit may be connected to the gate. In some embodiments, the RF switch may further include a second adjustable resistance circuit connected to the body. In some embodiments, the RF switch may further include a diode body contact connected to the body.

In some embodiments, the adjustable resistance circuit may be connected to the body rather than the gate. In some embodiments, when the FET is in an on-state, the first node may be configured to receive an RF signal having a power value, and the second node may be configured to output the RF signal. The at least one FET may include N FETs connected in series, where the number N is selected to allow the switching circuit to handle the power of the RF signal.

In some implementations, Example 5 relates to a method for operating a radio frequency (RF) switch. The method includes controlling at least one field effect transistor (FET) disposed between first and second nodes so that each FET is in an on state or an off state. The method further includes adjusting a resistance of a circuit connected to at least one of a gate and a body of each FET.

In some embodiments, the adjusting may include bypassing one of the first and second resistors connected in series.

According to various implementations, Example 5 relates to a semiconductor die comprising a semiconductor substrate and at least one field effect transistor (FET) formed on the semiconductor substrate. The die further comprises an adjustable resistance circuit connected to at least one of a gate and a body of each FET.

In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. The die may be a silicon-on-insulator (SOI) die.

In many implementations, Example 5 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate and forming at least one field effect transistor (FET) on the semiconductor substrate, wherein each of the at least one FET has a corresponding gate and body. The method further includes forming a coupling circuit on the semiconductor substrate. The method further includes connecting the adjustable resistance circuit to at least one of the gate and the body of each FET.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

According to some implementations, Example 5 relates to a radio frequency (RF) switch module, comprising a package substrate configured to house a plurality of components. The module further comprises a semiconductor die mounted on the package substrate, wherein the die comprises at least one field effect transistor (FET). The module further comprises an adjustable resistance circuit connected to at least one of a gate and a body of each FET.

In some embodiments, the semiconductor die may be a silicon on insulator (SOI) die. In some embodiments, the adjustable resistance circuit may be part of the same semiconductor die as the at least one FET. In some embodiments, the adjustable resistance circuit may be part of a second die mounted on the package substrate. In some embodiments, the adjustable resistance circuit may be arranged at a location external to the semiconductor die.

In some implementations, Example 5 relates to a wireless device comprising a transceiver configured to process an RF signal. The wireless device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises at least one field effect transistor (FET). The switch further comprises an adjustable resistance circuit connected to at least one of a gate and a body of each FET.

Description of Example 6

Intermodulation distortion (IMD) measures unwanted signals added to a desired signal due to mixing products from other RF signals. This effect can be particularly pronounced in multimode, multiband environments. IMD can result from two or more signals mixing together to produce non-harmonic frequencies.

System designers often strive to reduce interference susceptibility by, for example, improving linearity. The linearity of a given system can govern how much IMD will occur within it, which in turn can generate interference. By improving the linearity of system building blocks (such as RF switches), the system's overall susceptibility to interference can be reduced.

Performance characteristics such as lower IMD in RF switches can be important factors in wireless device design. For example, Long Term Evolution (LTE) systems can significantly benefit from RF switches with reduced IMD. As a more specific example, simultaneous voice and data over LTE (SVLTE) system designs can significantly benefit from RF switches with ultra-low levels of IMD.

19 shows an example switching circuit 360 having an SOI FET 120 configured to provide a switching function between a first node 144 and a second node 146. The gate terminal of the FET 120 can be biased, for example, to float the gate, by a gate resistor Rg. The body terminal of the FET 120 can be biased, for example, to float the body, by a body resistor Rb.

In some embodiments, the switching circuit 360 can be implemented to utilize the body terminal of the FET 120 to produce improved IMD performance. In the switching circuit 360, an RC circuit comprising a capacitor 362 (capacitor C) in series with a resistor 364 (resistance R) can couple the body and gate of the FET 120. This coupling can allow for discharge of interface charge from the body. In some embodiments, the values of capacitor C and resistor R can be selected to optimize or improve the IMD performance of the switching circuit 360.

FIG20 shows a switch arm 370 having multiple switch circuits 360 as described with reference to FIG19. In the example configuration 370, N such switch circuits are shown connected in series to provide switching functionality between terminals 144, 146. The number N can be selected based on power handling requirements. For example, N can be increased to handle higher power.

In some embodiments, the gate bias voltage (Vg) for the plurality of FETs 120 can be substantially the same and provided by a common gate bias circuit. This common gate bias voltage Vg is shown as being provided to the gate via a gate resistor Rg. In some embodiments, some or all of the gates of the FETs 120 can be biased separately. In some cases, such as when it is desired that the voltage division across the FETs be substantially equal, it can be advantageous to implement such separate biasing of the gates.

In the example configuration 370 of Figure 20, a circuit having a capacitor (capacitor C) and a resistor (resistance R) as described with reference to Figure 19 can be provided to each of N separate switching circuits 360, which can provide a common coupling between the bodies and gates of the N FETs or any combination thereof.

In some embodiments, the one or more capacitors and the one or more resistors described with reference to Figures 19 and 20 can be implemented on the same die as the one or more switching circuits 360, implemented below the die, or any combination thereof.

In some implementations, and as described herein, the aforementioned example configurations described with reference to Figures 19 and 20 can be relatively simpler and easier to implement and can yield numerous improvements. For example, the technique can improve the IMD performance of an RF switch. In another example, the technique can provide an improved roll-off characteristic of P1dB.

Summary of Example 6

According to many implementations, Example 6 relates to a radio frequency (RF) switch comprising at least one field effect transistor (FET) disposed between first and second nodes, wherein each of the at least one FET has a corresponding body and a gate. The RF switch further comprises a coupling circuit disposed between the corresponding body and the gate of each FET. The coupling circuit is configured to allow discharge of interface charge from the corresponding body.

In some embodiments, the FET may be a silicon-on-insulator (SOI) FET. In some embodiments, the coupling circuit may include a capacitor in series with a resistor. The capacitor and the resistor may be selected to produce improved intermodulation distortion (IMD) performance of the switch.

In some embodiments, the RF switch may further include a gate bias resistor connected to the gate. In some embodiments, the RF switch may further include a body bias resistor connected to the body.

In some embodiments, when the FET is in an on-state, the first node can be configured to receive an RF signal having a power value, and the second node can be configured to output the RF signal. The at least one FET can include N FETs connected in series, where the number N is selected to allow the switching circuit to handle the power of the RF signal.

According to some implementations, Example 6 relates to a method for operating a radio frequency (RF) switch. The method includes controlling at least one field effect transistor (FET) disposed between a first node and a second node so that the FET is in an on state or an off state. The method further includes discharging interface charge from the corresponding body of the FET via a coupling circuit disposed between the corresponding body and a corresponding gate of the FET.

In many implementations, Example 6 relates to a semiconductor die comprising a semiconductor substrate and at least one field effect transistor (FET) formed on the semiconductor substrate. The die further comprises a coupling circuit disposed between a body and a gate of each FET. The coupling circuit is configured to allow discharge of interface charge from the body.

In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. The die may be a silicon-on-insulator (SOI) die.

In some implementations, Example 6 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate and forming at least one field effect transistor (FET) on the semiconductor substrate, wherein each of the at least one FET has a gate and a body. The method further includes forming a coupling circuit on the semiconductor substrate, the coupling circuit connected to the corresponding body and gate of each FET to allow discharge of interface charge from the corresponding body.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate. In some embodiments, the coupling circuit may include a capacitor connected in series with a resistor.

According to some implementations, Example 6 relates to a radio frequency (RF) switch module comprising a package substrate configured to house a plurality of components. The module further comprises a semiconductor die mounted on the package substrate, wherein the die comprises at least one field effect transistor (FET). The module further comprises a coupling circuit disposed between a corresponding body and a gate of each FET. The coupling circuit is configured to allow discharge of interface charge from the body.

In some embodiments, the semiconductor die may be a silicon-on-insulator (SOI) die. In some embodiments, the coupling circuit may include a capacitor in series with a resistor.

In some embodiments, the coupling circuit can be part of the same semiconductor die as the at least one FET. In some embodiments, the coupling circuit can be part of a second die mounted on the package substrate. In some embodiments, the coupling circuit can be disposed at a location external to the semiconductor die.

According to many implementations, Example 6 relates to a wireless device comprising a transceiver configured to process an RF signal. The wireless device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises at least one field effect transistor (FET). The switch further comprises a coupling circuit disposed between a body and a gate of each FET. The coupling circuit is configured to allow discharge of interface charge from the body.

Description of Example 7

In many radio frequency (RF) applications, it is desirable to utilize a switch with low insertion loss and high isolation values. It is also desirable for such a switch to have high linearity. As described herein, such advantageous performance characteristics can be achieved without significantly degrading the reliability of the RF switch.

FIG21 shows an example switching circuit 380 having an SOI FET 120 configured to provide a switching function between a first node 144 and a second node 146. The gate of the FET 120 can be biased by a gate resistor Rg, for example, to float the gate. The body of the FET 120 is shown resistively coupled to the gate via a resistor 384 (resistance R), and this coupling can be turned on or off by a second FET 382 (denoted as M2). The operation of M2 can be controlled by a gate bias voltage provided to M2 via a gate resistor Rg2.

When FET 120 (represented as "M1") is on, switch circuit 380 is on and M2 can be off. This configuration can provide minimal or reduced insertion loss of switch circuit 380 by floating the body of M1. When M1 is off, switch circuit 380 is off and M2 can be on. This configuration can provide a DC voltage to the body and gate of M1 from the same node (e.g., gate node "G"). This configuration can prevent or reduce conduction of parasitic junction diodes and can reduce distortion associated with large voltage swings. In some embodiments, this configuration can also eliminate additional bias/control provided to the body of M1.

FIG22 shows a switch arm 390 having multiple switch circuits 380 as described with reference to FIG21 . In the example configuration 390, N such switch circuits are shown connected in series to provide switching functionality between terminals 144, 146. The number N can be selected based on power handling requirements. For example, N can be increased to handle higher power.

In some embodiments, the gate bias voltage (Vg) for the plurality of FETs 120 can be substantially the same and provided by a common gate bias circuit. This common gate bias voltage Vg is shown as being provided to the gate via a gate resistor Rg. In some embodiments, some or all of the gates of the FETs 120 can be biased separately. In some cases, such as when it is desired that the voltage division across the FETs be substantially equal, it can be advantageous to implement such separate biasing of the gates.

In the example configuration 390 of FIG22 , a switchable (via M2) resistive coupling circuit between the body and gate of each FET 120 as described with reference to FIG21 can be provided to each of the N individual switch circuits 380, which can provide a common coupling between the bodies and gates of the N FETs or any combination thereof. In some embodiments, some or all of the bodies of the FETs 120 can be biased separately. In some cases, such as when it is desired that the voltage division across the FETs is substantially equal, it can be advantageous to implement such separate biasing of the bodies.

In some embodiments, the one or more second FETs and the one or more resistors described with reference to Figures 21 and 22 can be implemented on the same die as the one or more switching circuits 320, implemented off the die, or any combination thereof.

In some implementations, and as described herein, the aforementioned example configurations described with reference to Figures 21 and 22 can be relatively simpler and easier to implement and can yield numerous improvements. For example, this technique can minimize or reduce insertion loss in the switch circuit 380 or switch arm 390. In another example, this technique can prevent or reduce conduction of parasitic junction diodes and can reduce distortion associated with large voltage swings.

Summary of Example 7

In some implementations, Example 7 relates to a radio frequency (RF) switch comprising at least one first field effect transistor (FET) disposed between a first node and a second node, wherein each of the at least one first FET has a corresponding body and a gate. The RF switch further comprises a coupling circuit coupling the corresponding body and gate of each of the at least one first FET. The coupling circuit is configured to enable switching between a resistive coupling mode and a body floating mode.

In some embodiments, the first FET may be a silicon-on-insulator (SOI) FET. In some embodiments, the coupling circuit may include a resistor connected in series with a coupling switch. The coupling switch may include a second FET. When the first FET is on, the second FET may be off to produce the body-floating mode. When the first FET is off, the second FET may be on to produce the resistor-coupled mode.

In some embodiments, the RF switch may further include a gate bias resistor connected to the gate. In some embodiments, when the first FET is in an on-state, the first node may be configured to receive an RF signal having a power value, and the second node may be configured to output the RF signal. The at least one first FET may include N FETs connected in series, where the number N is selected to allow the switch circuit to handle the power of the RF signal.

According to a number of implementations, Example 7 relates to a method for operating a radio frequency (RF) switch. The method includes controlling at least one field effect transistor (FET) disposed between first and second nodes so that each of the at least one FET is in an on state or an off state. The method further includes switching between a body-floating mode when each FET is on and a resistance-coupled mode when each FET is off.

In many implementations, Example 7 relates to a semiconductor die comprising a semiconductor substrate and at least one field effect transistor (FET) formed on the semiconductor substrate. The die further comprises a coupling circuit coupling a corresponding body and gate of each of the at least one FET. The coupling circuit is configured to switch between a resistive-coupled mode and a body-floating mode.

In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. In some embodiments, the die may be a silicon-on-insulator (SOI) die.

According to some implementations, Example 7 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate and forming at least one field effect transistor (FET) on the semiconductor substrate, wherein each of the at least one FET has a corresponding gate and body. The method further includes forming a coupling circuit on the semiconductor substrate. The method further includes connecting the coupling circuit to the corresponding body and gate of the at least one FET. The coupling circuit is configured to be switchable between a resistive-coupled mode and a body-floating mode.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

In some implementations, Example 7 relates to a radio frequency (RF) switch module, comprising a package substrate configured to accommodate a plurality of components and a semiconductor die mounted on the package substrate, wherein the die has at least one field effect transistor (FET). The switch module further comprises a coupling circuit coupled to a corresponding body and gate of each of the at least one FET. The coupling circuit is configured to switch between a resistive-coupled mode and a body-floating mode.

In some embodiments, the semiconductor die may be a silicon-on-insulator (SOI) die. In some embodiments, the coupling circuit may be part of the same semiconductor die as the at least one FET. In some embodiments, the coupling circuit may be part of a second die mounted on the package substrate. In some embodiments, the coupling circuit may be disposed at a location external to the semiconductor die.

According to some implementations, Example 7 relates to a wireless device comprising a transceiver configured to process an RF signal, and an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises at least one field effect transistor (FET) and a coupling circuit coupling a corresponding body and gate of each of the at least one FET. The coupling circuit is configured to switch between a resistive-coupled mode and a body-floating mode.

Description of Example 8

Some high-frequency switches using CMOS/SOI (complementary metal oxide semiconductor/silicon on insulator) or pHEMT (pseudo-type high electron mobility transistor) transistors can generate nonlinear distortion that can negatively impact, for example, the ability to meet FCC specifications. Various techniques have been used to reduce this distortion, but they generally do not necessarily address some of the fundamental issues associated with harmonics (e.g., third-order intermodulation distortion (IMD3) and second-order intermodulation distortion (IMD2)). For example, improving one (IMD3 or IMD2) can worsen the other.

FIG23A shows an example switching circuit 400 having an SOI FET 120 configured to provide a switching function between a first node 144 and a second node 146. The gate of the FET 120 can be biased by a gate resistor Rg, for example, to float the gate. The body of the FET 120 is shown coupled to the gate via a circuit having a capacitor 402 (capacitor C) arranged electrically in parallel with a diode 404. In the example, the anode of the diode 404 is connected to the body of the FET 120, and the cathode of the diode 404 is connected to the gate of the FET 120. In some embodiments, the diode 404 can be a PMOS diode, and the resulting parallel combination of the capacitor 402 and the PMOS diode can help improve harmonic management, including improving IMD3 and IMD2.

FIG23B shows another example of a switching circuit example 400 having an SOI FET 120 configured to provide a switching function between a first node 144 and a second node 146. The gate of the FET 120 can be biased by a gate resistor Rg, for example, to float the gate. The body of the FET 120 is shown coupled to the gate via a circuit having a capacitor 402 (capacitor C). In this example, the capacitor 402 can be used to couple the body and gate, but a separate body bias can be provided by a body resistor Rb. In some embodiments, such a body resistor can float the body.

FIG24A shows a switch arm 410 having multiple switch circuits 400 as described with reference to FIG23A . Similarly, FIG24B shows a switch arm 410 having multiple switch circuits 400 as described with reference to FIG23B . In each of the example configurations 410, N such switch circuits are shown connected in series to provide switching functionality between terminals 144, 146. The number N can be selected based on power handling requirements. For example, N can be increased to handle higher power.

In some embodiments, the gate bias voltage (Vg) for the plurality of FETs 120 can be substantially the same and provided by a common gate bias circuit. This common gate bias voltage Vg is shown as being provided to the gate via a gate resistor Rg. In some embodiments, some or all of the gates of the FETs 120 can be biased separately. In some cases, such as when it is desired that the voltage division across the FETs be substantially equal, it can be advantageous to implement such separate biasing of the gates.

In the example configuration 410 of Figures 24A and 24B, a coupling circuit as described with reference to Figures 23A and 23B can be provided between the body and gate of each FET 120 for each of the N individual switch circuits 400. In some embodiments, a common coupling between at least some of the bodies and gates of the N FETs can also be implemented.

In some embodiments, the capacitors and diodes described with reference to Figures 23 and 24 can be implemented on the same die as one or more switching circuits 400, off the die, or any combination thereof.

In some implementations, and as described herein, the aforementioned example configurations described with reference to Figures 23 and 24 can be relatively simpler and easier to implement, and can yield numerous improvements. For example, the configurations of Figures 23A and 23B can be implemented without the need for an additional external bias network. In another example, this technique can improve IMD2 performance while also substantially maintaining the IMD3 performance. In some implementations, a resistance (e.g., a resistor) can be provided between the source and drain of each FET. This configuration can help stabilize the voltage division across the FETs arranged in the stack.

Figures 25A-25D illustrate examples of simulation results that demonstrate some of the advantageous features that can be provided by the RF switch configurations described with reference to Figures 23 and 24. Figure 25A shows curves of simulated IMD2 versus phase shift for three example switch configurations. Curve 412a is for the IMD2 of a standard switch without a capacitor. Curve 412b is for the IMD2 of a standard switch with a capacitor (402 in Figure 23A). Curve 412c is for the IMD2 of a "TR" switch (a "trap-rich" configuration) with a capacitor (402 in Figure 23A). The two switch configurations (412b, 412c) with capacitors are shown to have significantly improved IMD2 values across the entire phase shift range compared to the IMD2 value of the configuration without capacitor (412a).

FIG25A further illustrates simulated IMD3 versus phase shift curves for the three aforementioned example switch configurations. Curve 414a is for the IMD3 of a standard switch without a capacitor. Curve 414b is for the IMD3 of a standard switch with a capacitor (402 in FIG23A). Curve 412c is for the IMD3 of a "TR" switch (a "trap-rich" configuration) with a capacitor (402 in FIG23A). As can be seen, overall IMD3 performance is maintained for each of the three examples. Thus, for the significant improvement in IMD2, the degradation in IMD3 resulting from the addition of capacitor 402 is relatively small.

Figures 25B-25D show simulated harmonic distortion versus input power (P_in) in dBM. Figure 25B is a composite graph of the second and third harmonics and gain of an example SP8T with a standard diode body bias ("w/o cap") and with a diode and shunt capacitor configuration ("w/cap"). Figure 25C shows the curve for the aforementioned diode and shunt capacitor configuration, and Figure 25D shows the curve for the aforementioned diode-only configuration. Looking at the various graphical markers at 32dBm P_in, it can be seen that the second harmonic has a value of approximately -34.5dBm for the "w/o cap" case and a value of approximately -48.4dBm for the "w/cap" case. For the third harmonic, the "w/o cap" case has a value of approximately -50.7dBm, and the "w/cap" case has a value of approximately -51.8dBm. For the comparison of gain, it is also noted that the "w/o cap" case has a value of approximately 0.536 dB, and the "w/cap" case has a value of approximately 0.606 dB. Based on the foregoing example, it can be seen that adding the capacitor improves the second harmonic performance by approximately 14 dB, with a relatively small effect on the third harmonic and the desired effect on the high-band insertion loss (approximately 0.07 dB).

Summary of Example 8

In some implementations, Example 8 relates to a radio frequency (RF) switch comprising at least one field effect transistor (FET) disposed between first and second nodes, wherein each of the at least one FET has a corresponding body and a gate. The RF switch further comprises a coupling circuit coupling the corresponding body and gate of each FET. The coupling circuit comprises a capacitor electrically connected in parallel with a diode.

In some embodiments, the FET may be a silicon-on-insulator (SOI) FET. In some embodiments, the coupling circuit may be configured to improve second-order intermodulation distortion (IMD2) performance without significantly degrading third-order intermodulation distortion (IMD3) performance. In some embodiments, the diode may comprise a PMOS diode. The anode of the diode may be connected to the body and the cathode of the diode may be connected to the gate.

In some embodiments, the RF switch may further include a gate bias resistor connected to the gate. In some embodiments, when the FET is in an on-state, the first node may be configured to receive an RF signal having a power value, and the second node may be configured to output the RF signal. The at least one FET may include N FETs connected in series, where the number N is selected to allow the switch circuit to handle the power of the RF signal.

According to some implementations, Example 8 relates to a method for operating a radio frequency (RF) switch. The method includes controlling at least one field effect transistor (FET) disposed between first and second nodes so that each of the at least one FET is in an on state or an off state. The method further includes coupling a corresponding body and gate of each of the at least one FET via a parallel combination of a capacitor and a diode.

According to many implementations, Example 8 relates to a semiconductor die comprising a semiconductor substrate and at least one field effect transistor (FET) formed on the semiconductor substrate. The die further comprises a coupling circuit coupling a corresponding body and gate of each of the at least one FET. The coupling circuit comprises a capacitor electrically connected in parallel with a diode.

In some embodiments, the die further comprises an insulator layer disposed between the FET and the semiconductor substrate.The die may be a silicon-on-insulator (SOI) die.

In many implementations, Example 8 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate and forming at least one field effect transistor (FET) on the semiconductor substrate, wherein each of the at least one FET has a corresponding gate and body. The method further includes forming a coupling circuit on the semiconductor substrate between the corresponding body and gate of each FET. The coupling circuit includes a capacitor electrically connected in parallel with a diode.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

In some implementations, Example 8 relates to a radio frequency (RF) switch module comprising a package substrate configured to house a plurality of components. The module further comprises a semiconductor die mounted on the package substrate, wherein the die comprises at least one field effect transistor (FET). The module further comprises a coupling circuit coupling a corresponding body and gate of each of the at least one FET. The coupling circuit comprises a capacitor electrically connected in parallel with a diode.

In some embodiments, the semiconductor die may be a silicon-on-insulator (SOI) die. In some embodiments, the coupling circuit may be part of the same semiconductor die as the at least one FET. In some embodiments, the coupling circuit may be part of a second die mounted on the package substrate. In some embodiments, the coupling circuit may be disposed at a location external to the semiconductor die.

According to some implementations, Example 8 relates to a wireless device comprising a transceiver configured to process an RF signal. The wireless device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises at least one field effect transistor (FET). The switch further comprises a coupling circuit coupling a corresponding body and gate of each of the at least one FET. The coupling circuit comprises a capacitor electrically connected in parallel with a diode.

In some implementations, Example 8 relates to a radio frequency (RF) switch comprising at least one field effect transistor (FET) disposed between first and second nodes, wherein each of the at least one FET has a corresponding body and a gate. The RF switch further comprises a coupling circuit coupling the corresponding body and gate of each FET. The coupling circuit comprises a capacitor.

In some embodiments, the FET may be a silicon-on-insulator (SOI) FET.In some embodiments, the coupling circuit may be configured to improve second-order intermodulation distortion (IMD2) performance without significantly degrading third-order intermodulation distortion (IMD3) performance.

In some embodiments, the RF switch may further include a gate bias resistor connected to the gate. In some embodiments, when the FET is in an on-state, the first node may be configured to receive an RF signal having a power value, and the second node may be configured to output the RF signal. The at least one FET may include N FETs connected in series, where the number N is selected to allow the switch circuit to handle the power of the RF signal.

Description of Example 9

It is highly desirable for radio frequency (RF) switches to have low insertion loss, high isolation, and very high linearity. These performance parameters can often conflict with each other. In some cases, these conflicting parameters can be dynamically adjusted by adjusting the gate bias resistor and the bias voltage applied to the body of the FET.

In some cases, a high-value gate resistor can be used to address the aforementioned challenges. However, this fixed high-value gate resistor can be problematic when the FET is in the off state and when it is necessary to short-circuit the signal to ground. In addition, in some cases, a body bias can be applied to float the body when the FET is in the on state, and to ground when the FET is in the off state to improve insertion loss, isolation, and linearity.

26 shows an example of a switching circuit 500 having an SOI FET 120 (also designated as M1) configured to provide a switching function between a first node 144 and a second node 146. The gate of the FET 120 can be biased in a switchable manner using Vctrl through a resistor R1 via a second FET 502 (also designated as M2) as described below. The body of the FET 120 is shown as being switchably resistively coupled to ground via a third FET 506 (also designated as M3) as also described below. The operation of M2 can be controlled by its gate bias voltage V_ctrl_comp provided to M2 via its gate resistor R2. The operation of M3 can be controlled by the same gate bias voltage V_ctrl_comp that would be provided to M3 without the gate resistor.

When the switch circuit 500 is on, M1 is on, and each of M2 and M3 can be off. This configuration can produce minimal or reduced insertion loss by floating the body and providing a high impedance to the gate of M1 (e.g., by making M2 behave like a high-value resistor when M2 is off).

When the switch circuit 500 is off, M1 is off, and each of M2 and M3 can be turned on. This configuration can generate a ground bias for the body of M1 and an Rf ground for the gate of M1, thereby preventing or reducing the effect of a parasitic junction diode and also reducing distortion associated with large voltage swings. When M1 is off, the RF shorting of the gate of M1 can also improve isolation performance.

FIG27 shows a switch arm 510 having multiple switch circuits 500 described with reference to FIG26 . In the example configuration 510, N such switch circuits are shown connected in series to provide switching functionality between terminals 144, 146. The number N can be selected based on power handling requirements. For example, N can be increased to handle higher power.

In some embodiments, a circuit including some or all of R1, R2, R3, M2, and M3 as described with reference to FIG 26 may be provided to each of the N individual switching circuits 500, may be provided to all N switching circuits 500 as a common circuit, or may be provided to any combination thereof.

In some embodiments, R1, R2, R3, M2, and M3 as described with reference to Figures 26 and 27 can be implemented on the same die as one or more switching circuits 500, implemented off the die, or any combination thereof.

In some implementations, and as described herein, the aforementioned example configurations described with reference to Figures 26 and 27 can be relatively simpler and easier to implement, and can yield numerous improvements. For example, when the switch circuit 500 or the switch arm 510 is on, the technique can provide minimal or reduced insertion loss, and when the switch circuit 500 or the switch arm 510 is off, the technique can provide desirable features such as reduced parasitic junction diode effects, reduced distortion associated with large voltage swings, and improved isolation performance.

Summary of Example 9

According to many implementations, Example 9 relates to a radio frequency (RF) switch comprising at least one field effect transistor (FET) disposed between first and second nodes, wherein each of the at least one FET has a corresponding body and a gate. The RF switch further comprises a switchable resistive coupling circuit connected to the corresponding gate of the at least one FET, and a switchable resistive grounding circuit connected to the corresponding body of the at least one FET.

In some embodiments, the FET can be a silicon-on-insulator (SOI) FET. In some embodiments, the switchable resistive coupling circuit can include a bias resistor connected in series with a first coupling switch. The switchable resistive grounding circuit can include a body resistor connected in series with a second coupling switch. When the FET is on, each of the first and second coupling switches can be turned off to generate reduced insertion loss by floating the body and the gate. When the FET is off, each of the first and second coupling switches can be turned on to generate a ground bias for the body and an RF ground for the gate, thereby improving the isolation performance of the RF switch.

In some embodiments, when the FET is in an on-state, the first node can be configured to receive an RF signal having a power value, and the second node can be configured to output the RF signal. The at least one FET can include N FETs connected in series, where the number N is selected to allow the switching circuit to handle the power of the RF signal.

In some implementations, Example 9 relates to a method for operating a radio frequency (RF) switch. The method includes controlling at least one field effect transistor (FET) disposed between a first node and a second node so that each of the at least one FET is in an on state or an off state. The method further includes floating a corresponding gate and body of each FET when each of the at least one FET is in the on state. The method further includes providing a ground bias to the corresponding body and providing an RF ground to the corresponding gate when each FET is in the off state.

In many implementations, Example 9 relates to a semiconductor die comprising a semiconductor substrate and at least one field effect transistor (FET) formed on the semiconductor substrate. The die further comprises a coupling circuit having a switchable resistive circuit connected to a respective gate of each of the at least one FET. The coupling circuit further comprises a switchable resistive grounding circuit connected to a respective body of each of the at least one FET.

In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. The die may be a silicon-on-insulator (SOI) die.

According to some implementations, Example 9 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate. The method further includes forming at least one field effect transistor (FET) on the semiconductor substrate, wherein each of the at least one FET has a corresponding gate and a body. The method further includes forming a switchable resistive coupling circuit on the semiconductor substrate connected to the corresponding gate of the at least one FET. The method further includes forming a switchable resistive grounding circuit on the semiconductor substrate connected to the corresponding body of the at least one FET.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

In some implementations, Example 9 relates to a radio frequency (RF) switch module comprising a package substrate configured to house a plurality of components. The module further comprises a semiconductor die mounted on the package substrate, wherein the die comprises at least one field effect transistor (FET). The module further comprises a coupling circuit comprising a switchable resistive circuit connected to a respective gate of each of the at least one FET. The coupling circuit further comprises a switchable resistive grounding circuit connected to a respective body of each of the at least one FET.

In some embodiments, the semiconductor die may be a silicon-on-insulator (SOI) die. In some embodiments, the coupling circuit may be part of the same semiconductor die as the at least one FET. In some embodiments, the coupling circuit may be part of a second die mounted on the package substrate. In some embodiments, the coupling circuit may be disposed at a location external to the semiconductor die.

In many implementations, Example 9 relates to a wireless device comprising a transceiver configured to process an RF signal. The wireless device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises at least one field effect transistor (FET). The switch further comprises a coupling circuit having a switchable resistive circuit connected to a respective gate of each of the at least one FET and a switchable resistive grounding circuit connected to a respective body of each of the at least one FET.

Description of Example 10

In many radio frequency (RF) transmission applications, switch designs often require high power operation capabilities, especially in the presence of mismatches. For example, switches used for antenna tuning are expected to tolerate mismatches of up to 20:1 at +35dBm input power. In addition, some switches utilized in wireless systems such as GSM are expected to tolerate mismatches of 5:1 at +35dBm input power. Higher field effect transistor (FET) stack heights are often used to tolerate high power in the presence of mismatches. However, uneven voltage distribution across the FET stack can lead to harmonic peaking, compression point degradation, and/or intermodulation distortion (IMD) in SOI-based switches.

28 shows an example configuration of a FET stack 520 configured to provide switching of an RF signal between a first node 144 and a second node 146. The first node 144 and the second node 146 may be, for example, an RF input and an RF output, respectively.

In some implementations, stack 520 may include N SOI FETs (denoted as M1, M2, ..., MN) connected in series between nodes 144, 146. The number N may be selected based on power handling requirements. For example, N may be increased to handle higher power.

In the example stack configuration 520, each gate of the FET is shown as being biased through a gate resistor Rg. N such gate resistors corresponding to the N FETs are shown connected to a common gate bias voltage source "G."

In the example stack configuration 520, each body of the FETs is shown as being biased through a body resistor Rb. N such body resistors corresponding to the N FETs are shown connected to a common body bias voltage source "B."

In some implementations, some or all of the gates of the FETs can be voltage compensated to produce an improved voltage distribution across each FET in the stack 520. This improved voltage distribution can result in improved compression point, harmonics, and IMD performance.

In the example shown in FIG28 , the aforementioned voltage compensation of the gate can be achieved by coupling the gate of the FET to a capacitive element Cgg (e.g., a capacitor). For example, Cgg1 is coupled to the gates of M1 and M2, Cgg2 is coupled to the gates of M2 and M3, and so on, and Cgg(N-2) is coupled to the gates of M(N-2) and M(N-1), and Cgg(N-1) is coupled to the gates of M(N-1) and MN.

In some embodiments, the coupling capacitive elements Cgg may have substantially the same value. In some embodiments, the capacitive elements Cgg may be scaled and/or optimized within the stack 520 to have different values for Cgg1, Cgg2, Cgg3, etc. An example of such scaling of Cgg values to achieve desired results is described in more detail with reference to FIG.

In some embodiments, a feed-forward capacitor Cfwd can be provided to couple the source/drain and gate of an end FET (e.g., M1). In some embodiments, the feed-forward capacitor Cfwd can couple the source/drain and gate of a non-end FET within the FET stack. The feed-forward capacitor Cfwd can ensure that the RF signal path between nodes 144, 146 is coupled to one of the gates of the FETs.

FIG29 shows that in some implementations, gate voltage compensation can be achieved by coupling the gate of the FET to a resistive element Rgg (e.g., a resistor). For example, Rgg1 is coupled to the gates of M1 and M2, Rgg2 is coupled to the gates of M2 and M3, and so on, and Rgg(N-2) is coupled to the gates of M(N-2) and M(N-1), and Rgg(N-1) is coupled to the gates of M(N-1) and MN. In the example of FIG29 , the feedforward coupling between the source/drain and gate of the FET (e.g., M1) is shown to include a capacitor Cfwd in series with a resistor Rfwd.

In some embodiments, the coupling resistive elements Rgg may have substantially the same value. In some embodiments, the resistive elements Rgg may have different values selected to achieve a desired result.

FIG30 shows that in some implementations, gate voltage compensation can be achieved by coupling the gate of the FET to a capacitive element Cgg (e.g., a capacitor) and a resistive element Rgg (e.g., a resistor). For example, Cgg1 and Rgg1 are coupled in series to the gates of M1 and M2, Cgg2 and Rgg2 are coupled in series to the gates of M2 and M3, and so on, as well as Cgg(N-2) and Rgg(N-2) are coupled in series to the gates of M(N-2) and M(N-1), and Cgg(N-1) and Rgg(N-1) are coupled in series to the gates of M(N-1) and MN. In the example of FIG30 , the feedforward coupling between the source/drain and gate of the FET (e.g., M1) is shown to include a capacitor Cfwd in series with a resistor Rfwd.

In some embodiments, the coupling capacitive elements Cgg can have substantially the same value. In some embodiments, the capacitive elements Cgg can have different values selected to achieve the desired result. Similarly, the coupling resistive elements Rgg can have substantially the same value, or different values selected to achieve the desired result.

FIG31 shows a graph of the voltage swing across each FET in an example stack having 16 FETs. The "baseline" configuration corresponds to a stack in which the gates are not voltage-compensated. The "gate-compensated" configuration corresponds to a stack in which the gates are voltage-compensated as described with reference to FIG28. For the graph shown in FIG31, the values of Cgg are selected as Cgg1>Cgg2>Cgg3>...>CggN. The voltage swing associated with this configuration is shown to be significantly smaller than the baseline case.

In some embodiments, the capacitive element Cgg described with reference to Figures 28 and 30 can be implemented on the same die as the FETs (M1, M2, etc.), off the die, or any combination thereof. Such on-die and/or off-die implementations of the capacitive element Cgg can include, for example, MIM capacitors and/or capacitive metal traces.

In some embodiments, the resistive element Rgg described with reference to Figures 29 and 30 can be implemented on the same die as the FETs (M1, M2, etc.), off the die, or any combination thereof.

In some implementations, and as described herein, the aforementioned example configurations described with reference to Figures 28-31 can be relatively simpler and easier to implement and can yield numerous improvements. For example, the technique can provide for less fluctuation in the voltage swing across each FET in the switch stack. This feature can yield other desirable characteristics, such as an improved compression point and improved harmonic and IMD performance.

In some implementations, various example configurations related to gate-to-gate compensation can be combined with one or more features that can improve the performance of one or more FETs in a given stack.

Summary of Example 10

In some implementations, Example 10 relates to a radio frequency (RF) switch comprising a plurality of field effect transistors (FETs) connected in series between first and second nodes, wherein each FET has a gate. The RF switch further comprises a compensation network having a coupling circuit coupling the gates of each pair of adjacent FETs.

In some embodiments, at least some of the FETs may be silicon-on-insulator (SOI) FETs. In some embodiments, the compensation network may be configured to reduce a voltage swing across each of the plurality of FETs. In some embodiments, the switch may further include a feedforward circuit coupled to a source of the terminal FET and a gate of the terminal FET. The feedforward circuit may include a capacitor. The feedforward circuit may further include a resistor coupled to the capacitor.

In some embodiments, the coupling circuit may include a capacitor. The capacitor may have a capacitance value that continuously decreases as the FET moves from the first node to the second node. The coupling circuit may further include a resistor connected in series with the capacitor.

In some embodiments, the coupling circuit may include a resistor. In some embodiments, the switch may further include a gate bias network connected to the gate of the FET and configured to provide a bias signal to the gate of the FET. The gate bias network may be configured so that all of the gates receive a common bias signal.

In some embodiments, the switch may further include a body bias network connected to the body of the FET and configured to provide a bias signal to the body of the FET. The body bias network may be configured such that all of the bodies receive a common bias signal.

In some embodiments, when the FET is in an on-state, the first node can be configured to receive an RF signal having a power value, and the second node can be configured to output the RF signal. The at least one FET can include N FETs connected in series, where the number N is selected to allow the switching circuit to handle the power of the RF signal.

According to many implementations, Example 10 relates to a method for operating a radio frequency (RF) switch. The method includes controlling a plurality of field effect transistors (FETs) connected in series between first and second nodes so that the FETs are collectively in an on state or an off state, wherein each FET has a gate. The method further includes coupling gates of each of adjacent FETs to reduce a voltage swing across each of the plurality of FETs.

According to many implementations, Example 10 relates to a semiconductor die comprising a semiconductor substrate and a plurality of field effect transistors (FETs) formed on the semiconductor substrate and connected in series, wherein each FET has a gate. The die further comprises a compensation network formed on the semiconductor substrate, the compensation network comprising a coupling circuit coupling the gates of each pair of adjacent FETs.

In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. The die may be a silicon-on-insulator (SOI) die.

In various implementations, Example 10 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate and forming a plurality of field effect transistors (FETs) connected in series on the semiconductor substrate, wherein each FET has a gate. The method further includes forming a coupling circuit on the semiconductor substrate to couple the gates of each pair of adjacent FETs.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

In many implementations, Example 10 relates to a radio frequency (RF) switch module comprising a package substrate configured to house a plurality of components. The module further comprises a semiconductor die mounted on the package substrate. The die comprises a plurality of field effect transistors (FETs) connected in series, each FET having a gate. The module further comprises a compensation network having a coupling circuit coupling the gates of each pair of adjacent FETs.

In some embodiments, the semiconductor die may be a silicon-on-insulator (SOI) die. In some embodiments, the compensation network may be part of the same semiconductor die as the at least one FET. In some embodiments, the compensation network may be part of a second die mounted on the package substrate. In some embodiments, the compensation network may be disposed at a location external to the semiconductor die.

According to some implementations, Example 10 relates to a wireless device comprising a transceiver configured to process an RF signal. The wireless device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises a plurality of field effect transistors (FETs) connected in series, each FET having a gate. The switch further comprises a compensation network having a coupling circuit coupling the gates of each pair of adjacent FETs.

Description of Example 11

Intermodulation distortion (IMD) measures unwanted signals added to a desired signal due to mixing products from other RF signals. This effect can be particularly pronounced in multimode, multiband environments. IMD can result from two or more signals mixing together and producing non-harmonic frequencies.

System designers often strive to reduce interference susceptibility through, for example, improved linearity. The linearity of a given system can manage how much IMD will occur within it, which in turn can generate interference. By improving the linearity of system building blocks (such as RF switches), the system's overall susceptibility to interference can be reduced.

Performance characteristics such as lower IMD in RF switches can be important factors in wireless device design. For example, Long Term Evolution (LTE) systems can significantly benefit from RF switches with reduced IMD. As a more specific example, system designs for simultaneous voice and data transmission over LTE (SVLTE) can significantly benefit from RF switches with ultra-low levels of IMD.

32 shows a switch configuration 250 in an example context of a single-pole, double-throw (SPDT) application. A single pole is shown connected to an antenna 252. One of the two throws is shown coupled to a receive (Rx) port via a switch circuit S. The Rx port can be coupled to ground via a shunt switch circuit.

Similarly, the other throw is shown coupled to a transmit (Tx) port via a switch circuit S. The Tx port may be coupled to ground via a shunt switch circuit.

In some embodiments, each of the switch circuits ("S" and "shunt") can include one or more FETs, such as SOI FETs. Reference numerals 120 or 122 are sometimes used herein to refer to a single FET, and reference numerals 140 or 142 are sometimes used herein to refer to a stack of such FETs. In some embodiments, the "S" and "shunt" switches can include one or more features described herein to provide various advantageous functions.

The switch configuration of Figure 32 is shown to include capacitors to prohibit low-frequency blockers from mixing with the fundamental frequency. For example, capacitor C1 is provided between the antenna node and the switch arm S of the Tx throw. Similarly, capacitor C2 is provided between the antenna node and the switch arm S of the Rx throw. For the shunt arm, capacitor C3 is provided between the Tx node and its shunt switch arm. Similarly, capacitor C4 is provided between the Rx node and its shunt switch arm. In some embodiments, a shunt arm may or may not be provided for the Rx node. Using the aforementioned capacitors, low-frequency interference signals can be prevented or reduced from mixing with any conductive or disconnected paths. This can lead to improved IMD performance, especially for low-frequency blocking signals.

FIG33 illustrates an example operating configuration in which some of the aforementioned capacitors can provide the desired switching functionality. In this example, the switch configuration is in transmit mode. Accordingly, the transmit switch arm is on (closed) and the receive switch arm is disconnected (open). The shunt arm for the Tx node is disconnected (open). In some embodiments, the capacitors C1-C4 described with reference to FIG32 and FIG33 can be implemented on the same die as their corresponding switching circuits, off the die, or in any combination thereof.

In some implementations, and as described herein, the aforementioned example configurations described with reference to Figures 32 and 33 can be relatively simpler and easier to implement and can yield numerous improvements. For example, the technique can provide improved IMD performance by preventing low-frequency blocker signals from mixing with the fundamental frequency signal.

Summary of Example 11

In some implementations, Example 11 relates to a radio frequency (RF) switch system comprising a switch having a stack of field effect transistors (FETs) connected in series between first and second nodes. The system further comprises a capacitor connected in series with the switch and configured to inhibit mixing of a fundamental frequency signal in the switch with a low frequency blocking signal.

In some embodiments, the FET may be a silicon-on-insulator (SOI) FET. In some embodiments, the first node may be an antenna node. The capacitor may be arranged between the switch and the antenna node. The switch may be part of a transmit path such that a second node of the switch is an input node for an amplified RF signal. The switch may be part of a receive path such that a second node of the switch is an output node for an RF signal received from the antenna.

According to some implementations, Example 11 relates to a semiconductor die having a semiconductor substrate and a switch formed on the semiconductor substrate and having a stack of field effect transistors (FETs) connected in series. The die further includes a capacitor formed on the semiconductor substrate and connected in series with the switch. The capacitor is configured to inhibit a fundamental frequency signal in the switch from mixing with a low-frequency blocking signal.

In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. The die may be a silicon-on-insulator (SOI) die.

In many implementations, Example 11 relates to a method for manufacturing a semiconductor die. The method includes providing a semiconductor substrate and forming a stack of field effect transistors (FETs) on the semiconductor substrate so as to be connected in series. The method further includes forming a capacitor on the semiconductor substrate so as to be connected in series with an end of the stack. The capacitor is configured to prevent a fundamental frequency signal in the stack from mixing with a low-frequency blocking signal.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

According to some implementations, Example 11 relates to a radio frequency (RF) switch module comprising a package substrate configured to accommodate a plurality of components. The module further comprises a semiconductor die mounted on the package substrate. The die comprises a switch having a stack of field effect transistors (FETs) connected in series. The module further comprises a capacitor connected in series with the switch. The capacitor is configured to inhibit mixing of a fundamental frequency signal in the switch with a low-frequency blocking signal.

In some embodiments, the semiconductor die can be a silicon on insulator (SOI) die. In some embodiments, the capacitor can be part of the same semiconductor die as the FET. In some embodiments, the capacitor can be part of a second die mounted on the package substrate. In some embodiments, the capacitor circuit can be arranged at a location external to the semiconductor die.

In many implementations, Example 11 relates to a wireless device comprising a transceiver configured to process RF signals. The wireless device further comprises an antenna in communication with the transceiver. The wireless device further comprises a switch module interconnected with the antenna and the power amplifier and configured to selectively route the RF signals to and from the antenna. The switch module comprises a switch comprising a stack of field effect transistors (FETs) connected in series. The switch module further comprises a capacitor connected in series with the switch. The capacitor is configured to inhibit mixing of a baseband signal in the switch with a low-frequency blocking signal.

Description of Example 12

In some implementations, body-to-body compensation techniques can be applied to a stack of FETs, such as SOI FETs. This technique can provide, for example, reduced fluctuations in the voltage swing across each FET in the switch stack. This feature can result in other desirable characteristics, such as an improved compression point and improved harmonic and IMD performance.

In some radio frequency (RF) applications, including those operating with high mismatch, it is desirable to operate transmit switches at high power. For example, a GSM switch can operate at +35dBm with a 5:1 mismatch, and switches used in antenna tuning can operate at 35dBm with up to a 20:1 mismatch.

In some RF applications, transmit switches operating at high power can experience uneven voltage distribution across the switch. Uneven voltage swings across the switch can produce adverse effects in device performance, including harmonic peaking, compression point degradation, and intermodulation distortion (IMD) performance of the switch.

Described herein are circuits, apparatus, and methods for providing more uniform voltage swings across a transfer switch for improved device performance. In some implementations, increased uniformity of the voltage swing across the transfer switch can result in improved compression point, harmonic, and intermodulation distortion performance.

The switching device can be in a first state or a second state, such that the switching device can allow RF signals to be transmitted between the first port and the second port when in one of the states. For example, when the RF switching device is in the first state, such as the on state, the RF switching device can enable RF signals to be transmitted from one port (e.g., the input port) to the second port (e.g., the output port). When in the second state, such as the off state, the RF switching device can prevent RF signals from being transmitted from the input port to the output port, thereby electrically isolating the input port from the output port.

34 , a switching device 10 having a first port and a second port can include a switching circuit 11. In some embodiments, the switching circuit 11 can further include a voltage distribution equalization circuit 12. When the switching circuit is in an on-state, in which an RF signal can be transmitted between the input port and the output port, the voltage distribution equalization circuit 12 can enable a more uniform voltage distribution across the switching circuit 11. In some embodiments, the voltage distribution equalization circuit 12 can improve the voltage distribution across the switching circuit 11 when operating at high power. The increased uniformity of the voltage swing across the switching circuit 11 can enable improved performance of the switching device 10, including improvements in compression point, harmonics, and intermodulation distortion performance.

The switching circuit 10 can be implemented on a semiconductor substrate. In the context of a semiconductor substrate, the switching device 10 can include a switching circuit 11 having a FET stack. In some embodiments, the FET stack can include one or more FETs, wherein the FETs have a source, a drain, a body node, or a gate node. Additional FETs can be connected in series to define an RF signal path between an input and an output. In some embodiments, the FET stack can be in a first or second state, such that when in the first state, such as the on state, an RF signal can be transmitted from the input to the output, allowing the switching device 10 to transmit RF signals from the input to the output. At the same time, when the FETs are in the second state, such as the off state, the FETs can prevent RF signals from being transmitted between the input and the output, thereby electrically isolating the input and output of the switching device 10. Figure 35 shows an example of a switching circuit having a FET stack, which includes five FETs connected in series and defining an input and an output: FET1, FET2, FET3, FET4, and FET5.

Increasing the FET stack height or number of FETs in a switch circuit can improve switch device performance, including performance when operating at high power. However, when the switch device is in the on-state and encounters an RF signal at its input port, the switch device can exhibit a non-uniform voltage distribution across the switch device FET stack. In some embodiments, the switch device can exhibit a non-uniform voltage distribution across the switch device FET stack when operating at high power. The non-uniform voltage swing across the FET stack can adversely affect device performance, including harmonic peaking, intermodulation distortion (IMD), or compression point degradation.

A voltage distribution balancing circuit can be coupled to a switching circuit to improve voltage swing uniformity across the switching circuit. A switching circuit having a FET stack can include a voltage distribution balancing circuit that utilizes the body nodes of the body-contacted FETs for voltage compensation, thereby improving voltage distribution uniformity across the FET stack or reducing voltage distribution variation. In some embodiments, the voltage distribution balancing circuit can include body node voltage compensation technology. For example, the voltage distribution balancing circuit of the switching circuit can include a capacitive element coupled to the body nodes of the FETs in the FET stack. In some embodiments, the capacitive element is coupled to the body node of each FET in the FET stack. The voltage distribution balancing circuit can also optionally include a resistive element coupled to the body nodes of the FETs in the FET stack. In some embodiments, the resistive element is coupled to the body node of each FET in the FET stack. In addition, a main RF signal can be coupled to the body nodes of the FETs in the FET stack. In some embodiments, the RF signal is coupled to the body nodes of the FETs in the FET stack via a feed-forward capacitive element Cfwd or a feed-forward resistive element Rfwd.

Referring to Figure 36, the voltage distribution equalization circuit of the switch circuit with the FET stack can optionally couple the capacitor element Cbb to the body node of the FET in the FET stack. In the example switch circuit of Figure 36 comprising five FETs (FET1, FET2, FET3, FET4 and FET5), the body nodes of FET1, FET2, FET3, FET4 and FET5 are coupled to the capacitor elements Cbb1, Cbb2, Cbb3 and Cbb4. The capacitance value of the capacitor element Cbb can be scaled to improve the performance of the switch device. The capacitance value of Cbb can be selected to increase the voltage swing uniformity across the FET stack. In some embodiments, the capacitance of the capacitor element Cbb can also optionally have different values. In addition, in some embodiments, the capacitor element Cbb can be implemented so that the capacitance of the Cbb element is in descending order starting from the Cbb coupled to the first FET in the FET stack. With reference to the embodiment shown in Figure 36, the capacitance values of Cbb1, Cbb2, Cbb3 and Cbb4 can be different from each other. The capacitance value of each of Cbb1, Cbb2, Cbb3, and Cbb4 can be selected to increase the uniformity of the voltage distribution across FET1, FET2, FET3, FET4, and FET 5. In addition, the elements Cbb can each have different capacitance values, such that the capacitance value of Cbb1 is greater than the capacitance value of Cbb2, the capacitance value of Cbb2 is greater than the capacitance value of Cbb3, and the capacitance value of Cbb3 is greater than the capacitance value of Cbb4.

In some embodiments, an implementation of a body node voltage compensation technique in a switch circuit having a FET stack further includes a feedforward capacitive element Cfwd coupling a main RF signal path to the body node. The RF signal path can be coupled to the body node via a FET in the FET stack. In an example embodiment, as shown in FIG36 , the feedforward capacitive element Cfwd can couple the RF signal path to the body node of a first FET in the FET stack. In such an embodiment, the RF signal path is coupled to the body node of the first FET via the source or drain of the first FET. Alternatively, the RF signal path can optionally be coupled via the source or drain of another FET in the FET stack.

Furthermore, as shown in FIG36 , the body node voltage compensation technique may further include a resistor element Rb, such as resistor elements Rb1, Rb2, Rb3, Rb4, and Rb5 in FIG36 , which is implemented to float the body node of each FET in the FET stack. Simultaneously, a resistor element Rg (such as resistor elements Rg1, Rg2, Rg3, Rg4, and Rg5 in FIG36 ) may be implemented to float the gate node of each FET in the FET stack.

FIG37 illustrates the improved voltage swing performance across a FET stack of a switch circuit implementing an embodiment of the voltage distribution balancing circuit. FIG37 compares the voltage swing performance across a FET stack of two example switch devices operating at 35 dBm and a 20:1 mismatch. For the graphical comparison, the voltage swing performance across a switch device incorporating an embodiment of the body node voltage compensation technique is compared to the voltage swing performance across a switch device incorporating an embodiment of the body node voltage compensation technique. The switch device coupled to the embodiment of the body node voltage compensation technique has Cbb elements with different capacitance values, such that the capacitance of Cbb1 is greater than the capacitance of Cbb2, the capacitance of Cbb2 is greater than the capacitance of Cbb3, and so on. Referring to FIG37 , the voltage swing across each FET of the example switch device incorporating an embodiment of the body node voltage compensation technique remains within a significantly narrower range compared to the switch device incorporating no body node voltage compensation technique. Thus, the example switch device incorporating an embodiment of the body node voltage compensation technique exhibits increased voltage swing uniformity across the constituent FETs compared to the example FET stack incorporating no body node voltage compensation circuit.

Referring to FIG38 , a resistor element Rbb can be coupled to the body nodes of FETs in a FET stack of a switching circuit to improve device performance. In some embodiments, the resistor element Rbb can be coupled to the body nodes of each FET in the FET stack of the switching circuit to provide increased voltage distribution uniformity across the FET stack of the switching circuit. For example, a switching circuit for transmitting RF signals at lower frequencies can optionally implement an embodiment of a body node voltage compensation technique, wherein the resistor element Rbb is coupled to the body nodes of each FET in the FET stack to increase voltage swing uniformity across the FET stack. The resistance of the resistor element Rbb can be selected to increase the uniformity of the voltage swing across the FET stack. The resistor elements Rbb coupled to the body nodes of the FETs in the FET stack of the switching circuit can have different resistance values. In some embodiments, the resistor elements Rbb can have resistance values that decrease sequentially, starting with the resistor element Rbb coupled to the first FET in the FET stack.

For example, as shown in FIG38 , in some embodiments of a switch circuit having a FET stack of five FETs connected in series, resistive elements Rbb1, Rbb2, Rbb3, and Rbb4 may be coupled to each of the body nodes of FET1, FET2, FET3, FET4, and FET5. To improve the uniformity of the voltage swing distribution across the FET stack, resistive elements Rbb1, Rbb2, Rbb3, and Rbb4 may also have resistance values in descending order, such that the resistance value of Rbb1 is greater than the resistance value of Rbb2, the resistance value of Rbb2 is greater than the resistance value of Rbb3, and the resistance value of Rbb3 is greater than the resistance value of Rbb4.

Referring to FIG38 , in some embodiments of the body node voltage compensation technique, a feed-forward resistive element may optionally be used from the main RF signal path to the body node of the FET stack. Furthermore, in some embodiments of the body node voltage compensation technique in which the resistive element Rbb is coupled to the body node of an FET in the FET stack, a feed-forward capacitive element may be used from the main RF signal path to the body node of the FET stack. The RF signal path may be coupled to the body node through an FET in the FET stack. In some embodiments implementing both a feed-forward capacitive element and a feed-forward resistive element, the feed-forward capacitive element may be connected in series with the feed-forward resistive element. Referring to FIG38 , a feed-forward capacitive element Cfwd connected in series with the feed-forward resistive element may be used to couple the RF signal to the body node of a first FET in the FET stack. In such embodiments, the RF signal path is coupled to the body node of the first FET through the source or drain of the first FET. Alternatively, the RF signal path may optionally be coupled through the source or drain of another FET within the FET stack.

38 , in some embodiments of the body node voltage compensation technique in which a resistor element Rbb is coupled to the body nodes of the FETs in the FET stack, the switch circuit may further include a resistor element Rb implemented to float the body node of each FET in the FET stack, such as resistor elements Rb1, Rb2, Rb3, Rb4, and Rb5 in FIG 38 . Simultaneously, a resistor element Rg (such as resistor elements Rg1, Rg2, Rg3, Rg4, and Rg5 in FIG 38 ) may be implemented to float the gate node of each FET in the FET stack.

A switching circuit with a voltage distribution equalization circuit can implement an embodiment of a body node voltage compensation technique, wherein the FETs in the FET stack are coupled to a capacitive element Cbb connected in series with a resistive element Rbb. Referring to FIG39 , an example switching circuit implementing an embodiment of a body node voltage compensation technique can couple the body node of each FET in the FET stack to a capacitive element Cbb connected in series with a resistive element Rbb. For example, the body nodes of FET1, FET2, FET3, FET4, and FET5 are coupled to Cbb1 connected in series with Rbb1, Cbb2 connected in series with Rbb2, Cbb3 connected in series with Rbb3, and Cbb4 connected in series with Rbb4, respectively.

Referring to FIG39 , in some embodiments where the body node of an FET in a FET stack is coupled to a capacitive element Cbb connected in series with a resistive element Rbb, a feedforward capacitive element Cfwd can be used from the main RF signal path to the body node of the FET stack. A feedforward resistive element Rfwd can also optionally be used from the main RF signal path to the body node of the FET stack. In some embodiments where both the feedforward capacitive element Cfwd and the feedforward resistive element Rfwd are implemented, the feedforward capacitive element Cfwd can be connected in series with the feedforward resistive element Rfwd. Referring to FIG39 , the feedforward capacitive element Cfwd connected in series with the feedforward resistive element Rfwd can be used to couple the RF signal to the body node of a first FET in the FET stack. In such embodiments, the RF signal path is coupled to the body node of the first FET in the FET stack via the source or drain of the first FET. Alternatively, the RF signal path can optionally be coupled via the source or drain of another FET in the FET stack.

Furthermore, as shown in FIG39 , in some implementations of the body node voltage compensation technique in which the body nodes of the FETs in the FET stack are coupled to the capacitive element Cbb connected in series with the resistive element Rbb, the resistive element Rb (e.g., the resistive elements Rb1, Rb2, Rb3, Rb4, and Rb5 in FIG39 ) can be implemented to float the body node of each FET in the FET stack. Simultaneously, the resistive element Rg (e.g., the resistive elements Rg1, Rg2, Rg3, Rg4, and Rg5 in FIG39 ) can be implemented to float the gate node of each FET in the FET stack.

For a switching circuit that includes different numbers of FETs in a FET stack, a voltage distribution balancing circuit can be implemented. For example, Figure 40 shows a switching circuit with two FETs (FET1 and FET2). For such a switching circuit, a voltage distribution balancing circuit including an embodiment of a body node voltage compensation technology having the characteristics described herein can be implemented. In some embodiments of such a switching circuit, the implementation of the body node voltage compensation technology can include a capacitive element Cbb1 coupled to the body nodes of FET1 and FET2. The body node voltage compensation technology of the example switching circuit can further optionally include a feedforward capacitive element Cfwd that couples the main RF signal path to the body node of the FET (e.g., the first FET, FET1) in the FET stack. In addition, resistor elements Rb1 and Rb2 can be implemented to float the body nodes of FET1 and FET2, respectively. At the same time, resistor elements Rg1 and Rg2 can be implemented to float the gate nodes of FET1 and FET2.

FIG41 illustrates a process 700 that can be implemented to fabricate a voltage swing distribution equalization circuit having one or more features as described herein. In block 702, an array of switches can be formed. In embodiments where the switches are formed on a semiconductor substrate, semiconductor switches, such as FETs, can be formed on the substrate. In block 704, a resistive element can be formed coupled to each of the switches. In the case of a semiconductor substrate, the resistive element can be coupled to the body node or gate node of the FET. As shown in block 706, a capacitive element can be formed coupled to the switch. In the case where the switch comprises a FET formed on the semiconductor substrate, a capacitive element can be formed coupled to the body node of the FET. In block 708, a capacitive element can also be formed from the RF path to the switches in the array. This capacitive element can optionally be formed from the RF path to any switch in the array (including the first switch in the array). In some embodiments where the array of switches comprises FETs formed on the semiconductor substrate, the capacitive element of block 708 can be formed from the source or drain of the first FET to the body node of the first FET.

FIG42 illustrates a process 800 that may be a more specific example of the process illustrated in FIG41 . In block 802 , a plurality of FETs may be formed on a semiconductor substrate. In block 804 , the plurality of FETs may be connected in series to define an input and an output. In block 806 , a resistive element may be coupled to a body node or gate node of each of the series-connected FETs defining the input and output. In block 808 , a capacitive element may be formed coupled to the body node of each of the FETs. Additionally, in block 810 , a capacitive element may be formed from the source or drain of the FET to the body node of the FET to couple the primary RF signal to the body node of the FET. Optionally, a capacitive element may be formed from the source or drain of a first FET to the body node of the first FET in the series of FETs defining the input and output.

Summary of Example 12

In some implementations, Example 12 relates to a radio frequency (RF) switch comprising a plurality of field effect transistors (FETs) connected in series between first and second nodes, wherein each FET has a body. The RF switch further comprises a compensation network having a body coupling circuit coupling each pair of adjacent FETs.

In some embodiments, at least some of the FETs may be silicon-on-insulator (SOI) FETs. In some embodiments, the compensation network may be configured to reduce a voltage swing across each of the plurality of FETs. In some embodiments, the switch may further include a feedforward circuit coupled to a source of the terminal FET and a body of the terminal FET. The feedforward circuit may include a capacitor. The feedforward circuit may further include a resistor in series with the capacitor.

In some embodiments, the coupling circuit may include a capacitor. The coupling circuit may further include a resistor connected in series with the capacitor.

In some embodiments, the coupling circuit may include a resistor. In some embodiments, the switch may further include a body bias network connected to the body of the FET and configured to provide a bias signal to the body of the FET. The body bias network may be configured such that all of the bodies receive a common bias signal.

In some embodiments, the switch may further include a gate bias network connected to the gates of the FETs and configured to provide a bias signal to the gates of the FETs. The gate bias network may be configured such that all the gates receive a common bias signal.

In some embodiments, when the FET is in an on-state, the first node may be configured to receive an RF signal having a power value, and the second node may be configured to output the RF signal. The at least one FET may include N FETs connected in series, where the number N is selected to allow the switching circuit to handle the power of the RF signal.

According to a number of implementations, Example 12 relates to a method for operating a radio frequency (RF) switch. The method includes controlling a plurality of field effect transistors (FETs) connected in series between first and second nodes so that the FETs are collectively in an on state or an off state, wherein each FET has a body. The method further includes coupling the bodies of each of adjacent FETs to reduce a voltage swing across each of the plurality of FETs.

According to many implementations, Example 12 relates to a semiconductor die comprising a semiconductor substrate and a plurality of field effect transistors (FETs) formed on the semiconductor substrate and connected in series, wherein each FET has a body. The die further comprises a compensation network formed on the semiconductor substrate, the compensation network comprising a coupling circuit coupling the bodies of each pair of adjacent FETs.

In some embodiments, the die may further include an insulator layer disposed between the FET and the semiconductor substrate. The die may be a silicon-on-insulator (SOI) die.

In various implementations, Example 12 relates to a method for fabricating a semiconductor die. The method includes providing a semiconductor substrate and forming a plurality of field effect transistors (FETs) on the semiconductor substrate so as to be connected in series, wherein each FET has a body. The method further includes forming a coupling circuit on the semiconductor substrate so as to couple the bodies of each pair of adjacent FETs.

In some embodiments, the method may further include forming an insulator layer between the FET and the semiconductor substrate.

In many implementations, Example 12 relates to a radio frequency (RF) switch module comprising a package substrate configured to house a plurality of components. The module further comprises a semiconductor die mounted on the package substrate. The die comprises a plurality of field effect transistors (FETs) connected in series, wherein each FET has a body. The module further comprises a compensation network having a coupling circuit coupling the bodies of each pair of adjacent FETs.

In some embodiments, the semiconductor die may be a silicon-on-insulator (SOI) die. In some embodiments, the compensation network may be part of the same semiconductor die as the at least one FET. In some embodiments, the compensation network may be part of a second die mounted on the package substrate. In some embodiments, the compensation network may be disposed at a location external to the semiconductor die.

According to some implementations, Example 12 relates to a wireless device comprising a transceiver configured to process an RF signal. The wireless device further comprises an antenna in communication with the transceiver and configured to facilitate transmission of an amplified RF signal. The wireless device further comprises a power amplifier connected to the transceiver and configured to generate the amplified RF signal. The wireless device further comprises a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna. The switch comprises a plurality of field effect transistors (FETs) connected in series, wherein each FET has a body. The switch further comprises a compensation network having a coupling circuit that couples the bodies of each pair of adjacent FETs.

In some implementations, Example 12 relates to a switch circuit comprising an input port configured to receive a radio frequency (RF) signal and an output port configured to output the RF signal. The switch circuit may further comprise one or more field effect transistors (FETs) defining an RF signal path between the input port and the output port, each FET having a source, a drain, a gate node, and a body node. The switch may be configured to be capable of being in a first and second state, the first state corresponding to the input and output ports being electrically connected so as to allow RF signals to pass therebetween, and the second state corresponding to the input and output ports being electrically isolated. The switch circuit may further comprise a voltage distribution circuit configured to reduce a voltage distribution variation across the switch, the voltage distribution circuit comprising one or more elements coupled to selected body nodes of one or more FETs to reduce a voltage distribution variation across the switch when the switch is in the first state and encounters an RF signal at the input port.

In some embodiments, the one or more elements coupled to the selected body nodes of the one or more FETs may include a capacitive element. The one or more elements coupled to the selected body nodes of the one or more FETs may include a resistive element. Furthermore, in some embodiments, the one or more elements coupled to the selected body nodes of the one or more FETs may include a capacitive element connected in series with a resistive element.

In some embodiments, the voltage distribution circuit may include a feed-forward capacitive element configured to couple the RF signal path to the body node of the FET defining the RF signal path (including the body node of the first FET defining the RF signal path). In some embodiments, the voltage distribution circuit includes a feed-forward capacitive element connected in series with a feed-forward resistive element and configured to couple the RF signal path to the body node of the FET defining the RF signal path.

In some embodiments, the voltage distribution circuit may include a resistive element coupled to a gate node of a FET defining an RF signal path, thereby enabling the gate node of the FET to float. The resistive element may also be coupled to a body node of the FET defining the RF signal path, thereby enabling the body node of the FET to float.

According to some implementations, Example 12 relates to an integrated circuit (IC) formed on a bare die. The IC may include a switch having one or more field effect transistors (FETs) defining an RF signal path between an input port and an output port, each FET having a body node. The switch may be configured to be capable of being in an on and off state. In some embodiments, a voltage distribution circuit may be coupled to the switch and configured to reduce a voltage distribution variation across the switch. The voltage distribution circuit may include one or more elements coupled to selected body nodes of one or more FETs to reduce a voltage distribution variation across the switch when the switch is in an on state and encounters a corresponding RF signal at the input port.

In some embodiments, transceiver circuitry may be electrically connected to the switch and configured to process RF signals.

As taught in many implementations, Example 12 relates to a package module for a radio frequency (RF) device. The module includes a package base and an integrated circuit (IC) formed on a semiconductor die and mounted on the package base. The IC may include a switch having one or more field effect transistors (FETs), the FETs defining an RF signal path between an input port and an output port, each FET having a body node, and the switch may be configured to be capable of being in an on and off state. The voltage distribution circuit may be coupled to the switch to reduce a voltage distribution variation across the switch when the switch is in an on state and encounters a corresponding RF signal at the input port. In some embodiments, the voltage distribution circuit may include one or more elements coupled to selected body nodes of one or more FETs defining the RF signal path.

In some embodiments, the package module may further include a package structure configured to facilitate passing signals to and from the switch. In some embodiments, the package module may further include a package structure configured to provide protection to the switch.

According to some implementations, Example 12 relates to a wireless device. The wireless device may include at least one antenna configured to facilitate transmission and reception of radio frequency (RF) signals. In addition, the wireless device may also include a transceiver coupled to the antenna and configured to process radio frequency (RF) signals. In some embodiments, the wireless device may include a switch having one or more field effect transistors (FETs) defining an RF signal path between an input port and an output port, each FET having a body node. In addition, the switch may be configured to be capable of being in an on and off state. In some embodiments, a voltage distribution circuit may be coupled to the switch to reduce a voltage distribution change across the switch when the switch is in an on state and encounters a corresponding RF signal at the input port, the voltage distribution circuit comprising one or more elements coupled to selected body nodes of the one or more FETs defining the RF signal path.

In some embodiments, the wireless device may further include a container configured to receive a battery and provide an electrical connection between the battery and the switch.

According to some implementations, Example 12 relates to a method of manufacturing a radio frequency (RF) switching circuit. The method may include providing or forming a substrate, and forming one or more FETs connected in series on the substrate to define an RF signal path between an input terminal and an output terminal, each FET having a source, a drain, a gate node, and a body node. The method may further include forming an element coupled to selected body nodes of the one or more FETs connected in series to provide reduced voltage distribution variation across the switching circuit.

In some embodiments, forming an element coupled to a selected body node of the one or more FETs includes forming a capacitive element. Forming an element coupled to a selected body node of the one or more FETs may also include forming a resistive element. In some embodiments, the substrate may include a semiconductor substrate. In some embodiments, the method may further include forming a feedforward capacitive element from the RF signal path to a body node of a selected FET defining the RF signal path between the input and the output. The method may further include forming a resistive element coupled to a gate node of the FET defining the input and the output, thereby floating the gate node of the FET. In some embodiments, the method may optionally include forming a resistive element coupled to a body node of the FET defining the input and the output, thereby floating the body node of the FET.

Examples of product implementations:

The various examples of FET-based switch circuits and biasing/coupling configurations described herein can be implemented in a number of different ways and at different product levels. Some such product implementations are described by way of example.

Semiconductor bare die implementation

Figures 43A-43D schematically illustrate non-limiting examples of such implementations on one or more semiconductor dies. Figure 43A illustrates that in some embodiments, the switch circuit 120 and bias/coupling circuit 150 having one or more features described herein can be implemented on the die 800. Figure 43B illustrates that in some embodiments, at least some of the bias/coupling circuit 150 can be implemented external to the die 800 of Figure 43A.

Figure 43C shows that in some embodiments, the switching circuit 120 having one or more features described herein can be implemented on the first die 800a, and the biasing/coupling circuit 150 having one or more features described herein can be implemented on the second die 800b. Figure 43D shows that in some embodiments, at least some of the biasing/coupling circuit 150 can be implemented external to the first die 800a of Figure 43C.

Encapsulation module implementation

In some embodiments, one or more bare cores having one or more features described herein may be implemented on a packaged module. Examples of such modules are shown in FIG44A (top view) and 44B (side view). Although described in the context of both the switching circuitry and the bias/coupling circuitry being located on the same bare core (e.g., the example configuration of FIG44A ), it will be understood that the packaged module may be based on other configurations.

Module 810 is shown as including a packaging substrate 812. Such a packaging substrate can be configured to accommodate multiple components and can include, for example, a laminate substrate. The components mounted on the packaging substrate 812 can include one or more bare die. In the example shown, a bare die 800 having a switching circuit 120 and a bias/coupling circuit 150 is shown as being mounted on the packaging substrate 812. The bare die 800 can be electrically connected to the rest of the module (and to each other in the case of using more than one bare die) via connections such as connecting wire bonds 816. Such connecting wire bonds can be formed between contact pads 818 formed on the bare die 800 and contact pads 814 formed on the packaging substrate 812. In some embodiments, one or more surface mount devices (SMDs) 822 can be mounted on the packaging substrate 812 to facilitate various functions of the module 810.

In some embodiments, package substrate 812 may include electrical connection paths to interconnect various components to each other and/or to externally connected contact pads. For example, connection path 832 is depicted as interconnecting example SMD 822 and bare die 800. In another example, connection path 832 is depicted as interconnecting SMD 822 and externally connected contact pad 834. In yet another example, connection path 832 is depicted as interconnecting bare die 800 and ground connection contact pad 836.

In some embodiments, the space above the package substrate 812 and the various components mounted thereon may be filled with an overmold structure 830. This overmold structure may provide a variety of desired functions, including protecting components and wire bonds from external elements and making it easier to handle the package module 810.

FIG45 is a schematic diagram illustrating an example switch configuration that can be implemented in module 810 described with reference to FIG44A and FIG44B . In this example, switch circuit 120 is depicted as an SP9T switch having a pole that can be connected to an antenna and throws that can be connected to various Rx and Tx paths. This configuration can enable, for example, multi-mode, multi-band operation in a wireless device.

Module 810 may further include an interface that receives power (e.g., supply voltage VDD) and control signals to facilitate operation of switch circuit 120 and/or bias/coupling circuit 150. In some implementations, the supply voltage and control signals may be applied to switch circuit 120 through bias/coupling circuit 150.

Wireless device implementation

In some implementations, devices and/or circuits having one or more features described herein may be included in an RF device, such as a wireless device. Such devices and/or circuits may be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device may include, for example, a cellular telephone, a smartphone, a handheld wireless device with or without telephone functionality, a wireless tablet computer, and the like.

FIG46 schematically illustrates an example wireless device 900 having one or more advantageous features described herein. In the context of various switches and various bias/coupling configurations as described herein, the switch 120 and the bias/coupling circuit 150 may be included as part of the module 810. In some embodiments, such a switch module may enable, for example, multi-band, multi-mode operation of the wireless device 900.

In the example wireless device 900, a power amplifier (PA) module 916 having multiple PAs can provide amplified RF signals to the switching circuit 120 (via the duplexer 920), and the switch 120 can route the amplified RF signals to the antenna. The PA module 916 can receive unamplified RF signals from a transceiver 914, which can be configured and operated in a known manner. The transceiver can also be configured to process received signals. The transceiver 914 is shown interacting with a baseband subsystem 910, which is configured to provide conversion between data and/or voice signals for a user and RF signals for the transceiver 914. The transceiver 914 is also shown connected to a power management component 906, which is configured to manage power for the operation of the wireless device 900. Such a power management component can also control the operation of the baseband subsystem 910 and the module 810.

The baseband subsystem 910 is shown connected to the user interface 902 to facilitate the input and output of various voice and/or data provided to and received from the user. The baseband subsystem 910 may also be connected to a memory 904 that is configured to store data and/or instructions to facilitate the operation of the wireless device and/or provide information storage to the user.

In some embodiments, duplexer 920 may allow simultaneous transmit and receive operations using a common antenna, such as 924. In FIG46, received signals are shown being routed to an "Rx" path (not shown) that may include, for example, a low noise amplifier (LNA).

Many other wireless device configurations can utilize one or more of the features described herein. For example, a wireless device need not be a multi-band device. In another example, a wireless device can include additional antennas, such as a diversity antenna, and additional connectivity features, such as Wi-Fi, Bluetooth, and GPS.

Combination of features from different examples

As described herein, one or more features associated with each example can produce one or more desired configurations. In some implementations, various features from different examples described herein can be combined to produce one or more desired configurations. Figure 47 schematically depicts a combined configuration 1000 in which a first feature (i, x) is shown as being combined with a second feature (j, y). The indices "i" and "j" are, for example, example numbers in N examples, where i = 1, 2, ..., N-1, N and j = 1, 2, ..., N-1, N. In some implementations, for the first and second features of the combined configuration 1000, i ≠ j. The index "x" can represent a single feature associated with the i-th example. The index "x" can also represent a combination of features associated with the i-th example. Similarly, the index "y" can represent a single feature associated with the j-th example. The index "y" can also represent a combination of features associated with the j-th example. As described herein, the value of N can be 12.

Although described in the context of combining features from two different examples, it will be understood that features from fewer than or more than two examples may also be combined. For example, features from one, three, four, five, etc. may be combined to produce a combined configuration.

Overall Comments

Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprises," "comprising," and the like are to be interpreted in an inclusive sense, and not in an exclusive or exhaustive sense; that is, in the sense of "including but not limited to." As generally used herein, the word "coupled" refers to two or more elements that may be connected directly or through one or more intermediate elements. In addition, when used in this application, the words "herein," "above," "below," and words of similar meaning shall refer to this application as a whole and not to any particular part of this application. When the context permits, words in the above specific embodiments that use the singular or plural may also include the plural or singular, respectively. When referring to a list of two or more items, the word "or" covers all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

The above detailed description of certain embodiments of the present invention is not intended to be exhaustive or to limit the present invention to the precise form disclosed above. As will be appreciated by those skilled in the relevant art, although specific embodiments and examples of the present invention have been described above for illustrative purposes, various equivalent modifications are possible within the scope of the present invention. For example, although processes or blocks are presented in a given order, alternative embodiments may perform routines with steps in different orders, or employ systems with blocks in different orders, and may delete, move, add, subdivide, combine and/or modify some processes or blocks. Each of these processes or blocks may be implemented in a variety of different ways. In addition, although processes or blocks are sometimes shown as being executed serially, these processes or blocks may be executed in parallel, or may be executed at different times, as an alternative.

The teachings of the invention provided herein can be applied to other systems, not necessarily the systems described above.The elements and acts of the various embodiments described above can be combined to provide further embodiments.

Although some embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the present disclosure.

Claims (15)

1. A radio frequency switching system, comprising: A first switching circuit connected between the antenna node and the transmission node; A second switching circuit connected between the antenna node and the receiving node; A first capacitor connected in series with the first switching circuit between the first switching circuit and the antenna node; A second capacitor connected in series with the second switching circuit between the second switching circuit and the antenna node; A first shunt arm connected to the first switching circuit and the transmission node, the first shunt arm including a third switching circuit connected to ground; and A second shunt arm is connected to the second switching circuit and the receiving node, the second shunt arm including a fourth switching circuit connected to ground. Each of the first, second, third, and fourth switching circuits includes a plurality of field-effect transistors and a compensation circuit. The plurality of field-effect transistors includes at least a first field-effect transistor and a second field-effect transistor connected in series. The compensation circuit includes a nonlinear capacitor connected at a first end to both the source of the first field-effect transistor and the drain of the second field-effect transistor, and further connected at a second end to a ground reference. The compensation circuit is configured to compensate for nonlinear effects generated by at least one of the plurality of field-effect transistors. 2. The radio frequency switching system of claim 1, wherein at least one of the first capacitor and the second capacitor is configured to prevent the low-frequency blocking signal from mixing with the baseband signal in the switch. 3. The radio frequency switching system of claim 1, wherein the first shunt arm includes a third capacitor connected between the third switching circuit and the transmitting node, and the second shunt arm includes a fourth capacitor connected between the fourth switching circuit and the receiving node. 4. A radio frequency switching system, comprising: A first switching circuit connected between the antenna node and the transmission node; A second switching circuit connected between the antenna node and the receiving node; A first capacitor connected in series with the first switching circuit between the first switching circuit and the antenna node; A second capacitor connected in series with the second switching circuit between the second switching circuit and the antenna node; A first shunt arm is connected to the first switching circuit and the transmission node. The first shunt arm includes a third switching circuit connected to ground and a third capacitor connected between the third switching circuit and the transmission node. Each of the first, second, and third switching circuits includes a plurality of field-effect transistors and a compensation circuit. The plurality of field-effect transistors includes at least a first field-effect transistor and a second field-effect transistor connected in series. The compensation circuit includes a nonlinear capacitor connected at a first end to both the source of the first field-effect transistor and the drain of the second field-effect transistor, and further connected at a second end to a ground reference. The compensation circuit is configured to compensate for nonlinear effects generated by at least one of the plurality of field-effect transistors. 5. A semiconductor bare die, comprising: Semiconductor substrate; A first switching circuit is formed on the semiconductor substrate and connected between the antenna node and the transmission node; A second switching circuit is formed on the semiconductor substrate and connected between the antenna node and the receiving node; A first capacitor is formed on the semiconductor substrate and connected in series with the first switching circuit between the first switching circuit and the antenna node; A second capacitor is formed on the semiconductor substrate and connected in series with the second switching circuit between the second switching circuit and the antenna node; A first shunt arm connected to the first switching circuit and the transmission node, the first shunt arm including a third switching circuit connected to ground; and A second shunt arm is connected to the second switching circuit and the receiving node, the second shunt arm including a fourth switching circuit connected to ground. Each of the first, second, third, and fourth switching circuits includes a plurality of field-effect transistors and a compensation circuit. The plurality of field-effect transistors includes at least a first field-effect transistor and a second field-effect transistor connected in series. The compensation circuit includes a nonlinear capacitor connected at a first end to both the source of the first field-effect transistor and the drain of the second field-effect transistor, and further connected at a second end to a ground reference. The compensation circuit is configured to compensate for nonlinear effects generated by at least one of the plurality of field-effect transistors. 6. The semiconductor die of claim 5, further comprising an insulating layer disposed between the first switching circuit and the semiconductor substrate. 7. The semiconductor bare die as claimed in claim 6, wherein the bare die is a silicon bare die on an insulator. 8. A method for manufacturing a semiconductor bare die, the method comprising: Provide semiconductor substrates; A first switching circuit is formed on the semiconductor substrate such that the first switching circuit is connected between the antenna node and the transmission node; A second switching circuit is formed on the semiconductor substrate such that the second switching circuit is connected between the antenna node and the receiving node; A first capacitor is formed on the semiconductor substrate such that the first capacitor is connected in series with the first switching circuit between the first switching circuit and the antenna node; A second capacitor is formed on the semiconductor substrate such that the second capacitor is connected in series with the second switching circuit between the second switching circuit and the antenna node; A first shunt arm is formed connecting the first switching circuit and the transmission node, the first shunt arm including a third switching circuit connected to ground; and A second shunt arm is formed connecting the second switching circuit and the receiving node, the second shunt arm including a fourth switching circuit connected to ground. Each of the first, second, third, and fourth switching circuits includes a plurality of field-effect transistors and a compensation circuit. The plurality of field-effect transistors includes at least a first field-effect transistor and a second field-effect transistor connected in series. The compensation circuit includes a nonlinear capacitor connected at a first end to both the source of the first field-effect transistor and the drain of the second field-effect transistor, and further connected at a second end to a ground reference. The compensation circuit is configured to compensate for nonlinear effects generated by at least one of the plurality of field-effect transistors. 9. The method of claim 8, further comprising forming an insulating layer between the first switching circuit and the semiconductor substrate. 10. A radio frequency switch module, comprising: A packaging substrate configured to accommodate multiple components; A semiconductor die mounted on the packaging substrate, the die including a first switching circuit and a second switching circuit, the first switching circuit being connected between an antenna node and a transmitting node, and the second switching circuit being connected between the antenna node and a receiving node; A first capacitor connected in series with the first switching circuit between the first switching circuit and the antenna node; A second capacitor connected in series with the second switching circuit between the second switching circuit and the antenna node; A first shunt arm connected to the first switching circuit and the transmission node, the first shunt arm including a third switching circuit connected to ground; and A second shunt arm is connected to the second switching circuit and the receiving node, the second shunt arm including a fourth switching circuit connected to ground. Each of the first, second, third, and fourth switching circuits includes a plurality of field-effect transistors and a compensation circuit. The plurality of field-effect transistors includes at least a first field-effect transistor and a second field-effect transistor connected in series. The compensation circuit includes a nonlinear capacitor connected at a first end to both the source of the first field-effect transistor and the drain of the second field-effect transistor, and further connected at a second end to a ground reference. The compensation circuit is configured to compensate for nonlinear effects generated by at least one of the plurality of field-effect transistors. 11. The radio frequency switch module of claim 10, wherein at least one of the first capacitor and the second capacitor is configured to prevent the low-frequency blocking signal from mixing with the baseband signal in the switch. 12. The radio frequency switch module of claim 10, wherein the first capacitor is part of the same semiconductor die as the semiconductor die in which the first switch circuit is located. 13. The RF switch module of claim 10, wherein the first capacitor is part of a second bare core mounted on the package substrate. 14. The radio frequency switch module of claim 10, wherein the first capacitor is disposed at a location outside the semiconductor die. 15. A wireless device, comprising: A transceiver configured to process radio frequency signals; An antenna communicating with the transceiver; and A switching module, interconnected with the antenna and the transceiver, and configured to selectively route the radio frequency (RF) signal to and from the antenna, includes a first switching circuit connected between an antenna node and a transmitting node, a second switching circuit connected between the antenna node and a receiving node, a first capacitor connected in series with the first switching circuit between the first switching circuit and the antenna node, a second capacitor connected in series with the second switching circuit between the second switching circuit and the antenna node, a first shunt arm connected to the first switching circuit and the transmitting node, and a second shunt arm connected to the second switching circuit and the receiving node. The first shunt arm includes a third switching circuit connected to ground, and the second shunt arm includes a fourth switching circuit connected to ground. Each of the first, second, third, and fourth switching circuits includes a plurality of field-effect transistors and a compensation circuit. The plurality of field-effect transistors includes at least a first field-effect transistor and a second field-effect transistor connected in series. The compensation circuit includes a nonlinear capacitor connected at a first end to both the source of the first field-effect transistor and the drain of the second field-effect transistor, and further connected at a second end to a ground reference. The compensation circuit is configured to compensate for nonlinear effects generated by at least one of the plurality of field-effect transistors.