HK1244354B - Metal layers for a three-port bit cell - Google Patents

Description

Metal layers for three-port bit cells

I. Priority Claim

This application claims priority to commonly owned U.S. Non-Provisional Patent Application No. 14/620,480, filed February 12, 2015, the entire contents of which are expressly incorporated herein by reference.

II. Technical Field

The present disclosure relates generally to bitcells.

III. Background Technology

Advances in technology have resulted in smaller and more powerful computing devices. For example, there are currently various portable personal computing devices, including wireless phones, such as mobile and smart phones, tablet computers, and laptop computers, which are small, lightweight, and easy to carry. These devices can transmit voice and data packets over wireless networks. In addition, many such devices include additional functions, such as digital cameras, digital video cameras, digital recorders, and audio file players. In addition, such devices can process executable instructions, including software applications that can be used to access the Internet, such as web browser applications. Therefore, these devices can include significant computing power.

An electronic device such as a wireless telephone may include a memory having a memory array including one or more memory cells. One type of memory cell that can be used for a memory (e.g., an L1/L2 cache) is a three-port bit cell. A three-port bit cell may include two read ports and one write port and may be used in a static random access memory (SRAM) device. A three-port SRAM bit cell may be fabricated by stacking two metal layers, referred to as M1 and M2 layers, using a double mask lithography-etch-lithography-etch (LELE) process. The top metal layer M2 may be patterned in a nonlinear manner and may include a "jog" (e.g., a turn). For fabricating very small size devices, self-aligned double patterning (SADP) may be preferred over LELE due to the reduced cost and improved process control (e.g., more precise line width and line spacing control) provided by SADP compared to LELE. However, SADP may not support nonlinear patterns that include jogs.

IV. Summary of the Invention

The present disclosure provides a bit cell design that includes a linear pattern compatible with SADP, such as for technology nodes less than 14nm (e.g., 10nm or 7nm). A three-port bit cell can have a first metal layer (M1), a second metal layer (M2), and a third metal layer (M3), wherein the length of the first metal layer (M1) is perpendicular to the length of the polysilicon gate in the bit cell, the length of the second metal layer (M2) is parallel to the length of the polysilicon gate, and the length of the third metal layer (M3) is parallel to the length of the polysilicon gate. Because the first metal layer (M1) and the second metal layer (M2) are oriented in a direction similar to the corresponding metal layers in a "standard bit cell", the first metal layer (M1) and the second metal layer (M2) can have a relatively low pitch (e.g., a pitch of approximately 42nm). Because the third metal layer (M3) is oriented in a direction opposite to the third metal layer in a standard bit cell, the third metal layer can have a relatively high pitch (e.g., a pitch of approximately 126nm).

Two read word lines may be formed from the second metal layer (M2), and a single write word line may be formed from the third metal layer (M3). The width of the single write word line of the third metal layer (M3) may be relatively large (e.g., approximately 66 nm (contacted polysilicon pitch (CPP) for a 10 nm process)), which may result in reduced latency and reduced resistor-capacitor (RC) delay compared to the latency of a write word line formed in a layer with read word lines. Furthermore, because the second metal layer (M2) has a relatively small pitch, two relatively narrow read word lines (e.g., approximately 23 nm each) may be included in the second metal layer without having to extend the width of the cell beyond 2×CPP for a 10 nm process.

In a particular embodiment, a device includes a first metal layer coupled to a bit cell. The device also includes a third metal layer including a write word line coupled to the bit cell. The device also includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

In another specific embodiment, a method includes patterning a first metal layer at a bit cell and patterning a third metal layer. The third metal layer includes a write word line coupled to the bit cell. The method also includes patterning a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

In another specific embodiment, a non-transitory computer-readable medium includes instructions that, when executed by a processor, cause the processor to initiate patterning of a first metal layer at a bit cell and to initiate patterning of a third metal layer. The third metal layer includes a write word line coupled to the bit cell. The instructions are also executable to cause the processor to initiate patterning of a second metal layer between the first and third metal layers. The second metal layer includes two read word lines coupled to the bit cell.

In another specific embodiment, an apparatus includes first means for routing current coupled to a bit cell and third means for routing current. The third means for routing current includes a write word line coupled to the bit cell. The apparatus also includes second means for routing current between the first means for routing current and the third means for routing current. The second means for routing current includes two read word lines coupled to the bit cell.

One particular advantage provided by at least one of the disclosed embodiments is the reduced latency and reduced resistor-capacitor (RC) delay based on the relatively large width of the write word line. For example, providing the write word line in the third metal layer (as opposed to providing two read word lines in the third metal layer) can enable the write word line to have a relatively large width. Additionally, because the length of the second metal layer is parallel to the length of the polysilicon gate, two read word lines can be provided in the second metal layer without increasing the width of the bit cell. Other aspects, advantages, and features of the present disclosure will become apparent upon review of the entire application, including the following sections: the Brief Description of the Figures, the Detailed Description, and the Claims.

V. Description of the Figures

1A and 1B are circuit diagrams of a first illustrative embodiment of a three-port bit cell;

FIG2 is a first layout diagram of a three-port bit cell array;

FIG3 is a second layout diagram of a three-port bit cell array;

FIG4 is a third layout diagram of a three-port bit cell array;

FIG5 is a flow chart of a particular illustrative embodiment of a method of forming a three-port bit cell;

FIG6 is a block diagram of an electronic device including the three-port bit cell of FIG1; and

7 is a data flow diagram of a particular illustrative embodiment of a fabrication process for making an electronic device including the three-port bitcell of FIG. 1 .

VI. Specific Implementation Methods

There may be challenges in scaling down from 14nm technology. For example, for technology nodes 14nm and larger, the width of the three-port bit cell may be limited to less than or equal to twice the contacted polysilicon pitch (CPP, the distance between the contacted polysilicon (gate) lines). For 14nm, the CPP may be about 80-90nm. As used herein, the cell "width" may be perpendicular to the polysilicon direction and along the fin direction. For technology nodes less than 14nm, the CPP decreases, which results in a reduction in the bit cell width. When the bit cell width decreases (i.e., narrows), the write and read word lines in the bit cell may also narrow, resulting in increased read/write delays due to the increased word line resistor-capacitor (RC) impedance.

To maintain a relatively wide spacing between the write and read word lines, a conventional bit cell may additionally include a third metal layer M3 formed above M2 using SADP to circumvent limitations associated with the bit cell. For a conventional bit cell, M3 may include two read word lines and M2 may include a write word line. When the bit cell is formed, adjacent metal layers of the bit cell are arranged in opposite directions. For example, if M1 is horizontal, M2 is vertical, and M3 is horizontal. Typically, M1 is perpendicular to the direction of the polysilicon gate of the bit cell. In addition, the metal layers (e.g., M2 and M3) that include the read and write word lines are typically in the same direction as the polysilicon gate. Therefore, if the polysilicon gate is in a vertical direction, M1 is in a horizontal direction (e.g., perpendicular to the polysilicon gate direction), and M2 and M3 are in a vertical direction. M3 is a "wrong direction layer" (e.g., a metal layer with a similar direction as the adjacent layers in the bit cell) and has a pitch that is approximately 2-3 times the CPP. Therefore, if there are two lines in M3 (e.g., two read word lines), the width of the bit cell may increase. Therefore, one of the word lines may require an additional metal layer (e.g., a fourth metal layer M4), thereby increasing the size and manufacturing cost of the bit cell.

To circumvent this problem, the present disclosure provides two read word lines formed by M2, and a single write word line can be formed by M3. The width of the single write word line of M3 can be relatively large (for example, about 66nm (for the contact polysilicon pitch (CPP) of a 10nm process)), which can result in reduced delay and reduced resistor-capacitor (RC) delay compared to the delay of the write word line formed in the layer with the read word line.

The specific embodiments of the present disclosure are described below with reference to the accompanying drawings. In the specification and drawings, common features are designated with common reference numerals for clarity of the depicted and described embodiments.

1A and 1B , circuit diagrams of a first illustrative embodiment of a bit cell 100 are shown. The bit cell 100 includes a storage latch 110. The storage latch 110 may include a pair of cross-coupled inverters 112, 114. Each of the inverters 112, 114 may include a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor, as shown in FIG. 1B .

The memory latch 110 can be connected (e.g., coupled) to a first write transistor 121 and a second write transistor 122. The write transistors 121 and 122 can be NMOS transistors, as shown. In other embodiments, the write transistors 121 and 122 can be PMOS transistors. The first write transistor 121 can be connected to a first write bit line (WBL1) 135 and a write word line (WWL) 137, and the second write transistor 122 can be connected to a second write bit line (WBL2) 136 and a write word line (WWL) 137. The first write transistor 121 and the second write transistor 122 can be complementary write transistors of the write port of the bit cell 100. When the write word line 137 and one of the write bit lines 135 or 136 are asserted, the write port can be used to write a logic zero (e.g., low) value into the memory latch 110. When write word line 137 and the other of write bit lines 135 or 136 are asserted, the write port can be used to write a logic one (eg, high) value into storage latch 110 .

Storage latch 110 may also be connected to a first read driver transistor 123 and a second read driver transistor 124. First read driver transistor 123 may be connected to a first read transistor 125, and second read driver transistor 124 may be connected to a second read transistor 126. Read driver transistors 123, 124 and read transistors 125, 126 may be NMOS transistors, as shown. In another embodiment, read driver transistors 123, 124 may be PMOS transistors. First read transistor 125 may be connected to a first read bit line (RBL1) 131 and a first read word line (RWL1) 133. Second read transistor 126 may be connected to a second read bit line (RBL2) 132 and a second read word line (RWL2) 134. Transistors 123 and 125 may correspond to a first read port of bit cell 100, and transistors 124 and 126 may correspond to a second read port of bit cell 100. Read word lines 133 and/or 134 may be asserted during a read operation, and the read ports may be complementary read ports. For example, when the data value at the first read port is a logic 0, the data value at the second read port is a logic 1, and vice versa. In the example of FIG. 1B , the first read port (left side) is shown as reading a logic zero value (“0”), and the second read port (right side) is shown as reading a logic one (“1”) value.

Thus, the bit cell 100 may include two read ports and one write port, and may be referred to as a "three-port" bit cell. Because the bit cell 100 includes ten transistors, the bit cell 100 may also be referred to as a "10T" bit cell. In a particular embodiment, the bit cell 100 is included in a static random access memory (SRAM) device and provides high-speed parallel memory access. As an illustrative, non-limiting example, an SRAM device including the bit cell 100 may be used in an L1 and/or L2 cache of a processor. The SRAM device may include one or more bit cell arrays arranged in a grid-like manner, including one or more rows of bit cells and one or more columns of bit cell columns.

As further described with respect to FIG. 2 , bit cell 100 may have a height (H) and a width (W). In accordance with the described techniques, the width (W) may be approximately twice the contact polysilicon pitch (CPP) associated with bit cell 100, where the CPP corresponds to the distance between the contact polysilicon (gate) lines. The CPP may alternatively be referred to as the gate pitch. For example, the CPP corresponds to the distance from the edge of a polysilicon line to the corresponding edge of an adjacent polysilicon line (e.g., top edge to top edge or bottom edge to bottom edge). Thus, the CPP may also be considered equal to the sum of one polysilicon width and one polysilicon pitch. In a 10 nm semiconductor manufacturing process (e.g., a process with a minimum usable line width/feature size of 10 nm), the CPP may be approximately equal to 60-66 nm. For comparison purposes, a 14 nm process (e.g., a process with a minimum usable line width/feature size of 14 nm) may have a CPP of approximately 80-90 nm.

To maintain a bit cell width of 2×CPP or less for a sub-14nm process (e.g., a 10nm process or a 7nm process), the disclosed technology (as further described with reference to FIG2 ) patterns two read word lines in the second metal layer M2 and patterns a write word line in the third metal layer M3. The second and third metal layers can be coupled to the bit cell and patterned such that the lengths of the second and third metal layers are parallel to the length of the polysilicon gate of the bit cell. Because the third metal layer is patterned in a direction parallel to the direction of the polysilicon gate (e.g., a “wrong direction layer”), as opposed to a conventional third metal layer patterned in a direction perpendicular to the direction of the polysilicon gate (e.g., a “correct direction layer”), the third metal layer can have a relatively large pitch (e.g., a pitch of approximately 126 nm). As further described with reference to FIG2 , the third metal layer can accommodate a relatively large single wide write word line (WWL) 137 in a bit cell having a width of 2×CPP, which can reduce latency and resistor-capacitor (RC) delays.

Additionally, the second metal layer can accommodate two read word lines (RWL1, RWL2) 133, 134 without expanding the width of the bit cell 100 beyond 2×CPP. For example, because the second metal layer is patterned in a direction parallel to the direction of the polysilicon gate (e.g., the second metal layer is a right-orientation layer), the second metal layer can have a relatively small pitch (e.g., a pitch of approximately 42 nm). Based on the relatively small pitch of the second metal layer, the second metal layer can accommodate two read word lines (RWL1, RWL2) 133, 134 without expanding the width of the bit cell 100 beyond 2×CPP.

2 , a first layout diagram of a bit cell array is shown and generally designated 200. For example, FIG2 depicts an array of four bit cells (e.g., a 2×2 bit cell array), wherein each bit cell has the circuit layout shown in FIG1A and FIG1B . When manufactured, the bit cell may include various components/layers, such as a fin (FinFET, including source/drain regions), a transistor gate (alternatively referred to as a polysilicon line), a centerline contact (e.g., a local interconnect) (MD) for the transistor source/drain regions, a centerline contact (e.g., a local interconnect) (MP) for the gate/polysilicon line, a first metal layer (M1), a via (Via0) connecting MD and MP to M1, a second metal layer (M2), a via (Via1) connecting M1 to M2, a third metal layer (M3), and a via (Via2) connecting M2 to M3.

FIG2 illustrates a first metal layer (M1), a second metal layer (M2), and a third metal layer (M3). The first metal layer (M1) can be coupled to a bit cell, the second metal layer (M2) can be patterned above the first metal layer (M1), and the third metal layer (M3) can be patterned above the second metal layer (M2). In an illustrative embodiment, the length of the first metal layer (M1) can be oriented in a first direction (e.g., horizontally), the length of the second metal layer (M2) can be oriented in a second direction (e.g., vertically), and the length of the third metal layer (M3) can be oriented in the second direction. The first metal layer (M1) can include a first read bit line (RBL1) 131 of FIG1A-1B, a second read bit line (RBL2) 134 of FIG1A-1B, a first write bit line (WBL1) 135 of FIG1A-1B, and a second write bit line (WBL2) 136 of FIG1A-1B. For example, the first metal layer (M1) may include a metal trace for providing a ground voltage (VSS), a metal trace for a write bit line (WBL), a metal trace for providing a power supply voltage (Vdd), a metal trace for a global read bit line (GRBL), and a metal trace for a read bit line (RBL).

In a standard bit cell including a polysilicon gate having a length oriented in a vertical direction, the first metal layer can have a length oriented in a horizontal direction (as shown in the embodiment of FIG. 2 ), the second metal layer can have a length oriented in a vertical direction (as shown in the embodiment of FIG. 2 ), and the third metal layer can have a length oriented in a horizontal direction. However, since the length of the third metal layer (M3) of FIG. 2 is oriented in the vertical direction, the third metal layer (M3) is a “wrong direction layer”. Therefore, the pitch of the third metal layer (M3) can be approximately equal to 126 nm. Because the first metal layer (M1) and the second metal layer (M2) of FIG. 2 are “correct direction layers” (e.g., layers having lengths oriented in a manner similar to corresponding layers in a standard bit cell), the first metal layer (M1) and the second metal layer (M2) have a relatively low pitch (e.g., approximately equal to 42 nm).

As described with reference to Figures 1A-1B, when migrating from a 14nm process to a 10nm process, SADP may be preferred for patterning the metal layers of the bit cell. Since SADP may not be suitable for bending/turning, the metal layers (M1, M2, and M3) of the bit cell may correspond to linear-only patterns. When using linear-only patterns at 10nm, three independently accessible word lines (2 read word lines and 1 write word line) can be patterned in the second and third metal layers (M2, M3). For example, the two read word lines (RWL1, RWL2) 133, 134 of the bit cell 100 can be patterned in the second metal layer (M2), and the write word line (WWL) 137 of the bit cell 100 can be patterned in the third metal layer (M3).

As described above, the second metal layer (M2) is a "right orientation layer" and has a relatively low pitch. Therefore, two read word lines (RWL1, RWL2) 133, 134 can be patterned in the second metal layer (M2) without expanding the width of the bit cell 100. For example, each read word line (RWL1, RWL2) 133, 134 can have a width of approximately 23 nm (satisfying the pitch requirement of the second metal layer (M2)) and can accommodate the width of the bit cell 100 (e.g., 2×CPP or 132 nm).

As described above, the third metal layer (M3) is a "wrong direction layer" and has a relatively high pitch. Therefore, a single write word line (WWL) 137 can be patterned in the third metal layer (M3) without expanding the width of the bit cell 100. Because a single write word line (WWL) 137 is patterned in the third metal layer (M3) (as opposed to two read word lines (RWL1, RWL2) 133, 134, which would increase the width of the bit cell 100), the write word line (WWL) 137 can have a relatively large width. For example, the write word line (WWL) 137 can have a width of approximately 66 nm (which meets the pitch requirements of the third metal layer (M3)) and can accommodate the width of the bit cell 100. The relatively large width of the write word line (WWL) 137 can reduce the write delay of the bit cell 100. For example, the increased width of the write word line (WWL) 137 can reduce the RC resistance of the write word line (WWL) 137, thereby resulting in reduced delay.

The bit cell described with reference to Figures 1A, 1B, and 2 can be compatible with SADP metal patterning for manufacturing processes less than 14nm (e.g., 10nm or 7nm). In addition, the bit cell can have an increased write word line width (compared to the write word line width of the write word line in another metal layer), which can reduce write latency. In addition, patterning the read word lines (RWL1, RWL2) 133, 134 in the second metal layer (M2) and the write word line (WWL) 137 in the third metal layer (M3) can circumvent the need to increase the width of the bit cell 100 or to use a fourth metal layer (M4) for the read word line. Therefore, the additional metal layers (M4, M5, M6, etc.) can be relatively "empty" and can be used for increased wiring porosity. For example, the additional metal layers can be used to interconnect other components of the bit cell 100.

3, a second layout diagram of the bitcell array is shown and generally designated 300. The second layout diagram 300 depicts the interconnection between the first metal layer (M1) and the second metal layer (M2) of the first layout diagram 200 of FIG.

A first via (Via1) may be formed to connect the first metal layer (M1) to the second metal layer (M2). Although the metal layers (M1, M2) of the bit cell may be patterned using SADP with a technology less than 14 nm, the first via (Via1) connecting the metal layers (M1, M2) may be formed using LELE (e.g., for cost-related and/or process-related reasons). Migrating to a process less than 14 nm may reduce the spacing between metal-to-metal vias in the bit cell, such as the first via (Via1) connecting the first metal layer (M1) to the second metal layer (M2). In particular, when the bit cell width is fixed at 2×CPP, the spacing between such vias may be reduced to less than 40 nm.

4, a third layout diagram of a bitcell array is shown and generally designated 400. Third layout diagram 400 depicts the interconnection between the second metal layer (M2) and the third metal layer (M3) of first layout diagram 200 of FIG.

A second via (Via2) may be formed to connect the second metal layer (M2) to the third metal layer (M3). Although the metal layers (M2, M3) of the bit cell 100 may be patterned using SADP with a technology less than 14 nm, the via (Via2) connecting the metal layers (M2, M3) may be formed using LELE (e.g., for cost-related and/or process-related reasons). Migrating to a process less than 14 nm may reduce the spacing between metal-to-metal vias in the bit cell 100, such as the second via (Via2) connecting the second metal layer (M2) to the third metal layer (M3). In particular, when the bit cell width is fixed at 2×CPP, the spacing between such vias may be reduced to less than 40 nm.

5 , a flow chart of a particular illustrative embodiment of a method 500 of forming a bitcell is shown and generally designated 500. In an illustrative embodiment, the method 500 may be performed during the fabrication of the bitcell 100. In a particular embodiment, the method 500 may be performed using the fabrication equipment described below with respect to FIG.

Method 500 may include, at 502, patterning a first metal layer of a bit cell. For example, referring to FIG. 2 , the first metal layer (M1) at bit cell 100 may be patterned. The first metal layer (M1) may include a first read bit line (RBL1), a second read bit line (RBL2), a first write bit line (WBL1), and a second write bit line (WBL2). In certain embodiments, the first metal layer (M1) may also include lines for providing a power supply voltage (Vdd) and a ground voltage (Vss).

At 504, a second metal layer overlying the first metal layer can be patterned. For example, referring to FIG. 2 , a second metal layer (M2) overlying the first metal layer (M1) can be patterned. A first read word line (RWL1) 133 and a second read word line (RWL2) 134 can be included in the second metal layer (M2) and can be coupled to the bit cell 100. For example, the first read word line (RWL1) 133 can be coupled to the gate of transistor 125, and the second read word line (RWL2) 134 can be coupled to the gate of transistor 134.

At 506, a third metal layer above the second metal layer can be patterned. For example, referring to FIG3 , a third metal layer (M3) can be patterned above the second metal layer (M2). A write word line (WWL) 137 can be included in the third metal layer (M3) and can be coupled to the bit cell 100. For example, the write word line (WWL) 137 can be coupled to the gate of transistor 121 and the gate of transistor 122.

In certain embodiments, method 500 may include forming a first via connecting the first metal layer to the second metal layer. For example, referring to FIG3 , a first via (Via1) may be formed (after forming the first metal layer (M1)) to connect the first metal layer (M1) to the second metal layer (M2). LELE may be used (e.g., for cost-related and/or process-related reasons) to form the first via (Via1) connecting the metal layers (M1, M2).

In certain embodiments, method 500 may include forming a second via connecting the second metal layer to the third metal layer. For example, referring to FIG. 4 , a second via (Via2) may be formed (after forming the second metal layer (M2)) to connect the second metal layer (M2) to the third metal layer (M3). LELE may be used (e.g., for cost-related and/or process-related reasons) to form the second via (Via2) connecting the metal layers (M2, M3).

In certain embodiments, method 500 may include patterning a fourth metal layer above the third metal layer. For example, the fourth metal layer (M4) may be formed above the third metal layer (M3) and may be coupled to the bit cell 100. The length of the fourth metal layer (M4) may be oriented in a vertical direction (e.g., the fourth metal layer (M4) may be a right-oriented layer), and the fourth metal layer (M4) may have a pitch of approximately 80 nm. A write global word line may be included in the fourth metal layer (M4).

The method 500 of FIG. 5 enables formation of a metal layer at the bit cell 100 that is compatible with SADP metal patterning for manufacturing processes less than 14 nm (e.g., 10 nm or 7 nm). Furthermore, the bit cell 100 can have an increased write word line width, which can reduce write latency. For example, including the write word line (WWL) 137 in the third metal layer (M3) can enable formation of a relatively wide (e.g., 66 nm) write word line (WWL) 137. Additionally, patterning the read word lines (RWL1, RWL2) 133, 134 in the second metal layer (M2) and the write word line (WWL) 137 in the third metal layer (M3) can circumvent increasing the width of the bit cell 100 or using a fourth metal layer (M4) for the read word line. Consequently, the additional metal layers (M4, M5, M6, etc.) can be relatively “empty” and can be used for increased wiring porosity.

It should be noted that the order of the steps shown in Figure 5 is for illustration purposes only and should not be considered limiting. In alternative embodiments, certain steps may be performed in a different order and/or may be performed simultaneously (or at least partially simultaneously).

Method 500 may be implemented by a processing unit such as a central processing unit (CPU), a controller, another hardware device, a firmware device, or any combination thereof. As an example, method 500 may be performed by a processor executing instructions as described with respect to FIG.

6 , a block diagram of a particular illustrative embodiment of an electronic device is depicted and generally designated 600. The electronic device 600 includes a processor 610, such as a digital signal processor (DSP) or a central processing unit (CPU), coupled to a memory 632. The processor 610 includes an SRAM device 664, wherein the SRAM device includes a bit cell 100 according to the metal layer patterning technique described with respect to FIG. 2-4. For example, the SRAM device 664 may correspond to an L1 and/or L2 cache memory. In an illustrative embodiment, the bit cells of the SRAM device 664 may be manufactured according to the method 500 of FIG. 5 . In an alternative embodiment, the SRAM device 664 may be external to and/or coupled to the processor 610. It should be noted that although FIG. 6 illustrates the use of the bit cell 100 in an SRAM of a particular electronic device, this should not be considered limiting. Bit cells according to the present disclosure, such as the bit cell 100, may be included in any type of memory in any type of electronic device.

FIG6 shows a display controller 626 coupled to a processor 610 and a display 628. A coder/decoder (CODEC) 634 may also be coupled to the processor 610. A speaker 636 and a microphone 638 may be coupled to the CODEC 634. FIG6 also indicates that a wireless controller 640 may be coupled to the processor 610 and an antenna 642. In certain embodiments, the processor 610, the display controller 626, the memory 632, the CODEC 634, and the wireless controller 640 are included in a system-in-package or system-on-chip device (e.g., a mobile station modem (MSM)) 622. In certain embodiments, an input device 630 and a power supply 644 are coupled to the system-on-chip device 622. Furthermore, in certain embodiments, as shown in FIG6, the display 628, the input device 630, the speaker 636, the microphone 638, the antenna 642, and the power supply 644 are external to the system-on-chip device 622. However, each of the display 628 , input device 630 , speaker 636 , microphone 638 , antenna 642 , and power supply 644 may be coupled to a component of the system-on-chip device 622 , such as an interface or controller.

In conjunction with the described embodiments, an apparatus includes a first means for routing current coupled to a bit cell. For example, the first means for routing current may include the first metal layer (M1) of Figures 2-3, one or more other devices configured to route current in the bit cell, or any combination thereof. The first means for routing current may include a first read bit line (RBL1), a second read bit line (RBL2), a first write bit line (WBL1), and a second write bit line (WBL2). In certain embodiments, the first means for routing current may also provide lines for providing a power supply voltage (Vdd) and a ground voltage (Vss).

The apparatus may further include a second means for routing current above the first means for routing current. For example, the second means for routing current may include the second metal layer (M2) of Figures 2-4, one or more other devices configured to route current in the bit cell, or any combination thereof. The second means for routing current may include a first read word line (RWL1) 133 coupled to the bit cell 100 and a second read word line (RWL2) 134 coupled to the bit cell 100.

The apparatus may further include a third means for routing current above the second means for routing current. For example, the third means for routing current may include the third metal layer (M3) of Figures 2 and 4, one or more other devices configured to route current in the bit cell, or any combination thereof. The third means for routing current may include a write word line (WWL) 137 coupled to the bit cell 100.

The devices and functions disclosed above can be designed and configured as computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer-readable medium. Some or all of such files can be provided to a manufacturing processor that manufactures devices based on such files. The resulting products include semiconductor wafers, which are then cut into semiconductor dies and packaged into semiconductor chips. The chips can be used in electronic devices. FIG7 depicts a specific illustrative embodiment of an electronic device manufacturing process 700. For example, the manufacturing process 700 can be used to manufacture an electronic device that includes a bit cell 100 according to the metal layer patterning technique described with respect to FIG2-4.

At a manufacturing process 700, such as at a research computer 706, physical device information 702 is received. The physical device information 702 may include design information representing at least one physical characteristic of the bit cell 100 according to the metal layer patterning technique described with respect to Figures 2-4. For example, the physical device information 702 may include physical parameters, material properties, and structural information input via a user interface 704 coupled to the research computer 706. The research computer 706 includes a processor 708, such as one or more processing cores, coupled to a computer-readable medium (e.g., a non-transitory computer-readable medium) such as a memory 710. The memory 710 may store computer-readable instructions executable to cause the processor 708 to transform the physical device information 702 to conform to a file format and generate a library file 712.

In certain embodiments, library file 712 includes at least one data file including the transformed design information. For example, library file 712 may include a bit cell library including bit cells 100 according to the metal layer patterning technique described with respect to FIG. 2-4 , which is provided for use with electronic design automation (EDA) tool 720 .

The library file 712 can be used in conjunction with an EDA tool 720 at a design computer 714 including a processor 716 (such as one or more processing cores) coupled to a memory 718. The EDA tool 720 can be stored as processor-executable instructions at the memory 718 to enable a user of the design computer 714 to design a circuit of the bit cell 100 of the library file 712 according to the metal layer patterning technique described with respect to FIGs. 2-4. For example, the user of the design computer 714 can input circuit design information 722 via a user interface 724 coupled to the design computer 714. The circuit design information 722 can include design information representing at least one physical property of the bit cell 100 according to the metal layer patterning technique described with respect to FIGs. 2-4. For example, the circuit design property can include identification of a particular circuit in the circuit design and its relationship to other elements, positioning information, feature size information, interconnection information, or other information representing physical properties of the bit cell 100 according to the metal layer patterning technique described with respect to FIGs. 2-4.

The design computer 714 can be configured to transform the design information, including the circuit design information 722, to conform to a file format. For illustration, the file format can include a database binary file format that represents planar geometry, text annotations, and other information about the circuit layout in a hierarchical format, such as a Graphics Data System (GDSII) file format. The design computer 714 can be configured to generate a data file, such as a GDSII file 726, that includes the transformed design information and that includes, in addition to other circuits or information, information describing the bit cell 100 according to the metal layer patterning technique described with respect to Figures 2-4. For illustration, the data file can include information corresponding to a system on a chip (SOC) that includes the bit cell 100 according to the metal layer patterning technique described with respect to Figures 2-4 and also includes additional electronic circuits and components within the SOC.

The GDSII file 726 can be received at a manufacturing process 728 to manufacture the bit cell 100 according to the metal layer patterning technique described with respect to Figures 2-4 based on the transformed information in the GDSII file 726. For example, the device manufacturing process can include providing the GDSII file 726 to a mask manufacturer 730 to create one or more masks, such as masks for use with a photolithography process, which is shown as representative mask 732. Mask 732 can be used during the manufacturing process to generate one or more wafers 733, which can be tested and separated into dies, such as representative die 736. Die 736 includes circuitry having a device including the bit cell 100 according to the metal layer patterning technique described with respect to Figures 2-4.

For example, manufacturing process 728 may include a processor 734 and a memory 735 to initiate and/or control manufacturing process 728. Memory 735 may include executable instructions, such as computer-readable instructions or processor-readable instructions. Executable instructions may include one or more instructions executable by a computer, such as processor 734. In certain embodiments, the executable instructions may cause the computer to perform method 500 of FIG. 5 , or at least a portion thereof.

The manufacturing process 728 can be implemented by a fully automated or partially automated manufacturing system. For example, the manufacturing process 728 can be automatically executed according to a schedule. The manufacturing system may include manufacturing equipment (e.g., a processing tool) for performing one or more operations to form a semiconductor device. For example, the manufacturing equipment can be configured to deposit one or more materials using chemical vapor deposition (CVD) and/or physical vapor deposition (PVD), pattern the materials using a single mask or multi-mask lithography-etch process (e.g., dual mask LELE), pattern the materials using a lithography-freeze-lithography-etch (LFLE) process, pattern the materials using a self-aligned double patterning (SADP) process, epitaxially grow one or more materials, conformally deposit one or more materials, apply a hard mask, apply an etch mask, perform etching, perform planarization, form a dummy gate stack, form a gate stack, perform standard clean type 1, etc. In a specific embodiment, the manufacturing process 728 corresponds to a semiconductor manufacturing process associated with a technology node less than 14 nm (e.g., 10 nm, 7 nm, etc.). The specific process or combination of processes used to manufacture a device (e.g., including bitcell 100 according to the metal layer patterning techniques described with respect to FIGs. 2-4 ) may be based on design constraints and available materials/equipment. Thus, in certain embodiments, a different process than that described with reference to FIGs. 1A-7 may be used during fabrication of the device.

As an illustrative example, a dual-mask LELE process used during the formation of Via1 of bit cell 100 according to the metal layer patterning technique described with respect to Figures 2-4 may include forming a first pattern on a first layer of the device (e.g., a nitride layer) using a first photoresist mask and etching the first pattern. A second pattern may then be formed on the device using a second mask, and the combined pattern may be etched down to a second lower layer of the device (e.g., an oxide layer). In the combined pattern, features (e.g., lines) of the first and second patterns may be interwoven. As a result, the combined pattern may have a smaller feature (e.g., line) pitch than the first and second patterns.

As another illustrative example, a SADP process for patterning the M1 or M2 layer of a bit cell 100 according to the metal layer patterning techniques described with respect to Figures 2-4 can include forming a "dummy" pattern on the device. A conformal dielectric layer can be formed (e.g., deposited) over the dummy pattern and can be etched. During etching, all of the dielectric layer can be removed except for "spacers" of dielectric material adjacent to the sidewalls of the dummy pattern. The dummy pattern can then be removed (e.g., without etching) to leave the spacers, which can form a pattern with a higher feature (e.g., line) density than the dummy pattern. The higher density spacer pattern can be used to pattern the M1 or M2 layer.

A manufacturing system (e.g., an automated system executing manufacturing process 728) can have a distributed architecture (e.g., a hierarchy). For example, a manufacturing system can include one or more processors (such as processor 734), one or more memories (such as memory 735), and/or controllers distributed according to the distributed architecture. The distributed architecture can include a high-level processor that controls or initiates the operation of one or more low-level systems. For example, the high-level portion of manufacturing process 728 can include one or more processors, such as processor 734, and each of the low-level systems can include or be controlled by one or more corresponding controllers. A particular controller of a particular low-level system can receive one or more instructions (e.g., commands) from a particular high-level system, can issue subcommands to slave modules or processing tools, and can transmit status data back to a particular high-level system. Each of the one or more low-level systems can be associated with one or more corresponding workpieces (e.g., processing tools) of a manufacturing facility. In certain embodiments, a manufacturing system can include multiple processors distributed throughout the manufacturing system. For example, a controller of a low-level system component can include a processor, such as processor 734.

Alternatively, the processor 734 may be part of a higher-level system, subsystem, or component of the manufacturing system. In another embodiment, the processor 734 includes distributed processing at various levels and components of the manufacturing system.

The executable instructions included in the memory 735 can enable the processor 734 to form the bit cell 100 (or initiate its formation) according to the metal layer patterning technique described with respect to Figures 2-4. In a particular embodiment, the memory 735 is a non-transitory computer-readable medium storing computer-executable instructions that are executable by the processor 734 to cause the processor 734 to initiate the formation of the device according to the method 500 of Figure 5. For example, the computer-executable instructions can be executable to enable the processor 1034 to initiate the formation of the bit cell 100 according to the metal layer patterning technique described with respect to Figures 2-4. As an illustrative example, the processor 734 can initiate or control one or more steps of the method 500 of Figure 5.

The die 736 may be provided to a packaging process 738, where the die 736 is incorporated into a representative package 740. For example, the package 740 may include a single die 736 or multiple dies, such as a system-in-package (SiP) arrangement. The package 740 may be configured to comply with one or more standards or specifications, such as a Joint Electron Device Engineering Council (JEDEC) standard.

Information about package 740 can be distributed to various product designers, such as via a component library stored at computer 746. Computer 746 can include a processor 748, such as one or more processing cores, coupled to memory 750. A printed circuit board (PCB) tool can be stored as processor-executable instructions at memory 750 to process PCB design information 742 received from a user of computer 746 via user interface 744. PCB design information 742 can include physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device corresponding to package 740 including bit cell 100 according to the metal layer patterning technique described with respect to Figures 2-4.

Computer 746 can be configured to convert PCB design information 742 to generate a data file, such as a GERBER file 752, having data including physical positioning information of a packaged semiconductor device on a circuit board, and a layout of electrical connections such as traces and vias, wherein the packaged semiconductor device corresponds to package 740 including bit cells 100 according to the metal layer patterning technique described with respect to FIGS. 2-4 . In other embodiments, the data file generated from the converted PCB design information can have a format other than the GERBER format.

The GERBER file 752 can be received at a circuit board assembly process 754 and used to create a PCB manufactured according to the design information stored in the GERBER file 752, such as a representative PCB 756. For example, the GERBER file 752 can be uploaded to one or more machines to perform the various steps of the PCB production process. The PCB 756 can be populated with electronic components including the package 740 to form a representative printed circuit assembly (PCA) 758.

The PCA 758 may be received at a product manufacturing process 760 and integrated into one or more electronic devices, such as a first representative electronic device 762 and a second representative electronic device 764. For example, the first representative electronic device 762, the second representative electronic device 764, or both may include or correspond to the electronic device 600 of FIG6 , or a component thereof, such as the SRAM device 664. As illustrative, non-limiting examples, the first representative electronic device 762, the second representative electronic device 764, or both may include a communication device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a satellite phone, a computer, a tablet computer, a portable computer, or a desktop computer. Alternatively or additionally, the first representative electronic device 762, the second representative electronic device 764, or both may include a set-top box, an entertainment unit, a navigation device, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a video player, a digital video player, a digital video disk (DVD) player, a portable digital video player, any other device that stores or retrieves data or computer instructions, or a combination thereof, in which the bit cell 100 according to the metal layer patterning technique described with respect to Figures 2-4 is integrated. As another illustrative, non-limiting example, one or more of the electronic devices 762 and 764 may include a remote unit such as a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit (such as a personal data assistant), a device using a global positioning system (GPS), a navigation device, a fixed location data unit (such as a meter reading device), or any other device that stores or retrieves data or computer instructions, or any combination thereof. Although Figure 7 shows remote units according to the teachings of the present disclosure, the present disclosure is not limited to these illustrated units. Embodiments of the present disclosure may be applicable to any device that includes an active integrated circuit with memory and on-chip circuitry.

1 and 2 can be manufactured, processed, and incorporated into electronic devices as described in illustrative process 700. One or more aspects of the embodiments disclosed with respect to FIGs. 1-6 can be included in various processing stages, such as in library file 712, GDSII file 726 (e.g., a file in GDSII format), and GERBER file 752 (e.g., a file in GERBER format), as well as stored in memory 710 of research computer 706, memory 718 of design computer 714, memory 750 of computer 746, and memory of one or more other computers or processors (not shown) used at various stages (such as at circuit board assembly process 754), and also incorporated into one or more other physical embodiments, such as mask 732, die 736, package 740, PCA 758, other products (such as prototype circuits or devices (not shown)), or any combination thereof. While various representative production stages from physical device design to final product are depicted, in other embodiments, fewer stages may be used or additional stages may be included. Similarly, process 700 may be performed by a single entity or by one or more entities performing various stages of process 700 .

Although one or more of Figures 1A-7 may illustrate systems, devices, and/or methods according to the teachings of the present disclosure, the present disclosure is not limited to these illustrated systems, devices, and/or methods. Embodiments of the present disclosure may be applicable to any device including an integrated circuit with a memory, a processor, and on-chip circuitry.

Although one or more of Figures 1A-7 may illustrate systems, devices, and/or methods according to the teachings of the present disclosure, the present disclosure is not limited to the systems, devices, and/or methods shown therein. One or more functions or components of any of Figures 1A-7 illustrated or described herein may be combined with one or more other parts of another of Figures 1A-7. Therefore, the individual embodiments described herein should not be construed as being restrictive, and the embodiments of the present disclosure may be appropriately combined without departing from the teachings of the present disclosure.

Those skilled in the art will further appreciate that the various illustrative logic blocks, configurations, modules, circuits, and algorithmic steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software executed by a processor, or both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or processor executable instructions depends on the specific application and design constraints imposed on the entire system. Technicians can implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as causing deviations from the scope of this disclosure.

The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module can reside in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-state storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium can be integrated with the processor. The processor and the storage medium can reside in an application specific integrated circuit (ASIC). The ASIC can reside in a computing device or a user terminal. In an alternative, the processor and the storage medium can reside in a computing device or a user terminal as discrete components.

The previous description of the disclosed embodiments is provided to enable those skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will be apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments shown herein, but should be consistent with the widest scope consistent with the principles and novel features defined by the appended claims.

Claims (30)

1. An apparatus comprising: A first metal layer is coupled to the bit cell and has a length perpendicular to the length of the polysilicon gate in the bit cell; A third metal layer, including a write word line coupled to the bit cell, the third metal layer having a length parallel to the length of the polysilicon gate; and A second metal layer between the first metal layer and the third metal layer, the second metal layer including two read word lines coupled to the bit cell, the second metal layer having a length parallel to the length of the polysilicon gate; The first and second metal layers have relatively low pitch, and the third metal layer has relatively high pitch. The width of the write word line is relatively large, and the width of the two read word lines is relatively narrow. 2. The apparatus according to claim 1, wherein the bit unit is a three-port bit unit. 3. The apparatus of claim 1, wherein the bit cell is manufactured using a semiconductor manufacturing process, and wherein the semiconductor manufacturing process is a sub-14 nanometer (nm) process. 4. The apparatus of claim 3, wherein the semiconductor manufacturing process includes a 10nm process. 5. The apparatus of claim 3, wherein the semiconductor manufacturing process includes a 7nm process. 6. The apparatus of claim 1, wherein the first metal layer, the second metal layer and the third metal layer are patterned using a self-aligned double patterning (SADP) process. 7. The apparatus according to claim 1, further comprising: A first via connects the first metal layer to the second metal layer; and The second via connects the second metal layer to the third metal layer. 8. The apparatus of claim 1, wherein the second metal layer does not include bending. 9. A method comprising: A first metal layer at the in-place cell is patterned, the first metal layer having a length perpendicular to the length of the polysilicon gate in the in-place cell. A third metal layer is patterned, the third metal layer including write word lines coupled to the bit cell, the third metal layer having a length parallel to the length of the polysilicon gate; and A second metal layer between the first metal layer and the third metal layer is patterned, the second metal layer including two read word lines coupled to the bit cell, and the second metal layer having a length parallel to the length of the polysilicon gate. The first and second metal layers have relatively low pitch, and the third metal layer has relatively high pitch. The width of the write word lines is relatively large, and the width of the two read word lines of the second metal layer is relatively narrow. 10. The method of claim 9, wherein the bit unit is a three-port bit unit. 11. The method of claim 9, wherein the bit cell is manufactured using a semiconductor manufacturing process, and wherein the semiconductor manufacturing process is a sub-14 nanometer (nm) process. 12. The method of claim 11, wherein the semiconductor manufacturing process includes a 10nm process. 13. The method of claim 11, wherein the semiconductor manufacturing process includes a 7nm process. 14. The method of claim 9, wherein the first metal layer, the second metal layer and the third metal layer are patterned using a self-aligned double patterning (SADP) process. 15. The method of claim 9, further comprising: A first via is formed, the first via connecting the first metal layer to the second metal layer; and A second via is formed, which connects the second metal layer to the third metal layer. 16. The method of claim 9, wherein the second metal layer does not include bending. 17. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to perform the following operations: Initiate patterning of a first metal layer at the in-place cell, the first metal layer having a length perpendicular to the length of the polysilicon gate in the in-place cell; Initiate patterning of a third metal layer, the third metal layer including write word lines coupled to the bit cell, the third metal layer having a length parallel to the length of the polysilicon gate; and Initiate patterning of a second metal layer between the first metal layer and the third metal layer, the second metal layer including two read word lines coupled to the bit cell, the second metal layer having a length parallel to the length of the polysilicon gate; The first and second metal layers have relatively low pitch, and the third metal layer has relatively high pitch. The width of the write word lines is relatively large, and the width of the two read word lines of the second metal layer is relatively narrow. 18. The non-transitory computer-readable medium of claim 17, wherein the bit unit is a three-port bit unit. 19. The non-transitory computer-readable medium of claim 17, wherein the bit cells are manufactured using a semiconductor manufacturing process, and wherein the semiconductor manufacturing process is a sub-14 nanometer (nm) process. 20. The non-transitory computer-readable medium of claim 19, wherein the semiconductor manufacturing process includes a 10nm process. 21. The non-transitory computer-readable medium of claim 19, wherein the semiconductor manufacturing process includes a 7nm process. 22. The non-transitory computer-readable medium of claim 17, wherein the first metal layer, the second metal layer and the third metal layer are patterned using a self-aligned double patterning (SADP) process. 23. The non-transitory computer-readable medium of claim 17, further comprising instructions that, when executed by the processor, cause the processor to perform the following operations: A first via is formed, the first via connecting the first metal layer to the second metal layer; and A second via is formed, which connects the second metal layer to the third metal layer. 24. The non-transitory computer-readable medium of claim 17, wherein the second metal layer does not include bending. 25. The non-transitory computer-readable medium of claim 17, wherein the bit cells are included in a static random access memory (SRAM) device. 26. An apparatus comprising: A first means for routing current to a bit cell, the first means having a length perpendicular to the length of the polysilicon gate in the bit cell; A third means for routing current, the third means for routing current including a write word line coupled to the bit cell, the third means having a length parallel to the length of the polysilicon gate; and A second current routing device between the first current routing device and the third current routing device, the second current routing device comprising two read word lines coupled to the bit cell, the second device having a length parallel to the length of the polysilicon gate; The first and second devices have relatively low pitches, and the third device has a relatively high pitch. The width of the write word lines is relatively large, and the width of the two read word lines is relatively narrow. 27. The apparatus of claim 26, wherein the bit unit is a three-port bit unit. 28. The apparatus of claim 26, wherein the first means for routing current, the second means for routing current, and the third means for routing current are patterned using a self-aligned double patterning (SADP) process. 29. The apparatus of claim 26, wherein the bit cell is manufactured using a semiconductor manufacturing process, and wherein the semiconductor manufacturing process is a sub-14 nanometer (nm) process. 30. The apparatus of claim 29, wherein the semiconductor manufacturing process includes a 10nm process or a 7nm process.