HK1243241B - Apparatus and method for power conversion - Google Patents

Description

Power conversion device and method

This application claims the benefit of U.S. Application No. 14/873,043, filed October 1, 2015, which claims priority to U.S. Provisional Application Serial No. 62/059,067, filed October 2, 2014.

Background of the invention.

Technical Field

The disclosed subject matter relates generally to power supplies.

Background Art

U.S. Patent No. 8,576,592 discloses various power supply circuits for generating DC power with very low ripple. Figure 1 shows an embodiment of the low-ripple power supply disclosed in the '592 patent, also known as an Euler power converter. The power supply includes a pair of transformers 10 and 12 connected to bridge rectifiers 14 and 16. Each of transformers 10 and 12 includes a center tap, Vs. The outputs of bridge rectifiers 14 and 16 are combined at a load 18 (CI and RL1). Transformer 10 is coupled to a pair of FET transistors 20 and 22 driven by broadband operational amplifiers 24 and 26. Similarly, transformer 12 is coupled to a pair of FET transistors 28 and 30 driven by broadband operational amplifiers 32 and 34. Figure 1 shows the input waveforms to the operational amplifiers and the resulting waveforms at the secondary windings of transformers 10 and 12. The input waveforms are shaped so that the secondary current waveforms provided by transformers 10 and 12 are 90 degrees out of phase. The secondary waveforms combine at the load 18 so that the resulting waveform provides a DC power supply with very little ripple. The low ripple removes the requirement for any storage capacitors, thereby allowing fewer components and a smaller power supply.

The input waveform causes the transistors for each transformer 10 and 12 to turn on and off sequentially. For example, when transistor 20 is on, transistor 22 is off. Similarly, when transistor 22 is on, transistor 20 is off. When one of the transistors is initially turned off, the voltage across the primary winding of the transformer will combine with the rail voltage Vs to double the voltage at the drain terminal of the transistor. Such high voltages require the use of high-voltage transistors. It would be desirable to reduce the voltage requirements of the transistors.

Summary of the Invention

A power supply includes a first current generator circuit coupled to a first transformer and generating a first waveform, and a second current generator circuit coupled to a second transformer and generating a second waveform out of phase with the first waveform. The first and second waveforms are rectified and combined into a DC output signal. The power supply includes a first coupling circuit coupling the first current generator circuit to the first transformer and a second coupling circuit coupling the second current generator circuit to the second transformer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a power supply of the prior art;

FIG2 is a schematic diagram of an embodiment of a power supply of the present invention;

FIG3 is a schematic diagram of an alternative embodiment of a power supply;

4A-4G are graphs showing waveforms at various points of the power supply;

FIG5 is a schematic diagram of another alternative embodiment of a power supply;

FIG6 is a schematic diagram of another alternative embodiment of a power supply;

FIG7 is a schematic diagram of another alternative embodiment of a power supply;

FIG8 is a schematic diagram of a power supply with voltage boosting capability;

FIG9 is an alternative embodiment of the power supply shown in FIG8;

FIG10 is a graph showing various waveforms of a power supply having a tuning capacitor coupled to a transformer; and,

11 is a graph showing various waveforms for a power supply with an impedance network coupled to a transformer.

DETAILED DESCRIPTION

A power supply is disclosed that includes a first current generator circuit coupled to a first transformer and generating a first waveform, and a second current generator circuit coupled to a second transformer and generating a second waveform out of phase with the first waveform. The first and second waveforms are rectified and combined into a DC output signal. The power supply includes a first coupling circuit coupling the first current generator circuit to the first transformer and a second coupling circuit coupling the second current generator circuit to the second transformer. A switching circuit can reduce the operating voltage across transistors within the current generator circuit. Separating the switching circuit and the current generating circuit allows for optimization of the two different operations and also allows the regulation control circuit to be associated with the current control circuit without having to cross the transformer isolation boundary.

Referring to the drawings, and more particularly by reference numerals, FIG2 illustrates an embodiment of a power supply 100 of the present invention. Power supply 100 includes transformers 102 and 104 coupled to rectifiers 106 and 108, respectively. The outputs of rectifiers 106 and 108 are combined at load 110 (C2 and RL2). Transformers 102 and 104 are each coupled to current generator circuits 112 and 114, respectively, and to coupling circuits 116 and 118, respectively. Current generator circuits 112 and 114 include FET transistors 120, 122, 124, and 126, and operational amplifiers 128, 130, 132, and 134. Coupling circuits 116 and 118 include FET transistors 136, 138, 140, and 142, and operational amplifiers 144, 146, 148, and 150. Transistors 136, 138, 140, and 142 are connected to rail voltage Vs.

Figure 2 shows the input waveforms for current generating circuits 112 and 114 and coupling circuits 116 and 118. The input waveforms are generated by a waveform generator (not shown). The input waveforms have relative phases such that in one state, transistors 122 and 136 are on and transistors 120 and 138 are off. In this state, current flows through the conductive transistors 122 and 136 and the primary winding of transformer 102. The input waveform then turns on transistors 120 and 138 and turns off transistors 122 and 136. The shape of the waveform at the transformer is determined by the linear current control of transistors 120 and 122. Because transistors 136 and 138 are connected to the rail voltage Vs, the voltage across the off transistors when switching is Vs, which is half the voltage seen by the transistors in the prior art power supply shown in Figure 1. Therefore, this circuit reduces the voltage requirements of the transistors.

Current generator circuit 114 and coupling circuit 118 operate in a similar manner, with transistors 126 and 140 turned on and transistors 124 and 142 turned off, and then switching is performed so that transistors 124 and 142 are turned on and transistors 126 and 140 are turned off. The input waveforms have relative phases so that the output waveforms of rectifiers 106 and 108 are 180 degrees out of phase. The outputs are combined at load 110, resulting in a DC output with little ripple.

This arrangement has an additional aspect that broadens its application - the functions of voltage control and current control of the transformer have now been at least partially separated. It is this realization that leads to the concept of current in the DC-DC converter being defined not by means of a current output amplifier, but by means of a controlled impedance within the converter and thus the concept of Control Euler (or ContrEuler).

In reality, a semiconductor device configured as a linear amplifier is actually a controlled impedance, as it determines the flow of current from the DC supply, but often the two aspects of amplification and control are mixed. By separating them, other ways of implementing a DC-DC converter become possible.

FIG3 shows an alternative embodiment 100′ of a power supply. In this embodiment, current generator circuits 112 and 114 are coupled to the secondary windings of transformers 102′ and 104′. Transformers 102′ and 104′ include center taps on their primary windings. Rectifiers 106′ and 108′ each include a pair of diodes. The input waveforms are shown with relative phases such that transistors 120, 122, 124, 126, 136, 138, 140, and 142 switch in the same manner as described with respect to FIG2 . The secondary circuit may have a lower voltage, so placing current generator circuits 112 and 114 on the secondary side of the power supply may result in lower voltage requirements.

Although the input and output grounds are shown as being shared in this example, this need not be the case. Switches 136, 138, 140, and 142 control the connection of the primary side of the transformer. In this example, a center-tapped primary is shown with push-pull switching for simplicity, but a half-bridge or full-bridge could be used instead to remove the need for a center tap and reduce the voltage requirements on the switches.

Thus, system current control is achieved on the secondary of the transformer where the voltage may be lower. Additionally, it may be advantageous for the current control circuit to be on the same side of the transformer as the output voltage regulation circuit.

Figures 4A-4G show various waveforms of power supply 100'. The voltage at the drain of primary-side FET transistors 136 and 138 is plotted along with the current through secondary-side control transistors 120 and 122. In addition, the total primary-side current in transformer 102 is shown. The drain voltage of control transistors 120 and 122 and the output voltage ripple are also plotted. Of interest are the current-control FET drain voltages of transistors 120 and 122. The voltages across 120, 122, 124, and 126 remain low throughout the operating cycle. This means that very low-voltage FETs can be used, optimized for linear control characteristics rather than high-voltage switching characteristics. However, the voltage rating of the FETs must be such that they can handle any mismatch between the actual output voltage delivered to the load and the optimized voltage determined from the input voltage and the transformer turns ratio. The low voltage across the control transistors also results in high efficiency for the DC-DC conversion process.

In this particular example, the output is a negative DC voltage, allowing the use of N-channel FETs. The output voltage is essentially ripple-free, with an ideal transformer and rectifier, even without any output smoothing capacitors or filters. With practical components, the ripple is still extremely low, totaling <0.1% for a 38V/110W output using only 1.1 uF of total effective capacitance in this example.

The drain currents of the two current control FETs (e.g., 120 and 122) of each transformer are added together to produce the total control current waveform (because these drain currents are in parallel). However, this is only one specific implementation used to illustrate the expansion of the secondary-side control elements from the basic circuit of Figure 2. Alternatively, only one FET can be used, which is driven appropriately to define the raised cosine control current.

It can be seen that the system current has the expected characteristics - the raised cosine secondary current is converted to an Euler current in the primary. The primary voltage is also seen to be square and therefore the primary side circuit is valid.

The current control FET drain voltage is also of interest. The voltage across transistors 120/122 and 124/126 remains low throughout the operating cycle. This means that very low voltage FETs can be used, optimized for linear control characteristics rather than high voltage switching characteristics. However, their voltage ratings must be such that they can handle any mismatch between the actual output voltage delivered to the load and the optimized voltage determined from the input voltage and transformer turns ratio. The low voltage across the control transistors also results in high efficiency for the DC-DC conversion process.

FIG5 is another alternative embodiment of a power supply 100″, in which current generator circuits 112″ and 114″ are coupled to the secondary windings and each has only one transistor 120 and 124 and operational amplifiers 128 and 132. Transistors 120 and 124 connect the grounds of rectifiers 106 and 108 to system ground. The input waveforms are such that the power supply operates in a manner similar to the power supply shown in FIG3 . The output phase is shifted to provide a positive output voltage. Unlike the power supply shown in FIG3 , the power supply shown in FIG5 does not require a center tap on the secondary winding.

The ContrEuler arrangement shown in these schematics focuses on the basic arrangement of signal generation and control. As such, the output from the secondary side of the DC-DC converter takes the form of a current applied to the load. It is generally desired that the output voltage be largely independent of the applied load impedance. To achieve this load-independent output, a voltage feedback control loop can be applied that senses the output voltage and generates an error voltage to control the amplitude of the current control waveform (e.g., the voltage applied to the inputs of amplifiers 128 and 132). This error detection and control loop is implemented only on the secondary side of the transformer. There is no need for the error signal to be transmitted across the isolation barrier formed by the transformer, so the control loop can have increased bandwidth and linearity compared to the control loop of a conventional DC-DC converter.

FIG6 is another alternative embodiment of a power supply 100″, in which rectifiers 106″ and 108″ include a switch 160. Load 108 is also located in the primary side of the circuit. If the energy source is connected to the secondary side of the circuit, then by appropriately adjusting the timing of the control voltages to primary-side switches 136, 138, 140, and 142, a ripple-free DC output can be obtained at the center taps of transformers 102′ and 104′.

Thus, this active rectifier version of the Euler implementation can be used in forward mode to convert a DC power source on the primary side to a power source at a different voltage on the secondary side to power a secondary-side load, or vice versa (if the power source is on the secondary side). This feature is useful, for example, in regenerative braking applications, where power is normally applied to the motor on the secondary side, but where under blocking conditions the motor effectively becomes a generator and it is desirable to return power to the battery on the primary side. Conversion in both directions will be ripple-free, on both the input and output sides of the DC-DC conversion.

FIG7 shows another alternative embodiment 100''' of a power supply in which coupling circuits 116' and 118' have additional FET transistors 170, 172, 174 and 176 and operational amplifiers 178, 180, 182 and 184. Operation is similar to the power supply shown in FIG2. Transistors 136 and 172 are turned on and transistors 138 and 170 are turned off, and then switching is performed so that transistors 138 and 170 are turned on and transistors 136 and 172 are turned off. Coupling circuit 118' operates in the same manner. In this embodiment, both transformer switching and current control are performed on the primary side. Although the voltage is often higher on the primary side of the DC-DC converter, the operating mode of this topology acts so that the voltage appearing across the current control transistors 120 and 124 is still much lower than the primary supply voltage so that transistors 120 and 124 can still be optimized for linear current control. Such a configuration may be useful when maximum efficiency is desired or where it is the drain voltages of transistors 120 and 124 that are being controlled.

Both transformer switching and current control are performed on the primary side. Although the voltage is often higher on the primary side of the DC-DC converter, the action of the operating mode of this topology is that the voltage appearing across the current control transistors 120 and 122 is still much lower than the primary supply voltage, so that transistors 120 and 124 can be optimized for linear current control.

Such a configuration may be useful when maximum efficiency is desired or where it is the drain voltages of transistors 120 and 124 that are controlled - all drive and control circuitry is then on the primary side of the transformer.

FIG8 illustrates an embodiment of a power supply 200 that provides voltage boosting. Power supply 200 includes four amplifier stages 202, 204, 206, and 208. Each amplifier stage includes charge FET transistors 210, 212, 214, and 216 connected to operational amplifiers 218, 220, 222, and 224, and waveform generators 226, 228, 230, and 232. Each amplifier stage also includes discharge FET transistors 234, 236, 238, and 240 connected to operational amplifiers 242, 244, 246, and 248, and waveform generators 250, 252, 254, and 256. Amplifier stages 202 and 204 are connected to capacitors 258 and 260 and diode pairs 262 and 264. Similarly, amplifier stages 206 and 208 are connected to capacitors 266 and 268 and diode pairs 270 and 272. Power supply 200 is connected to load 274, which is also connected to ground. The waveforms generated by the waveform generator are shown in Figure 8. The waveforms are out of phase.

In operation, transistor 210 is turned on to charge capacitor 258 to a certain voltage. Transistor 210 is then turned off and transistor 234 is turned on, causing capacitor 258 to discharge into load 274. The output of capacitor 258 is added to rail voltage V1 so that the additional voltage is applied to load 274, thereby increasing the output voltage. The other amplifier stages 204, 206, and 208 operate in a similar manner to charge and discharge capacitors 260, 266, and 268. Amplifier stages 202 and 204 are timed to charge one of capacitors 258 or 260 while the other of capacitors 260 or 258 is discharged. Similarly, amplifier stages 206 and 208 charge and discharge capacitors 266 and 268 in an alternating manner. The waveforms of each stage 202, 204, 206, and 208 are offset so that a ripple-free DC output is provided to load 274.

9 is an embodiment of a power supply 300 that provides a boosted voltage to a load 302. The power supply 300 includes a controller circuit that includes FET transistors 304, 306, 308, and 310, operational amplifiers 312 and 314, and waveform generators 316 and 318. The controller circuit is coupled to capacitors 320, 322, 324, and 326 and diode pairs 328, 330, 332, and 334. The power supply also includes a plurality of switches 336, 338, 340, 342, 344, 346, 348, and 350.

In operation, switches 338 and 340 are turned on, and switches 336 and 342 are turned off. Transistors 304 and 306 are also turned on, defining the waveform of the current flowing into capacitor 320. In this state, capacitor 320 is charged and capacitor 322 is discharged. Switches 336 and 342 are then turned on, and switches 338 and 340 are turned off. Transistors 304 and 306 are also turned on, again defining the waveform of the current flowing into capacitor 322. In this state, capacitor 320 is discharged into load 302. The voltage across the capacitor is added to the rail voltage to provide an increased voltage to load 302. During this state, capacitor 322 is charged. This sequence continues, with capacitors 320 and 322 alternately charging and discharging. The transistors and circuits on the right-hand side of the circuit operate in the same manner, with capacitors 324 and 326 charging and discharging alternately. The waveform provided by the right-hand side of the circuit is offset by ¼ cycle from the waveform provided by the left-hand circuit, resulting in a ripple-free DC output.

This embodiment eliminates some of the FET transistors required for the power supply shown in FIG8 . The embodiment of FIG9 also requires only two operational amplifiers, as opposed to the eight required in the embodiment of FIG8 . By utilizing switches, the charging and discharging of each capacitor can be controlled by a unipolar current controller. Furthermore, the defined current is the same for each of the devices controlling the charge and discharge cycles, thus simplifying the control circuitry. The current waveform is also simpler, effectively an offset sine wave.

The basic Eulcap configuration shown in Figure 8 includes four stages of charging and discharging to achieve both a ripple-free input and a ripple-free output. Under these operating conditions, the output storage capacitor can be eliminated (ideally—in practice, some capacitance will be required to smooth out ripple caused by imperfections). However, there may be applications where an output storage capacitor is required for other reasons, and in such cases, it may be acceptable to then compromise the converter's inherent output ripple current cancellation properties and eliminate two of the four stages. This would require eliminating amplifiers 242 and 244, along with their associated capacitors and diodes. In this reduced configuration, the output current delivered to the load will be a continuous raised cosine wave and will therefore rely on the output storage for smoothing to a low-ripple DC output. However, the input current will still retain the inherent ripple-free properties of a standard EulCap converter.

This reduction can be taken even further. If only amplifier 218 and the associated diodes and capacitors were used, both the input and output currents would be in the form of raised cosines and would therefore require capacitive filtering. However, the harmonic content of the waveforms would be low compared to the current spikes inherent in standard switched capacitor designs, and thus this mode of operation would still be of considerable benefit.

The efficiency limitation of the Euler principle is the ripple voltage induced on the primary-side square wave voltage due to leakage inductance in the transformer. In the case of the Euler waveform shape shown in Figures 4A-4G, this manifests itself as an arcsine component at twice the square wave frequency on top of the square wave. This ripple current limits how close the amplifier output can swing to ground or the rail voltage without clipping and thus introducing linearity losses. To minimize these losses, the leakage inductance must be kept low, typically 1/2,000 to 1/10,000 of the primary magnetizing inductance.

This ripple voltage can be reduced by including a tuning network in series with the transformer primary or secondary. This tuning network can include a single capacitor or a more complex network of impedance elements. The purpose of this network is to reduce the parasitic impedance seen at the drain of the current-controlled drive transistor in order to reduce the voltage drop caused by transformer parasitic impedance (such as leakage inductance) and Euler current.

If a single capacitor is used, it is tuned to partially resonate with the leakage inductance to partially cancel the ripple voltage. Since the Euler waveform is not a sine wave, it is not possible to completely eliminate the ripple with a single capacitor, but enough ripple reduction can be obtained to significantly reduce the dissipation in the drive transistor.

The ripple can be further reduced using more complex tuning networks (which may, for example, include a series tuned LC network placed in series with the transformer primary or secondary, across a parallel resistor/capacitor).

The tuning network can be used to minimize the power losses in the system for a given transformer and its leakage inductance, or to reduce the leakage inductance requirements for given acceptable losses in the driver transistor.

Figure 10 illustrates sample waveforms. V(P1) represents the primary voltage of the first phase of the Euler circuit, and V(P2) represents the primary voltage of the second phase. I(P1) and I(P2) are the corresponding primary current waveforms. In the Phase 1 circuit, ripple is partially eliminated using appropriately selected capacitors, while in the Phase 2 circuit, no such capacitors are used. The reduction in overall voltage ripple is clear.

In the phase 1 circuit, partial cancellation of the ripple has been achieved using appropriately chosen capacitors, whereas in the phase 2 circuit no such capacitors are used. It can be seen that there is a reduction in the overall voltage ripple.

Figure 11 shows the further ripple reduction possible using a more complex impedance network placed in series with the transformer primary. This network includes a capacitor in series and an inductor placed in parallel with a further resistor and capacitor. As in the case of Figure 10, V(P1) represents the primary voltage of the first phase with the ripple reduction network, and V(P2) represents the primary voltage of the second phase without the ripple reduction network. An even greater ripple reduction effect is observed.

Although the tuning capacitor has been described as being in series with the primary winding(s) of the transformer, a suitably sized capacitor may be used on the secondary side instead.

This principle of ripple reduction by partially detuning parasitic elements can also be employed with the embodiment shown in FIG8 . In this case, a small inductor can be placed in series with each of capacitors 258 , 260 , 266 , and 268 to reduce the ripple voltage at the control transistor output. With appropriate selection of the capacitors, this inductor can be implemented as the inherent parasitic inductance of the capacitors themselves. If this is not the case, the inductor can be constructed as a PCB coil. As in the case of the Euler transformer-based approach, further ripple reduction can be achieved by employing a more complex impedance network using the EulCap.

While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive of the broad invention, and that the invention is not limited to the specific construction and arrangements shown and described, since various other modifications will occur to those skilled in the art.

Claims (19)

1. A power supply, comprising: The first transformer has a first primary winding and a first secondary winding; The second transformer has a second primary winding and a second secondary winding; A first current generator circuit is coupled to the first transformer and generates a first waveform, wherein the first current generator circuit receives a first analog input; A first rectifier circuit rectifies the first waveform; A second current generator circuit is coupled to the second transformer and generates a second waveform that is out of phase with the first waveform, wherein the second current generator circuit receives a second analog input; The second rectifier circuit rectifies the second waveform; A combiner that combines the first rectified waveform and the second rectified waveform into a DC output signal; A first coupling circuit couples the first current generator circuit to the first transformer; and... A second coupling circuit couples the second current generator circuit to the second transformer. 2. The power supply of claim 1, wherein the first current generator circuit includes a first current generator transistor and a second current generator transistor, the first coupling circuit includes a first switching transistor connected to the first current generator transistor and a second switching transistor connected to the second current generator transistor, the power supply operating such that: in a first state the first switching transistor and the second current generator transistor are turned on and the second switching transistor and the first current generator transistor are turned off; and in a second state the first switching transistor and the second current generator transistor are turned off and the second switching transistor and the first current generator transistor are turned on. 3. The power supply according to claim 2, wherein the first switching transistor and the second switching transistor are connected to the primary winding and rail voltage of the first transformer. 4. The power supply according to claim 1, wherein the first current generator circuit and the first coupling circuit are coupled to the primary winding of the first transformer, and the second current generator circuit and the second coupling circuit are coupled to the primary winding of the second transformer. 5. The power supply of claim 1, wherein the first current generator circuit includes a first current generator transistor, the first coupling circuit includes a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor coupled to the first current generator transistor, the power supply operating such that: in a first state the first switching transistor and the third switching transistor are turned on and the second switching transistor and the fourth switching transistor are turned off; and in a second state the first switching transistor and the third switching transistor are turned off and the second switching transistor and the fourth switching transistor are turned on. 6. The power supply according to claim 1, further comprising at least one first tuning element connected to the first primary winding and at least one second tuning element connected to the second primary winding. 7. A power supply, comprising: The first transformer has a first primary winding and a first secondary winding; The second transformer has a second primary winding and a second secondary winding; A first current generator circuit is coupled to the first transformer and generates a first waveform; A first rectifier circuit rectifies the first waveform; A second current generator circuit is coupled to the second transformer and generates a second waveform that is out of phase with the first waveform. The second rectifier circuit rectifies the second waveform; A combiner that combines the first waveform and the second waveform into a DC output signal; First coupling circuit; and, Second coupling circuit; The first current generator circuit is coupled to the secondary winding of the first transformer, and the first coupling circuit is coupled to the primary winding of the first transformer. The second current generator circuit is coupled to the secondary winding of the second transformer, and the second coupling circuit is coupled to the primary winding of the second transformer. 8. The power supply according to claim 7, wherein each of the first rectifier circuit and the second rectifier circuit includes a pair of diodes. 9. The power supply according to claim 7, wherein the first rectifier circuit and the second rectifier circuit include switches, and the output of the power supply is coupled to the first primary winding and the second primary winding. 10. The power supply according to claim 7, further comprising at least one first tuning element connected to the first primary winding and at least one second tuning element connected to the second primary winding. 11. A method for power conversion, comprising: A first waveform is generated by a first current generating circuit that flows through a first transformer having a first primary winding and a second secondary winding, and the first current generating circuit receives a first analog input. The first waveform is rectified; A second current generating circuit is used to generate a second waveform that flows through a second transformer having a second primary winding and a second secondary winding. The second waveform is out of phase with the first waveform. The second current generating circuit receives a second analog input. The second waveform is rectified; The first rectified waveform and the second rectified waveform are combined into a DC output signal; The coupling from the first current generator circuit to the first transformer is controlled using a first coupling circuit; and, The coupling between the second current generator circuit and the second transformer is controlled by the second coupling circuit. 12. The method of claim 11, wherein the first current generator circuit includes a first current generator transistor and a second current generator transistor, the first coupling circuit includes a first switching transistor connected to the first current generator transistor and a second switching transistor connected to the second current generator transistor, the method further comprising the steps of: operating in a first state such that the first switching transistor and the second current generator transistor are turned on and the second switching transistor and the first current generator transistor are turned off; and operating in a second state such that the first switching transistor and the second current generator transistor are turned off and the second switching transistor and the first current generator transistor are turned on. 13. A power source, comprising: Multiple current generator circuits receive multiple logic inputs and generate multiple out-of-phase waveforms; A capacitor circuit comprising a plurality of capacitors that are charged and discharged sequentially to change the voltage of the waveform; Multiple switching circuits control the charging and discharging of the capacitor; and, A combiner that combines the waveforms into a DC output signal. 14. The power supply of claim 13, wherein each switching circuit comprises a plurality of transistors. 15. The power supply of claim 13, wherein each switching circuit comprises a plurality of switches. 16. The power supply of claim 13, further comprising a plurality of tuning elements connected to the capacitor. 17. A method for performing power conversion using a power supply according to any one of claims 1 to 10, comprising: Generate multiple out-of-phase waveforms; Multiple switching circuits are used to sequentially charge and discharge multiple capacitors to change the voltage of the waveform; and, The waveforms are combined into a DC output signal. 18. The method of claim 17, wherein each switching circuit controls the charging and discharging of the capacitor by turning the transistor on and off. 19. The method of claim 17, wherein each switching circuit controls the charging and discharging of the capacitor by closing and opening a switch.