HK1138685B - Cyclic delay diversity and precoding for wireless communication - Google Patents

Description

Cyclic delay diversity and precoding for wireless communications

This patent application claims priority to U.S. provisional application No.60/888,494 entitled "EFFICIENTCYCLIC DELAY DIVERSITY BASED previous" filed on 6.2.2007, which is assigned to the assignee of the present application and is hereby incorporated by reference.

Technical Field

The present disclosure relates generally to communication, and more specifically to techniques for transmitting data in a wireless communication system.

Background

Wireless communication systems have been widely deployed to provide various communication content such as voice, video, packet data, messaging, broadcast, and so on. These wireless systems may be multiple-access systems capable of supporting multiple users by sharing the available system resources. Examples of such multiple access systems include: code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal FDMA (OFDMA) systems, and single carrier FDMA (SC-FDMA) systems.

A wireless communication system may support multiple-input-multiple-output (MIMO) transmissions. For MIMO, a transmitter may utilize multiple (T) transmit antennas to transmit data to a receiver equipped with multiple (R) receive antennas. Multiple transmit and receive antennas form a MIMO channel, which may be used to increase throughput and/or improve reliability. For example, the transmitter may transmit a maximum of T data streams simultaneously from T transmit antennas to improve throughput. Alternatively, the transmitter may transmit one data stream from all T transmit antennas to improve reliability. In any case, the MIMO transmission needs to be sent in a way that achieves good performance.

Disclosure of Invention

Techniques for transmitting MIMO transmissions using a combination of cyclic delay diversity (cyclic delay diversity) and precoding are described. In an aspect, a set of delays for cyclic delay diversity and a set of precoding matrices may be supported. The combination of precoding matrix and delay may be selected according to one or more criteria such as data performance, rank (rank), geometry (geometry), mobility, channel type, feedback reliability, etc. In one design, the set of delays may include a zero delay, a small delay less than a cyclic prefix length, and a large delay greater than the cyclic prefix length. The large delay corresponds to a cyclic delay of K/L, where K is the number of samples of the useful part of the OFDM symbol and L is the number of antennas used for cyclic delay diversity, where these antennas may be virtual antennas or physical antennas. L is also referred to as rank.

In one design, a first entity (e.g., a transmitter or a receiver) may select a delay from a set of delays and send the selected delay to a second entity (e.g., a receiver or a transmitter). The first entity may then exchange data with the second entity (e.g., transmit data to or receive data from the second entity) based on the selected delay.

In one design, the first entity is a node B and the second entity is a UE. The node B may select a delay dedicated to the UE and transmit the selected delay to the UE. Alternatively, the node B may select the delays for a group of UEs served by the node B and broadcast the selected delays to the UEs. In one design, the node B may perform precoding using a precoding matrix and then perform cyclic delay diversity processing based on the selected delay. In another design, the node B may perform cyclic delay diversity processing based on the selected delay and then perform precoding using a precoding matrix. Precoding refers to performing spatial processing to obtain virtual antennas from physical antennas.

In another design, the first entity is a UE and the second entity is a node B. The UE may evaluate a set of precoding matrices and a set of delays based on at least one metric, such as a capacity and (sum-capacity) metric. The UE may determine the combination of the precoding matrix and the delay with the best performance and transmit the precoding matrix and the delay in the combination to the node B. The UE may then receive the data transmission sent by the node B based on the selected precoding matrix and the delay. The UE may derive a valid MIMO channel estimate based on the selected precoding matrix and delay and then perform MIMO detection based on the valid MIMO channel estimate.

Various aspects and features of the disclosure are described in further detail below.

Drawings

Fig. 1 shows a wireless multiple-access communication system.

Fig. 2 shows a block diagram of one node B and one UE.

Fig. 3A and 3B show two Transmit (TX) MIMO processor designs.

Fig. 4 shows a design of a Receive (RX) MIMO processor.

Fig. 5A and 5B show cyclic delay diversity with large delay for 2 and 4 antennas, respectively.

Fig. 6A, 6B, and 6C illustrate transmissions via four, three, and two virtual antennas, respectively, using layer switching.

Fig. 7 shows a design of an evaluation unit for selecting a precoding matrix and a delay.

Fig. 8 shows a process for exchanging data.

Fig. 9 shows a process performed by the node B for data transmission.

Fig. 10 shows a process performed by the UE for data reception.

Fig. 11 shows an apparatus for exchanging data.

Detailed Description

The techniques described herein may be used for various wireless communication systems such as CDMA, TDMA, FDMA, OFDMA, SC-FDMA and other systems. The terms "system" and "network" are often used interchangeably. A CDMA system may implement a radio technology such as Universal Terrestrial Radio Access (UTRA), CDMA2000, and so on. UTRA includes wideband-CDMA (W-CDMA) and other CDMA variations. cdma2000 covers IS-2000, IS-95 and IS-856 standards. TDMA systems may implement wireless technologies such as global system for mobile communications (GSM). OFDMA systems may implement methods such as evolved UTRA (E-UTRA), Ultra Mobile Broadband (UMB), IEEE802.11(Wi-Fi), IEEE 802.16(WiMAX), IEEE802.20、Flash-OFDM And so on. UTRA and E-UTRA are part of the Universal Mobile Telecommunications System (UMTS). The 3GPP Long Term Evolution (LTE) is a release-soon version of UMTS that uses E-UTRA. UTRA, E-UTRA, UMTS, LTE, and GSM are described in documents from an organization entitled "third Generation partnership project" (3 GPP). Cdma2000 and UMB are described in a document from an organization entitled "third Generation partnership project 2(3rd Generation partnership project 2)" (3GPP 2). The various wireless technologies and standards described above are known in the art.

Fig. 1 shows a wireless multiple-access communication system 100 with multiple node bs 110 and multiple User Equipments (UEs). A node B may be a fixed station that communicates with the UEs and may also be referred to as an evolved node B (enb), a base station, an access point, etc. Each node B110 may provide communication coverage for a particular geographic area. UEs 120 are dispersed throughout the system, and each UE may be stationary or mobile. A UE may also be called a mobile station, terminal, access terminal, subscriber unit, station, or the like. The UE may be a cellular phone, a Personal Digital Assistant (PDA), a wireless modem, a wireless communication device, a handheld device, a laptop computer, a cordless phone, and so on. A UE may communicate with a node B via transmissions on the downlink and uplink. The downlink (or forward link) refers to the communication link from the node bs to the UEs, and the uplink (or reverse link) refers to the communication link from the UEs to the node bs.

The techniques described herein may be used for MIMO transmission on the downlink and uplink. For clarity, some aspects of the present techniques are described below for MIMO transmission on the downlink in LTE. LTE uses Orthogonal Frequency Division Multiplexing (OFDM) on the downlink and single carrier frequency division multiplexing (SC-FDM) on the uplink. OFDM and SC-FDM partition the system bandwidth into multiple (K) orthogonal subcarriers, which are also commonly referred to as tones (tones), bins (bins), and so on. Each subcarrier may be modulated with data. In general, OFDM transmits modulation symbols in the frequency domain and SC-FDM transmits modulation symbols in the time domain.

Fig. 2 shows a block diagram of a design of node B110 and UE 120, where node B110 and UE 120 are one node B and one UE, respectively, in fig. 1. Node B110 is equipped with multiple (T) antennas 234a through 234T and UE 120 is equipped with multiple (R) antennas 252a through 252R. Each of antennas 234 and 252 may be considered a physical antenna.

At node B110, a TX data processor 220 receives data from a data source 212 and processes (e.g., encodes and symbol maps) the data in accordance with one or more modulation and coding schemes to provide data symbols. As used in the present invention, a data symbol is a symbol for data, a pilot symbol is a symbol for pilot, and the symbols may be real-valued or complex-valued. The data symbols and pilot symbols may be modulation symbols in a modulation scheme such as PSK or QAM. The pilot is data known a priori by both the node B and the UE. TX MIMO processor 230 may process the data symbols and pilot symbols in a manner described below and provide T output symbol streams to T Modulators (MODs) 232a through 232T. Each modulator 232 may process a respective output symbol stream (e.g., for OFDM) to obtain an output sample stream. Each modulator 232 may further condition (e.g., convert to analog, filter, amplify, and upconvert) its output sample stream and generate a downlink signal. T downlink signals from modulators 232a through 232T may be transmitted via antennas 234a through 234T, respectively.

At UE 120, R antennas 252a through 252R receive T downlink signals from node B110, and each antenna 252 provides a received signal to an associated demodulator (DEMOD) 254. Each demodulator 254 conditions (e.g., filters, amplifies, downconverts, and digitizes) its received signal to obtain samples and further processes the samples (e.g., for OFDM) to obtain received symbols. Each demodulator 254 provides received data symbols to an RX MIMO processor 260 and received pilot symbols to a channel processor 294. Channel processor 294 estimates a MIMO channel response from node B110 to UE 120 based on the received pilot symbols and provides a MIMO channel estimate to RX MIMO processor 260. RX MIMO processor 260 performs MIMO detection on the received data symbols based on the MIMO channel estimates and provides detected symbols, which are estimates of the transmitted data symbols. RX data processor 270 may process (e.g., symbol demap and decode) the detected symbols and provide decoded data to a data sink 272.

UE 120 may evaluate channel conditions and generate feedback information, which may include various types of information as described below. The feedback information and data from a data source 278 may be processed (e.g., coded and symbol mapped) by a TX data processor 280, spatially processed by a TX MIMO processor 282, further processed by modulators 254a through 254R to generate R uplink signals, and transmitted via antennas 252a through 252R. At node B110, the R uplink signals from UE 120 are received by antennas 234a through 234t, processed by demodulators 232a through 232t, spatially processed by an RX MIMO processor 236, and further processed (e.g., symbol demapped and decoded) by an RX data processor 238 to recover the feedback information and data sent by UE 120. A controller/processor 240 may control data transmission to UE 120 based on the feedback information.

Controllers/processors 240 and 290 may direct the operation at node B110 and UE 120, respectively. Memories 242 and 292 may store data and program codes for node B110 and UE 120, respectively. Scheduler 244 may schedule UE 120 and/or other UEs for data transmission on the downlink and/or uplink based on the feedback information received from all UEs.

The node B may simultaneously transmit L data symbols via L layers on each subcarrier in each symbol period, where L ≧ 1. One layer typically corresponds to one spatial dimension of each subcarrier used for transmission. The node B110 may transmit data symbols using various transmission schemes.

In one design, node B110 may process the data symbols for each subcarrier k by:

y (k) ═ d (k) wux (k), formula (1)

Wherein the content of the first and second substances,

x (k) is an L × 1 vector containing L data symbols to be transmitted via L layers on subcarrier k in one symbol period;

u is a L × L layer-to-virtual antenna mapping matrix;

w is a T × L precoding matrix;

d (k) is a cyclic delay matrix of T × T for subcarrier k;

y (k) is a T × 1 vector containing T output symbols for T transmit antennas on subcarrier k in one symbol period.

Equation (1) is for one subcarrier k. The same process may be performed for each subcarrier used for transmission. In the description of the present invention, a matrix may have one or more columns.

The precoding matrix may be used to construct up to T virtual antennas using T physical antennas 234a through 234T. Each virtual antenna is formed by one column in W. The data symbols may be multiplied by one column in W and then transmitted on one virtual antenna and all T physical antennas. W is based on a Fourier matrix or some other matrix. W may be selected from a set of precoding matrices.

A layer-to-virtual antenna mapping matrix U may be used to map the data symbols of the L layers to L virtual antennas selected from the T available virtual antennas. As described below, U may be specified according to the selected layer to virtual antenna mapping. U may also be an identity matrix I with 1 along the diagonal and 0 elsewhere. The same mapping matrix may be used for K subcarriers or different mapping matrices may be used for K subcarriers.

The cyclic delay matrix d (k) may be used to implement cyclic delay diversity, which may provide beamforming gain, frequency selective scheduling gain, and/or diversity gain. D (k) may also be used to implement layer swapping (layer authentication) with some advantages. D (k) may be selected and applied in the manner described below.

In the design shown in equation (1), W is used for precoding before d (k) is used for processing. Thus, cyclic delay diversity is applied on the physical antennas, not on the virtual antennas formed by using the pre-coding matrix W. This design is primarily for zero delay and small delay, but may also be used for large delay.

Fig. 3A shows a block diagram of TX MIMO processor 230a, which is one design of TX MIMO processor 230 of node B110 in fig. 2, for implementing equation (1). Within TX data processor 220, S stream processors 320a through 320S may receive S data streams from data source 212, where S ≧ 1. Each stream processor 320 may encode, interleave, scramble, and symbol map its data stream to obtain data symbols. Each data stream may carry one transport block or packet in each Transmission Time Interval (TTI). Each stream processor 320 may process its transport block to obtain codewords (codewords) and then map the codewords to blocks of modulation symbols. The terms "data stream", "transport block", "packet" and "codeword" may be used interchangeably. Stream processors 320a through 320S may provide S streams of data symbols.

In TX MIMO processor 230a, a layer mapper 332 may map the data symbols for the S data streams onto the selected L layers. The virtual antenna mapper 334 may map the data symbols of the L layers onto subcarriers and virtual antennas for transmission. The mappers 332 and 334 may also be combined into one mapper. Precoder 336 may multiply the mapped symbols for each subcarrier with a precoding matrix W to provide precoded symbols for each subcarrier. The cyclic delay diversity processor 338 may multiply the precoded symbols for each subcarrier with the cyclic delay matrix d (k) to obtain an output symbol for each subcarrier. The cyclic delay diversity processor 338 may provide T output symbol streams to the T modulators 232a through 232T.

Each modulator 232 performs OFDM modulation on a respective output symbol stream. In each modulator 232, K output symbols to be transmitted on a total of K subcarriers in one OFDM symbol period may be subjected to an Inverse Discrete Fourier Transform (IDFT) of K points to obtain a useful portion comprising K time-domain samples. Each time domain sample is a complex value to be transmitted in one sample period. The last C samples of the useful portion may be copied and added to the front of the useful portion to form an OFDM symbol comprising K + C samples. The copied portion is called a cyclic prefix, which is used to prevent inter-symbol interference (ISI) caused by frequency selective fading. Each modulator 232 may further process its sample stream to generate a downlink signal.

Controller/processor 240 may receive feedback information from UE 120 and generate control for stream processor 320 and mappers 332 and 334. Controller/processor 240 also provides a precoding matrix W to a precoder 336 and a cyclic delay matrix d (k) to a processor 338.

In another design, node B110 may process the data symbols for each subcarrier k by:

y (k) ═ wd (k) ux (k), formula (2)

Where d (k) is an L × L cyclic delay matrix for subcarrier k.

In the design shown in equation (2), before precoding with W, processing is performed with d (k). Thus, cyclic delay diversity is applied to virtual antennas rather than physical antennas. This design may be used primarily for large delays, but may also be used for zero delays and small delays.

Fig. 3B shows a block diagram of TX MIMO processor 230B for implementing equation (2), which is another design of TX MIMO processor 230 of node B110 in fig. 2. In TX MIMO processor 230b, a layer mapper 342 may map the data symbols for the S data streams onto the selected L layers. The virtual antenna mapper 344 may map the data symbols of the L layers onto subcarriers and virtual antennas. The cyclic delay diversity processor 346 may multiply the mapped symbols for each subcarrier by a cyclic delay matrix d (k). Precoder 348 multiplies the symbols of each subcarrier from processor 346 with precoding matrix W to obtain output symbols for each subcarrier. Precoder 348 may provide T output symbol streams to T modulators 232a through 232T.

Fig. 4 shows a block diagram of a design for RX MIMO processor 260 and RX data processor 270 for UE 120 in fig. 2. In RX MIMO processor 260, a computation unit 410 may receive MIMO channel estimates h (k) from channel estimator 294 and may receive selected mapping matrix U, precoding matrix W, and cyclic delay matrix d (k). Unit 410 may calculate an effective MIMO channel estimate by:

H_eff(k) h (k) d (k) WU, or formula (3)

H_eff(k) H (k) wd (k) U, formula (4)

Wherein H_eff(k) Is the R x T MIMO channel matrix estimated for subcarrier k.

If the node B performs precoding and cyclic delay diversity processing as shown in equation (1), equation (3) is used. If the node B performs precoding and cyclic delay diversity processing as shown in equation (2), equation (4) is used. D (k) W and wd (k) may be considered as an extended precoding matrix. Then, unit 410 may be based on H_eff(k) And calculates the subcarrier k's Minimum Mean Square Error (MMSE), linear MMSE (LMMSE), zero-forcing (ZF), or some other MIMO detection techniqueThe spatial filter matrix m (k).

MIMO detector 412 may obtain R received symbol streams from R demodulators 254a through 254R. MIMO detector 412 performs MIMO detection on the R received symbol streams using the spatial filter matrix m (k) for each subcarrier k and provides L detected symbol streams for the L selected virtual antennas. Layer demapper 414 demaps the L-way detected symbol stream, which may include inverse swapping (inverse permation), in a manner that is inverse to the mapping operation performed by layer mapper 332 in fig. 3A or mapper 342 in fig. 3B. Demapper 414 may provide an S-way detected symbol stream for the S-way data stream.

RX data processor 270 includes S stream processors 420a through 420S for S data streams. Each stream processor 420 may symbol demap, descramble, deinterleave, and decode its detected symbol stream and provide a decoded data stream.

For the designs shown in equations (1) and (2), various types of precoding matrices may be used. In one design, a set of Q precoding matrices may be defined as follows:

W_i＝Λ_if, wherein i ═ 0., Q-1 formula (5)

Wherein the content of the first and second substances,

f is a Fourier matrix;

Λ_iis the ith phase-shifting matrix;

W_iis the ith precoding matrix.

The precoding matrix W may also be_iIs denoted as P_i。

The elements of the T Fourier matrix F can be expressed as:

wherein, u is 0, 1, v is 0, 1, T-1, formula (6)

Wherein f is_u，vIs the element in the u-th row and v-th column of the fourier matrix.

In one design, the phase-shift matrix Λ_iCan be expressed as:

formula (7)

Wherein λ is_i，vIs the phase for the v-th antenna in the i-th phase shift matrix. Different phases λ may be used_i，vAnd/or by rotating one or more of the basis matrices to define Q different phase-shifting matrices.

For the design shown in equation (5), it is possible to use a fourier matrix F and Q different phase-shifting matrices Λ_iTo define Q different T precoding matrices W_i. For selective virtual antenna transmission, different combinations of columns (or sub-matrices) of Q precoding matrices may be evaluated and will provide the best performing precoding matrix W_iIs used as a precoding matrix W of T L, where typically 1 ≦ L ≦ T. The selection of W is described below.

For a2 x 2MIMO configuration with two transmit antennas and two receive antennas, W_iCan be expressed as:

formula (8)

The precoding matrix W may comprise W_iOne or two columns of.

For a 4 × 4MIMO configuration with four transmit and four receive antennas, W_iCan be expressed as:

formula (9)

The precoding matrix W may comprise W_iOne column, two columns, three columns, or all four columns.

In the embodiments shown in the formulae (5) to (9), W may be_iConsidered as a fourier based frequency invariant precoding matrix. The set of precoding matrices may also be defined in other ways, e.g., W_i＝F^HΛ_iF, wherein "^H"denotes conjugate transpose. Instead of or in addition to the fourier matrix, other unitary or non-unitary matrices may be used to define the precoding matrix groups. The precoding matrix set may also include an identity matrix I for transmitting each layer on one physical antenna.

In one design, a set of cyclic delay matrices (sets) may be defined for a set of delays. For each delay, a zero phase ramp (phase ramp) may be applied to antenna 0, and V-1 non-zero phase ramps may be specified for antennas 1 through V-1. If cyclic delay diversity processing is performed before precoding as shown in fig. 3B, V is L, and V antennas correspond to L selected virtual antennas. If the cyclic delay diversity processing is performed after precoding as shown in fig. 3A, V ═ T, V antennas correspond to T physical antennas. Thus, the dimensionality of the cyclic delay matrix d (k) depends on whether the cyclic delay diversity processing is performed before or after precoding. For clarity, the following description assumes for the most part that the cyclic delay diversity processing is performed before precoding, and that D (k) has dimensions of L.

In one design, the set of cyclic delay matrices is defined as:

wherein M is 0, 1, M-1, formula (10)

Wherein the content of the first and second substances,

0_m，vis the phase ramp for the mth delay, the vth antenna;

D_m(k) is a cyclic delay matrix for the mth delay.

In the design shown in equation (10), the phase ramp for each antenna may be based on an arbitrary cyclic delay value. Cyclic delay matrix D_m(k) May also be represented by Λ_m(k) Or Λ_l(k)。

In another design, the set of cyclic delay matrices is defined as:

formula (11)

Wherein, tau_mIs the mth delay, which is the delay interval between adjacent antennas. In the design shown in equation (11), the cyclic delay value τ for each antenna v_m，vAnd phase ramp theta_m，vCan be expressed as:

τ_m，v＝τ_mv, wherein v ═ 0.., L-1, formula (12)

Wherein, v ═ 0., L-1, formula (13)

Equation (11) is that the cyclic delay values for different antennas of equation (10) have uniform intervals τ_mSpecific examples of (3). Since it can be based on a single τ_mValue to specify all L daysCyclic delay value tau of a line_m.0To tau_m，L-1The uniform delay interval can reduce signaling overhead.

In one design, a set of M — 3 delays may be specified that includes the following delays:

for zero delay, τ₀0, formula (14)

For small delays, τ₁Is 2, formula (15)

For a large delay the delay of the delay is,formula (16)

Small delays may be used to improve beamforming gain and frequency selective scheduling gain, which may be particularly beneficial for low mobility channels, low geometry channels, low rank channels, and so on. Large delays may be used to improve transmit diversity gain, which is suitable for high mobility channels (e.g., for mobile UEs moving at 30 km/hour or faster), high geometry channels, higher rank channels, coarser time-frequency feedback, and so on. In low mobility channels, large delays may provide similar performance as zero delays, which may enhance the robustness of the system when feedback information is interfered. The geometry is related to the signal to noise plus interference ratio (SINR). A low geometry corresponds to a low SINR and a high geometry corresponds to a high SINR. Rank refers to the number of virtual antennas selected for use, which is also referred to as the spatial multiplexing order. In one design, zero delay or small delay may be used for rank-1 (rank-1) transmissions and large delay may be used for rank-2 or higher order transmissions. Cyclic delay diversity processing with large delay can equalize SINRs of L layers for data transmission.

In general, the cyclic delay matrix may be defined for any number of delays or any particular delay. For example, τ may be for small delays_m1 or certainThe cyclic delay matrix may be defined for large delays less than or greater than K/L, and so on. In general, a small delay may be any delay less than the cyclic prefix length, and a large delay may be any delay greater than the cyclic prefix length. For the sake of clarity, the following description is mostly directed to the embodiments shown in the formulae (14) to (16).

When the cyclic delay matrix is applied as shown in equation (2), table 1 provides the cyclic delay matrix for zero delay, small delay, and large delay for different numbers of layers. When the cyclic delay matrix is applied as shown in equation (1), a table of cyclic delay matrices for zero delay, small delay and large delay for different numbers of physical antennas (T) may be generated.

TABLE 1 Cyclic delay matrix

A cyclic delay matrix d (k), which may be a function of subcarrier k, may be applied in the frequency domain. At a delay interval τ of uniform_mIn the case of (d), (k) is used in the frequency domain equivalently to τ in the time domain of the antenna v_mCyclic shift of v samples.

For tau₀For zero delay of 0, the cyclic delay matrix D in the second column of table 1₀(k) Is an identity matrix. Thus, no phase ramp or cyclic delay is applied to each antenna.

For tau₁For a small delay of 2, each cyclic delay matrix D in the third column of table 1₁(k) Providing small phase jumps in the K subcarriers on each antennaLiter (i.e., less linear phase shift). The slope of the phase ramp is different for different antennas, with antenna 0 having no phase ramp and antenna L-1 having the largest phase ramp. Applying phase ramping in the frequency domain is equivalent to cyclically shifting the samples in the useful part of the OFDM symbol in the time domain. For tau₁For 2, the samples in the useful portion may be cyclically shifted by zero samples for virtual antenna 0, two samples for virtual antenna 1, four samples for virtual antenna 2, six samples for virtual antenna 3, and so on.

For tau₂For large delays of K/L, each cyclic delay matrix D₂(k) A large linear phase shift is provided in the K subcarriers on each antenna. Equivalently, the samples in the useful portion may be cyclically shifted by an integer multiple of K/L samples (or an integer multiple of K/L samples in the useful portion) for each antenna.

Fig. 5A shows the use of D in the frequency domain for L-2 antennas₂(k) Corresponding cyclic delay diversity with large delay in the time domain is processed. For antenna 0, the useful part is cyclically shifted by zero samples; for the antenna 1, the useful part is cyclically shifted by half of the useful part.

Fig. 5B shows the use of D in the frequency domain for L-4 antennas₂(k) Corresponding cyclic delay diversity with large delay in the time domain is processed. For antenna 0, the useful part is cyclically shifted by zero samples; for the antenna 1, the useful part is cyclically shifted by a quarter of the useful part; for antenna 2, the useful part is cyclically shifted by half of the useful part; for the antenna 3, the useful part is cyclically shifted by three quarters of the useful part.

Fig. 5A and 5B depict time domain processing for cyclic delay diversity, which is applicable to the case when cyclic delay diversity processing is performed after precoding as shown in fig. 3A. The frequency domain processing for cyclic delay diversity (e.g., as shown in equation (2)) is applicable to the case where cyclic delay diversity processing is performed before precoding as shown in fig. 3B.

It is desirable to apply large delays on the virtual antennas before precoding, for example, as shown in equation (2) and fig. 3B. Precoding gain may be lost if a large delay is applied on the physical antennas after precoding. Zero delay or small delay may be applied on the virtual antennas before precoding (e.g., as shown in equation (2)), or zero delay or small delay may be applied on the physical antennas after precoding (e.g., as shown in equation (1)).

The system may support selective virtual antenna switching (S-VAP), which is a combination of selective virtual antenna and layer switching. Selective virtual antenna refers to selecting the L best virtual antennas from the T available virtual antennas for data transmission. Layer switching refers to mapping data symbols of each layer to L selected virtual antennas in a cyclic manner in all K subcarriers. Some of the advantages that layer switching can provide are for example: (i) performance improvement due to increased spatial diversity per layer; (ii) the feedback overhead due to similar channel conditions observed by all L layers is reduced. Layer switching may be achieved by mapping the data symbols for each layer to the appropriate subcarriers and virtual antennas, as described below. It is also possible to use D for large delays as shown in Table 1₂(k) Processing is performed to implicitly implement the layer exchange.

Fig. 6A shows transmission on four layers via four virtual antennas using layer switching. Four virtual antennas 0 to 3 are available, and all four virtual antennas may be selected. The four layers may be mapped to the four virtual antennas according to a mapping pattern for cyclically mapping the layers to the four virtual antennas over the K subcarriers. Thus, layer 0 is mapped to virtual antenna 0 on subcarriers 0, 4, etc., virtual antenna 1 on subcarriers 1, 5, etc., virtual antenna 2 on subcarriers 2, 6, etc., and virtual antenna 3 on subcarriers 3, 7, etc. Each of the remaining layers is also cyclically mapped into four virtual antennas on the K subcarriers as shown in fig. 6A. Because of the use of layer crossingIn exchange for mapping each layer to all four virtual antennas, each layer can observe the average SINR of the four virtual antennas. D for four layers in Table 1 can be used₂(k) To implement the layer exchange in fig. 6A.

Fig. 6B shows transmission on three layers using layer switching. Four virtual antennas 0 to 3 are available, and a set of three virtual antennas {0, 1, 2}, {0, 1, 3}, {0, 2, 3} or {1, 2, 3} may be selected from among the four virtual antennas to be used. In the example shown in fig. 6B, virtual antennas 0, 1, and 3 are selected. Three layers are mapped to three selected virtual antennas using layer swapping, wherein each layer is mapped into the three selected virtual antennas in a round robin fashion. D in Table 1 for three layers can be used₂(k) To implement the layer exchange in fig. 6B.

Fig. 6C shows transmission on both layers using layer switching. Four virtual antennas 0 to 3 are available, and a pair of virtual antennas {0, 1}, {0, 2}, {0, 3}, {1, 2}, {1, 3} or {2, 3} may be selected from among the four virtual antennas to be used. In the example shown in fig. 6C, virtual antennas 1 and 3 are selected. Two layers are mapped to two selected virtual antennas using layer switching, wherein each layer is mapped into the two selected virtual antennas in a round-robin fashion. D in Table 1 for the two layers can be used₂(k) To implement the layer exchange in fig. 6C.

For simplicity, fig. 6A to 6C show the mapping of layers on all K subcarriers. In general, layers may be mapped on subcarriers used for transmission, which are a subset of all K subcarriers.

Different delays are applicable to different channel conditions. Various schemes may be used to select the appropriate delay to use.

In a first scheme, the node B may determine and translate the delay long term, semi-statically. In one design, referred to as cell-based cyclic delay diversity, the node B may perform semi-static switching for all UEs in a cell and apply a common delay to all UEs. The node B may select a delay that provides good performance for all UEs and broadcast the delay to the UEs. In another design, referred to as UE-based cyclic delay diversity, the node B may perform semi-static switching independently for each UE and apply different delays to different UEs. The node B may select a delay that provides good performance for each UE and send the delay to the UE. For both designs, the node B may select precoding and cyclic delay diversity structures, e.g., equation (1) for zero and small delays and equation (2) for large delays.

The node B may select the delay based on various criteria. In one design, the node B may select a large delay when the feedback information from the UE is deemed unreliable. A large delay may maximize transmit diversity (independent of the number of layers) and may reduce the number of precoding matrices and/or CQI feedback. The node B may select a small delay when frequency selective beamforming gain is required.

In one design, referred to as rank-specific cyclic delay diversity, the node B may select the delay based on the rank of the transmission. In one design, a set of delay combinations may be specified, where each combination includes one delay for each rank. A delay combination may be selected and sent to its active UEs.

In one design of a2 x 2MIMO configuration, a set of delay combinations includes the following combinations:

(0, 0), (0, K/2), (K/2, 0) and (K/2 ),

where combining (a, b) means that delay a is for rank 1 and delay b is for rank 2.

For the combination (0, 0), the node B applies no delay for rank 1 and rank 2. For the combination (0, K/2), the node B applies no delay for rank 1 and a large delay for rank 2. This combination enables layer switching when rank 2 is selected. For the combination (K/2, 0), the node B applies a large delay for rank 1 and no delay for rank 2. For the combination (K/2 ), the node B applies a large delay for both rank 1 and rank 2.

In one design of a 4 x 4MIMO configuration, a set of delay combinations includes the following combinations:

(0, 0, 0, 0), (0, 0, 0, K/4), (0, 0, K/3, 0). (K/2, K/3, K/4), where the combination (a, b, c, d) means delay a for rank 1, delay b for rank 2, delay c for rank 3 and delay d for rank 4.

For the combination (0, 0, 0, 0), the node B applies no delay to all four ranks 1 to 4. For the combination (0, 0, 0, K/4), the node B applies no delay for ranks 1, 2, and 3, and applies a large delay for rank 4. This combination achieves layer switching when rank 4 is selected. For the combination (0, 0, K/3, 0), the node B applies no delay for ranks 1, 2, and 4 and applies a large delay for rank 3. This combination achieves layer switching when rank 3 is selected. Other combinations may also be explained in a similar manner.

In a second scheme, the UE may select a delay and send the selected delay to the node B. The UE may evaluate different combinations of precoding matrix and delay and select the combination of precoding matrix and delay that provides the best performance. The UE may send the precoding matrix and the delay in the combination to the node B for data transmission to the UE. The UE may also select precoding and cyclic delay diversity structures, e.g., equation (1) for zero and small delays and equation (2) for large delays.

Fig. 7 shows a block diagram of a design of an evaluation unit 700 for selecting a precoding matrix and a delay according to a capacity and (sum-capacity) metric. Unit 700 may be implemented by processor 290 of UE 120 or some other processor in fig. 2. In evaluation unit 700, controller 710 may traverse a set of precoding matrices and a set of delays and provide different combinations of precoding matrices and delays for evaluation. For example, controller 710 may traverse the set of precoding moments for a first time for zero delayThe array may be traversed the set of precoding matrices for a small delay a second time, and then for a large delay a third time. The controller 710 may provide a combined delay index m and precoding matrix index i to be evaluated. Delay codebook 712 may store a set of cyclic delay matrices, receive a delay index m, and provide a corresponding cyclic delay matrix D_m(k) In that respect The precoding codebook 714 may store a set of precoding matrices, receive a precoding matrix index i, and provide a corresponding precoding matrix W_i。

The spatial mapper 720 may receive the MIMO channel estimates H (k), the precoding matrix W_iAnd a cyclic delay matrix D_m(k) And calculating an effective MIMO channel estimate H_eff(k) For example, as shown in formula (3) or formula (4). H_eff(k) T columns comprising T antennas for subcarrier k. Different hypotheses may be evaluated, where each hypothesis corresponds to a different combination of virtual antennas that may be used for data transmission (i.e., H)_eff(k) Different subsets of columns). For the case of T-4, a total of 15 hypotheses may be evaluated: four hypotheses for four single virtual antennas, six hypotheses for six possible virtual antenna pairs, four hypotheses for four possible sets of three virtual antennas, and one hypothesis for all four virtual antennas. Each hypothesis s and its respective precoding sub-matrix W_i，sCorrelating, wherein the sub-matrix W is pre-encoded_i，sComprising W_iUp to T specific columns.

The SINR estimator 722 may be based on H_eff(k) And MIMO detection techniques used by the UE to determine a set of SINRs for each hypothesis. For rank 1, the SINR estimator 722 may be based on H_eff(k) And estimating the SINR of each virtual antenna, wherein all transmit power is allocated to one virtual antenna. For rank 2, the SINR estimator 722 may be based on H_eff(k) To estimate the SINR of each possible virtual antenna pair, wherein the transmit power is (e.g., evenly) allocated to both virtual antennas. For rank 3, the SINR estimator 722 may be based on H_eff(k) Three columns in a corresponding group, where transmit power is allocated to three virtual antennas, to estimate the SINR for each possible set of three virtual antennas. For rank 4, the SINR estimator 722 may be based on H_eff(k) And the SINR of all four virtual antennas to which the transmission power is allocated. For the case of T-4, the SINR estimator 722 may provide 15 sets of SINRs for 15 hypotheses: for rank 1, four sets of single SINRs for four different virtual antennas; for rank 2, six sets of two SINRs for six different virtual antenna pairs; for rank 3, four sets of three SINRs for four possible sets of three virtual antennas; for rank 4, a set of four SINRs for all four virtual antennas. The number of hypotheses may be different for rank dependent precoding matrices.

The capacity mapper 724 may map SINRs to capacity according to an unrestricted capacity function or a restricted capacity function. Then, for each hypothesis, capacity mapper 724 may accumulate the capacities of all K subcarriers for all virtual antennas to obtain a capacity sum for that hypothesis. The adjusting unit 726 may adjust the sum of the capacities of each hypothesis according to the penalty factor for the rank of the hypothesis to obtain the total capacity of the hypothesis. A larger penalty factor may be used for higher ranks to handle the possible higher implementation loss (penalty) for higher ranks.

Rank selector and CQI generator 728 may receive the total capacity for all hypotheses and select the hypothesis with the largest total capacity. Unit 728 may store information regarding the selected hypotheses.

The same process is repeated for each possible combination of precoding matrix and delay. As long as the best assumed total capacity for a given combination is greater than the saved total capacity, unit 728 saves the greater total capacity and related information. After evaluating all combinations of precoding matrices and delays, unit 728 may combine the best combined precoding matrix W_i，sAnd the delay is taken as the selected precoding matrix W and the selected delay. The precoding matrix W comprises the precoding matrix W in the optimal combination_iAnd represents the best assumed rank L. The L columns of W are for the L selected virtual antennas. Rank selection may also be made in other ways. For example, the precoding matrix W may correspond to the best rank-dependent T × L available precoding matrix in the precoding codebook.

Unit 728 may also determine S SINRs for S data streams to be transmitted on the L selected virtual antennas, where S ≧ 1. The SINR of the data streams may be determined based on the SINR of the subcarriers and the virtual antenna for each data stream. Unit 728 may then determine S Channel Quality Indicator (CQI) values based on the SINR of the S data streams. The CQI value may include an average SINR, a Modulation and Coding Scheme (MCS), a packet format, a transmission format, a rate, and/or some other information for indicating signal quality or transmission capacity. Unit 728 may provide S CQI values for the S data streams. Alternatively, unit 728 may provide a base CQI value and a differential CQI value. The base CQI value represents the SINR of the first decoded data stream and the differential CQI value represents the difference between the SINRs of the two data streams.

Fig. 7 shows a design for selecting a precoding matrix W and delay based on capacity and metric. The precoding matrix and delay may also be selected based on criteria such as feedback reliability (e.g., considering latency, error, and possibly UE speed), and/or other factors.

In one design, the UE may send the precoding matrix W, the delay, and the CQI value to the node B at each reporting interval. In another design, the UE may send the precoding matrix W and CQI values at each reporting interval and send the delay at a lower rate. The delay is slowly varying in most channel environments. Transmitting the delay at a lower frequency may reduce feedback overhead while only slightly impacting performance.

The node B may select a delay and transmit the selected delay to the UE. In this case, the UE may evaluate the precoding matrix set only in conjunction with the selected delay. To reduce the computational complexity and feedback overhead of the UE, the node B may also define different delay groups for each rank. For example, for rank 1, only zero delay is allowed, for rank 2, both zero and large delays are allowed, and so on. The UE may evaluate the set of precoding matrices in conjunction with each allowed delay for each rank.

The node B may receive the precoding matrix W and the delay reported by the UE. The node B may use the reported precoding matrix and delay for data transmission to the UE. Alternatively, the node B may select a different precoding matrix and/or a different delay than reported by the UE. The node B may use the reported or selected precoding matrix and delay for data transmission to the UE. The node B may also receive CQI values from the UE and process data according to the received CQI values. The node B may transmit data along with control information indicating the selected precoding matrix, the selected delay, the MCS for each data stream, time-frequency resources for data transmission, and so on.

The precoding and cyclic delay diversity processing described herein may be performed for data channels, control channels, and so on. The control channel may be used to send control information/signaling to different UEs located in different locations. A large delay may be used for the control channel to maximize transmit diversity.

For the data channel, the designs shown in equations (1) and (2) and fig. 3A and 3B may support various MIMO modes such as closed-loop spatial multiplexing (for rank 2 or higher), beamforming (for rank 1), open-loop spatial multiplexing (for rank 2 or higher), open-loop transmit diversity (for rank 1), and so on. Precoding and cyclic delay diversity processing may be performed in different ways for different modes. In one design, one or more of the following modes may be supported:

open-loop mode with no Precoding Matrix Information (PMI) available:

1) and the high-mobility UE: a large delay and a fixed precoding matrix are used.

Closed loop mode with available precoding matrix information:

1) low mobility UEs with a lot of feedback: a small delay and a reported precoding matrix are used,

2) low mobility to high mobility UEs with reduced amount of feedback: a large delay and reported precoding matrix is used.

Closed loop mode with available precoding matrix and delay information:

1) the reported delay and the reported precoding matrix are used. The above-described modes can maximize transmit diversity and/or beamforming gain according to a channel environment.

Because the large delay is greater than the cyclic prefix length, the pilot may be inserted after precoding (e.g., at the input of modulator 232 in fig. 3A and 3B or at the input of precoder 348 in fig. 3B). This may ensure that the performance of pilot-based channel estimation is not degraded by the use of large delays for cyclic delay diversity processing. The UE may derive a MIMO channel estimate from the pilot. If pilots are inserted at the input of modulator 232, the UE may apply the precoding matrix and the cyclic delay matrix to obtain an efficient MIMO channel estimate. If pilots are inserted at the input of precoder 348 of fig. 3B, the UE may apply a cyclic delay matrix to obtain an efficient MIMO channel estimate. In any case, the UE may use the valid MIMO channel estimates for MIMO detection.

Fig. 8 shows a design of a process 800 for exchanging data in a wireless communication system. Process 800 may be performed by a UE, a node B, or some other entity. A delay may be selected from a plurality of delays (block 812). The selected delay is transmitted from the first entity to the second entity (block 814). Data is exchanged with (e.g., transmitted to or received from) the second entity using cyclic delay diversity based on the selected delay (block 816).

The plurality of delays may include a zero delay, a small delay less than the cyclic prefix length, a large delay greater than the cyclic prefix length, other delays, or a combination thereof. The large delay may correspond to a cyclic delay of K/L, where K is the number of samples of the useful portion of the OFDM symbol and L is the number of antennas used for cyclic delay diversity. The delay may be selected based on data performance, rank, geometry, mobility, channel type, feedback reliability, etc. For example, zero delay may be selected for rank 1, low geometry, low mobility, data channel, and so on. Large delays may be selected for rank 2, high geometry, high mobility, control channels, and so on.

Fig. 9 shows a design of a process 900 performed by a node B. Process 900 is one design of process 800, wherein the first entity is a node B and the second entity is a UE. In one design of blocks 812 and 814 of fig. 8, the node B may select a delay dedicated to the UE (block 912) and send the selected delay to the UE (block 914). In another design of blocks 812 and 814, the node B may select delays for a group of UEs served by the node B and broadcast the selected delays to the group of UEs. In one design of block 816, which may be used for no delay or small delay, for example, as shown in equation (1) and fig. 3A, the node B performs precoding using a precoding matrix (block 916), and then performs cyclic delay diversity processing based on the selected delay (block 918). In another design of block 816, which may be used for large delays, for example, as shown in equation (2) and fig. 3B, the node B may perform cyclic delay diversity processing based on the selected delay (block 926) and then perform precoding using a precoding matrix (block 928).

Fig. 10 shows a design of a process 1000 performed by a UE. Process 1000 is another design of process 800, wherein the first entity is a UE and the second entity is a node B. In one design of block 812 of fig. 8, the UE may evaluate multiple delays based on at least one metric (block 1010) and select the delay with the best at least one metric (block 1012). The UE may evaluate each delay according to capacity and metric and select the delay with the largest capacity and metric. In another design of block 812, the UE may evaluate multiple precoding matrices in combination with multiple delays based on at least one metric. The UE may determine the combination of precoding matrix and delay with the best at least one metric and select the precoding matrix and delay in that combination. For both designs, the plurality of delays may include a plurality of delay sets (delay sets) for a plurality of ranks. Each delay group includes at least one delay that is available for the corresponding rank and is selected from all supported delays. The UE may evaluate only at least one delay in the delay group for each rank.

The UE may send the selected delay to the node B (block 1014). In one design of block 816 of fig. 8, the UE may receive the data transmission sent by the node B using cyclic delay diversity based on the selected delay (block 1016). The UE may derive an effective MIMO channel estimate based on the selected delay, the selected precoding matrix, and so on (block 1018). The UE may then perform MIMO detection for the received data transmission based on the valid MIMO channel estimates (block 1020).

For data transmission on the downlink, the node B may perform the process 900 in fig. 9 and the UE may perform the process 1000 in fig. 10. For data transmission on the uplink, the UE may perform process 900 in fig. 9 and the node B may perform process 1000 in fig. 10.

Fig. 11 illustrates an apparatus 1100 for exchanging data in a wireless communication system. The apparatus 1100 comprises: means for selecting a delay from a plurality of delays (block 1112); means for sending the selected delay from the first entity to the second entity (block 1114); means for exchanging data with the second entity using cyclic delay diversity based on the selected delay (block 1116). The modules in fig. 11 may comprise processors, electronics devices, hardware devices, electronics components, logical circuits, memories, etc., or any combination thereof.

Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to carry or store desired program code means in the form of instructions or data structures and which can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Further, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks (disks) usually reproduce data magnetically, while discs (discs) reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (33)

1. An apparatus for wireless communication, comprising:

at least one processor configured to:

selecting a delay from a plurality of delays for cyclic delay diversity for multiple-input-multiple-output (MIMO) transmission;

transmitting the selected delay from the first entity to the second entity;

exchanging data with the second entity using cyclic delay diversity based on the selected delay, wherein a plurality of symbol streams carrying different information are generated based on the data and delayed by different amounts for cyclic delay diversity;

a memory coupled with the at least one processor.

2. The apparatus of claim 1, wherein the first entity is a User Equipment (UE) and the second entity is a node B.

3. The apparatus of claim 1, wherein the at least one processor is configured to:

evaluating the plurality of delays according to at least one metric;

the delay with the best at least one metric is selected.

4. The apparatus of claim 1, wherein the at least one processor is configured to:

evaluating each of the plurality of delays according to a capacity and a metric;

the delay with the largest capacity and metric is selected.

5. The apparatus of claim 1, wherein the plurality of delays comprises a plurality of delay groups for a plurality of ranks, each rank corresponding to a different number of antennas, and each group comprising at least one delay available for the corresponding rank.

6. The apparatus of claim 1, wherein the at least one processor is configured to:

evaluating a plurality of precoding matrices in conjunction with the plurality of delays according to at least one metric;

determining a combination of precoding matrix and delay having the best at least one metric;

selecting a precoding matrix and a delay in the combination having the best at least one metric.

7. The apparatus of claim 2, wherein the at least one processor is configured to:

transmitting the selected delay from the UE to the node B;

receiving a data transmission sent by the node B using cyclic delay diversity based on the selected delay.

8. The apparatus of claim 1, wherein the at least one processor is configured to:

deriving an effective MIMO channel estimate from a cyclic delay matrix for the selected delay;

performing MIMO detection on the received data transmission according to the effective MIMO channel estimate.

9. The apparatus of claim 1, wherein the first entity is a node B and the second entity is a User Equipment (UE).

10. The apparatus of claim 9, wherein the at least one processor is configured to:

selecting a delay dedicated to the UE;

transmitting the selected delay to the UE.

11. The apparatus of claim 9, wherein the at least one processor is configured to:

selecting a delay for a set of UEs served by the node B;

transmitting the selected delay to the group of UEs.

12. The apparatus of claim 1, wherein the at least one processor is configured to:

performing cyclic delay diversity processing according to the selected delay;

performing precoding using a precoding matrix after the cyclic delay diversity processing.

13. The apparatus of claim 1, wherein the at least one processor is configured to:

performing precoding using a precoding matrix;

after the pre-coding, a cyclic delay diversity process is performed based on the selected delay.

14. The apparatus of claim 1, wherein the plurality of delays comprises a zero delay and a large delay greater than a cyclic prefix length.

15. The apparatus of claim 14, wherein the large delay corresponds to a cyclic delay of K/L, where K is a number of samples in a useful portion of an Orthogonal Frequency Division Multiplexing (OFDM) symbol and L is a number of antennas used for cyclic delay diversity.

16. The apparatus of claim 14, wherein the plurality of delays further comprises a small delay that is less than the cyclic prefix length.

17. The apparatus of claim 1, wherein the at least one processor is configured to:

the delay is selected according to data performance, or rank corresponding to number of antennas, or geometry corresponding to signal to noise plus interference ratio (SINR), or mobility, or channel type, or feedback reliability, or a combination thereof.

18. The apparatus of claim 16, wherein the at least one processor is configured to:

selecting the zero delay or the small delay for rank 1 corresponding to one antenna;

the large delay is selected for rank 2 corresponding to two antennas.

19. The apparatus of claim 16, wherein the at least one processor is configured to:

selecting the zero delay or the small delay for a low geometry corresponding to a low signal-to-noise-plus-interference ratio (SINR);

the large delay is selected for high geometry conditions corresponding to high SINR.

20. The apparatus of claim 16, wherein the at least one processor is configured to:

selecting the zero delay or the small delay for a data channel;

the large delay is selected for the control channel.

21. The apparatus of claim 1, wherein the first and second electrodes are disposed on opposite sides of the housing,

wherein the plurality of delays comprises a delay for each of a plurality of ranks, each rank corresponding to a different number of antennas;

wherein the at least one processor is configured to:

the delay is selected according to the rank of transmission.

22. A method for wireless communication, comprising:

selecting a delay from a plurality of delays for cyclic delay diversity for multiple-input-multiple-output (MIMO) transmission;

transmitting the selected delay from the first entity to the second entity;

exchanging data with the second entity using cyclic delay diversity based on the selected delay, wherein a plurality of symbol streams carrying different information are generated based on the data and delayed by different amounts for cyclic delay diversity.

23. The method of claim 22, wherein the selecting a delay comprises:

evaluating the plurality of delays according to at least one metric;

the delay with the best at least one metric is selected.

24. The method of claim 22, wherein the selecting a delay comprises:

evaluating a plurality of precoding matrices in conjunction with the plurality of delays according to at least one metric;

determining a combination of precoding matrix and delay having the best at least one metric;

selecting a precoding matrix and a delay in the combination having the best at least one metric.

25. The method of claim 22, wherein the exchanging data with the second entity comprises:

receiving a data transmission sent by the second entity using cyclic delay diversity based on the selected delay;

deriving an effective MIMO channel estimate from a cyclic delay matrix for the selected delay;

performing MIMO detection on the received data transmission according to the effective MIMO channel estimate.

26. The method of claim 22, wherein the exchanging data with the second entity comprises:

performing cyclic delay diversity processing according to the selected delay;

performing precoding using a precoding matrix after the cyclic delay diversity processing.

27. The method of claim 22, wherein the exchanging data with the second entity comprises:

performing precoding using a precoding matrix;

after the pre-coding, a cyclic delay diversity process is performed based on the selected delay.

28. An apparatus for wireless communication, comprising:

a delay selection module to select a delay from a plurality of delays for cyclic delay diversity for multiple-input-multiple-output (MIMO) transmission;

a delay transmission module for transmitting the selected delay from the first entity to the second entity;

a module for exchanging data with a second entity using cyclic delay diversity based on the selected delay, wherein a plurality of symbol streams carrying different information are generated based on the data and delayed by different amounts for cyclic delay diversity.

29. The apparatus of claim 28, wherein the delay selection module comprises:

means for evaluating the plurality of delays according to at least one metric;

means for selecting the delay having the best at least one metric.

30. The apparatus of claim 28, wherein the delay selection module comprises:

means for evaluating a plurality of precoding matrices in combination with the plurality of delays according to at least one metric;

means for determining a combination of precoding matrix and delay having the best at least one metric;

means for selecting a precoding matrix and delay in the combination having the best at least one metric.

31. The apparatus of claim 28, wherein the means for exchanging data with a second entity comprises:

means for receiving a data transmission sent by the second entity using cyclic delay diversity based on the selected delay;

means for deriving an effective MIMO channel estimate from a cyclic delay matrix for the selected delay;

means for performing MIMO detection on the received data transmission based on the effective MIMO channel estimate.

32. The apparatus of claim 28, wherein the means for exchanging data with a second entity comprises:

means for performing cyclic delay diversity processing based on the selected delay;

means for performing precoding using a precoding matrix after the cyclic delay diversity processing.

33. The apparatus of claim 28, wherein the means for exchanging data with a second entity comprises:

means for performing precoding using a precoding matrix;

means for performing cyclic delay diversity processing according to the selected delay after the encoding.