HK1137863B - Multi-function passive frequency mixer - Google Patents

Description

Multifunctional passive mixer

Technical Field

The present invention relates generally to radio frequency telecommunications and, in particular, to passive radio frequency mixers (passive mixers).

Background

A radio transceiver typically includes a mixer that converts a signal from baseband to a Radio Frequency (RF) band or vice versa. The mixers up-convert the transmit signal from baseband to RF band in transmission and/or down-convert the receive signal from RF band to baseband in reception. Optionally, in some implementations, the received RF signal may be converted to an intermediate frequency band.

The mixer has as input signals a signal to be mixed (i.e. a signal to be up-or down-converted) and one or more local oscillator signals, and it produces an output signal at a frequency which is a linear combination of the frequencies of the input signals. Usually, the local oscillator signals input to the mixers are the same signal but with different phase shifts.

The mixer may be a passive mixer or an active mixer. Passive mixers have no energy source but an input signal and a local oscillator signal. Accordingly, the output power may not be greater than the input power. Active mixers, on the other hand, require an additional energy source in order to amplify the input signal. Accordingly, the output power may be higher than the input power.

Active mixers offer advantages over passive mixers in that: the active mixer amplifies the mixed signal. As a result, the power of the resulting signal is higher when an active mixer is utilized. On the other hand, the amplification also causes an increase in noise power. In addition, the linearity characteristics of active mixers are generally quite poor and active mixers consume power, which may be a limited resource in some implementations.

In contrast, passive mixers generally have good linearity and noise characteristics, and they do not consume power. The only disadvantages of passive mixers are: they attenuate the mixed signal rather than amplify it. The level of attenuation depends on the implementation.

Fig. 1 shows a prior art receiver architecture for converting a received radio signal directly to baseband. The receiver comprises a first amplifier 2 before mixers 4 and 5. The amplifier 2 is typically a low noise amplifier. Band pass filters 1 and 3 have been provided before and after the amplifier 2 to remove undesired frequency components. Mixers 4 and 5 mix in-phase (I) and quadrature (Q) components of the received radio signal with local oscillation signals LO _0, LO _90, LO _180, and LO _270 to baseband. The numbers refer to the phase shifts of the corresponding local oscillator signals. After down-mixing (downmixing), the baseband amplifiers 6 and 7 amplify the I and Q components, respectively, which are down-mixed, and the low-pass filters 8 and 9 remove harmonic signal components resulting in the down-mixing. Amplifiers 10 and 11 further amplify the low pass filtered signals before analog to digital (a/D) conversion in a/D-converter 12.

In general, the noise coefficients (noise configurations) of the baseband amplifiers 6 and 7 are relatively poor, especially due to flicker noise (also referred to as 1/f noise). Therefore, the signal levels obtained from the mixers 4 and 5 need to be higher than the noise levels of the baseband amplifiers 6 and 7. If the mixers 6 and 7 are passive mixers, the overall noise figure of the receiver can be improved only in the first amplifier 2 before the mixers 4 and 5. In this case, the level of the output signal of the amplifier 2 may rise so high that good linearity characteristics of the passive mixer are wasted. As a result, the advantages of passive mixers over active mixers are also wasted.

Another problem associated with passive mixers is: designing a low pass filter that follows a passive mixer can be a difficult task. The low pass filter should be located before the first baseband amplifier in order to prevent cross modulation and intermodulation caused by undesired strong signal components. In CMOS implementations, it is extremely difficult to accurately define the corner frequency (corner frequency) of the filter, since the corner frequency is affected by the output impedance of the mixer, the pulse ratio of the local oscillator, and the tolerance of the capacitance values of the mixer components. Thus, the filter is typically arranged to follow the first baseband amplifier, which results in performance close to that of an active mixer, and therefore, the advantages obtained by using a passive mixer are wasted.

Disclosure of Invention

It is an object of the present invention to overcome the limitations and problems associated with conventional mixers by providing an improved mixer, an improved mixing method and an improved radio transceiver.

According to another aspect of the present invention, there is provided an apparatus comprising: an input interface including a balanced input port to receive a balanced input signal and an oscillating signal input port to receive first and second oscillating signals; first, second and third capacitors; a first set of switches responsive to a first oscillating signal and arranged to connect first and second capacitances between first and second ones of said balanced input ports in response to said first oscillating signal; a second set of switches responsive to a second oscillating signal and arranged to connect the first capacitance between the first input port and the third capacitance and the second capacitance between the second input port and the third capacitance in response to the second oscillating signal; and an output port connected to a terminal of the third capacitance.

According to another aspect of the invention, a mixing apparatus is provided comprising the above-described apparatus.

According to another aspect of the invention, there is provided a radio apparatus comprising the apparatus described above.

According to another aspect of the present invention, there is provided a method comprising: receiving an input signal through first and second of the balanced input ports and first and second oscillating signals through the oscillating signal input port; connecting first and second capacitances between first and second ones of the balanced input ports in a first phase responsive to a first oscillating signal; in a second phase in response to a second oscillating signal, connecting the first capacitance between the first input port and a third capacitance and connecting the second capacitance between the second input port and the third capacitance; and obtaining the voltage on the third capacitor as an output voltage.

According to another aspect of the present invention, there is provided an apparatus comprising: an input device comprising first and second input ports of a balanced input port receiving a balanced input signal and an oscillating signal input device receiving first and second oscillating signals; first, second and third capacitive means; means for connecting the first and second capacitive means between first and second ones of the balanced input ports in a first phase responsive to the first oscillating signal; means for connecting, in a second phase responsive to the second oscillating signal, a first capacitance between the first input port and a third capacitance and a second capacitance between the second input port and a third capacitance; and means for obtaining the voltage on the third capacitance as an output voltage.

Drawings

The invention will be described in more detail below with reference to embodiments and the accompanying drawings, in which:

fig. 1 shows the structure of a conventional radio receiver including a conventional mixer;

FIG. 2 shows a mixer according to an embodiment of the invention;

FIG. 3A shows an equivalent circuit in a first stage of operation of the passive mixer shown in FIG. 2;

FIG. 3B shows an equivalent circuit in a second stage of operation of the passive mixer shown in FIG. 2;

FIG. 4 shows signals input to the passive mixer shown in FIG. 2 and voltage levels in components of the passive mixer;

figure 5A shows a filter structure implemented according to the switched capacitor filter principle;

FIG. 5B shows an equivalent circuit for the filter structure shown in FIG. 5A;

FIG. 6 illustrates a mixer with automatic gain control features according to an embodiment of the present invention;

FIG. 7A illustrates a mixer with automatic gain control features according to another embodiment of the present invention;

FIG. 7B illustrates a mixer with automatic gain control features according to yet another embodiment of the present invention;

FIG. 8 illustrates features of a mixer according to an embodiment of the invention;

FIG. 9 shows a mixer with an adjustable low-pass corner frequency according to an embodiment of the invention;

fig. 10 shows a detailed structure of a mixer according to an embodiment of the present invention;

fig. 11 shows a receiver structure of a radio transceiver according to an embodiment of the present invention;

fig. 12 shows a receiver structure of a radio transceiver according to another embodiment of the present invention; and

fig. 13 shows a receiver structure of a radio transceiver according to a further embodiment of the present invention.

Detailed Description

Referring to fig. 2, a mixer according to an embodiment of the invention is studied. In addition to the mixing function, the mixer also functions as a voltage multiplier and a low pass filter. The mixer according to an embodiment of the invention is a passive mixer, i.e. it does not introduce additional power to the input signal. However, with appropriate use of passive components, the amplitude of the input signal may be multiplied. That is, by utilizing the same passive components, the input signal may be mixed (down/up converted), amplified, and low pass filtered. The embodiment of the invention described with reference to fig. 2 triples the input voltage approximately.

The mixer comprises an input interface comprising a balanced input port for receiving a balanced input signal to be amplified. The balanced input port includes first and second input ports IN1 and IN2 for receiving balanced input signals. As is known in the art, a balanced input signal comprises two components with opposite phases. Referring to fig. 2, the signal input to the second input port IN2 is accordingly an inverted version (inverted version) of the signal input to the first input port IN 1.

The input interface further comprises an oscillation signal input port for receiving first and second oscillation signals LO _0 and LO _ 180. The local oscillator may provide a local oscillation signal that may be modified into first and second oscillation signals LO _0 and LO _180 that are input to the oscillation signal input port of the amplifier. The oscillation signals LO _0 and LO _180 may be modified to have substantially the same frequency and opposite phases. That is, if the phase of the first local oscillation signal LO _0 is zero degrees, the phase of the second local oscillation signal LO _180 is 180 degrees.

The mixer further comprises a first and a second output port OUT1 and OUT2 that balance the output ports. Accordingly, the mixer outputs balanced output signals through the output ports OUT1 and OUT2 of the balanced output port.

The mixer according to the embodiment of the present invention includes a first capacitor C41, a second capacitor C42, and a third capacitor C43. The first capacitor C41 has its first terminal connected to the first input port IN1 of the balanced input port. Correspondingly, the second capacitor C42 has its first terminal connected to the second input port IN2 of the balanced input port. The third capacitor C43 has its first terminal connected to the first output port OUT1 of the balanced output port and its second terminal connected to the second output port OUT2 of the balanced output port.

In addition, the mixer includes a first set of switches responsive to the first oscillation signal LO _0 and a second set of switches responsive to the second oscillation signal LO _ 180. Accordingly, each switch of the first set of switches receives the first oscillation signal LO _0 as a control signal that controls the operation of the switches. Correspondingly, each switch of the second set of switches receives the second oscillator signal LO _180 as a control signal controlling the operation of these switches. The switches may be configured to be closed when the level of the control oscillation signal is high and to be opened when the level of the control oscillation signal is low.

In the embodiment shown in fig. 2, the first set of switches comprises a first switch 33 and a second switch 34. The first switch 33 may be disposed between the second terminal of the first capacitance C41 and the second input port IN2, and the second switch 34 may be disposed between the first input port IN1 and the second terminal of the second capacitance C42. The second set of switches comprises a third switch 31 and a fourth switch 32. The third switch 31 may be disposed between the second terminal of the first capacitance C41 and the first terminal of the third capacitance C43. The fourth switch 32 may be disposed between the second terminal of the second capacitance C42 and the second terminal of the third capacitance C43.

The operation of the mixer according to an embodiment of the present invention may be divided into two phases within one cycle of the oscillation signals LO _0 and LO _ 180. The first phase comprises a first half-cycle of the period of the oscillating signal and the second phase comprises a second half-cycle following the first half-cycle. Since the oscillation signals LO _0 and LO _180 have opposite phases, the level of the first oscillation signal LO _0 is high in the first phase, and the level of the second oscillation signal LO _180 is kept low. In the second stage, the level of the second oscillation signal LO _180 is high, and the level of the first oscillation signal LO _0 is kept low.

Accordingly, the first set of switches (switches 33 and 34) is closed in the first phase, while the second set of switches (switches 31 and 32) is opened. Thus, the switches 31 to 34 form the circuit shown in fig. 3A. That is, the first and second capacitors C41 and C42 are connected IN parallel between the first and second input ports IN1 and IN 2. IN more detail, first ends of the first and second capacitors C41 and C42 remain connected to the first and second input ports IN1 and IN2, respectively. The first switch 33 connects the second terminal of the first capacitor C41 to the second input port IN2, and the second switch 34 connects the second terminal of the second capacitor C42 to the first input port IN 1.

IN the first phase, the voltages on the input ports IN1 and IN2 are charged to the first and second capacitors C41 and C42. The voltages on the first and second input ports IN1 and IN2 are shown IN fig. 4. Referring to fig. 2 and 4, a voltage V1A represents a voltage between the first input port IN1 and a ground level, and a voltage V1B represents a voltage between the second input port IN2 and a ground level. The voltage V1 represents the voltage between the first and second input ports IN1 and IN2, the voltage V2 represents the voltage across the first capacitor C41, and the voltage V3 represents the voltage across the second capacitor C42. Also shown IN fig. 4 are signals input to the input ports IN1 and IN 2. Accordingly, the first and second capacitors C41 and C42 are both charged at the voltage V1 during the first phase. In other words, V2 and V3 are equal to V1.

In the second phase, the first set of switches (switches 33 and 34) is opened and the second set of switches (switches 31 and 32) is closed. Thus, the switches 31 to 34 form the circuit shown in fig. 3B. That is, the first and second capacitors C41 and C42 are now connected IN series with the third capacitor C43 between the input ports IN1 and IN 2. In more detail, the third switch 31 connects the second terminal of the first capacitor C41 to the first terminal of the third capacitor C43, and the fourth switch 32 connects the second terminal of the second capacitor C42 to the second terminal of the third capacitor C43.

Thus, the first and second capacitors C41 and C42 release their charge to the third capacitor C43 in the second phase. IN addition to the voltages charged to the first and second capacitors C41 and C42 IN the first phase, the third capacitor C43 is charged IN the second phase with the current voltages on the input ports IN1 and IN2, plus the voltages IN the first and second capacitors C41 and C42. Referring to fig. 4, a voltage V2 represents a voltage charged to the first capacitor C41 immediately before the second set of switches is closed, and a voltage V3 represents a voltage charged to the second capacitor C42 immediately before the second set of switches is closed. Accordingly, the sum of the voltages V2 and V3 is charged to the third capacitance C43 together with the present voltage V1 'between the input ports IN1 and IN2 of the balanced input port, i.e., the voltage V4 on the third capacitance C43 becomes V4 ═ V1' + V2+ V3. The first and second output ports OUT1 and OUT2 of the balanced output port may be connected to first and second terminals of the third capacitor C43, respectively.

We now analyze figure 4 in more detail. The oscillation signals LO _0 and LO _180 have the same frequency as the input signals fed to the input ports IN1 and IN2, and therefore, the input signals are directly down-converted to baseband. For simplicity, the input signal considered in this example is a sinusoidal signal. IN the first stage, the level of the signal IN the first input port IN1 reaches its positive maximum, and the level of the signal IN the second input port IN2 reaches its negative maximum. This difference in level (shown as a block with diagonal lines in fig. 4) is charged to both the first and second capacitors C41 and C42. IN the second stage, the level of the signal IN the first input port IN1 reaches its negative maximum, and the level of the signal IN the second input port IN2 reaches its positive maximum. Such a difference in the level of the input signal (i.e., a peak-to-peak voltage difference) is charged to the third capacitor C43 together with the voltages contained in the first and second capacitors C41 and C42. Since the third capacitor is charged with the peak-to-peak voltage of the present input signal and the peak-to-peak voltages contained in the first and second capacitors C41 and C42, the input voltage V1 is approximately tripled. In other words, the amplification of the passive amplifier according to this embodiment of the invention is 9.5dB, which is naturally influenced by the actual implementation and the characteristics of the components used in the amplifier. In fact, the amplification is about 9.5dB higher than that of a conventional passive mixer. An amplification of 9.5dB is obtained with a passive mixer structure without an additional power supply (except, of course, for the oscillator signal). Although the mixer according to embodiments of the invention does not add additional power to the input signal, it improves the noise figure of a radio receiver utilizing the mixer.

The principle of the mixer according to the embodiment of the invention is based on charging the first and second capacitance C42 and discharging them in series with the input signal to the third capacitance C43. This operation of sequentially charging and discharging the first capacitor C41 causes the first capacitor C41 and the first and third switches 33 and 31 to function as a resistor implemented using a switched capacitor filter (SC filter) technology.

Fig. 5A and 5B show schematic diagrams of a low-pass filter (fig. 5A) and its equivalent circuit (fig. 5B) implemented with SC filter technology. The switches 25 and 26 operated according to the respective oscillation signals CLK _0 and CLK _180 and the first capacitor between the switches 25, 26 function as a resistor having a resistance R2 ═ T/C1, where T is the period of the oscillation signals CLK _0 and CLK _180, and C1 is the capacitance of the first capacitor. V _ in represents an input port of the filter, and V _ out represents an output port of the filter. In fig. 5B an equivalent circuit is shown, in which the switches 25 and 26 and the first capacitor have been replaced by a resistor with a resistance R2. In addition, the SC filter includes a second capacitor connected in parallel with the second switch 26. The corner frequency of the SC filter is defined as:

where C2 is the capacitance of the second capacitor. It can be seen that if the frequency of the oscillating signal is constant, the corner frequency depends on the ratio of the capacitances C1 and C2. In a CMOS implementation, absolute capacitance values can have high variability, but the ratio of capacitances remains very accurate. That is, the ratio C1/C2 remains fairly constant regardless of changes in the absolute values of C1 and C2. Accordingly, the corner frequency can be precisely defined and it has only marginal variations (margin).

Therefore, the mixer according to the embodiment of the present invention may be used as a low pass filter by appropriately designing components, i.e., the first, second, and third capacitors C41 through C43, the first and second sets of switches 31 through 34, and the oscillation signals LO _0 and LO _ 180. Now, the first and third switches 33 and 31 and the first capacitance C41 function as a first resistor, and the second and fourth switches 34 and 32 and the second capacitance C42 function as a second resistor. The corner frequency is defined by the ratio of the capacitance values of the first and third capacitors C41 and C43 and the ratio of the capacitance values of the second and third capacitors C42 and C43. If the capacitance value of the second capacitor C42 is equal to the capacitance value of the first capacitor C41, the corner frequency is reduced to:

accordingly, the mixer according to the embodiment of the present invention is configured to also function as a low pass filter having a corner frequency defined by the capacitance values of the first, second and third capacitances C41, C42 and C43. Therefore, no additional components are required to implement the low pass filter. This reduces the size of a receiver structure employing a passive mixer according to an embodiment of the invention. Although the first and second capacitances C41 and C42 are now connected in series to the input port of the mixer instead of the parallel connection of the first capacitor as shown in fig. 5A, they still have the same functionality to achieve the low pass filtering characteristic of the mixer.

Corner frequency f if the mixer is configured to mix the incoming RF signal to an intermediate frequency other than baseband_cCan be designed into feetHigh enough so that undesired high frequency components will be filtered out.

The above description of the mixer embodiments includes simplifications to aid the reader in understanding the functionality of the mixer. For example, a sinusoidal input signal is considered. However, in the case of modulating the input signal, the effect is the same. Let us assume that the RF frequency of the input signal is 2GHz and the modulation bandwidth is 2MHz, and that the input signal is mixed to baseband. In order to generate one cycle of the output baseband signal, approximately 1000 cycles of the RF signal must be processed. Due to the low pass filtering characteristic, the individual operations of charging and discharging the capacitors C41-C43 do not occur as individual occurrences (singlencidences) in the output signal.

Fig. 6 shows an amplifier configuration similar to that shown in fig. 2. In the embodiment shown in fig. 6, the first connection port a is arranged to be connected to a terminal of the first switch 33 instead of being connected to the first capacitance C41. In a similar manner, the second connection port B is arranged to be connected to a terminal of the second switch 34, instead of being connected to the second capacitance C42. Accordingly, the first switch 33 is located between the first connection port a and the second terminal of the first capacitor C41, and the second switch 34 is located between the second connection port B and the second terminal of the second capacitor C42. The first switching mechanism 35 is arranged to be connected to the first connection port a and the second switching mechanism 36 is arranged to be connected to the second connection port B. The first switching mechanism 35 is configured to connect the first connection port a to one of the output ports C, D or E of the first switching mechanism 35. Similarly, the second switching mechanism 36 is configured to connect the second connection port B to one of the output ports F, G or H of the second switching mechanism 36. The output port C of the first switching mechanism 35 and the output port H of the second switching mechanism 36 are connected to a first input port IN1 of the balanced input port. The output ports D and G are connected to each other, while the output port E and the output port F are connected to the second input port IN2 of the balanced input port. In this embodiment it is possible to control the amplification or voltage multiplication factor of the mixer by connecting the connection ports a and B appropriately, thereby adding Automatic Gain Control (AGC) amplification functionality to the mixer.

The first and second switching mechanisms may be controlled by the controller 60 according to a desired voltage multiplication factor. The controller 60 may determine the desired voltage multiplication factor according to methods known in the art relating to AGC amplifiers. When the desired voltage multiplication factor is three (amplification is 9.5dB), the controller 60 may control the first switching mechanism 35 to connect the first connection port a to the output port E, i.e., to the second input port IN2, and the second switching mechanism 36 to connect the second connection port B to the output port H, i.e., to the first input port IN 1. This configuration corresponds to the embodiment described above with reference to fig. 2. Accordingly, IN the first stage, the first and second capacitors C41 and C42 are connected IN parallel between the input ports IN1 and IN2 of the balanced input port (as shown IN fig. 3A), and IN the second stage, IN series with the third capacitor C43 between the input ports (as shown IN fig. 3B).

When the desired voltage multiplication factor is two (amplification is 6dB), the controller 60 may control the first switching mechanism 35 to connect the first connection port a to output port D and the second switching mechanism 36 to connect the second connection port B to output port G. In other words, the first connection port a is connected to the second connection port B. Accordingly, IN the first stage, the first and second capacitances C41 and C42 are connected IN series between the input ports IN1 and IN2 of the balanced input port. Now, IN the first phase, the voltage between the input ports IN1 and IN2, and thus the voltage charged to the first and second capacitors C41 and C42, is divided between the first and second capacitors C41 and C42, while the voltage multiplication factor of the amplifier is lower than when the capacitors C41 and C42 are connected IN parallel. If the capacitance values of the first and second capacitors C41 and C42 are equal, the input voltage is equally divided between the first and second capacitors. The second stage is likewise similar to that shown IN fig. 3B, i.e., first, second and third capacitances C41, C42 and C43 are connected IN series between the input ports IN1 and IN 2.

When the desired voltage multiplication factor is one, the controller 60 may control the first switching mechanism 35 to connect the first connection port a to the output port C, i.e., to the first input port IN1, and the second switching mechanism 36 to connect the second connection port B to the output port F, i.e., to the second input port IN 2. In this case, the first and second capacitors are not charged in the first stage, and thus no voltage multiplication (amplification is 0dB) is obtained. In effect, the charge remaining in the first and second capacitors after the second phase of the previous clock cycle is discharged in the first phase of the immediately following clock cycle. The second stage is likewise similar to that shown IN fig. 3B, i.e., first, second and third capacitances C41, C42 and C43 are connected IN series between the input ports IN1 and IN 2.

However, in some cases, the desired voltage multiplication factor may be different than 1(0dB), 2(6dB), or 3(9 dB). Fig. 7A shows an embodiment of the invention which is similar to the configuration shown in fig. 6, except that the first and second switching mechanisms 45 and 46 now each have four output ports. The first switching mechanism 45 comprises the same output ports C, D and E as described above and an additional output port I. The second switching mechanism 46 includes the same output ports F, G and H and an additional output port J as described above. The output ports are connected as described above, and the same letters indicate the output ports corresponding to the above description. The additional output port I of the first switching mechanism 45 is connected to the additional output port J of the second switching mechanism 46 through a fourth capacitor C44. Accordingly, IN the first phase, the first set of switches connects the first, second and fourth capacitances C41, C42 and C44 IN series between the input ports IN1 and IN 2. Accordingly, a portion of the total input voltage is charged to the fourth capacitor C44, and the remaining portion of the input total voltage is charged to the first and second capacitors C41 and C42. The extent to which the voltage of the fourth capacitor C44 is charged depends on the capacitance value of the fourth capacitor C44 relative to the capacitance values of the first and second capacitors C41 and C42. IN the second phase, the second set of switches connects the first and second capacitors C41 and C42 IN series with the third capacitor C43 between the input ports IN1 and IN 2. Now, the voltage charged to the first and second capacitors C41 and C42 is discharged to the third capacitor C43 together with the input voltage in series. Accordingly, in the second stage, the fourth capacitor C44 is isolated from the circuit.

In this embodiment, the voltage multiplication factor depends on the amount of input voltage charged to the fourth capacitance C44, i.e. on the capacitance value of the fourth capacitance C44. The higher the capacitance value of the fourth capacitor C44, the lower the voltage across the fourth capacitor C44 during the first phase, i.e. the higher the voltage multiplication factor of the amplifier. The capacitance value of the fourth capacitor C44 may be designed such that the mixer provides a voltage multiplication factor of, for example, 1.4(3dB amplification).

The voltage multiplication factor of the mixer can be adjusted instantaneously (on-the-fly) by connecting the connection ports a and B to each other through the fourth capacitor C44 and adjusting the capacitance value of the fourth capacitor C44 according to the desired voltage multiplication factor. This may be achieved, for example, by arranging an additional capacitance in parallel with the fourth capacitance C44, and a selection mechanism that selects the number of capacitances to be connected in parallel with the fourth capacitance C44 in accordance with a desired voltage multiplication factor (i.e., a desired combined capacitance value of the fourth capacitance C44 and the additional capacitance to be connected in parallel with the fourth capacitance C44). The more capacitors connected in parallel with the fourth capacitor C44, the higher their combined capacitance value, i.e. the higher the effective capacitance caused by the fourth capacitor C44.

In the embodiment described above with reference to fig. 7A, the voltage multiplication factor of the amplifier can be adjusted up to 6dB when the output ports I and J are connected to each other by the fourth capacitor C44. Fig. 7B shows another embodiment in which the voltage multiplication factor of the amplifier is adjustable up to 9dB when the output port I of the first switching mechanism and the output port J of the second switching mechanism are selected. This embodiment is based on the embodiment shown in fig. 2. IN the embodiment shown IN fig. 7B, the fifth capacitance C54 is arranged between the output port I of the first switching mechanism 45 and the second input port IN 2. Correspondingly, a sixth capacitance C55 is arranged between the output port J of the second switching mechanism and the first input port IN 1. The wording "fifth" and "sixth" capacitance is used in order to avoid confusion with the fourth capacitance comprised in the above described embodiments.

When the output ports I and J are selected, the first set of switches (first and second switches 33 and 34) connects the first capacitor C41 IN series with the fifth capacitor C54 and IN parallel with the second and sixth capacitors C42 and C55 between the input ports IN1 and IN 2. Obviously, the second and sixth capacitances C42 and C55 are also connected in series with respect to each other. Thus, the voltage between the input ports IN1 and IN2 is divided between the first and fifth capacitors C41 and C54 and between the second and sixth capacitors C42 and C55. Therefore, the voltage across the first capacitor C41 depends on the capacitance value of the fifth capacitor C54, and the voltage across the second capacitor C42 depends on the capacitance value of the sixth capacitor C55. The higher the capacitance values of the fifth and sixth capacitors C54 and C55, the higher the voltages across the first and second capacitors C41 and C42, respectively. The second stage is similar to the embodiment described above, i.e. the second set of switches connects the first and second capacitances C41 and C42 IN series with the third capacitance C43 between the input ports IN1 and IN 2. Accordingly, in the second stage, the fifth and sixth capacitors C54 and C55 are isolated from the circuit.

Referring to fig. 7B and 9, additional capacitors C50, C51, C52, C53 may be arranged in parallel with the third capacitor C43 in order to adjust the corner frequency of the low pass filter. Referring to equation (2), the corner frequency is now affected by the combined capacitance of the third capacitance C43 and the additional capacitances C50 to C53. In fig. 9, additional capacitances C50 to C53 are arranged in pairs in parallel with the third capacitance C43, and switches 61 and 62 are provided between the additional capacitance pairs. For example, the capacitances C50 and C51 are arranged in series with respect to each other and in parallel with respect to the third capacitance C43, and a switch 61 is provided between the capacitances C50 and C51 to select the pair of capacitances. Capacitors C52 and C53 and switch 62 are similarly arranged. Additional capacitors may be arranged in pairs to maintain the balance of the mixer. Alternatively, switches may be arranged across one additional capacitance, i.e. the additional capacitances C50 to C53 may be replaced by switches and the switches 61 and 62 may be replaced by capacitances. There may be more additional capacitances connectable in parallel with the third capacitance C43 than shown in fig. 7B and 9, and the number of additional capacitances connectable in parallel with the third capacitance C43 may depend on the actual implementation.

When the switching mechanisms 45 and 46 are controlled according to the desired amplification of the mixer, the corner frequency of the low-pass filter may vary depending on the selected output port of the first and second switching mechanisms 45 and 46. The additional capacitances C50 to C53 may be selected to compensate for variations in corner frequency. Accordingly, switches 61 and 62 may be controlled by the same controller 70 that controls switching mechanisms 45 and 46.

The above-described structure for tuning the corner frequency can be utilized in a mixer belonging to a multimode telephone operating on several frequency bands, and the corner frequency can be set according to the bandwidth of the transmitted or received radio signal. For example, the corner frequency may be set to 100kHz when operating with signals according to the GSM specification, and to 2MHz when operating with signals according to the WCDMA specification.

In summary and with reference to fig. 2, 6, 7A and 7B, a mixer according to an embodiment of the invention implements the following operations:

1. the input signal radio frequency signal is mixed with the local oscillation signal LO (element 38 in fig. 8), thereby generating an output signal having a frequency that is the difference between the frequencies of the input signal and the local oscillation signals LO _0 and LO _ 180. Accordingly, f_{IF_OUT}＝f_{RF_IN}-f_LOOr f_{IF_OUT}＝f_LO-f_{RF_IN}。

2. Multiplying the voltage level of the input signal during the mixing process by a factor that can be selected between a required minimum and maximum (9.5dB) voltage multiplication factor. The amplification, i.e. the voltage multiplication factor, can be selected on the fly, thereby providing the mixer with AGC functionality. The amplification can be made selectable between-infinity and 9 dB. Accordingly, the mixer may also operate as a passive attenuator. Accordingly, the output voltage level may be up to three times higher than that of prior art passive mixers (which do not provide amplification features).

3. During the mixing process, the input signal is low-pass filtered. The corner frequency of the low-pass filtering may be defined by the ratio of the capacitances in the mixer.

Although embodiments are described above in connection with balanced input and output ports, embodiments employing double balanced input and output ports may be formed by arranging two balanced passive mixer structures in parallel and providing input signals of opposite phase to corresponding balanced input ports of the parallel structures, and also obtaining output signals of opposite phase from corresponding balanced output ports of the parallel structures. In this configuration, oscillation signals of the same phase may be input to the corresponding input ports of the parallel configuration. Alternatively, the oscillating signals of opposite phases may be provided to corresponding oscillating signal input ports of the parallel structure, and the signals in the corresponding input or output ports of the parallel structure are arranged to be of opposite phases. In a further alternative solution, the input, oscillation or output signals may be provided to (or derived from) corresponding ports of the parallel structures in opposite phases, and the switches of one structure may be implemented with NMOS transistors, while the switches of the other structure may be implemented with PMOS transistors. Other solutions for arranging the double balanced structure are also possible. The advantages obtained with a double balanced structure depend on the actual implementation, but in general the leakage of the oscillation signal to the input port is low in the case of a double balanced structure. In addition, the load to which the oscillating signal is subjected is better balanced with respect to the balanced structure, and this characteristic facilitates the maintenance of the correct phasing of the oscillating signal.

The functionality of the mixer according to an embodiment of the invention corresponds to the block diagram shown in fig. 8. The mixer according to an embodiment of the invention implements the mixing operation (block 38), the voltage multiplication operation (block 39) and the low-pass filtering (block 40) operation by alternately closing and opening the switches 31 to 34. The only difference is that the operations implemented in the three blocks shown in fig. 8 are implemented in one block in a mixer according to an embodiment of the invention. Accordingly, these three operations may be performed using the same components.

Fig. 10 shows a detailed implementation of the mixer according to the embodiment of the invention shown in fig. 2. Obviously, this implementation has a very simple structure. This implementation has balanced input and output ports IN _1, IN _2, OUT _1 and OUT _2, which are common IN today's RF integrated circuits. The similarity between the embodiments described next and the embodiment of the balanced mixer shown in fig. 2 is apparent.

In the implementation shown in fig. 10, the capacitors C1, C2, and C3 through C5 correspond to the first, second, and third capacitances C41, C42, and C43, respectively, of fig. 2. In other words, the third capacitance C43 has been realized with three capacitances C3, C4, and C5. Very small capacitances C3 and C4 may be chosen because their main function is to attenuate the local oscillator signals LO _1 and LO _2 in order to prevent them from leaking to the output ports (OUT _1 and OUT _ 2).

The first switch 33 may be implemented with a MOS transistor Q1, and the second switch 34 may be implemented with a MOS transistor Q2. The transistors Q1 and Q2 are implemented such that the local oscillation signal LO _1 (corresponding to LO _0) is applied to the gates of the transistors Q1 and Q2. Accordingly, the gates of the transistors Q1 and Q2 are connected to each other. A source of the transistor Q1 may be connected to the second input port IN _2, and a source of the transistor Q2 may be connected to the first input port IN _ 1. Drains of the transistors Q1 and Q2 are connected to the first capacitor C1 and the second capacitor C2, respectively.

The third and fourth switches 31 and 32 have been implemented with MOS transistors Q3 and Q4. The second oscillation signal LO _2 may be applied to the gates of the transistors Q3 and Q4. A source of the transistor Q3 may be connected to a first terminal of the capacitor C5, and a source of the transistor Q4 may be connected to the other terminal of the capacitor C5. The drains of transistors Q3 and Q4 may be connected to capacitors C1 and C2, respectively.

A DC voltage source Va may be connected to the gates of MOS transistors Q1 and Q2. The DC voltage supplied by the voltage source Va may be selected according to the implementation. The DC voltage sets the bulk-source voltage of transistors Q1 and Q2 to the appropriate level. In practice, the voltage supplied by the voltage source Va has an effect on the threshold voltage of the transistors Q1 and Q2, and the actual voltage level may depend on the duty cycle of the first oscillation signal LO _ 1. Similarly, the same DC voltage may be applied to the gates of MOS transistors Q3 and Q4, if necessary.

These switches may be implemented, for example, by NMOS and/or PMOS transistors. In case all switches are NMOS or PMOS transistors, two local oscillation signals having opposite phases (i.e. two different local oscillation signals) may be applied to the mixer, as described above. Alternatively, the transistors Q1 and Q2 may be NMOS transistors, and the transistors Q3 and Q4 may be PMOS transistors. Now, two local oscillator signals are not necessary. The same local oscillation signal may be applied to all of the transistors Q1 to Q4. The transistors Q1 and Q2 are turned off during the positive half cycle of the local oscillation signal and turned on during the negative half cycle of the local oscillation signal. On the other hand, the transistors Q3 and Q4 are turned off during the negative half cycle of the local oscillation signal and turned on during the positive half cycle of the local oscillation signal. Of course, Q1 and Q2 may be PMOS transistors, while Q3 and Q4 are NMOS transistors. Accordingly, the operation of the first and second sets of switches may be complementary in the sense that both sets of switches are not closed simultaneously.

When designing an SC low-pass filter implemented with the circuit shown in fig. 10, the starting point is equation (2) described above. Since this implementation involves RF circuitry, the design cannot be based on equation (2) alone. Problems to be considered in implementation include on-resistances of the MOS transistors Q1, Q2, Q3, and Q4, output impedances of previous stages (e.g., an amplifier or a band pass filter) before the mixer, impedances of a load of the mixer, pulse waveforms and pulse ratios of local oscillation signals, and various capacitances caused by components of the mixer.

In fig. 10, resistors R1, R2, R3, R4 and capacitors C6, C7, C8 and C9 are specific to the implementation and are selected accordingly.

Fig. 11 shows the structure of a radio receiver (or transceiver) using a mixer according to an embodiment of the invention. The received RF signal may be band-pass filtered in a band-pass filter 41 and amplified in a low noise amplifier 42 before mixers 43 and 44. With appropriate selection of the phase of the local oscillator signal, the received RF signal is separated into an in-phase (I) component and a quadrature (Q) component. The local oscillation signals LO _0 and LO _180 having zero degree and 180 degree phase shifts may be applied to the first mixer 44, and the local oscillation signals LO _90 and LO _270 having 90 degree and 270 degree phase shifts may be applied to the second mixer 43. The mixers 43 and 44 may be implemented according to any of the embodiments described above. The mixed output signals of the mixers 43 and 44 may be further amplified in respective baseband amplifiers 45 and 46 and low-pass filtered in respective low-pass filters 47 and 48. In this implementation, the pulse ratio of the local oscillator signal may be less than or equal to 25/75 to prevent overlap of the local oscillator signal pulses.

Fig. 12 shows an implementation in which the pulse ratio of the local oscillator signals LO _0, LO _90, LO _180 and LO _270 may be 50/50, since amplifiers 62 and 63 before the respective mixers 64 and 65 separate the I and Q components from each other on the input RF port side. The band pass filter 60 and the low noise amplifier 61 may be common to the I and Q components of the received RF signal.

Fig. 13 shows an implementation in which the same local oscillator signals LO _0 and LO _180 may be applied to both mixers 74 and 75. Likewise, a band pass filter 70 and a low noise amplifier 71 may precede the mixers 74 and 75. Phase shifters 72 and 73 before mixers 74 and 75 shift the phase of the input RF signal by +45 degrees and-45 degrees, respectively, thereby separating the I component and the Q component. Alternatively, the phase shifters 72 and 73 may shift the phase of the input signal by different phase shifts so as to produce a 90-degree phase shift between the I and Q components. One of the phase shifters 72 and 73 may even be omitted (if the other is 90 degree phase shifted). After mixers 74 and 75, the mixed signals are fed to amplifiers 76 and 77 for further amplification.

Those skilled in the art will appreciate that a mixer and a radio transceiver utilizing the mixer according to embodiments of the present invention may be implemented in a number of different ways. The switches in the mixer may be implemented with GaAs FET transistors, SOI-CMOS transistors, diodes, etc. The mixer may be implemented as an integrated circuit or on a printed circuit board, for example. The mixer according to embodiments of the invention may be utilized in virtually any radio communication device. The radio communication device may be a radio transceiver or simply a radio receiver. The radio communication device may be a mobile telephone, a Global Positioning System (GPS) receiver, a Galileo receiver, a Wireless Local Area Network (WLAN) transceiver,(Bluetooth)) A transceiver, an FM radio receiver, a television signal receiver (e.g., DVB-T or DVB-H), an AM receiver, a short wave radio transceiver, and so forth.

The mixer described herein mixes the input RF signal down, i.e., converts the input RF signal to baseband. Alternatively, the mixer according to the embodiment of the present invention may mix the input signal down to an Intermediate Frequency (IF). Although the mixer according to an embodiment of the invention is preferably utilized in a radio receiver, the mixer may also be implemented as an up-conversion mixer converting an input baseband signal into an RF signal. Even though the invention has been described above with reference to an example according to the accompanying drawings, it is clear that the invention is not restricted thereto but it can be modified in several ways within the scope of the appended claims.

Claims (36)

1. A frequency mixing device, comprising:

an input interface comprising a balanced input port configured to receive a balanced input signal and an oscillating signal input port configured to receive a first oscillating signal and a second oscillating signal;

a first capacitor;

a second capacitor;

a third capacitor;

a first set of switches responsive to the first oscillating signal and configured to connect the first capacitance and the second capacitance between a first input port and a second input port of the balanced input ports in response to the first oscillating signal;

a second set of switches responsive to the second oscillating signal and configured to connect the first capacitance between the first input port and a first end of the third capacitance and the second capacitance between the second input port and a second end of the third capacitance in response to the second oscillating signal; and

an output port connected to the first and second ends of the third capacitance.

2. The apparatus of claim 1, wherein a first terminal of the first capacitance is connected to the first input port and a first terminal of the second capacitance is connected to the second input port, wherein the first set of switches is configured to: when closed, connecting a second terminal of the first capacitance to the second input port and a second terminal of the second capacitance to the first input port; and wherein the second set of switches is configured to: when turned off, the second terminal of the first capacitor is connected to the first terminal of the third capacitor, and the second terminal of the second capacitor is connected to the second terminal of the third capacitor.

3. The apparatus of claim 1 or 2, wherein the first and second oscillating signals are the same oscillating signal.

4. The apparatus of claim 1 or 2, further comprising:

a local oscillation signal generator configured to generate and apply the first and second oscillation signals to an oscillation input port, wherein the first and second oscillation signals have opposite phases.

5. The apparatus of claim 4, wherein the apparatus is configured to receive a radio frequency input signal through the balanced input port, and the local oscillating signal generator is configured to generate the first and second oscillating signals having frequencies suitable for converting the frequency of the input signal to a desired target frequency.

6. The apparatus of claim 1, further comprising:

a controllable switching mechanism configured to: connecting the first and second capacitances in series or in parallel between the first and second input ports when the first set of switches is closed, depending on a desired voltage multiplication factor achieved by the apparatus on an input signal input to the balanced input port.

7. The apparatus of claim 6, wherein the switching mechanism is configured to: the first and second capacitors are connected in series between the first and second input ports when the desired voltage multiplication factor is two, and the first and second capacitors are connected in parallel between the first and second input ports when the desired voltage multiplication factor is three.

8. The apparatus of claim 6 or 7, wherein the switching mechanism is further configured to: when the desired voltage multiplication factor is one, connecting both ends of the first capacitance to the first input port and both ends of the second capacitance to the second input port when the first set of switches is turned off.

9. The apparatus of claim 1 or 2, wherein the apparatus is configured to function as a low pass filter having a corner frequency defined by a ratio of capacitance values of the first and third capacitances and a ratio of capacitance values of the second and third capacitances, respectively.

10. The apparatus of claim 1 or 2, wherein a first terminal of the first capacitance is connected to the first input port and a first terminal of the second capacitance is connected to the second input port, wherein the first set of switches comprises: a first switch connected between the second terminal of the first capacitance and the second input port, and a second switch connected between the second terminal of the second capacitance and the first input port, and wherein the second set of switches comprises: a third switch connected between the second terminal of the first capacitor and the first terminal of the third capacitor, and a fourth switch connected between the second terminal of the second capacitor and the second terminal of the third capacitor.

11. The apparatus of claim 1, further comprising:

a fourth capacitance which is a capacitance of the fourth capacitor,

wherein the first set of switches is configured to: when closed, connecting the fourth capacitance in series with the first and second capacitances between the first and second input ports of the balanced input port.

12. The apparatus of claim 11, further comprising:

an adjustment circuit configured to: adjusting a capacitance value of the fourth capacitor, and controlling a voltage multiplication factor of the apparatus.

13. The apparatus of claim 1 or 2, wherein the apparatus is further configured to function as a voltage multiplier by: configuring the first oscillating signal so as to close the first set of switches and charge the first and second capacitors accordingly during a first half-cycle of the first oscillating signal; and configuring the second oscillating signal to close the second set of switches and correspondingly discharge the charge in the first and second capacitances to the third capacitance along with the input signal during a second half-cycle of a second local oscillating signal, thereby summing the voltage charged to the first and second capacitances and the voltage on the first and second input ports.

14. The device according to claim 1 or 2, which has a double balanced structure.

15. A mixing apparatus comprising an apparatus according to any of claims 1 to 14.

16. A radio apparatus comprising an apparatus according to any of claims 1 to 14.

17. The radio apparatus of claim 16, wherein the radio transceiver is configured to receive a radio frequency signal comprising an in-phase component and a quadrature component, and further comprising a separate mixer for the in-phase component and a separate mixer for the quadrature component.

18. The radio apparatus of claim 17, wherein a phase of an oscillation signal applied to the discrete mixer associated with the quadrature component and a corresponding phase of an oscillation signal applied to the discrete mixer associated with the in-phase component differ by 90 degrees, and wherein the local oscillation signal has a maximum pulse ratio of 25/75.

19. The radio device of claim 17, further comprising:

a discrete amplifier for each of the discrete mixers prior to the discrete mixer,

wherein a phase of a local oscillation signal applied to the discrete mixer associated with the quadrature component and a corresponding phase of a local oscillation signal applied to the discrete mixer associated with the in-phase component differ by 90 degrees, and wherein the local oscillation signal has a maximum pulse ratio of 50/50.

20. The radio device of claim 17, further comprising:

a phase shifter before at least one of the discrete mixers,

wherein the phase shifter before the at least one mixer is configured to: shifting the phase of at least one of the in-phase component and the quadrature component, thereby producing a phase difference of 90 degrees between the in-phase component and the quadrature component.

21. A radio apparatus according to claim 20, wherein the same local oscillator signal is applied to both discrete mixers.

22. A method of mixing, comprising:

receiving an input signal through a first input port and a second input port of the balanced input ports, and receiving a first oscillation signal and a second oscillation signal through the oscillation signal input port;

connecting a first capacitance and a second capacitance between a first input port and a second input port of the balanced input ports in a first phase responsive to a first oscillating signal;

in a second phase in response to a second oscillating signal, connecting the first capacitance between the first input port and a first end of a third capacitance, and connecting the second capacitance between the second input port and a second end of the third capacitance; and

and obtaining the voltage on the third capacitor as an output voltage.

23. The method of claim 22, further comprising:

in the second phase, connecting the first terminal of the first capacitance connected to the second input port in the first phase to the third capacitance; and

in the second phase, connecting the first terminal of the second capacitance connected to the first input port in the first phase to the second terminal of the third capacitance.

24. The method according to claim 22 or 23, further comprising:

charging the first and second capacitors with voltages corresponding to voltages on the first and second input ports in the first stage; and

in the second phase, discharging the charge in the first and second capacitances in series with the present voltage on the first and second input ports to the third capacitance, thereby generating a voltage on the third capacitance, the generated voltage being the sum of the voltage charged to the first capacitance in the first phase, the voltage charged to the second capacitance in the first phase and the present voltage on the first and second input ports.

25. The method according to claim 22 or 23, further comprising:

configuring the first oscillation signal and the second oscillation signal as a same oscillation signal.

26. The method according to claim 22 or 23, further comprising:

configuring the first and second oscillation signals to have the same frequency and different phases.

27. The method according to claim 22 or 23, further comprising:

configuring the received input signal into a radio frequency input signal; and

configuring the first and second oscillating signals to have a frequency suitable for converting the frequency of the radio frequency input signal to a desired target frequency.

28. The method of claim 22, further comprising:

in the first stage, the first and second capacitances are connected in series or in parallel between the first and second input ports depending on a desired voltage multiplication factor of an output signal relative to the input signal.

29. The method of claim 28, further comprising:

in the first stage, the first and second capacitances are connected in series between the first and second input ports when the desired voltage multiplication factor is two, and the first and second capacitances are connected in parallel between the first and second input ports when the desired voltage multiplication factor is three.

30. The method according to claim 28 or 29, further comprising:

in the first stage, when the desired voltage multiplication factor is one, connecting both ends of the first capacitor to the first input port; and

connecting both ends of the second capacitor to the second input port.

31. The method of claim 28, further comprising:

connecting the first and second capacitances in series between the first and second input ports in the first stage; and

providing an additional capacitance in series with the first capacitance and the second capacitance, the additional capacitance having a capacitance value determined according to a desired voltage multiplication factor.

32. The method of claim 22, further comprising:

defining a corner frequency of a low pass filter using capacitance values of the first, second, and third capacitors; and

low pass filtering input signals input to the first input port and the second input port.

33. The method of claim 22, further comprising:

connecting the first and second capacitances in series between the first and second input ports in the first stage;

providing a fourth capacitance in series between the first capacitance and the second capacitance in the first phase; and

adjusting a capacitance value of the fourth capacitance according to a desired voltage multiplication factor of the output signal relative to the input signal.

34. The method according to claim 22 or 23, further comprising:

interleaved with the third capacitor to charge the first capacitor and the second capacitor.

35. A method according to claim 22 or 23, which is carried out in an apparatus having a double balanced structure.

36. A mixing apparatus, comprising:

an input device, comprising: first and second input ports of the balanced input port configured to receive a balanced input signal, and an oscillating signal input device configured to receive a first oscillating signal and a second oscillating signal;

first capacitive means for storing charge;

second capacitance means for storing charge;

third capacitive means for storing charge;

first connecting means for connecting the first and second capacitive means between first and second input ports of the balanced input port in a first phase responsive to the first oscillating signal;

second connection means for connecting, in a second phase responsive to the second oscillating signal, the first capacitive means between the first input port and a first end of the third capacitive means and the second capacitive means between the second input port and a second end of the third capacitive means; and

output means for obtaining a voltage across said third capacitance means as an output voltage.