HK1135821B

HK1135821B - Method and device for arithmetic code package outputting

Info

Publication number: HK1135821B
Application number: HK09112379.7A
Authority: HK
Inventors: 刘浩
Original assignee: 深圳市同洲电子股份有限公司
Filing date: 2009-12-31
Publication date: 2012-01-06

Description

Method and apparatus for packed output of arithmetic coding

Technical Field

The present invention relates to an arithmetic coding technique in video processing, and more particularly, to a method and apparatus for packed output of arithmetic coding.

Background

In the h.264 protocol, arithmetic coding is a common coding method for realizing data compression in the video processing process, and the basic principle is as follows: and processing the probability space according to the value of binary data in the current video coding circuit to obtain a processed probability space, then performing renormalization processing on the processed probability space as a probability space to be updated to obtain an updated probability space, and simultaneously generating a corresponding code stream according to the probability space to be updated. The generated corresponding code stream comprises a plurality of coding output bytes, and the coding output bytes are the final result output by the coding end.

The probability space described above is generally expressed as: the starting position of the probability space (CodLow) and the length of the probability space (CodRange). CodLow and CodRange are commonly represented as binary numbers. In the h.264 protocol, the CodRange value and CodLow value are updated as follows:

the CodRange value is typically nine bits, each bit having a value of "0" or "1", the most significant bit being the 8 th bit, the next most significant bit being the 7 th bit, and so on, the least significant bit being the 0 th bit. If the value of a certain bit in the CodRange value to be updated is 1, and the values of all the high bits before the bit are 0, the bit is marked as the mth bit, all the high bits before the mth bit are shifted out, the mth bit and the subsequent bits are sequentially shifted to the positions starting from the highest bit, and all the low bits left after shifting out are filled with zero, so that the obtained CodRange value is the updated CodRange value. For example, when a CodRange value is 0001 XXXX, and an update is performed, bits 8, 7, and 6 "0" are shifted out, the subsequent "1 XXXX" is used as bits 8 to 3 of the updated CodRange value, and bits 2 to 0 left after the shift-out is filled with 0, so that an updated CodRange value is obtained: 1 xxx × 000, the updated CodRange value will be used for the next renormalization process.

The CodLow value is typically ten bits, each bit is "0" or "1", the highest bit is the 9 th bit, the next highest bit is the 8 th bit, and so on, and the lowest bit is the 0 th bit. And updating the CodLow value according to the CodRange value to be updated and the CodLow value to be updated. Specifically, starting from the highest bit of the CodRange value to be updated, if the value of a certain bit is 1 and the values of all the high bits before the bit are 0, the number of all the high bits before the bit is recorded as n; if all the high n bits of the CodLow to be updated are '1', namely the high n bits are '1.. 1', the high n bits in the CodLow are shifted out, the rest bits after the n bits are shifted out are sequentially shifted to the position from the highest bit, and all the low bits left after the shifting out are filled with zero; if the high n bits of the CodLow are not completely '1', the high n bits in the CodLow are shifted out, the highest position is set to '0' after shifting out, the rest bits after shifting out the n bits are sequentially shifted to the position from the next highest position, then all the low bits left after shifting out are filled with zero, and the CodLow value obtained in this way is the updated CodLow value. The updated CodLow value will be used for the next renormalization process.

And in the process of updating the CodRange value and the CodLow value, outputting the coded output bytes at the same time. When the 8-bit output characters of the encoded output byte are all filled, the encoded output byte is output. 8bit output characters in the encoding output byte are arranged from high order to low order according to the sequence of the obtained output characters. The following describes conditions that need to be satisfied to obtain an 8-bit output character of the encoded output byte.

The encoded output bytes are derived from the CodRange value and the CodLow value. The output character contained in the output byte is determined by two adjacent bits in the CodLow value, and the sequence of the output character is determined to be the high bit and then the low bit. Specifically, an output character is determined from the 9 th bit and the 8 th bit, an output character is determined from the 8 th bit and the 7 th bit, an output character is determined from the 7 th bit and the 6 th bit, an output character is determined from the 6 th bit and the 5 th bit, and so on, to determine each output character. The number of valid output characters determined by a CodLow value to be updated is the number of bits of the upper bits shifted out when the CodRange value is updated. For example, if the number of bits of the high bits shifted out when updating the CodRange value is 3, the number of valid output characters determined by the current CodLow value to be updated is 3, including: an output character determined by the 9 th bit and the 8 th bit, an output character determined by the 8 th bit and the 7 th bit, and an output character determined by the 7 th bit and the 6 th bit.

The principle of determining the output character from two adjacent bits in the CodLow value includes:

if the adjacent two bits are 00, the corresponding output character is 0;

if the adjacent two bits are 01, the corresponding output character is an undetermined state output character;

if the adjacent two bits are 10, the corresponding output character is 1;

if the adjacent two bits are 11, the corresponding output character is 1;

in the process of determining the output character by two adjacent bits of the codLow value, if any one of the 9 th bit and the 8 th bit is 0, when determining the output character according to each two adjacent bits after the two adjacent bits, the value of the highest bit of each two adjacent bits after the two adjacent bits needs to be set to be 0; if the value of the adjacent 9 th bit and 8 th bit is 11, when the output character is determined according to each adjacent two bits after the adjacent two bits, the value of each adjacent two bit after the adjacent two bits does not need to be changed. For example, if the CodLow value is 1010110001, the output character determined by bits 9 and 8 is 1; at this time, if one of the 9 th bit and the 8 th bit is 0 (i.e., the 9 th bit is 0), when the 8 th bit and the 7 th bit (i.e., 01) determine the output character, the 8 th bit is set to 0, and if the 8 th bit is originally 0, the 8 th bit and the 7 th bit are used to determine the corresponding output character, which is the output character in the undetermined state; when the 7 th bit and the 6 th bit (namely 10) determine output characters, setting the 7 th bit of the output characters to be 0, namely determining the corresponding output characters to be 0 by 00; when the 6 th bit and the 5 th bit (namely 01) determine output characters, the 6 th bit is set as 0, and the 6 th bit is originally 0, the 6 th bit and the 5 th bit are originally used for determining corresponding output characters which are output characters in an undetermined state; when the 5 th bit and the 4 th bit (namely 11) determine the output character, setting the 5 th bit to 0, namely determining the corresponding output character from 01, and outputting the character in an undetermined state; and so on to determine the other respective output characters.

After obtaining an output character according to the CodRange value and the CodLow value, judging the currently obtained output character, and if the currently obtained output character is judged to be an output character in an undetermined state, performing cumulative counting on the number of the output characters in the undetermined state, and continuously obtaining the next output character; if the current obtained output character is not the output character in the undetermined state, judging whether the number of the output characters in the undetermined state is 0 or not, if the number of the output characters in the undetermined state is 0, typing the current obtained output character into the current encoding output byte, and if the number of the output characters in the undetermined state is not 0, typing the current obtained output character into the current encoding output byte, and then typing a plurality of output characters, which are opposite to the current obtained output character, into the current encoding output byte.

In order to satisfy the conditions of renormalization and packaging output in a protocol and realize the renormalization and packaging output of arithmetic coding, a serial processing method realized by software is adopted in the prior art, and the method needs to carry out multiple cycles to finish once renormalization, generates output characters while renormalizing and outputs corresponding code streams.

In the h.264 protocol, the range of CodRange is [2, 255], and the range of CodLow is [0, 1023 ]. The detailed description of the renormalization and packing process of the prior art is illustrated by the flow of fig. 1, where the reference probability space is [0, 1023], and the method includes the following steps:

step 101, determine whether CodRange is less than 256, that is, whether CodRange is less than 1/4 of the total length of the reference probability space, if yes, execute step 102, otherwise, end the process.

Whether the CodRange is smaller than 256 is judged, and binary representation is corresponded, namely whether the highest bit of the nine CodRange is 0 is judged.

Step 102, determining whether the CodLow is less than 256, that is, whether the current probability space is located at the lower half of the reference probability space, if so, executing step 104, otherwise, executing step 103.

And judging whether the CodLow is less than 256 or not, and corresponding to binary representation, namely judging whether the highest bit and the second highest bit of the ten-bit CodLow are both 0 or not.

Step 103, determining whether the CodLow is greater than or equal to 512, that is, whether the current probability space is located at the upper half of the reference probability space, if so, executing step 106, otherwise, executing step 105.

Step 104, generating 10 as an output character, generating count 1 as an output character, clearing the count and executing step 108.

Step 105, subtract 256 from the CodLow value, that is, move the position of the current probability space in the reference probability space to 1/4 of the total length of the reference probability space toward the lower half, add 1 to the count value, and then execute step 108.

And 106 to 107, subtracting 512 from the value of CodLow, that is, moving the position of the current probability space in the reference probability space to 1/2 of the total length of the reference probability space to the lower half, then generating 1 to 1 as output characters, generating count to 0 as output characters, clearing the count, and executing 108.

And 108, multiplying the value of CodLow and the value of CodRange by 2 respectively, namely, doubling the current probability space length, and then returning to the step 101.

In the above flow, the operation process from step 101 to step 108 is a cycle.

It can be seen from the above flow that updating the values of CodLow and CodRange realizes updating the probability space, and the output character is obtained while updating the probability space by renormalization processing. However, when each loop is executed to step 108, the length of the probability space is doubled and the process returns to step 101 to perform the determination, and the current renormalization process flow is ended when the CodRange is not less than 256. If the CodRange when step 101 is performed is at its minimum value of 2, 7 cycles are required to complete the entire flow of the renormalization process, which takes a significant amount of unit time.

Therefore, the existing renormalization processing efficiency is not high, so that the updating speed of a probability space is low, the arithmetic coding efficiency is low, and the video processing speed is influenced. And the updates to CodLow, CodRange are interleaved with the generation of output characters, which are difficult to improve processing efficiency.

Disclosure of Invention

The invention provides a packing output method of arithmetic coding, which can simplify the packing output process and improve the coding speed.

The invention provides a packing output device for arithmetic coding, which can simplify the packing output process and improve the coding speed.

A method of arithmetic coded packed output, the method comprising:

obtaining a high-order 7-bit output string and a 7-bit flag string according to an initial position CodLow value of a probability space to be updated, wherein the 7-bit flag string identifies an undetermined state output character in the 7-bit output string; obtaining an effective number according to the CodRange value of the probability space to be updated, wherein the effective number represents the number of effective output characters in a 7-bit output string obtained according to the CodLow value to be updated;

extracting a plurality of effective output characters from the 7-bit output string, and identifying output characters in an undetermined state in the extracted output characters according to the 7-bit marker string;

and processing the extracted output characters to obtain coded output bytes and outputting the coded output bytes.

A arithmetic coding packing output device comprises a CodLow analysis module, a CodRange analysis module, an output character extraction cache module and an undetermined state identification and packing output module;

the CodLow analysis module is used for obtaining a high-order 7-bit output string and a 7-bit flag string according to a CodLow value to be updated, transmitting the high-order 7-bit output string and the 7-bit flag string to the output character extraction cache module, and identifying an undetermined state output character in the 7-bit output string by the 7-bit flag string;

the CodRange analyzing module is used for obtaining the effective number according to the CodRange to be updated and transmitting the effective number to the output character extracting and caching module, wherein the effective number represents the bit number of the effective output character in the 7-bit output string;

the output character extraction and cache module is used for extracting a plurality of effective output characters from the 7-bit output string, identifying output characters in an undetermined state in the extracted output characters according to the 7-bit marker string, and storing the extracted output characters;

and the undetermined state recognition and packaging output module is used for reading the output characters from the output character extraction cache module, processing the output characters to obtain coded output bytes according to the output characters, and outputting the coded output bytes.

According to the scheme, the effective number is obtained according to the CodRange value to be updated, and the 7-bit output string and the 7-bit mark string are obtained according to the CodLow value to be updated; then, an encoded output byte is generated based on the valid number, the 7-bit output string, and the 7-bit flag string. The invention separates the acquisition of the encoding output byte from the updating of the CodRange value and the CodLow value, so that the packing output process with unfixed cycle times can be completed in one clock period, thereby reducing the realization complexity and improving the encoding speed.

Drawings

FIG. 1 is a flow chart of a prior art method for renormalization and packed output of arithmetic coding;

FIG. 2a is a schematic diagram of a packing output device for arithmetic coding according to the present invention;

FIG. 2b is a schematic diagram of the undefined state identifying and packing output module shown in FIG. 2 a;

FIG. 3 is a flowchart of a packing output method of arithmetic coding according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following embodiments and the accompanying drawings.

The invention adopts a hardware circuit implementation mode of parallel processing, and simultaneously updates the CodRange value and the CodLow value respectively to obtain the updated CodRange value and CodLow value; during the process of updating the CodRange value, the effective number is also obtained, and during the process of updating the CodLow value, a 7-bit output string and a 7-bit flag string are also obtained, wherein the 7-bit flag string identifies an undetermined state output character in the 7-bit output string; then, an output character is generated based on the effective number, the 7-bit output string, and the 7-bit flag string. The invention independently updates the CodRange value and the CodLow value in parallel and separates the updating process from the packaging output process, thus, the renormalization process with unfixed cycle times in the prior art can be completed in one clock period, and the packaging output process based on renormalization can be completed in another clock period, so that the renormalization and the packaging output process thereof are completed in two clock periods, thereby reducing the realization complexity and improving the coding speed.

In the scheme of the invention, the updating of the CodRange value and the CodLow value can be realized not only by a hardware circuit realization mode of parallel processing, but also by a serial realization mode in the prior art, and the packing output still adopts the mode of generating output characters according to the effective number, the 7-bit output string and the 7-bit mark string; at this time, updating the CodRange value and CodLow value by using the prior art can be realized by performing other steps except steps 104, 105 and 107 in fig. 1.

Referring to fig. 2a, a schematic structural diagram of a renormalization and packing output device for arithmetic coding in the present invention includes a CodRange parsing module, a CodLow parsing module, an output character extraction buffer module, and an undetermined state identification and packing output module.

Optionally, the CodLow parsing module is implemented by a hardware circuit, and is further configured to obtain an updated CodLow value according to a CodLow value to be updated and a CodRange value to be updated.

By adopting the implementation mode of the hardware circuit, all conditions required to be met by updating the CodLow value can be simultaneously realized through the hardware circuit, so that the updating of the CodLow value can be completed in one clock cycle.

The output character contained in the output byte is determined by two adjacent bits in the CodLow value, and the sequence of the output character is determined to be the high bit and then the low bit. Specifically, an output character is determined from the 9 th bit and the 8 th bit, an output character is determined from the 8 th bit and the 7 th bit, an output character is determined from the 7 th bit and the 6 th bit, an output character is determined from the 6 th bit and the 5 th bit, and so on, to determine each output character. The method for obtaining the output characters by using the existing software implementation mode of serial processing needs 7 cycles to complete one renormalization at most, that is, 7 output characters can be output at most in one renormalization process, so in the invention, a CodLow analysis module obtains a high-order 7-bit output string according to a CodLow value to be updated while updating the CodLow value, and the 7-bit output string is 7 output characters on the high order obtained by two adjacent bits in the CodLow value, and specifically comprises the following steps: an output character determined by the 9 th bit and the 8 th bit, an output character determined by the 8 th bit and the 7 th bit, an output character determined by the 7 th bit and the 6 th bit, an output character determined by the 6 th bit and the 5 th bit, an output character determined by the 5 th bit and the 4 th bit, an output character determined by the 4 th bit and the 3 rd bit, and an output character determined by the 3 rd bit and the 2 nd bit.

if the adjacent two bits are 00, the corresponding output character is 0;

if the adjacent two bits are 10, the corresponding output character is 1;

if the adjacent two bits are 11, the corresponding output character is 1;

in the process of determining the output character by two adjacent bits of the codLow value, if any one of the 9 th bit and the 8 th bit is 0, when determining the output character according to each two adjacent bits after the two adjacent bits, the value of the highest bit of each two adjacent bits after the two adjacent bits needs to be set to be 0; if the value of the adjacent 9 th bit and 8 th bit is 11, when the output character is determined according to each adjacent two bits after the adjacent two bits, the value of each adjacent two bit after the adjacent two bits does not need to be changed. For example, if the CodLow value is 1010110001, the output character determined by bits 9 and 8 is 1; at this time, if one of the 9 th bit and the 8 th bit is 0 (i.e., the 9 th bit is 0), when the 8 th bit and the 7 th bit (i.e., 01) determine the output character, the 8 th bit is set to 0, and if the 8 th bit is originally 0, the 8 th bit and the 7 th bit are used to determine the corresponding output character, which is the output character in the undetermined state; when the 7 th bit and the 6 th bit (namely 10) determine the output character, the 7 th bit is set to 0, namely the corresponding output character is determined to be 0 by 00; when the 6 th bit and the 5 th bit (namely 01) determine output characters, the 6 th bit is set as 0, and the 6 th bit is originally 0, the 6 th bit and the 5 th bit are originally used for determining corresponding output characters which are output characters in an undetermined state; when the 5 th bit and the 4 th bit (namely 11) determine the output character, setting the 5 th bit to 0, namely determining the corresponding output character from 01, and outputting the character in an undetermined state; and so on to determine the other respective output characters.

The CodLow analysis module obtains a 7-bit output string and records an undetermined state output character in the 7-bit output string, wherein the record is represented by a mark string with the same 7-bit length and is called a 7-bit mark string.

Optionally, the CodRange parsing module is implemented by a hardware circuit, and is further configured to obtain an updated CodRange value according to a CodRange value to be updated.

The CodRange value is typically nine bits, each bit having a value of "0" or "1", the most significant bit being the 8 th bit, the next most significant bit being the 7 th bit, and so on, the least significant bit being the 0 th bit. If the value of a certain bit in the CodRange to be updated is 1, and the values of all the high bits before the bit are 0, the bit is marked as the mth bit, all the high bits before the mth bit are shifted out, the mth bit and all the subsequent bits are sequentially shifted to the positions starting from the highest bit, and all the low bits left after shifting out are filled with zero, so that the obtained CodRange value is the updated CodRange value. For example, when a CodRange value is 0001 XXXX, and an update is performed, bits 8, 7, and 6 "0" are shifted out, the subsequent "1 XXXX" is used as bits 8 to 3 of the updated CodRange value, and bits 2 to 0 left after the shift-out is filled with 0, so that an updated CodRange value is obtained: 1 xxx × 000, the updated CodRange value will be used for the next renormalization process. Typically, the number of all high bits preceding the m-th bit is 0, 1, 2, 3, 4, 5, 6, or 7.

With a hardware circuit implementation, the update of the CodRange value can be completed within one clock cycle.

And the CodRange analysis module updates the CodRange value and simultaneously outputs an effective number, wherein the effective number represents the number of effective output characters in a 7-bit output string obtained according to the CodLow value to be updated. The number of effective output characters determined by a CodLow value to be updated is the number of high-order bits shifted out when the CodRange value is updated; that is, the number of bits of the valid output character in the 7-bit output string is the number of bits of the upper bits shifted out when updating the CodRange value. For example, if the number of bits of the high bits shifted out when updating the CodRange value is 3, the number of valid output characters determined by the current CodLow value to be updated is 3, including: an output character determined by the 9 th bit and the 8 th bit, an output character determined by the 8 th bit and the 7 th bit, and an output character determined by the 7 th bit and the 6 th bit.

The number of effective output characters determined by a CodLow value to be updated is at most 7, binary system is adopted, and the effective number can represent a certain number from 0 to 7 by a three-digit number.

And the output character extraction and cache module is used for extracting a plurality of effective output characters from the 7-bit output string, identifying output characters in an undetermined state in the extracted output characters according to the 7-bit marker string, and storing the extracted output characters.

The undetermined state identification and packaging module is used for reading the output characters from the output character extraction and cache module, and performing cumulative counting on the number of the output characters in the undetermined state and continuously reading the next output character if the output characters read currently are judged to be the output characters in the undetermined state; if the current read output character is not the output character in the undetermined state, judging whether the number of the output characters in the undetermined state is 0 or not, if the number of the output characters in the undetermined state is 0, typing the current read output character into the current encoding output byte, if the number of the output characters in the undetermined state is not 0, typing the current read output character into the current encoding output byte, then typing a plurality of output characters in the undetermined state, which are opposite to the current read output character, into the current encoding output byte, and clearing the number of the output characters in the undetermined state to carry out the cumulative counting of the output characters in the next undetermined state.

The current encoding output byte is the byte which is currently encoded and is about to be output, and when the 8-bit output characters of the encoding output byte are all filled, the encoding output byte is output. 8bit output characters in the encoding output byte are arranged from high order to low order according to the sequence of the obtained output characters.

Optionally, the output character extracting and buffering module includes a First-in-First-out (FIFO) buffering module, an output character string converting module, and an output character FIFO buffering module.

The first FIFO cache module is used for receiving and storing the 7-bit output string and the 7-bit mark string transmitted by the CodLow analysis module; and receiving and storing the effective number transmitted by the CodRange parsing module.

The output character string conversion module is used for reading the effective number and the 7-bit identification string stored in the first FIFO cache module, extracting effective output characters from the 7-bit output string stored in the first FIFO cache module, identifying output characters in an undetermined state in the extracted output characters according to the 7-bit identification string, and serially outputting the output characters to the output character FIFO cache module.

When the output character string conversion module outputs the extracted 7-bit output string to the output character FIFO buffer module, each output character output can be represented by 2 bits, specifically, a character "0" output is represented by "00", a character "1" output is represented by "01", and an undetermined status character output is represented by "10".

And the output character FIFO buffer module is used for storing the output characters transmitted by the output character string conversion module.

Optionally, the undetermined state identifying and packing module includes an output character judging module, a counting module and an output character cache processing module, and the structure of the output character cache processing module is shown in fig. 2 b.

The output character judgment module is used for reading each output character in the output character string one by one from the output character FIFO cache module, judging whether the currently read output character is an undetermined state output character or not, and sending a counting instruction to the counting module if the currently read output character is the undetermined state output character; if the output character is not in the undetermined state, judging whether the number of the output characters in the undetermined state stored in the counting module is 0 or not, if the number of the output characters in the undetermined state is 0, transmitting the currently read output character to the output character cache processing module, and if the number of the output characters in the undetermined state is not 0, transmitting the currently read output character and the number of the output characters in the undetermined state acquired from the counting module to the output character cache processing module together, and clearing the number of the output characters in the undetermined state.

And the counting module is used for receiving a counting instruction and performing accumulated counting on the output character number in the undetermined state.

The output character cache processing module is used for receiving the output characters transmitted by the output character judging module and inputting the output characters into the corresponding positions of the current encoding output bytes; and receiving the output characters transmitted by the output character judgment module and the number of the output characters in the undetermined state acquired from the counting module, firstly, inputting the output characters into the corresponding position of the current coding output byte, and then, inputting a plurality of output characters in the undetermined state, which are opposite to the currently read output characters, into the corresponding position of the current coding output byte.

Referring to fig. 3, a flowchart of a method for renormalization and packed output of arithmetic coding in the present invention is shown, the method includes the following steps:

step 301, obtaining a high-order 7-bit output string and a 7-bit flag string according to a codLow value to be updated, wherein the 7-bit flag string identifies an undetermined state output character in the 7-bit output string; and obtaining the effective number according to the CodRange value to be updated, wherein the effective number represents the effective bit number of the output character in the 7-bit output string obtained according to the CodLow value to be updated.

Step 302, extracting a plurality of valid output characters from the 7-bit output string, and identifying an undetermined state output character in the extracted output characters according to the 7-bit flag string.

And 303, processing the extracted output characters to obtain coded output bytes, and outputting the coded output bytes.

The method specifically comprises the following steps: judging the extracted output characters, and if the currently extracted output characters are judged to be output characters in an undetermined state, performing cumulative counting on the number of the output characters in the undetermined state, and continuously extracting the next output character; if the current extracted output character is not the output character in the undetermined state, judging whether the number of the output characters in the undetermined state is 0 or not, if the number of the output characters in the undetermined state is 0, typing the current extracted output character into the current encoding output byte, and if the number of the output characters in the undetermined state is not 0, typing the current extracted output character into the current encoding output byte, and then typing a plurality of output characters, which are opposite to the current extracted output character, into the current encoding output byte. When the 8-bit output characters of the encoded output byte are all filled, the encoded output byte is output.

Optionally, before step 301, the method comprises: obtaining an updated CodLow value according to the CodLow value to be updated and the CodRange value to be updated through an implementation mode of a hardware circuit; and obtaining an updated CodRange value according to the CodRange to be updated through an implementation mode of a hardware circuit.

By adopting a software implementation mode of serial processing in the prior art, the updates of the CodRange value and the CodLow value are interleaved, a CPU (central processing unit) cannot simultaneously meet all conditions of the CodRange value and the CodLow value during updating, multiple times of circulation are needed for implementation, and 7 times of circulation are needed at most. In the scheme of the invention, after acquiring the CodRange value to be updated and the CodLow value to be updated in a parallel mode, updating the CodRange value and the CodLow value is respectively and independently processed, the effective number, the 7-bit character string and the 7-bit mark string are obtained while updating, and the final output character is obtained according to the effective number, the 7-bit character string and the 7-bit mark string. By adopting the scheme of the invention, the renormalization and the packaging output can be finished only by two clock cycles, wherein the updating is finished in the first clock cycle, and the effective number, the 7-bit character string and the 7-bit mark string are obtained; and obtaining an output character according to the effective number, the 7-bit character string and the 7-bit mark string in the second clock period.

Therefore, the invention separates the renormalization processing from the packaging output processing, and separates the updating of the CodRange value and the CodLow value in the renormalization processing, so that the arithmetic coding is easy to realize on a hardware circuit, the renormalization process with unfixed cycle times is solidified and completed in two clock periods, the renormalization and packaging output processes are simplified, and the coding speed is improved.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A method for packed output of arithmetic coding, the method comprising:

obtaining a 7-bit mark string and a high-order 7-bit output string according to an initial position CodLow value of a probability space to be updated, wherein the 7-bit mark string marks an undetermined state output character in the 7-bit output string; obtaining an effective number according to the CodRange value of the probability space to be updated, wherein the effective number represents the number of effective output characters in a 7-bit output string obtained according to the CodLow value to be updated;

2. The method of claim 1, wherein before deriving the 7-bit flag string and the upper 7-bit output string according to the CodLow value to be updated, the method comprises:

obtaining an updated CodLow value according to the CodLow value to be updated and the CodRange value to be updated through an implementation mode of a hardware circuit; and obtaining an updated CodRange value according to the CodRange to be updated through an implementation mode of a hardware circuit.

3. The method as claimed in claim 2, wherein the method of obtaining the updated CodLow value according to the CodLow value to be updated and the CodRange value to be updated comprises the steps of:

calculating the number of all bits with the value of '0' from the highest bit of the CodRange value to be updated to the bit with the first value of '1', and counting as n;

judging whether all high n bits of the CodLow value to be updated are ' 1 ', if so, judging that all high n bits of the CodLow value to be updated are ' 1

Shifting the CodLow value to be updated by n bits to the left, and filling zero in the low bits to obtain the updated CodLow value;

if not, the CodLow value to be updated is shifted to the left by n bits, the low bit is filled with zero, and the highest bit is set to be 0, so that the updated CodLow value is obtained;

the method for obtaining the updated CodRange value according to the CodRange to be updated comprises the following steps:

and shifting the CodRange value to be updated by n bits to the left, and filling zero in the lower bits to obtain the updated CodRange value.

4. The method of claim 2, wherein the output character is represented by 2 bits, the output "0" character is represented by "00", the output "1" character is represented by "01", and the output of the undetermined status character is represented by "10".

5. The packing output device of arithmetic coding is characterized by comprising a CodLow analysis module, a CodRange analysis module, an output character extraction cache module and an undetermined state identification and packing output module;

the CodLow analysis module is used for obtaining a 7-bit mark string and a high-order 7-bit output string according to a CodLow value to be updated, transmitting the 7-bit mark string to the output character extraction cache module, and identifying an undetermined state output character in the 7-bit output string by the 7-bit mark string;

6. The apparatus of claim 5, wherein the CodLow parsing module is implemented by a hardware circuit, and is further configured to obtain an updated CodLow value according to a CodLow value to be updated and a CodRange value to be updated;

the CodRange parsing module is realized through a hardware circuit and is further used for obtaining an updated CodRange value according to the CodRange value to be updated.

7. The apparatus of claim 6, wherein the CodLow analysis module obtains the updated CodLow value by shifting the CodLow value to the left by n bits and performing zero padding on the low bits; and when the high n bits of the CodLow value to be updated are not all "1", setting the highest bit of the updated CodLow value to be "0"; the CodRange analysis module is specifically used for obtaining an updated CodRange value by shifting the CodRange value to be updated by n bits to the left and carrying out zero padding on a low bit; where n is the number of bits of all values "0" starting from the most significant bit of the CodRange value to be updated to the bit of the first value "1".

8. The apparatus of claim 5, wherein the output character is represented by 2 bits, the output "0" character is represented by "00", the output "1" character is represented by "01", and the output of the undetermined status character is represented by "10".

9. The apparatus according to claim 5, 6, 7 or 8, wherein the output character extracting buffer module comprises a first-in first-out (FIFO) buffer module, an output character string converting module and an output character FIFO buffer module;

the first FIFO cache module is used for receiving and storing the 7-bit output string and the 7-bit mark string transmitted by the CodLow analysis module; receiving and storing the effective number transmitted by the CodRange analysis module;

the output character string conversion module is used for reading the effective number and the 7-bit mark string stored in the first FIFO cache module, extracting effective number of output characters from the 7-bit output string stored in the first FIFO cache module, identifying output characters in an undetermined state in the extracted output characters according to the 7-bit mark string, and serially outputting the extracted output characters to the output character FIFO cache module;

10. The apparatus of claim 9, wherein the undetermined state recognition and packing output module comprises an output character judgment module, a counting module, and an output character cache processing module;

the output character judgment module is used for reading output characters one by one from the output character FIFO cache module, judging whether the currently read output character is an output character in an undetermined state or not, and if so, sending a counting instruction to the counting module; if not, judging whether the number of the output characters in the undetermined state stored in the counting module is 0 or not, if so, transmitting the currently read output characters to the output character cache processing module, and if not, transmitting the currently read output characters and the number of the output characters in the undetermined state acquired from the counting module to the output character cache processing module;

the counting module is used for receiving a counting instruction and performing accumulated counting on the output character number in the undetermined state;

the output character cache processing module is used for receiving the output characters transmitted by the output character judging module and inputting the output characters into the current coding output byte; and receiving the output characters transmitted by the output character judgment module and the number of the output characters in the undetermined state acquired from the counting module, firstly, inputting the output characters into the current coding output byte, and then, inputting a number of output characters in the undetermined state, which are opposite to the currently read output characters, into the current coding output byte.